JP7744035B2 - High-performance semiconductor devices - Google Patents

Description

Article 30, Paragraph 2 of the Patent Act applies. Institute of Electrical Engineers of Japan, Journal D (Industrial Applications Journal), Vol. 140, No. 12, pp. 972-982, published December 1, 2020.

The present invention relates to semiconductor devices, and in particular to high-performance reverse conducting semiconductor devices with high reliability and small chip size.

Currently, semiconductor devices made of silicon (Si) are primarily used for high-voltage, high-power, and medium-power applications. Among these, Si-IGBTs are widely used as the primary semiconductor device in a variety of application fields, with products available up to the 6.5 kV class. In recent years, efforts have been made to improve the performance of these Si-IGBTs, such as by reducing their loss, and various innovations have been devised to shorten the turn-off speed and reduce losses. Representative examples of these innovations include the development of conventional Si reverse-conducting IGBTs, such as Conventional Example 1 shown in FIG. 7 and Conventional Example 2 shown in FIG. 8, which are disclosed in Non-Patent Documents 1 and 2, respectively.
In the shorted collector Si-IGBT of Conventional Example 1, the n ^- drift layer is shorted to the collector electrode by an n ⁺ short circuit portion provided in the p-collector layer, and at turn-off, carriers remaining in the n ^- drift layer are removed via this n ⁺ short circuit portion, thereby shortening the turn-off time and reducing losses.

On the other hand, the Si reverse-conducting IGBT of Conventional Example 2 is composed of a reverse-conducting Si-IGBT region and a pilot IGBT region. In the Si reverse-conducting IGBT region, the n-drift layer is shorted to the collector electrode by an n ⁺ short circuit portion provided in the p-collector layer, as in Conventional Example 1, and carriers remaining in the n-drift layer are removed via this n ⁺ short circuit portion at turn-off, thereby shortening the turn-off time and reducing losses. In addition, the collector width of the pilot IGBT region is made significantly larger than the collector width of the reverse-conducting IGBT region, so that the pilot IGBT region turns on before the reverse-conducting IGBT region.
In addition, these disclosed IGBTs have been collectively referred to as reverse conducting IGBTs in recent years because the n drift layer is shorted to the collector electrode by an n ⁺ short circuit, and therefore they have no blocking capability against reverse voltage. Therefore, hereinafter, all of them will be referred to as reverse conducting IGBTs.
In recent years, the development of high-voltage, high-power and medium-power semiconductor devices using wide-gap semiconductors such as SiC semiconductors has been promoted, and significant performance improvements have been made compared to Si semiconductor devices. However, there are no examples of prototype development or practical application of reverse-conducting IGBTs using wide-gap semiconductors such as SiC semiconductors.

Hajime Akiyama and five others, "Effects of Shorted Collector on Characteristics of IGBTs," Proceedings of the 2nd International Symposium on Power Semiconductor Devices & ICs, April 1990, pp. 131-136 Litauras Storasta and two others, "A Comparison of Charge Dynamics in the Reverse-Conducting RCIGBT and Bi-mode Insulated Gate Transistor (BiGT)," Proceedings of the 22nd International Symposium on Power Semiconductor Devices and ICs Power Semiconductor Devices & ICs), June 2010, p. 391-394

The output characteristics of the disclosed Si reverse-conducting IGBTs of Conventional Examples 1 and 2, i.e., the Ice-Vce characteristics between the collector-emitter voltage (hereinafter referred to as Vce) and the collector-emitter current (hereinafter referred to as Ice), exhibit a snapback phenomenon in which the collector-emitter voltage immediately before turning on is greater than the collector-emitter voltage immediately after turning on. The collector-emitter voltage immediately before turning on is called the knee point voltage in Conventional Example 1 and the pre-snapback peak voltage in Conventional Example 2, but below it will be called the snapback voltage and abbreviated as Vsb. The collector-emitter current at this Vsb will be called the snapback current and abbreviated as Isb.

However, because these reverse-conducting IGBTs have a short turn-on time, the time it takes for them to transition from just before turning on to just after, snapback causes a steep voltage change (hereafter referred to as dV/dt) and a steep current change (hereafter referred to as dI/dt) when they turn on. As a result, parasitic capacitance within the circuit causes a steep current jump (C dv/dt), and parasitic reactors cause a steep voltage jump (L dI/dt), which in turn induces large transients. This causes major disturbances in circuits using these reverse-conducting IGBTs, resulting in malfunctions and, in some cases, destruction of the elements or circuits. Therefore, suppressing or eliminating snapback within an acceptable range is an extremely serious primary challenge.

In addition, in the Si reverse conducting IGBT of Conventional Example 2, a pilot IGBT region is provided adjacent to a reverse conducting IGBT region consisting of multiple reverse conducting IGBT cells. The p collector width of the pilot IGBT region is made significantly larger than the p collector width of the IGBT cells in the reverse conducting IGBT region, thereby increasing the lateral resistance of the buffer layer on the p collector. Therefore, the pilot IGBT region is first turned on with a small ice. This suppresses the snapback phenomenon in the pilot IGBT region. As a result, the pilot IGBT region, where the snapback phenomenon is suppressed, first turns on with a small ice, allowing a larger on-current to flow. This on-current then spreads and flows into the nearest reverse conducting IGBT cell. The p-collector of the nearest reverse-conducting IGBT cell has a small width, so the lateral resistance of the buffer layer on the p-collector is low. However, because part of the on-current of the pilot IGBT flows in as a large spreading current, the p-collector junction of the nearest reverse-conducting IGBT cell easily reaches its built-in voltage and turns on. As a result, the on-current increases further, and the reverse-conducting IGBT cell adjacent to this nearest reverse-conducting IGBT cell also turns on. This operation is repeated, and the reverse-conducting IGBT cells closest to the pilot IGBT region are turned on one after another, until the entire reverse-conducting Si-IGBT is turned on.

However, in the case of Reference 2, the area of the pilot IGBT region relative to the overall IGBT chip area becomes significantly larger. For example, in Reference 2, the data indicates that the p-collector width of a 3.3 kV Si reverse-conducting IGBT standard cell is 240 microns, while the p-collector width of the pilot IGBT is set to 650 microns, more than three times that width, to maintain Vsb at the built-in voltage of approximately 0.7 V. As the breakdown voltage of a semiconductor device increases, the snapback phenomenon becomes more severe, and the p-collector width of the pilot IGBT must be further increased significantly. While this eliminates the snapback phenomenon, it also reduces the area of the reverse-conducting IGBT region relative to the overall IGBT chip area, reducing the number of standard cells integrated. This increases on-resistance and impairs the reverse-conducting IGBT's inherent function of eliminating residual carriers during turn-off. Furthermore, given that element chip sizes are typically set to around 15mm x 15mm or less due to economic considerations such as yield, this is a major issue and is the second challenge that must be resolved.

As described in [0007], in SiC IGBTs, reverse-conducting IGBT cells adjacent to the pilot IGBT region are sequentially turned on until the entire reverse-conducting Si-IGBT is turned on, causing higher-order snapback to occur following the primary snapback. While measures to suppress primary snapback, such as the pilot IGBT described above, have been disclosed, measures to suppress this higher-order snapback phenomenon have not been clarified. The higher the breakdown voltage and current of a semiconductor device, the greater the higher-order snapback phenomenon, causing significant disturbances in the circuits used, resulting in malfunctions and, in some cases, destruction of elements and circuits. Improving reliability by suppressing this higher-order snapback phenomenon is an important third challenge.

SiC IGBTs suffer from a degradation phenomenon known as on-voltage degradation. This is a phenomenon in which the on-voltage increases over time due to current stress. This phenomenon poses a significant reliability problem, resulting in a decrease in the efficiency of power conversion devices over time and an imbalance between SiC IGBTs in a module, resulting in excessive current concentration in a specific chip and potentially device destruction. Furthermore, it is unclear how current and voltage stresses associated with first-order snapback and higher-order snapback accelerate or suppress on-voltage degradation in wide-gap semiconductor reverse-conducting IGBTs such as SiC. A fourth important challenge is to improve reliability by suppressing on-voltage degradation caused by first-order snapback and higher-order snapback.
In the following description, the degradation due to the snapback phenomenon is defined as rapid on-state voltage degradation, and will be referred to as such, in order to distinguish it from the on-state voltage degradation that occurs as a result of operation of a wide-gap semiconductor reverse conducting IGBT.

The present invention aims to solve the problems of the prior art by providing a high-performance reverse-conducting IGBT that can suppress Vsb to an acceptable range and effectively remove residual carriers at turn-off. It also aims to provide a high-performance reverse-conducting semiconductor device that can suppress Vsb to an acceptable value with a smaller occupied area and reduce chip size. It also aims to provide a high-performance reverse-conducting semiconductor device that is highly reliable and can suppress high-order snapback phenomena.

The above "Problem to be Solved by the Invention" does not provide a detailed explanation of suppressing Vsb to an allowable range and the dependency of Vsb on the breakdown voltage, so these will be explained below. Note that the following supplements the explanation to make the present invention easier to understand, and does not add any new matter.
Hideki Takahashi (Mitsubishi Electric) wrote in a paper at a famous international conference (Non-Patent Document 3: Proceedings of ISPSD 2004, pp.133-136) that "in the 1.2 kV reverse conducting IGBT he developed, Vsb was 2.8 V (room temperature) and Isb current density was 5 A/cm. ² "However, because this occurred in a small current density region, this Vsb is tolerable for standard inverter operation," the company announced. In other words, it is not necessary to eliminate Vsb, but as long as it is kept within an acceptable range, it is acceptable for practical use in inverters, etc.
Furthermore, in a paper at the same international conference (Non-Patent Document 4: Proceedings of ISPSD 2020, pp. 482-485), FM Rahimo (MTAL, Switzerland) published the following: "In a circuit in which two 1.2 kV Si reverse-conducting IGBTs are connected in parallel (which corresponds to a widely used IGBT module), the degree of snapback phenomenon (specifically, Vsb and Isb) of each reverse-conducting IGBT was changed to examine the degree of imbalance in the shared current at turn-on. The results showed that when the Vsb difference in the snapback phenomenon is small, both reverse-conducting IGBTs turn on, and the shared current imbalance is small and poses no problem. However, when the Vsb difference is large, the shared current imbalance is large, and one of the reverse-conducting IGBTs turns off during turn-on, causing all the current to flow into the other reverse-conducting IGBT, creating a risk of damage." In other words, in a parallel-connected circuit (which also applies to commercially available IGBT modules, etc.), a small Vsb is tolerable, but a large Vsb will result in damage to the element, so there is a clear tolerance range for Vsb, and this shows that even if Vsb is not eliminated, it can be used in practical IGBT modules, etc., as long as it is kept within the tolerance range.
Incidentally, Vsb is highly dependent on the breakdown voltage. Specifically, the resistance Rdrift of the drift layer of the device increases significantly as the breakdown voltage increases, so even if Isb is small, Vsb becomes significantly larger (see equation (1) in [0017]). Non-Patent Document 2, cited above, reports that for a reverse-conducting IGBT with a breakdown voltage of 3.3 kV, Vsb is approximately 20 V (at room temperature). In the case of reverse-conducting semiconductor devices with a breakdown voltage of 15 kV for power and industrial applications, which are the subject of the present invention, there is concern that if no countermeasures are taken, Vsb will become extremely large (more than 100 times larger), and reducing this value is a serious and important issue.
To reduce Vsb, it is essential to quantitatively clarify the relationship between Vsb and the main device structural factors related to Vsb in a reverse conducting semiconductor device with a specified breakdown voltage, and to clarify the device structure that results in an acceptable Vsb range. Therefore, it is essential to analyze the snapback phenomenon in detail and establish an analytical formula that can quantitatively calculate the relationship between Vsb and the type of semiconductor material and the main device structural factors.
The inventors have succeeded in deriving the analytical formula and have previously used this analytical formula to apply for a patent that can eliminate the snapback phenomenon by configuring the active region of a reverse conducting IGBT solely with IGBT cells with pilot functions that have a collector width derived from this analytical formula, and this patent application was disclosed in JP 2022-158357.
Here, we are filing a patent application for an invention that has even greater practical benefits and can further significantly reduce cell size. Although the snapback phenomenon is not eliminated, the active region of a reverse-conducting IGBT is composed solely of IGBT cells with a pilot function, and this device structure can accurately suppress Vsb within an acceptable range. As will be explained in detail below, even if the snapback phenomenon is not eliminated, once an appropriate Vsb specification value within the suppression acceptable range is submitted for various applications, a reverse-conducting IGBT structure with structural factors (width, thickness, impurity concentration, etc. of the drift layer, buffer layer, collector layer, etc.) that matches the specification can be quickly identified and products can be quickly brought to market, resulting in high reliability, low loss, high speed, and reduced device area due to Vsb suppression. This has enormous potential for a wide range of industrial applications, as well as significant performance improvements and economic benefits.

In the following, to avoid complexity and to facilitate understanding, an n-channel type IGBT will be described.
In order to solve the above problems and achieve the object of the present invention, a semiconductor device according to the present invention is
The reverse conducting semiconductor device is configured by connecting a unipolar transistor and a bipolar transistor in parallel, and is configured of a wide gap semiconductor and has a standard cell in an active region , wherein the standard cell is a standard cell with a pilot function, the standard cell having a collector with a collector width Wp derived using a graph relating a snapback voltage Vsb of the snapback phenomenon to a collector width Wp of the standard cell or an analytical method for deriving the graph, so that the Vsb is approximately equal to a predetermined Vsb at which the snapback phenomenon is suppressed or eliminated within an allowable range, and the standard cell is configured solely from the standard cell with a pilot function.
When the reverse conducting semiconductor device is a reverse conducting IGBT , the pilot IGBT-equipped cell, which is a cell that constitutes the active region, is defined as a pilot function-equipped IGBT standard cell, and will be referred to as a pilot function-equipped IGBT standard cell hereinafter.
Therefore, when the reverse conducting semiconductor device is a reverse conducting IGBT, the standard cells in the active region of the reverse conducting IGBT are constructed solely from the pilot function-equipped IGBT standard cells, which are the pilot function-equipped standard cells.

The semiconductor device according to the present invention is the above-mentioned invention,
The active region of the reverse conducting semiconductor device is formed only by the pilot function-equipped IGBT standard cell, and the pilot function-equipped IGBT standard cell has a buffer layer, and the buffer layer has a single structure or a multiple structure of two or more layers.

The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the semiconductor device is a reverse conducting IGBT semiconductor device made of a wide gap semiconductor, the p collector width Wp of the pilot function-equipped IGBT standard cell is a collector width that can suppress snapback within an allowable range, one or more MOSFET surface portions are provided on the front surface of the pilot function-equipped IGBT standard cell, and a short circuit portion that connects the buffer layer and a collector electrode of the reverse conducting IGBT is provided in the center of the back surface opposite to the front surface of the pilot function-equipped IGBT standard cell, and collectors having approximately half the width are provided on both ends of the short circuit portion. The reason why the collector width at both ends is 1/2 as described above is due to the derivation model of the collector width Wp and its analytical method . Please refer to the derivation model diagram in Figure 1 of Patent No. 6383971 by the present inventor and the analytical method in the paper (Institute of Electrical Engineers, Journal D (Industrial Applications Journal) Vol. 140, No. 12, p. 980, published December 1, 2020).
This analytical method is described in the left column of page 980 of the above-mentioned paper, from lines 8 to 39. As stated on lines 38 to 39, "Using Rbuffer calculated from equation [3], Isb can be calculated from equation [2], and Vsb can be calculated from equation [1]," Vsb and the corresponding Wp (Wp is included in equation [3]) can be calculated, and by rearranging these, we can derive a relationship diagram of Vsb and Wp using Nd as a parameter, as shown in Figure 3.

The semiconductor device according to the present invention is the above-mentioned invention,
By applying the TEDEREC method or the Mach-TEDREC method, which are the inventors' previous inventions, not only the on-voltage degradation but also the rapid on-voltage degradation can be suppressed or eliminated.
TEDEREC and Mach-TEDREC are operating methods invented by the present inventor and are respectively disclosed in Japanese Patent Nos. 4741630, 5835679, and 6232687. The Mach-TEDREC method is briefly explained in [0024], but is described in detail from the first line of the right column on page 976 to the 18th line of the left column on page 979 of the above paper.

In order to solve the above problems and achieve the object of the present invention, according to the present invention,
Based on the inventor's analysis, Vsb and Isb in the snapback phenomenon of a reverse conducting IGBT can be approximately calculated using equation (1).
Vsb=IsbxRch+KxIsbxRdrift+Vbi (1)
Here, Rch is the channel resistance of the MOS gate, Rdrift is the resistance of the drift layer, and Vbi is the built-in voltage of the collector junction. K is the current spreading factor of Isb, which can be made closer to 1 by reducing the parasitic JFET width. In high-voltage reverse-conducting IGBTs, Rch is significantly smaller than Rdrift and can be ignored.

Wide-gap semiconductor materials have superior physical properties compared to Si, making it possible to significantly reduce the Vsb of the pilot IGBT. For example, in the case of SiC semiconductors, Vbi is approximately 2.7 V, which is about four times that of Si, making it disadvantageous for reducing Vsb. However, Rdrift can theoretically be significantly reduced to about 1/1000, so as a result, Vsb of the pilot IGBT can be significantly reduced (to about 1/250), more than making up for the disadvantage of Vbi.
As a result, by applying a standard cell with a pilot function constructed using a SiC semiconductor, Vsb can be significantly reduced and induced transient phenomena can be significantly suppressed, thereby suppressing malfunctions of circuits using this reverse conducting IGBT and the resulting destruction of elements and circuits, thereby improving reliability.

Furthermore, in order to solve the above-mentioned problems and achieve the object of the present invention, according to the present invention,
As described above, Vsb can be significantly reduced by using SiC compared to Si, so that the p collector width can be significantly reduced for the same Vsb. Therefore, instead of constructing a chip by combining a standard cell and a pilot IGBT as in Reference 2, a chip is constructed by using the pilot IGBT itself, which can be significantly reduced, as the standard cell. As described above, this standard cell is defined as an IGBT standard cell with a pilot function.
For the same Vsb, the area of a SiC chip composed of a given number of pilot-function-equipped IGBT standard cells is much smaller than the area of a Si chip composed of a combination of standard cells and pilot IGBTs. For example, in the case of the 3.3 kV Si reverse-conducting IGBT of Reference 2, the standard cell width is 240 micrometers and the pilot IGBT width is 650 micrometers or more. However, in the case of 15 kV-class SiC, by applying pilot-function-equipped IGBT standard cells, the standard cell width can be significantly reduced to 196 micrometers according to analytical calculations described below, despite the significantly higher breakdown voltage. Moreover, the large-width pilot IGBT can be eliminated.
Therefore, in the case of a reverse conducting IGBT with the same chip size and with the same breakdown voltage, a SiC chip can have a larger excess space than a Si chip. Therefore, by adding multiple standard cells with pilot functions in this excess space, the on-resistance can be reduced, and by utilizing the excess space to increase the width of the short-circuit region in the standard cell, the reverse conducting function can also be improved.

In order to solve the above problems and achieve the object of the present invention, according to the present invention,
As described above, in the semiconductor device, each standard cell in the chip is provided with a pilot function. As a result, all cells in the chip are essentially composed of pilot IGBTs of the same size, so that they can be turned on almost simultaneously when put into operation.
Furthermore, if n MOSFET surface portions are provided in an IGBT standard cell with a pilot function, only higher-order snapbacks up to nth order will occur. These higher-order snapbacks can be suppressed by suppressing the first-order snapback phenomenon, and various problems in the circuit caused by higher-order snapbacks can be suppressed.

Furthermore, by providing n-shorting layers at both ends of the standard cell and providing only the collector between them, the width of the standard cell can be effectively utilized, maximizing the collector width. Also, because the Wp of the standard cell is equal to or greater than the critical Wp and an even number of MOSFET surface regions are provided within the standard cell, the p-collector can be used most effectively to suppress Vbi.

According to the present invention, in the above-mentioned invention,
The single-layer n-buffer layer allows for high-precision control of Vsb. Furthermore, the dual-layer structure allows for suppression or elimination of Vsb with a smaller collector width. This is because the dual-layer structure increases the lateral resistance of the buffer layer, thereby enabling the semiconductor device to be turned on at a low Vbs. The dual n-buffer layer has a dual structure consisting of a highly doped, thin first buffer layer in contact with the p-collector and a lightly doped, thick second buffer layer in contact with the n-drift layer. It is important that the first buffer layer has a thickness and impurity concentration that ensures complete depletion when the built-in voltage Vbi is applied to the junction between the collector and buffer layer. It is also important that the second buffer layer is only partially depleted, with the remaining undepleted portion achieving a high lateral resistance.
In the case of a two or more layer multiplex structure, it is essential that all layers other than the Nth layer, which corresponds to the low-concentration, thick second buffer layer in contact with the drift layer, be set to a thickness and impurity concentration such that they are completely depleted when the built-in voltage Vbi is applied. As a result, the Nth buffer layer can be easily made even more lightly doped, and the non-depleted portion of the Nth buffer layer can easily achieve a higher lateral resistance than in the case of two layers. This allows the buffer layer width and p-collector width to be further reduced, further reducing the cell size and ultimately the chip size, resulting in significant economic benefits.

According to the present invention, in the above-mentioned invention,
Higher-order snapback phenomena can be suppressed or eliminated. This is due to the fact that, as described above, the collector width of a SiC reverse conducting IGBT can be made significantly smaller than that of a Si reverse conducting IGBT, and primary snapback phenomena can be suppressed or completely eliminated.
Furthermore, by reducing the number of MOSFET surface portions to a number less than the maximum number N of MOSFET surface portions that can fit within the standard cell width defined by the collector width Wpc and the short-circuit width Wn, which can eliminate the first snapback phenomenon, it is possible to suppress or eliminate high-order snapback in the pilot-function-equipped IGBT standard cell. In this case, the on-resistance of the pilot-function-equipped IGBT standard cell increases, but this can be fully offset by increasing the number of standard cells in the chip, since the standard cell becomes significantly smaller.

According to the present invention, in the above-mentioned invention,
By applying the Mach-TEDREC method, on-state voltage degradation can be suppressed or eliminated. That is, the rapid on-state voltage degradation described above, which is caused by current and voltage stress associated with primary snapback and higher-order snapback phenomena, can be suppressed or eliminated by raising the element temperature at startup and during operation to a degradation suppression temperature or higher, and therefore can be suppressed or eliminated by operating only the SiC MOSFET portion via the short-circuit region of the SiC reverse-conducting IGBT to allow only majority carrier current, which does not cause degradation, to flow and raising the element temperature to a degradation suppression temperature or higher.

As described above, the present invention allows for the construction of a reverse conducting semiconductor device using a wide-gap semiconductor, and for the construction of a SiC chip using standard cells with pilot functions that can be significantly smaller in area than standard Si cells. This reduces the chip area, reduces disturbance and destruction of circuit operation by suppressing the snapback phenomenon, thereby achieving high reliability, and reduces switching losses by more effectively removing residual carriers at turn-off and shortening the turn-off time. Furthermore, primary and higher-order snapback can be significantly suppressed, suppressing the rapid on-voltage degradation caused by the snapback phenomenon and its adverse effects, thereby improving reliability.

1 is a schematic cross-sectional view of a SiC reverse conducting IGBT according to a first embodiment; Output characteristics of the 15 kV-class SiC reverse conducting IGBT according to the first embodiment Relationship between Vsb and Wp of the 15 kV-class SiC reverse conducting IGBT according to the first embodiment Schematic cross-sectional view of a SiC reverse conducting IGBT according to a second embodiment. Relationship between Vsb and Wp of the 15 kV-class SiC reverse conducting IGBT according to the second embodiment 10 is a schematic cross-sectional view of a SiC reverse conducting IGBT according to a third embodiment. Schematic cross-sectional view of a high-voltage Si reverse-conducting IGBT according to Conventional Example 1 Schematic cross-sectional view of a high-voltage Si reverse-conducting IGBT according to Conventional Example 2

Preferred embodiments of semiconductor devices according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes, respectively, are the majority carriers. In the drawings, numbers and arrows indicating layers and regions are generally shown for only one representative layer or region, and the others are omitted. Furthermore, the figures are intended to better explain the invention, and there is no proportionality or other correlation between the dimensions within and between the figures.

(Embodiment 1)
Fig. 1 is a cross-sectional view schematically illustrating a semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment illustrated in Fig. 1 is a reverse conducting IGBT 100 having a planar gate structure and a designed breakdown voltage of, for example, 15 kV, fabricated using a SiC (silicon carbide) semiconductor.
Compared to Si, Vsb can be significantly reduced by using SiC, so for the same Vsb, the p collector width can be significantly reduced. Therefore, rather than constructing a chip by combining a standard cell and a pilot IGBT as in Reference 2, the SiC reverse conducting IGBT of this invention is characterized by constructing a chip using a cell that includes the pilot IGBT itself, which can be made significantly smaller, in the standard cell, that is, an IGBT standard cell with a pilot function.
This SiC reverse conducting IGBT is characterized by the fact that the p collector width Wp is set in coordination with the constraints imposed by the need to suppress snapback at high breakdown voltages, the constraints imposed by the MOSFET section from a performance standpoint, and the constraints imposed by the chip area from a practical standpoint.

First, the structure of the SiC reverse conducting IGBT 100 will be described.
FIG. 1 shows only a portion of the active region of the reverse conducting IGBT 100. The SiC reverse conducting IGBT 100 includes, for example, a breakdown voltage structure (not shown) surrounding the active region. The active region is the region through which current flows when the semiconductor device is on, and the breakdown voltage structure is a structure that reduces the electric field strength near the pn junction constituting the semiconductor device and achieves a desired breakdown voltage. The chip size is 8 mm x 8 mm, the active region is 6 mm x 6 mm, and the width of the breakdown voltage structure surrounding the active region is 1 mm. The reverse conducting IGBT standard cells in the active region are striped, and the width of the standard cells is 196 micrometers. The width of the standard cell is defined as the sum of the width Wn of the n short-circuit portion 103 and the width Wp of the p collector region 102.

As shown in FIG. 1 , in a SiC reverse conducting IGBT 100, a p-collector layer 102 and a plurality of n ⁺ short circuits penetrating this layer are provided on the surface in contact with a collector electrode 101, with p-collector regions 102 and n ⁺ short circuit regions 103 being alternately formed. The impurity concentration and thickness of the p-collector region 102 may be, for example, 3.5×10 ¹⁷ cm ⁻³ and 1.5 micrometers, respectively. The impurity concentration and thickness of the n ⁺ short circuit 103 may be, for example, 1×10 ¹⁹ cm ⁻³ and 1.5 micrometers, respectively. An n-buffer layer 104 is provided on the front surfaces of these regions 102 and 103.

An n ^- drift layer 106 is provided on the surface of the buffer layer 104. The impurity concentration of the ^n- drift layer 106 is lower than the impurity concentration of the n-buffer layer 104. Specifically, the impurity concentration and thickness of the n ^- drift layer 106 may be, for example, 2×10 ¹⁴ cm ⁻³ and 150 micrometers, respectively. Roughly speaking, with an impurity concentration of this order, a breakdown voltage of, for example, 1 kV per 10 micrometers of thickness of the n ^- drift layer 106 can be easily achieved. Therefore, by setting the thickness of the n ^- drift layer 106 to 150 micrometers, a breakdown voltage of 15 kV can be expected.

One or more p-body regions 107 constituting a MOSFET are selectively provided in the surface layer of the n ^- drift layer 106. The impurity concentration of the p-body region 107 is higher than that of the n ^- drift layer 106. Specifically, the impurity concentration and thickness of the p-body region 107 may be, for example, 1×10 ¹⁸ cm ⁻³ and 0.3 micrometers, respectively. The width of the n ^- drift layer 106 sandwiched between adjacent p-body regions 107 in the direction in which the p-body regions 107 are arranged side by side (hereinafter referred to as the horizontal direction) may be, for example, 3 micrometers to 12 micrometers. Note that the adjacent p-body regions 107 and the n ^- drift layer 106 sandwiched therebetween also function as a parasitic junction FET portion.
The p-body region 107 is a semiconductor layer formed by, for example, aluminum ion implantation. The impurity concentration of the n ^- layer 114, which also functions as a parasitic junction FET portion, may be 2×10 cm ⁻³ , the same as that of the n ^- drift layer ¹⁰⁶ , or may be different within a range that does not impair the function as a parasitic junction FET portion. The thickness may be 0.6 micrometers.

Incidentally, since impurity diffusion in the direction perpendicular to the depth direction is less in SiC semiconductors than in silicon semiconductors, the semiconductor layers are illustrated as rectangular in Figure 1 (similarly, the semiconductor layers are illustrated as rectangular in the reverse conducting IGBTs shown in the following figures).

An n ⁺ emitter region 108, a p ^- low-concentration channel region 109, and a p+ contact region 110, which function as the source of the MOSFET portion, are selectively provided in the surface layer of the p-body region 107. The n ⁺ emitter region 108, the p ^- low-concentration channel region 109, and the p ⁺ contact region 110 are semiconductor layers formed by, for example, ion implantation. The p ^- low-concentration channel region 109 is provided at one end of the p-body region 107 and contacts the parasitic junction FET portion. The n ⁺ emitter region 108 contacts the end of the p ^- low-concentration channel region 109 opposite to the end that contacts the parasitic junction FET portion.

The end of the n ⁺ emitter region 108 in the MOSFET portion that is not in contact with the p ⁺ lightly doped channel region 109 is in contact with the p + contact region 110. The p ⁺ lightly doped channel region 109 and the n ⁺ emitter region 108 provided in each p body region 107 are arranged symmetrically with other adjacent n ⁺ emitter regions 108 and p ⁺ lightly doped channel regions 109 on the p body region 107 with the p + contact region 110 interposed therebetween.

The impurity concentration of the p ^- lightly doped channel region 109 in the MOSFET section is lower than the impurity concentration of the p-body region 107. Specifically, the impurity concentration and thickness of the p ^- lightly doped channel region 109 may be, for example, 1×10 ¹⁶ cm ⁻³ or more and 7×10 ¹⁸ cm ⁻³ or less, respectively, and the thickness may be 0.3 micrometers.
The impurity concentration of the n ⁺ emitter region 108 is higher than the impurity concentration of the ^n- drift layer 106. Specifically, the impurity concentration and thickness of the n ⁺ emitter region 108 may be, for example, 5×10 ¹⁹ cm ⁻³ and 0.3 micrometers, respectively. The impurity concentration and thickness of the p ⁺ contact region 110 may be, for example, 1×10 ¹⁹ cm ⁻³ and 0.3 micrometers, respectively.
The p ^- lightly doped channel region 109 and the n ⁺ emitter region 108 are each formed by ion implantation in the surface layer of the p body region 107. The p ^- lightly doped channel region 109 and the n ⁺ emitter region 108 are provided in the surface layer of the p body region 107 to a depth of, for example, 0.3 micrometers, and therefore the thickness of the portion of the p body region 107 sandwiched between the p ^- lightly doped channel region 109 and the n ⁺ emitter region 108 is, for example, 0.3 micrometers.

The horizontal width of the p ^- lightly doped channel region 109 may be, for example, 0.75 micrometers, and the horizontal width of the n ⁺ emitter region 108 may be, for example, 6 micrometers.

A gate electrode (control electrode) 112 is provided on the surface of the p ^- low-concentration channel region 109 via a gate insulating film 111. The thickness of the gate insulating film 111 may be approximately 600 angstroms. An emitter electrode 113 contacts the n ⁺ emitter region 108 and also electrically contacts the p body region 107 via a p ⁺ contact layer 110. The emitter electrode 113 is insulated from the gate electrode 112.
The MOSFET components on the n ^- drift layer 106 are collectively defined as a MOSFET surface portion, and will be referred to hereinafter by this name.

Next, the novel features of the SiC reverse conducting IGBT according to this embodiment will be described.
The higher the breakdown voltage of a SiC reverse-conducting IGBT, the thicker the n ^- drift layer 106 and the lower the impurity concentration, resulting in a larger Rdrift. Consequently, the snapback voltage Vsb increases (see equation (1)). For this reason, it is preferable to maximize the width of the p-collector 102. However, this requires increasing the width of the MOSFET surface facing the p-collector 102, which is undesirable from a performance perspective due to increased on-state loss of the SiC reverse-conducting IGBT. Therefore, the p-collector width Wp of this SiC reverse-conducting IGBT is set by balancing the constraints of eliminating or suppressing the snapback phenomenon to an acceptable range at high breakdown voltages, the constraints of the MOSFET section from a performance perspective (i.e., reducing loss), and the constraints of chip area from a practical perspective. Furthermore, the chip is characterized by being constructed using a newly conceived and defined IGBT standard cell with a pilot function, which assigns the function of the pilot IGBT to the standard cell itself. By filling the active region of the chip with only such IGBT standard cells with a reduced cell width and a pilot function, it is possible to eliminate or significantly suppress primary snapback and also eliminate or suppress higher-order snapback.

Figure 2 shows the output characteristics of the 15 kV-class SiC reverse-conducting IGBT 100 of this embodiment, i.e., the simulation results of the relationship between Jce and Vce, as shown by the solid line. Jce is the current density between the collector and emitter, and Vce is the voltage between the collector and emitter. In consideration of the computer's calculation capabilities, the simulation model is not the same as the embodiment of Figure 1, but rather has a structure in which only one of the seven MOSFET surface regions, located in the center, is present (this structure corresponds to the single buffer layer structure in Figure 4, described below, in which the first buffer layer 204 is not present). A snapback phenomenon was observed in the output characteristics, and Vsb was approximately 7.2 V.
In FIG. 7, from the intersection of the dotted curve representing the self-heating density of the element of 300 W/ ^cm2 and the output characteristics, the output current density Jce at 175°C is approximately 65 A/ ^cm2 at approximately 4.5 V, which is a sufficiently high value for an element with a withstand voltage of 15 kV.
It should be noted that this SiC reverse conducting IGBT is almost completely turned on at a Vce of about 3.8 V. Therefore, it is clear that the snapback phenomenon can be almost completely eliminated by setting the snapback voltage to 3.7 V or less.

FIG. 3 shows the analytical calculation results of the relationship between Vsb and Wp of the 15 kV-class SiC reverse conducting IGBT 100 of this embodiment.
The analytical model is the same as that shown in Figure 2 above. This shows that if the impurity concentration of the buffer layer is 1 x 10 ¹⁵ cm ^-3 , setting Wp to approximately 175 microns or more will reduce Vsb to approximately 3.7 V or less, thereby substantially eliminating the snapback phenomenon. The Wp at which the snapback phenomenon can be eliminated is defined as the critical collector width, denoted Wpc. Here, Wp is set to 180 microns to allow for some margin. While Wn is based on 8 microns, it is doubled to 16 microns to further reduce switching loss during turn-off. Therefore, the cell width is 196 microns. Incidentally, this 196 micron cell width is seven times larger than the MOSFET surface area in the standard cell described above, which is increased from 24 microns to 28 microns. Therefore, the number of MOSFET surface areas can be increased to seven, as shown in the figure. As a result, the on-resistance can be reduced to approximately one-seventh, resulting in low loss. Furthermore, by doubling the width Wn of the short-circuit portion 103, the carrier removal function that is inherent to reverse conducting IGBTs when they are turned off can be significantly increased, resulting in a reduction in turn-off time and a significant reduction in switching loss, resulting in a dramatic reduction in loss overall.

When the area of this SiC chip is compared with that of a Si reverse conducting IGBT configured by combining a standard cell and a pilot IGBT as in Reference 2, it is found to be much smaller than the area of the Si chip. For example, in the case of the 3.3 kV reverse conducting IGBT of Reference 2, the critical collector Wpc of the pilot IGBT is approximately 650 micrometers, and the standard cell width is 240 micrometers. The standard cell width of the SiC reverse conducting IGBT with pilot function described above is only 82% of the standard cell width of a 3.3 kV Si reverse conducting IGBT, despite the withstand voltage being 15 kV. When the collector width of the pilot IGBT is taken into account, the width becomes even smaller, and when the withstand voltage is further increased by several times, the width becomes even smaller.
Therefore, for the same chip size and with the same breakdown voltage, a SiC chip can secure a sufficiently large excess space compared to a Si chip. Therefore, by adding multiple standard cells with pilot functions to this excess space, the on-resistance can be significantly reduced, and by increasing the width of the short-circuit region in the standard cell, the reverse conduction function can also be improved.

Next, the characteristics of the SiC reverse-conducting IGBT 100 will be described. The IGBT chip 100 was die-bonded to a three-terminal high-voltage package, and then wire-bonded to the gate electrode and emitter electrode. The chip and Al wires were then completely coated with a protective high-voltage, high-heat-resistant resin (Nanotech Resin) to form a semiconductor device, which was then subjected to an operational test. When a forward voltage was applied between the emitter electrode 113 and the collector electrode 101 without applying a gate voltage, leakage current flowed, but the device exhibited good forward blocking characteristics, with a breakdown voltage at room temperature, i.e., avalanche breakdown voltage, of approximately 15.2 kV. Furthermore, the leakage current before avalanche breakdown was good, at 7× ^10-6 A/cm2 or ^less at room temperature and 9× ^10-5 A/cm2 or ^less even at a high temperature of 250°C.

When a forward voltage is applied between the collector electrode 101 and the emitter electrode 113, and then a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 112, the MOSFET section turns on. As the gate voltage is further increased, a current proportional to the forward voltage flows. This current is utilized to suppress on-voltage degradation. Furthermore, even when the forward voltage between the collector electrode and emitter electrode is increased and the IGBT section is turned on at a certain voltage (snapback voltage), no snapback phenomenon, from primary to higher orders, in which the on-voltage suddenly decreases, was observed.

As the forward voltage is further increased, the current increases nonlinearly, and when the collector-emitter voltage (hereinafter referred to as Vce) is 5 V, the collector-emitter current density Jce is approximately 120 A/cm ² , which is favorable.
Estimating from the data of Reference 2, in the case of a Si reverse conducting IGBT with a breakdown voltage of 3.3 kV, the snap voltage becomes equal to Vbi, and in order to eliminate the snapback phenomenon, Wp needs to be approximately 650 micrometers or more. In the case of a breakdown voltage of 15 kV, an even greater increase in Wp is required, so the effect of the present invention, in which the snapback phenomenon can be eliminated with a Wpc of 175 micrometers, is clear.

When a 15 kV-class reverse-conducting SiC-IGBT according to this embodiment is turned on by applying a DC power supply voltage of 5 kV and measuring with a current density of 50 A/cm, the turn-off time is approximately 2.4 μs, which is approximately half that of a SiC-IGBT in the same voltage class. As a result of reducing and speeding up the turn-off time, switching losses can be significantly reduced, resulting in lower losses.

In the snapback phenomenon, Vsb is larger and Isb is smaller as the order decreases, but Vsb decreases and Isb increases as the order increases. On the other hand, on-voltage degradation is a degradation phenomenon specific to bipolar elements such as SiC-IGBTs, and progresses as stacking faults expand due to current stress. Therefore, there is a concern that the stress caused by large Isb associated with higher-order snapback will expand stacking faults further, leading to increased rapid on-voltage degradation. In this embodiment, since there are seven MOSFET surface areas in the standard cell, up to seventh-order snapback can occur.

The application of the above-described pilot function-equipped standard cell significantly reduces the width of the standard cell, significantly increasing the current density of the standard cell and the current density during high-order snapback, raising concerns about the worsening of on-state voltage degradation and rapid on-state voltage degradation. Therefore, the above-described Mach-TEDREC method was applied to conduct current tests and on/off cycle tests to examine the occurrence of on-state voltage degradation and rapid on-state voltage degradation. In both tests, the increase in on-state voltage due to degradation was extremely small, with most devices remaining at 0.2 V or less, the same as that of a Si reverse-conducting IGBT. No significant adverse effects on reliability were observed, confirming high reliability, and the effectiveness of this embodiment is clear.
In addition, in the case of an element in which snapback can be completely eliminated by using a pilot-equipped SiC reverse-conducting IGBT configuration, it is inevitable that higher-order snapback phenomena can also be eliminated. In this case, the test results were similar to those described above, with no significant adverse effect on reliability being observed, confirming high reliability.

As described above, the semiconductor device according to the first embodiment can eliminate or suppress the snapback phenomenon, achieve higher performance through further speed and lower loss, and suppress on-voltage degradation, thereby realizing a highly reliable reverse conducting IGBT 100.

(Embodiment 2)
4 is a cross-sectional view schematically illustrating a SiC reverse conducting IGBT semiconductor device 200 according to a second embodiment. This is a SiC reverse conducting IGBT with a design breakdown voltage of 15 kV. Compared to the semiconductor device of the first embodiment, this device has substantially the same structure as the semiconductor device of the first embodiment, except that the buffer layer is a double buffer layer, the p collector width Wp of the pilot function-equipped standard cell is shortened to reduce the cell width, and one MOSFET surface portion is provided in the standard cell.

In this embodiment, the buffer layer is a double buffer layer, which may be a SiC epitaxial layer or an ion-implanted layer.
The double n-buffer layer has a double structure consisting of a thin, highly-doped first buffer layer 204 in contact with the p-collector and a thick, lightly-doped second buffer layer 205 in contact with the n-drift layer. It is important that the first buffer layer 204 has a thickness and impurity concentration that allows it to be completely depleted when the built-in voltage Vbi is applied, and that the second buffer layer 205 has a thickness and impurity concentration that allows it to be only partially depleted and achieve high lateral resistance. The impurity concentration Nd1 and thickness of the first buffer layer 204 are 1×10 ¹⁶ cm ^-3 and 0.3 micrometers, respectively, and the impurity concentration Nd2 and thickness of the second buffer layer 205 are 1×10 ¹⁵ cm ^-3 and 0.3 micrometers, respectively. It may be 1.5 micrometers. In order to maximize the effect of the double n-buffer layer, it is preferable that the SiC reverse conducting element has a non-punch-through structure, but a punch-through structure is also possible by changing the structural factors of the double n-buffer layer.
The application of a double n-buffer layer significantly reduces the p-collector width of the pilot-function standard cell, eliminating snapback in a small area and creating a larger excess space on the chip compared to a Si reverse-conducting IGBT with the same Vsb and breakdown voltage. Adding multiple pilot-function standard cells to this excess space simultaneously reduces chip size and loss due to reduced on-resistance. Furthermore, by utilizing this excess space to increase the width Wn of the short-circuit portion 203 of the pilot-function standard cell, the reverse-conducting IGBT's inherent carrier removal function during turn-off can be significantly enhanced, thereby reducing switching loss by shortening the turn-off time and achieving lower loss.

5 shows the results of analytical calculation of the relationship between Vsb and p-collector width Wp for this standard cell with pilot IGBT function. The impurity concentration Nd1 and thickness of the first buffer layer 204 are 1×10 ¹⁶ cm ⁻³ and 0.3 μm, respectively, and the thickness of the second buffer layer 205 is The calculation is performed with the impurity concentration Nd2 fixed at 1.5 micrometers and the impurity concentration Nd2 as a parameter. As mentioned above, Vsb at which snapback can be almost eliminated is approximately 4 V, and to achieve this, if the impurity concentration Nd2 is set to 1×10 ¹⁵ cm ^-3 , the collector width Wpc at which Vsb of 3.7 V or less at which snapback is eliminated as mentioned above is 44 micrometers. Note that the width Wn of the n+ short circuit portion 203 may be 8 micrometers, in which case the cell width will be 52 micrometers.
If the chip area of a SiC semiconductor device is 8 mm x 8 mm, the area of the active region is 6 mm x 6 mm. To improve the performance of a SiC semiconductor device, it is preferable to provide as many standard cells with the above-mentioned pilot IGBT function as possible within this limited chip area, as this reduces steady-state on-state loss. In this case, it is preferable to be able to integrate 115 stripe cells in a 6 mm-wide active region.

When a forward voltage is applied between emitter electrode 213 and collector electrode 201 in the absence of a gate voltage to the SiC reverse conducting IGBT according to the second embodiment, a leakage current flows but the device exhibits good forward blocking characteristics, and the breakdown voltage at room temperature for most semiconductor devices, i.e., the voltage at which avalanche breakdown occurs, is around 16.2 kV. The leakage current before avalanche breakdown is good, being 1.5×10 ⁻⁶ A/cm ² or less at room temperature and 2×10 ⁻⁵ A/cm ² or less even at a high temperature of 250°C.
When a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 212, and then a forward voltage is applied between the collector and emitter and increased, a current proportional to the forward voltage flows, and the IGBT turns on at a certain voltage, but no snapback phenomenon is observed, including primary and higher orders, demonstrating the effectiveness of the present invention.
Further increasing the forward voltage causes the current to increase nonlinearly. When the collector-emitter voltage (hereinafter referred to as Vce) is 5 V, Jce is a good 75 A/ ^cm2 .

Furthermore, in order to reduce Vsb of a Si reverse conducting IGBT with a breakdown voltage of 3.3 kV to Vbi (0/7 V) or less, the experimental value of Wp of the pilot IGBT is approximately 650 micrometers or more, and increasing the breakdown voltage further increases Vsb. According to the second embodiment, even though the standard cell has a significantly high breakdown voltage of approximately 15 kV, Wp only needs to be 44 micrometers or more, and a significant reduction can be achieved, demonstrating the effect of the present invention.
By adding multiple standard cells with pilot function in the extra space created by the application of the double n-buffer layer, it is possible to reduce the chip size and loss by reducing the on-resistance at the same time. Also, by utilizing this extra space to increase the width Wn of the short-circuit part 203 of the standard cell with pilot function, it is possible to significantly increase the carrier removal function that is inherent to reverse conducting IGBTs when they are turned off, thereby reducing switching loss by shortening the turn-off time and achieving low loss.

The application of the above-described pilot function-equipped standard cell significantly reduces the width of the standard cell, significantly increasing the current density of the standard cell and the current density during high-order snapback, raising concerns about the worsening of on-voltage degradation and rapid on-voltage degradation. Therefore, the above-described Mach-TEDREC method was applied to conduct current tests and on/off cycle tests to examine the occurrence of on-voltage degradation and rapid on-voltage degradation. However, in both tests, the increase in on-voltage due to degradation was extremely small, with most elements remaining at 0.2 V or less, the same as for Si reverse-conducting IGBTs, and no significant adverse impact on reliability was observed, confirming the effectiveness of this embodiment.

As described above, the semiconductor device according to the second embodiment can eliminate the snapback phenomenon, and can achieve even higher performance through further chip miniaturization, lower loss, and higher speed, while also eliminating the rapid on-voltage degradation associated with high-order snapback, thereby realizing a highly reliable SiC reverse conducting IGBT. Furthermore, the new operating method according to the present invention can eliminate or suppress not only on-voltage degradation but also rapid on-voltage degradation, thereby realizing an even more reliable operating method for a SiC reverse conducting IGBT.

(Embodiment 3)
6 is a cross-sectional view schematically showing a SiC reverse conducting IGBT semiconductor device 300 according to the third embodiment. The SiC reverse conducting IGBT has a design breakdown voltage of 15 kV. Compared to the semiconductor device of the first embodiment,
The structure is almost the same except for the following points: an n-shorting portion is provided only at one end of the standard cell, and one such standard cell is paired with one inverted standard cell, which is inverted around the other end, where the n-shorting portion is not provided, as an inversion axis, to form a hybrid cell configuration, and further, a plurality of MOSFET surface portions of the same size as in embodiment 1 are provided opposite the p-collector of this standard cell.
The present SiC reverse conducting IGBT is characterized by its hybrid cell configuration, which allows the width of the p collector in one cell to be utilized as a collector that is approximately twice as wide as that in the second embodiment, thereby enabling even greater suppression of the snapback phenomenon.

In this embodiment, the MOSFET surface portion closest to the inversion axis in each cell functions as the pilot IGBT. Focusing on this portion allows for efficient use of the full width of the p-collector of the standard cell, significantly suppressing or eliminating snapback. Incidentally, in the case of Figure 6, based on the analysis results of Figure 2, Wp, which can be used to almost completely eliminate snapback when Vsb is set to 3.7 V, is 44 micrometers, and the standard cell width including the n-shorting portions at both ends is 52 micrometers. Meanwhile, because the width of the MOSFET surface portion is 24 micrometers, the number of integrated MOSFET surface portions can be increased to two. As a result, the on-resistance per standard cell can be halved, significantly reducing loss. Furthermore, after the IGBT on the surface of the MOSFET that functions as the pilot IGBT is turned on, the IGBTs on the surface of the other MOSFETs are subsequently turned on, causing a secondary snapback. However, since the Vsb of the IGBTs on the surface of the MOSFET is approximately 3.7V and primary snapback is almost completely eliminated, the Vsb of the secondary snapback is naturally smaller than 3.7V, so the effect does not pose a practical problem.

When a forward voltage is applied between emitter electrode 314 and collector electrode 301 in the absence of a gate voltage, the SiC reverse conducting IGBT according to the third embodiment exhibits good forward blocking characteristics, although leakage current flows, and the breakdown voltage at room temperature, i.e., the voltage at which avalanche breakdown occurs, is approximately 15.5 kV. Furthermore, the leakage current before avalanche breakdown is good, being 3×10 ⁻⁶ A/cm ² or less at room temperature and 3.5×10 ⁻⁵ A/cm ² or less even at a high temperature of 250°C.

When a gate voltage of, for example, 20 V, which is equal to or greater than the threshold voltage is applied to the gate electrode 312, and then a forward voltage is applied between the collector and emitter and increased, a MOSFET current proportional to the forward voltage flows, and the IGBT turns on at a certain voltage, but no snapback phenomenon is observed, including primary and higher orders, demonstrating the effectiveness of the present invention.
As the forward voltage is further increased, the current increases nonlinearly. When the collector-emitter voltage (hereinafter referred to as Vce) is 5 V, Jce is a good 145 A/ ^cm2 .

In the case of the SiC reverse conducting IGBT of this embodiment, Wn is 8 micrometers and the standard cell width is 52 micrometers, which means that Wp and therefore the cell width are much smaller than those of a Si reverse conducting IGBT with a snapback voltage of approximately 4V. Therefore, compared to a 3.3 kV Si reverse conducting IGBT with a low breakdown voltage, the number of cells can be increased by approximately four times for the same chip area, thereby reducing on-resistance and reducing loss. Furthermore, by not increasing the number of standard cells to the maximum, but instead using some of them to increase the Wn width within each cell, the reverse conducting IGBT's inherent ability to remove carriers during turn-off can be enhanced. As a result, turn-off time can be shortened, increasing speed and significantly reducing switching losses, which, combined with the above-mentioned reduction in on-resistance, results in a dramatic overall reduction in loss.

The application of the above-described pilot function-equipped standard cell significantly reduces the width of the standard cell, significantly increasing the current density of the standard cell and the current density during high-order snapback, raising concerns about the worsening of on-voltage degradation and rapid on-voltage degradation. Therefore, the above-described Mach-TEDREC method was applied to conduct current tests and on/off cycle tests to examine the occurrence of on-voltage degradation and rapid on-voltage degradation. However, in both tests, the increase in on-voltage due to degradation was extremely small, with most elements remaining at 0.2 V or less, the same as for Si reverse-conducting IGBTs, and no significant adverse impact on reliability was observed, confirming the effectiveness of this embodiment.

As described above, the semiconductor device according to the third embodiment can eliminate or suppress the snapback phenomenon, and can achieve significantly improved performance through further reduction in loss and increased speed. It can also eliminate or suppress the rapid on-state voltage degradation associated with secondary snapback, thereby achieving a highly reliable SiC reverse conducting IGBT.

While the present invention has been described above based on the first through third embodiments, it is clear to those skilled in the art that the present invention is not limited to these embodiments and can be easily modified and applied in various ways. For example, by changing the numerical values of the structural specifications and expanding the cell structure, it is naturally possible to develop wide-gap semiconductor reverse-conducting IGBTs with low breakdown voltages such as 3 kV or even higher breakdown voltages such as 25 kV. It is also natural that various cell shapes, such as a mesh shape, can be adopted in addition to the stripe shape mentioned above. It is also natural that the present invention can be applied to trench-type IGBTs in addition to the planar-type IGBTs mentioned above. It is also natural that various values can be adopted for the cell width, n-shorting portion width, and p-collector width, depending on the specifications of the reverse-conducting IGBT, other than the values mentioned above. Furthermore, while n-type reverse-conducting SiC-IGBTs have been mentioned, it is also natural that the present invention can be similarly developed for p-type reverse-conducting SiC-IGBTs with different polarities. Furthermore, while reverse conducting SiC-IGBTs have been mentioned, the present invention can also be applied to reverse conducting IGBTs using other wide-gap semiconductors such as GaN or diamond. Furthermore, snapback can also occur in devices other than reverse conducting IGBTs that combine unipolar and bipolar devices, such as reverse conducting IGBTs, such as devices that combine SI transistors and SI thyristors, and JMGBTs that combine accumulation-mode MOSFETs and IGBTs, so it is clear that the present invention can also be applied to counter these situations.

The present invention can be used in high-voltage inverters directly connected to power distribution systems, where it is possible to significantly reduce the size of transformers or even eliminate them entirely, thereby enabling significant system size and weight reduction and energy and resource savings. It can also be used not only in current power distribution systems, but also in smart grids, which are next-generation power grids. Furthermore, by lowering the withstand voltage of semiconductor devices, they can be effectively used in control devices for industrial equipment such as large fans, pumps, and rolling mills, inverters for electric railway vehicles such as bullet trains and subways, and inverters for large EVs and HEVs.

1, 101, 101, 301: Collector electrode 2, 102, 202, 302: p collector layer 3, 103, 203, 303: n ⁺ short circuit portion 4, 104, 204, 304: n buffer layer or first buffer layer 5, 105, 305: n second buffer layer 6, 106, 206, 306: n ^- drift layer 7, 107, 207, 307: p body region 8, 108, 208, 308: n ⁺ emitter region 9, 109, 209, 309: channel region 10, 110, 210, 310: p ⁺ Contact regions 11, 111, 211, 311: Gate oxide films 12, 112, 212, 312: Gate electrodes 13, 113, 213, 313: Emitter electrodes 14, 114, 214, 314: Parasitic JFET portions

Claims (6)

a reverse conducting semiconductor device comprising a standard cell in an active region of a semiconductor element, the standard cell being made of a wide-gap semiconductor, the standard cell having a collector with a collector width Wp derived using a graph relating the snapback voltage Vsb of the snapback phenomenon to the collector width Wp of the standard cell or an analytical method for deriving the graph so that Vsb is approximately equal to a predetermined suppressed Vsb so as to prevent element breakdown even when a steep jump voltage (L·dI/dt) is generated by a parasitic reactor in a circuit using the reverse conducting semiconductor device in which the snapback phenomenon occurs and a large transient phenomenon is induced due to this , and the reverse conducting semiconductor device is characterized in that the standard cell is composed solely of the pilot function-equipped standard cell. The reverse conducting semiconductor device described in [Claim 1] is a reverse conducting IGBT constructed from the wide-gap semiconductor, and the standard cells in the active region of the reverse conducting IGBT are constructed solely from pilot function-equipped IGBT standard cells, which are the pilot function-equipped standard cells. In the reverse conducting semiconductor device described in [Claim 2], the active region of the reverse conducting semiconductor device is composed only of the pilot function-equipped IGBT standard cell, the pilot function-equipped IGBT standard cell has a buffer layer, and the buffer layer has a single structure or a multiple structure of two or more layers. 4. The reverse conducting semiconductor device according to claim 3, wherein a plurality of MOSFET surface portions are provided within the pilot function-equipped IGBT standard cell of the reverse conducting IGBT, and a short circuit portion connecting the buffer layer and a collector electrode of the reverse conducting IGBT is provided at approximately the center of a back surface opposite to the front surface of the pilot function-equipped IGBT standard cell, and the collector having approximately half the width is provided on both ends of the short circuit portion. A reverse conducting semiconductor device according to any one of claims 2 to 4, characterized in that the temperature of the built-in pn junction diode is raised above the degradation suppression temperature specific to the wide-gap semiconductor that is the base material of the reverse conducting semiconductor device by passing a majority carrier current through the MOSFET section, and then the device performs predetermined electrical operations. a reverse conducting semiconductor device comprising a standard cell in an active region of a semiconductor element , the standard cell being made of a wide-gap semiconductor; the standard cell having a collector with a collector width Wp derived using a graph relating the snapback voltage Vsb of the snapback phenomenon to the collector width Wp of the standard cell or an analytical method for deriving the graph so that Vsb is approximately equal to a predetermined suppressed Vsb so as to prevent element breakdown even when a steep jump voltage (L·dI/dt) is generated by a parasitic reactor in a circuit using the reverse conducting semiconductor device in which the snapback phenomenon occurs and a large transient phenomenon is induced as a result; the pilot function-equipped standard cell is a reverse conducting semiconductor device composed only of the pilot function-equipped standard cell; and the reverse conducting semiconductor device is characterized in that the temperature of a built-in pn junction diode is raised to a degradation suppression temperature specific to the wide-gap semiconductor that is the base material of the reverse conducting semiconductor device by passing a majority carrier current through a MOSFET section, and then the reverse conducting semiconductor device performs predetermined electrical operations.