JP7744178B2 - Evaluation methods for ceramic electronic components - Google Patents

Description

The present invention relates to a method for evaluating ceramic electronic components.

Ceramic electronic components such as multilayer ceramic capacitors are used in a variety of devices. High reliability is required for these ceramic electronic components. Ceramic electronic components used in automotive electrical equipment, communication equipment, and other devices require especially high reliability. Measuring long-term reliability under conditions similar to those of actual use requires a long period of time, from several weeks to several months. For this reason, high-temperature accelerated life tests are generally conducted by increasing the voltage and temperature (see, for example, Non-Patent Document 1). However, it is difficult to accurately estimate the life under actual use conditions from the results of high-temperature accelerated life tests. Therefore, attempts have been made to revise life estimation formulas to estimate reliability closer to actual measurement data (see, for example, Non-Patent Document 2).

Highly accelerated lifetesting of base-metal-electrode ceramic chip capacitors, Jonathan L. Paulsen, Eric K. Reed, Microelectronics Reliability, 42, 2002, 815-820 Modified lifetime prediction for multilayer ceramic capacitors based on space charge evolution, Koichiro Morita*, Tetsuo Shimura, Shinichi Abe, and Yukihiro Konishi, Japanese Journal of Applied Physics 57, 11UC03 (2018)

However, it is difficult to accurately evaluate the reliability of long-life ceramic electronic components.

The present invention has been developed in consideration of the above-mentioned problems, and aims to provide a method for evaluating the reliability of ceramic electronic components that can accurately evaluate the reliability of ceramic electronic components.

The reliability evaluation method for ceramic electronic components according to the present invention includes the steps of: extracting a plurality of ceramic electronic components from a population of ceramic electronic components each having a plurality of laminated dielectric layers and a plurality of internal electrode layers, and performing a high-temperature accelerated life test on each of the plurality of ceramic electronic components; identifying IR degradation locations in the dielectric layers where leakage current occurs for a plurality of samples among the plurality of ceramic electronic components whose leakage current exceeds a threshold value in the high-temperature accelerated life test; measuring characteristic values of the IR degradation locations; calculating a voltage acceleration coefficient n from the characteristic values and the IR degradation time from the start of the high-temperature accelerated life test for the plurality of samples until the leakage current exceeds the threshold value; and evaluating the quality of the ceramic electronic components in the population using the voltage acceleration coefficient n.

In the above-described reliability evaluation method for a ceramic electronic component, the characteristic value may be a thickness d _min of the dielectric layer at the IR-deteriorated portion, or a maximum electric flux density D _min at the IR-deteriorated portion.

In the above-mentioned method for evaluating the reliability of ceramic electronic components, the IR degradation time of the ceramic electronic components in the population may be estimated from the voltage acceleration coefficient n and the average thickness of the dielectric layers of the ceramic electronic components in the population, and the quality of the ceramic electronic components in the population may be evaluated from the estimated IR degradation time.

In the above-mentioned method for evaluating the reliability of ceramic electronic components, the ceramic electronic components in the population may be multilayer ceramic capacitors.

In the above-described reliability evaluation method for ceramic electronic components, the characteristic value may be a thickness d _min of the dielectric layer at the occurrence location, and the ceramic electronic components in the population may be evaluated using an IR degradation time t _min from the start of the high-temperature accelerated life test of the plurality of samples until the leakage current exceeds the threshold value, the thickness d _min of the plurality of samples, an average thickness d of the dielectric layer of the ceramic electronic components in the population, and the following formula:

In the reliability evaluation method for ceramic electronic components, the characteristic value is a maximum electric flux density D _min that is a maximum value of the electric flux density on a line passing through a midpoint between the internal electrode layers at the occurrence location, and the ceramic electronic components in the population may be evaluated using an IR degradation time t _min from the start of the high-temperature accelerated life test of the plurality of samples until the leakage current exceeds the threshold value, the maximum electric flux density D _min of the plurality of samples, an average thickness d of the dielectric layer of the ceramic electronic components in the population, and a maximum electric flux density D in the case where it is assumed that there is no occurrence location and the thickness of the dielectric layer at each location is the average thickness d, and the following formula:

In the above-described method for evaluating the reliability of ceramic electronic components, at least one dielectric layer included in each of the ceramic electronic components in the population may be a dielectric layer that is fired in a single container using a common dielectric material produced in the same raw material powder production process.

In the above-described method for evaluating the reliability of ceramic electronic components, at least one dielectric layer included in each of the ceramic electronic components in the population may be a dielectric layer obtained by firing each dielectric green sheet cut from a single dielectric green sheet.

In the above-mentioned method for evaluating the reliability of ceramic electronic components, the ceramic electronic components in the population may be fired in the same furnace at the same time.

The present invention provides a method for evaluating the reliability of ceramic electronic components, which allows for accurate evaluation of the reliability of ceramic electronic components.

FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. 3A and 3B are diagrams illustrating the structure of external electrodes. 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. 1A and 1B are diagrams illustrating a lamination process. FIG. 10 is a flow diagram for firing the external electrodes after firing the laminated chip. FIG. 1 is a flow chart illustrating the procedure of a reliability evaluation method. FIG. 10 is a diagram illustrating the relationship between the HALT test time and the leakage current for each multilayer ceramic capacitor. 4A and 4B are diagrams illustrating defective locations in internal electrode layers; FIG. 10 is a diagram illustrating the layer thickness d _min . 10A and 10B are diagrams illustrating simulation results of maximum electric flux density in the vicinity of a bulge in an internal electrode layer. FIG. 10 is a diagram showing plot results. FIG. 10 is a diagram showing plot results.

The following describes the embodiment with reference to the drawings.

(Structure of multilayer ceramic capacitor)
First, an overview of a multilayer ceramic capacitor, an example of a ceramic electronic component, will be described. FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to a first embodiment. As illustrated in FIG. 1, the multilayer ceramic capacitor 100 includes a rectangular parallelepiped-shaped laminated chip 10 and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom, and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a, 20b are spaced apart from each other.

The multilayer chip 10 is configured by alternately stacking dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material. The edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. This allows each internal electrode layer 12 to be alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 is configured by stacking multiple dielectric layers 11 with the internal electrode layers 12 interposed therebetween. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is disposed as the outermost layer in the stacking direction, and the top and bottom surfaces of the laminate are covered by cover layers 13. The cover layers 13 are primarily composed of a ceramic material. For example, the material of the cover layers 13 may be made of the same primarily ceramic material as the dielectric layers 11.

The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 1.6 mm in length, 0.8 mm in width, and 0.8 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

The internal electrode layers 12 are primarily composed of base metals such as Ni (nickel), Cu (copper), and Sn (tin). Noble metals such as Pt (platinum), Pd (palladium), Ag (silver), and Au (gold), or alloys containing these metals, may also be used as the internal electrode layers 12.

The dielectric layer 11 has a main phase made of a ceramic material having a perovskite structure represented by the general formula _ABO3 . The perovskite structure includes _ABO3-α , which is a non-stoichiometric composition. For example, the ceramic material can be selected from at least one _{of BaTiO3} (barium titanate), _CaZrO3 (calcium zirconate), _CaTiO3 (calcium titanate), _SrTiO3 (strontium titanate), _MgTiO3 (magnesium titanate), and Ba1 _{-x- yCaxSryTi1 - zZrzO3} (0≦x≦1, 0≦ _y ≦1, 0≦z≦1) that form a _perovskite structure. Ba _1-x-y Ca _x Sr _y Ti _1-z Zr _z O ₃ is barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate and barium calcium titanate zirconate, etc.

The external electrodes 20a and 20b are primarily composed of Ni, Cu, or the like. As illustrated in FIG. 2, a plating layer 21 may be provided on the surface of the external electrode 20a. Hatching is omitted in FIG. 2. The plating layer 21 is primarily composed of a metal such as Cu, Ni, Al, Zn, or Sn, or an alloy of two or more of these metals. The plating layer 21 may be a plating layer of a single metal component, or multiple plating layers of different metal components. For example, the plating layer 21 may have a structure in which, from the external electrode 20a side, a first plating layer 22, a second plating layer 23, and a third plating layer 24 are formed. The first plating layer 22 is, for example, a Cu plating layer. The second plating layer 23 is, for example, a Ni plating layer. The third plating layer 24 is, for example, a Sn plating layer. Note that while FIG. 2 illustrates the external electrode 20a, the external electrode 20b also has a similar structure.

Next, we will explain the manufacturing method of the multilayer ceramic capacitor 100. Figure 3 is a diagram illustrating the flow of the manufacturing method of the multilayer ceramic capacitor 100.

(Raw material powder preparation process)
First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are typically contained in the dielectric layer 11 in the form of a sintered body of _ABO3 particles. For example, _BaTiO3 is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This _BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that is the main component of the dielectric layer 11, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

The resulting ceramic powder is then doped with a specific additive compound depending on the intended purpose. Examples of additive compounds include oxides of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), and Yb (ytterbium)), as well as oxides or glasses of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon).

For example, a ceramic material is prepared by wet-mixing a ceramic raw material powder with a compound containing an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as needed to adjust the particle size, or may be combined with a classification process to adjust the particle size. The above process results in a dielectric material. For example, the dielectric material in the amounts required for multiple multilayer ceramic capacitors can be produced in the same process in a single container.

(Lamination process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. Using the obtained slurry, a dielectric green sheet 52 having a thickness of, for example, 4 μm or more is coated on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

Next, as illustrated in FIG. 4( a), a metal conductive paste containing an organic binder for forming internal electrodes is printed on a dielectric green sheet 52 by screen printing, gravure printing, or the like, to form multiple internal electrode patterns 53 spaced apart from one another. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main ceramic component of the dielectric layer 11. For example, _BaTiO3 with an average particle diameter of 50 nm or less may be uniformly dispersed. In FIG. 4( a), as an example, four layers of internal electrode patterns 53 are formed on the dielectric green sheet 52 at predetermined intervals. The dielectric green sheet 52 on which the internal electrode patterns 53 are formed is considered a stacking unit.

Next, while peeling the dielectric green sheet 52 from the substrate 51, a predetermined number of lamination units (e.g., 1 to 100 layers) are stacked so that the internal electrode layers 12 and dielectric layers 11 described in FIG. 1 alternate, and so that the edges of the internal electrode layers 12 are alternately exposed at both longitudinal end faces of the dielectric layers 11 and alternately drawn out to a pair of external electrodes 20a, 20b of opposite polarity, as illustrated in FIG. 4(b). Cover sheets for forming the cover layers 13 are pressure-bonded to the top and bottom of the laminate obtained by stacking the lamination units, and the laminate is then cut to the specified chip dimensions (e.g., 3.2 mm x 1.6 mm).

(Metal paste application process)
The obtained laminate is debindered in an _N2 atmosphere, and then a metal paste containing a metal filler including the main component metal of the external electrodes 20a, 20b, a co-material, a binder, a solvent, etc. is applied to both end faces and each side face of the laminate, and then dried.

(Firing process)
The molded body thus obtained is subjected to a binder removal process in an _N2 atmosphere at 250 to 500°C, and then fired at 1100 to 1300°C for 10 minutes to 2 hours in a furnace in a reducing atmosphere with an oxygen partial pressure of ^10-8 to ^10-13 atm, sintering each particle of the molded body. In this way, a laminated chip 10 having external electrodes 20a, 20b formed thereon is obtained. For example, multiple molded bodies are fired in a single firing process carried out at the same time in a single furnace.

(Reoxidation treatment process)
Thereafter, a re-oxidation treatment is performed in a _N2 gas atmosphere, for example, at 950°C for 2 hours.

(Plating process)
Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, Sn, etc. by plating. Through the above steps, the multilayer ceramic capacitor 100 is completed.

In the manufacturing method shown in Figure 3, the laminated chip 10 and external electrodes 20a, 20b are fired simultaneously, but the external electrodes 20a, 20b may be fired after the laminated chip 10 is fired. Figure 5 is a flow diagram for firing the external electrodes 20a, 20b after firing the laminated chip 10. The same steps as in Figure 3 are followed up to the lamination process.

(Firing process)
The molded body thus obtained is subjected to a binder removal process in an _N2 atmosphere at 250 to 500°C, and then fired at 1100 to 1300°C for 10 minutes to 2 hours in a reducing atmosphere with an oxygen partial pressure of ^10-8 to ^10-13 atm, thereby sintering the particles of the molded body. In this way, the laminated chip 10 is obtained.

(Reoxidation treatment process)
Thereafter, a re-oxidation treatment may be performed in an N ₂ gas atmosphere at 600° C. to 1000° C.

(External electrode formation process)
A metal paste containing metal powder, glass frit, binder, and solvent is applied to both end surfaces of the laminated chip 10 and allowed to dry. The metal paste is then baked, thereby forming the external electrodes 20a, 20b. The binder and solvent evaporate during baking.

(Plating process)
Thereafter, the external electrodes 20a, 20b may be coated with a metal such as Cu, Ni, Sn, etc. by plating. Through the above steps, the multilayer ceramic capacitor 100 is completed.

To evaluate the reliability of the multilayer ceramic capacitor 100 thus completed, a high-temperature accelerated life test is often performed by increasing the voltage or temperature. Because high temperatures and high voltages create a significant gap between these conditions and actual usage conditions, it is highly likely that the mechanism of IR (insulation resistance) reliability degradation will differ from that observed under actual usage conditions. Furthermore, the voltage acceleration coefficient can vary depending on the sample shape and measurement conditions, which can lead to an inaccurate estimation of the lifespan. On the other hand, if the acceleration conditions are weak, it takes a long time (several months) to confirm the degradation behavior, which is not practical. Therefore, the following describes a reliability evaluation method that can accurately evaluate the reliability of the multilayer ceramic capacitor 100.

Figure 6 is a flow diagram illustrating the steps of the reliability evaluation method. The reliability evaluation method will be explained below with reference to Figure 6.

(High temperature accelerated life test process)
A plurality of multilayer ceramic capacitors 100 are randomly selected from a population of multilayer ceramic capacitors 100 and subjected to a high temperature accelerated limit test (HALT) under conditions of constant temperature and constant load voltage. For example, 10 to 50 multilayer ceramic capacitors 100 are subjected to the high temperature accelerated limit test (HALT). In this HALT test, the temperature is lower and the load field strength is smaller than in a typical HALT test. For example, in a typical HALT test, the temperature is often set to 150°C and the load field strength is often set to 25 V/μm or more. Therefore, the temperature is set to a predetermined constant value in the range of 125°C to 150°C, and the load field strength is set to a predetermined constant value in the range of 10 V/μm to 20 V/μm. Alternatively, the temperature is set to a predetermined constant value in the range of 100°C to 125°C, and the load field strength is set to a predetermined constant value in the range of 20 V/μm to 25 V/μm. As an example, the temperature is set to 125° C., the load electric field strength is set to 15 V/μm, and the threshold current is set to 10 μA. The threshold here is set to a value within a range that does not lead to structural destruction.

Figure 7 is a diagram illustrating the relationship between HALT test time and leakage current for each multilayer ceramic capacitor 100. In Figure 7, the horizontal axis represents the time from the start of the HALT test, and the vertical axis represents the leakage current. As illustrated in Figure 7, there is variation in the IR degradation time from the start of the HALT test until the leakage current reaches the threshold current. Specifically, there are cases where the IR degradation time is short and cases where the IR degradation time is long. This is thought to be because the state of the IR degradation areas occurring in the internal electrode layers 12 differs for each multilayer ceramic capacitor 100. Note that because the application of the voltage load was stopped before structural breakdown occurred, no structural breakdown occurred in any of the multilayer ceramic capacitors 100.

(Analysis process of deteriorated parts)
Next, for samples whose leakage current exceeded the threshold current within a predetermined time, IR degradation locations were analyzed. (1) First, one of the external electrodes was removed by polishing, etching, or the like. (2) Next, IR was measured between the remaining external electrode and each internal electrode layer 12 exposed on the end surface where the external electrode had been removed, and the IR degradation layer was identified. If the IR degradation layer was identified, the vicinity of the IR degradation layer was exposed by polishing, etching, or the like. (3) Next, OBIRCH (optical beam heating resistance variation method) was used to identify the IR degradation location within the surface. (4) Next, the IR degradation location was exposed with a focused ion beam (FIB), observed with a scanning electron microscope (SEM), and an SEM image was taken.

IR degradation areas are defects in the internal electrode layers 12. For example, as shown in Figure 8, defects in the internal electrode layers 12 include undulations 61 in the internal electrode layers 12, bulges 62 in the internal electrode layers 12, inflows 63 into voids in the dielectric layer 11, and bends 64 in the internal electrode layers 12. The undulations 61 are areas where the internal electrode layers 12 are not flat but have a wave-like shape. The bulges 62 are areas where the internal electrode layers 12 are thicker than their average thickness. The inflows 63 are branching areas formed when the metal conductive paste for the internal electrode layers flows into voids in the dielectric layer 11. The bends 64 are areas where the internal electrode layers 12 are convex toward the adjacent internal electrode layers 12. At these defect areas, the distance between two adjacent internal electrode layers 12 is shorter, and therefore the thickness of the dielectric layers 11 corresponding to that distance is also smaller.

(Voltage acceleration coefficient estimation process)
(1) Next, the layer thickness d _min of the dielectric layer 11 at the IR degradation location is measured from an SEM image. FIG. 9 shows, as an example, the layer thickness d _min at the IR degradation location where a bulge 62 has occurred. (2) Next, the relationship between the measured layer thickness d _min and the IR degradation time is plotted. In this case, the horizontal axis represents the layer thickness d _min , and the vertical axis represents the IR degradation time. (3) From the plotted diagram and the layer thickness d _min , the voltage acceleration coefficient n is estimated. (4) Next, the estimated voltage acceleration coefficient n is used to estimate the actual IR degradation time.

Here, the estimation of the voltage acceleration coefficient n will be described in detail. First, the relationship shown in the following formula ( ₁ ) is obtained between the IR degradation time _t1 when a HALT test is performed at a voltage _V1 at a predetermined temperature and the IR degradation time _t2 when a HALT test is performed at a voltage V2 at the same temperature. The relationship shown in the following formula (1) is disclosed in Non-Patent Document 1.

The above formula (1) can be rewritten as the following formula (2). In the following formula (2), voltage V represents the load voltage during the HALT test. IR degradation time t represents the IR degradation time when no defective portions as illustrated in FIG. 8 occur and the thickness of each portion of the dielectric layer 11 is layer thickness d, which is the average value (target value) of the dielectric layers 11 of the multilayer ceramic capacitors 100 in the population. Voltage V _min represents the voltage applied to the portion with layer thickness d _min during the HALT test. IR degradation time t _min represents the IR degradation time at the portion with layer thickness d _min .

The above formula (2) can be rewritten as the following formula (3). In the following formula (3), the IR degradation time t _min is the IR degradation time in FIG. 7 measured in the high-temperature accelerated life test process. The layer thickness d _min is obtained from the IR degradation location. The layer thickness d is also obtained because it is a target value. The IR degradation time t is an unmeasured variable. The voltage acceleration coefficient n can be estimated by performing regression analysis or the like using the diagram plotted in the voltage acceleration coefficient estimation process and the following formula (3).

(Step of Estimating IR Deterioration Time)
Once the voltage acceleration coefficient n is estimated, the IR degradation time t at the layer thickness d can be estimated. This IR degradation time t can be evaluated as the original IR degradation time of the population of multilayer ceramic capacitors 100. The estimated IR degradation time t is the time until the threshold current is reached as explained in FIG. 7 . However, since the current exceeds the threshold and continues to rise sharply, leading to breakdown, as illustrated in FIG. 7 , it can also be considered as the lifespan until the multilayer ceramic capacitor is broken.

According to this embodiment, by identifying multiple samples from a population of multilayer ceramic capacitors 100 in which the leakage current exceeded a threshold value within a predetermined time, it is possible to identify samples in which defects have occurred in the internal electrode layers 12. Furthermore, by extracting multiple samples in which the leakage current exceeded a threshold value within a predetermined time, it is possible to extract samples before structural breakdown. Since no structural breakdown has occurred, it is possible to identify IR degradation locations through analysis and measure the layer thickness d _min of the dielectric layer 11 at the IR degradation locations. By measuring the layer thickness d min of the multiple samples, it is possible to estimate the voltage acceleration coefficient n using the above formula (3). Estimating the voltage acceleration coefficient n makes it possible to evaluate the actual IR degradation time in the population of multilayer ceramic capacitors 100. Therefore, it is possible to accurately evaluate the reliability of the population of multilayer ceramic capacitors 100.

The lifetime of ceramic capacitors 100 is more likely to be similar within the same production lot than across different production lots. Therefore, it is preferable to define a group of multilayer ceramic capacitors manufactured in the same production lot as a population and extract multiple multilayer ceramic capacitors 100 from that population. For example, a group of multilayer ceramic capacitors manufactured in the same production lot is preferably multiple multilayer ceramic capacitors made using dielectric material produced in the same raw powder production process in a single container. This is because slight differences in the particle size and particle size distribution contained in the dielectric material may occur each time the dielectric material is produced. Alternatively, a group of multilayer ceramic capacitors manufactured in the same production lot is preferably multiple multilayer ceramic capacitors obtained from the same dielectric green sheet 52 described in Figure 4(a). This is because slight differences in sheet thickness, etc. may occur between different dielectric green sheets. Alternatively, a group of multilayer ceramic capacitors manufactured in the same production lot is preferably multiple multilayer ceramic capacitors obtained through a single firing process performed at the same time in a single furnace. This is because each time the firing process is performed, differences in the oxygen partial pressure inside the furnace may occur, which could result in differences in the reduction state of the dielectric (amount of oxygen vacancies).

(Modification)
The maximum electric flux density tends to be large at defective portions of the internal electrode layers 12. Fig. 10 is a diagram illustrating simulation results of the maximum electric flux density in the vicinity of the bulge 62 of the internal electrode layers 12. In Fig. 10, the lighter the color, the larger the electric flux density. The voltage acceleration coefficient n may be estimated by focusing on this maximum electric flux density.

For example, the above formula (1) can be rewritten as the following formula (4). In the following formula (4), the maximum electric flux density D represents the maximum electric flux density when no defects such as those illustrated in FIG. 8 occur and the thickness of each location of the dielectric layer 11 is the layer thickness d, which is the target value for the dielectric layer 11. The maximum electric flux density D _min is determined by calculating the electric flux density on a line passing through the midpoint between the internal electrode layers in the portion of the layer thickness d _min , and taking the maximum value as D _min . Furthermore, assuming that the dielectric layer is an insulator having a dielectric constant of 3000, that the insulator is sandwiched between the internal electrode layers, and that a voltage of 5 V is applied, D _min can be calculated by electromagnetic field simulation. The IR degradation time t represents the IR degradation time when no defects such as those illustrated in FIG. 8 occur and the thickness of each location of the dielectric layer 11 is the layer thickness d, which is the target value for the dielectric layer 11. The IR degradation time t _min represents the IR degradation time at the portion of layer thickness d _min , and is the IR degradation time shown in Fig. 7 measured in the high-temperature accelerated life test process. Therefore, the voltage acceleration coefficient n can be estimated by performing regression analysis or the like using a graph plotting the relationship between the maximum electric flux density D _min and the IR degradation time t _min and the following equation (4).

The voltage applied to the dielectric layer 11 is not determined solely by the thickness of the dielectric layer 11, but is also affected by the shape, etc. On the other hand, the maximum electric flux density D _min at the d _min portion takes these factors into consideration, and therefore it is believed that reliability can be predicted with higher accuracy.

In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but this is not limiting. For example, other electronic components such as a varistor or a thermistor may also be used.

The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were investigated.

Example 1
In Example 1, the target thickness of the internal electrode layers 12 was 1.0 μm, and the target thickness of the dielectric layers 11 was 3.0 μm. The number of stacked internal electrode layers 12 was 10. The size of the obtained multilayer ceramic capacitor was 3.2 mm in length, 1.6 mm in width, and 0.6 mm in height. As a group of multilayer ceramic capacitors manufactured in the same production lot, a plurality of multilayer ceramic capacitors obtained through a single firing process carried out in one furnace at the same time were used.

100 samples were selected from a group of multilayer ceramic capacitors manufactured in the same production lot and subjected to a high-temperature accelerated life test. The temperature was 150°C, the load voltage was 15 V/μm, and the threshold current was 10 μA. Samples whose leakage current exceeded the threshold current within 2,300 min were analyzed for IR degradation locations. First, one of the external electrodes was removed by polishing, etching, etc. Next, the IR between the remaining external electrode and each internal electrode layer 12 exposed on the end surface where the external electrode was removed was measured to identify the IR-degraded layer. If the IR-degraded layer was identified, the area near the IR-degraded layer was exposed by polishing, etching, etc. Next, OBIRCH was used to identify the IR-degraded location within the surface. Next, the IR-degraded location was exposed using an FIB and observed with an SEM, and SEM images were taken.

Next, the layer thickness d _min of the dielectric layer 11 at the IR degradation location was measured using an SEM image. The results are shown in Table 1. Next, the relationship between the measured layer thickness d _min and the IR degradation time t _min was plotted. FIG. 11 shows the plotted results. From the plotted diagram and the layer thickness d min, the voltage acceleration coefficient n was estimated using the above formula (3). The estimated voltage acceleration coefficient n was 3.6621. Since the voltage acceleration coefficient obtained from the results of high-temperature accelerated life tests requiring several hundred hours for other multilayer ceramic capacitors using the same material and having the same shape was 3 to 4, the results of Example 1 can be said to be reasonable. Next, the IR degradation time t was calculated using the estimated voltage acceleration coefficient n. The calculated IR degradation time was 76,518 min.

Example 2
In Example 2, the firing temperature was 10°C higher than in Example 1. Other conditions were the same as in Example 1. Analysis was performed using the same method as in Example 1. The analysis results are shown in Table 2. Next, the relationship between the measured layer thickness d _min and the IR degradation time t _min was plotted. FIG. 12 shows the plot results. From the plotted diagram and the layer thickness d min, the voltage acceleration coefficient n was estimated using the above formula (3). The estimated voltage acceleration coefficient n was 3.8085. Next, the IR degradation time t was calculated using the estimated voltage acceleration coefficient n. The calculated IR degradation time was 133,356 min.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as set forth in the claims.

REFERENCE SIGNS LIST 10 Multilayer chip 11 Dielectric layer 12 Internal electrode layer 13 Cover layer 20a, 20b External electrode 21 Plating layer 22 First plating layer 23 Second plating layer 24 Third plating layer 51 Substrate 52 Dielectric green sheet 53 Internal electrode pattern 61 Waviness 62 Bulge 63 Flow 64 Bending 100 Multilayer ceramic capacitor

Claims (9)

a step of extracting a plurality of ceramic electronic components from a population of ceramic electronic components each including a plurality of dielectric layers and a plurality of internal electrode layers stacked thereon, and performing a high-temperature accelerated life test on each of the ceramic electronic components;
identifying an IR degradation location in the dielectric layer where leakage current has occurred in a plurality of samples of the plurality of ceramic electronic components whose leakage current has exceeded a threshold value in the high-temperature accelerated life test;
measuring a characteristic value of the IR degradation portion;
calculating a voltage acceleration coefficient n from the characteristic value and an IR degradation time from the start of the high-temperature accelerated life test of the plurality of samples until the leakage current exceeds the threshold value;
and evaluating the quality of the ceramic electronic components in the population using the voltage acceleration coefficient n. 2. The method for evaluating a ceramic electronic component according to claim 1, wherein the characteristic value is a thickness d _min of the dielectric layer at the IR-deteriorated portion or a maximum electric flux density D _min at the IR-deteriorated portion. The method for evaluating ceramic electronic components described in claim 1 or 2, characterized in that the IR degradation time of the ceramic electronic components in the population is estimated from the voltage acceleration coefficient n and the average thickness of the dielectric layers of the ceramic electronic components in the population, and the quality of the ceramic electronic components in the population is evaluated from the estimated IR degradation time. The method for evaluating ceramic electronic components described in any one of claims 1 to 3, characterized in that the ceramic electronic components in the population are multilayer ceramic capacitors. the characteristic value is the thickness d _min of the dielectric layer at the IR degradation location ,
5. The method for evaluating a ceramic electronic component according to claim 1, wherein the ceramic electronic components in the population are evaluated using an IR degradation time t _min from the start of the high-temperature accelerated life test of the plurality of samples until the leakage current exceeds the threshold value, the thicknesses d _min of the plurality of samples, an average thickness d of the dielectric layers of the ceramic electronic components in the population, and the following formula:
the characteristic value is a maximum electric flux density D _min that is a maximum value of the electric flux density on a line passing through a midpoint between the internal electrode layers at the IR deterioration location ,
5. The method for evaluating a ceramic electronic component according to claim 1, wherein the ceramic electronic components in the population are evaluated using an IR degradation time t _min from the start of the high-temperature accelerated life test of the plurality of samples until the leakage current exceeds the threshold value, the maximum electric flux density D _min of the plurality of samples, an average thickness d of the dielectric layer of the ceramic electronic components in the population, and a maximum electric flux density D in a case where it is assumed that there is no IR-degraded portion and the thickness of each portion of the dielectric layer is the average thickness d, and the following formula:
A method for evaluating ceramic electronic components according to any one of claims 1 to 6, characterized in that at least one dielectric layer included in each of the ceramic electronic components in the population is a dielectric layer that is fired in a single container using a common dielectric material produced using the same raw material powder production process. 7. The method for evaluating a ceramic electronic component according to claim 1, wherein at least one dielectric layer included in each of the ceramic electronic components in the population is obtained by firing each dielectric green sheet cut from a single dielectric green sheet . 7. The method for evaluating a ceramic electronic component according to claim 1, wherein the ceramic electronic components in the population are fired in a single furnace at the same time.