JP7745510B2 - Verification pattern check device and program - Google Patents

Description

This disclosure relates to a verification pattern check device and program.

Verification patterns written in a hardware description language (HDL) are used to detect faults in logic circuits such as semiconductor integrated circuits. The verification patterns are input to the input terminals of the logic circuit, and fault detection in the logic circuit is performed based on the results of comparing the output state from the logic circuit's output terminals with the expected output pattern corresponding to the verification pattern. However, when using verification patterns to detect faults in logic circuits, if the number of input terminals of the logic circuit being detected increases, the number of verification patterns required to test the logic circuit also increases. For this reason, it is necessary to inspect the verification patterns used to detect faults in logic circuits.

For example, Patent Document 1 describes a verification method in which a verification pattern is executed step by step in a logic simulation, and when the logical state of a net within a logic circuit changes, it determines whether the change in logical state is observable at the output terminal of the logic circuit, and counts up the number of valid toggles for that net only if it is determined that the change is observable. This verification method can effectively evaluate the fault detection capability of a verification pattern by obtaining verification results that primarily consist of the number of valid toggles for each net within the logic circuit.

Patent No. 2642250

Conventional verification methods have the problem of being unable to check the verification purpose of a verification pattern. Here, the verification purpose is information that indicates the function of the logic circuit being verified, and the verification pattern is created with content that is in line with the verification purpose. However, since a large number of verification patterns are generally used to verify logic circuits, and the logic circuit design and verification pattern generation are often performed separately, it has been difficult to check which verification purpose a verification pattern corresponds to.

The present disclosure aims to solve the above problem by providing a verification pattern checking device and program that can check the verification purpose of a verification pattern.

The verification pattern checking device according to the present disclosure includes a signal extraction unit that extracts signal names for each module from the circuit description of a verification pattern written in HDL; a counter generation unit that generates a counter that counts the toggle amount of the signal for the signal name; a module identification unit that identifies, as a module to be verified, a module whose counter value satisfies a first discrimination condition when the verification pattern is executed; a signal identification unit that identifies signal names in the module to be verified whose counter value satisfies a second discrimination condition; a keyword extraction unit that extracts a first keyword corresponding to the identified signal name from a comment field in the circuit description and extracts a second keyword corresponding to the first keyword from verification specification information that describes the specifications of the verification pattern; and a verification purpose identification unit that identifies the verification purpose of the verification pattern using the first keyword and the second keyword.

According to the present disclosure, signal names are extracted for each module from the circuit description of a verification pattern; a module whose counter value of the signal toggle amount when the verification pattern is executed satisfies a first judgment condition is identified as a module to be verified; signal names whose counter values in the module to be verified satisfy a second judgment condition are identified; a first keyword corresponding to the identified signal name is extracted from the comment field of the circuit description; a second keyword corresponding to the first keyword is extracted from the verification specification information; and the verification purpose of the verification pattern is identified using the first keyword and the second keyword. This allows a verification pattern checking device according to the present disclosure to check the verification purpose of a verification pattern.

1 is a block diagram showing a configuration of a logic verification system according to a first embodiment; 1 is a block diagram showing a configuration of a verification pattern check device according to a first embodiment; 4 is a flowchart showing the operation of the verification pattern check device according to the first embodiment; FIG. 10 is a diagram showing signal names of each module in the circuit description of the verification pattern. FIG. 10 is a diagram illustrating an outline of a process for counting the toggle amount of a signal indicated by a signal name. FIG. 10 is a diagram illustrating an outline of a process for identifying a verification target function, which is a verification objective. 1 is a block diagram showing a hardware configuration for realizing the functions of a verification pattern check device according to a first embodiment;

Embodiment 1.
FIG. 1 is a block diagram showing the configuration of a logic verification system 1 according to a first embodiment. In FIG. 1, the logic verification system 1 is a system for verifying the function and timing of a logic circuit, and includes a verification pattern check device 2, a storage unit 3, and a logic simulator 4. The verification pattern check device 2 checks the verification purpose of verification patterns used to verify the logic circuit. The verification patterns are files written in HDL and are used to verify the logic circuit hardware. The verification patterns are also called test benches. The storage unit 3 stores a large number of verification patterns used to verify the logic circuit. The logic simulator 4 inputs the verification patterns into a model that simulates the logic circuit hardware to be verified, observes the response of the logic circuit, and verifies the operation of the logic circuit.

Logic circuit verification using the logic simulator 4 includes RTL (Register Transfer Level) verification. For example, the logic circuit and verification patterns are written in Verilog-HDL, and RTL verification is performed. A typical logic circuit is verified using a large number of verification patterns, on the order of 1,000 to 2,000. Each verification pattern is created based on the verification objectives described in the verification specifications.

However, in reality, the procedure for creating verification specifications is sometimes simplified to reduce the man-hours required for creating them. However, if this simplification is excessive, the verification specifications may not clearly state the purpose of the verification. This is particularly true in development where previously developed products are reused in the development of a new product. When the purpose of the verification is not clearly stated, it is often unclear what verification purpose the verification pattern corresponds to. In light of this situation, the verification pattern checking device 2 checks the verification purpose of the verification pattern while the logic simulator 4 is executing the verification pattern to verify the logic circuit. This makes it possible to check whether the verification pattern complies with the verification specifications, improving the reliability of logic verification.

Figure 2 is a block diagram showing the configuration of the verification pattern check device 2 according to the first embodiment. As shown in Figure 2, the verification pattern check device 2 includes a signal extraction unit 21, a counter generation unit 22, a module identification unit 23, a signal identification unit 24, a keyword extraction unit 25, and a verification objective identification unit 26. The signal extraction unit 21 extracts signal names for each module from the circuit description of a verification pattern written in HDL. A verification pattern written in HDL has a basic structure of modules. In Verilog-HDL, a module has the reserved word "module" written on the first line and "endmodule" written on the last line, with the contents of the module written between "module" and "endmodule."

The declaration section follows the first line, "module." The declaration section is where the signals used within the module are declared. The declaration section includes input/output declarations, net declarations, and variable declarations. The input/output declaration defines the input or output direction, data type, bit width, and terminal name. The net declaration declares the nets used in the circuit description, and includes a wire declaration. The wire declaration specifies the signal names of internal wiring signals. The variable declaration declares signals that hold values such as flip-flops or latches, and includes a reg declaration. The reg declaration specifies the signal name of the signal that holds the value of a register.

As a pre-processing step before a verification pattern is executed, the signal extraction unit 21 extracts signal names from the declaration section in the circuit description of the verification pattern. For example, for each module, the signal extraction unit 21 extracts signal names from at least one data type: input/output declaration, wire declaration, or reg declaration. This allows the signal names of signals used in the circuit description of the verification pattern to be accurately extracted for each module.

The counter generation unit 22 generates a counter that counts the amount of toggling of a signal with a signal name extracted by the signal extraction unit 21. For example, as a pre-processing step before the verification pattern is executed, the counter generation unit 22 automatically generates a counter that uses the signal with the signal name extracted by the signal extraction unit 21 as its clock. The counter is synchronized with the clock and counts the amount of toggling, which is a change in the clock's logical state (a transition between 0 and 1). Furthermore, a counter is generated for each module and signal name, and begins counting when the verification pattern is executed.

The module identification unit 23 identifies a module whose counter value when the verification pattern is executed satisfies a first judgment condition as a module to be verified. For example, the module identification unit 23 acquires the counter value for each signal name from when the logic simulator 4 starts to when it finishes executing the verification pattern, and identifies a module whose acquired counter value satisfies the first judgment condition as a module to be verified.

For example, the first discrimination condition is that the module containing the signal name with the largest counter value be the module to be verified. In this case, the module identification unit 23 compares the counter values for each signal name within a module and between modules to determine the module containing the signal name with the largest counter value and identify that module as the module to be verified. This allows the module identification unit 23 to accurately identify the module to be verified.

The first discrimination condition may also be a condition for determining, as a module to be verified, a module that includes a signal name whose counter value is equal to or greater than a predetermined first threshold. The first threshold is a threshold related to the counter value. In this case, the module identification unit 23 compares the counter value for each signal name with the first threshold within the module and between modules, determines modules that include signal names whose counter value is equal to or greater than the first threshold, and identifies the resulting module as a module to be verified. This allows the module identification unit 23 to accurately identify modules to be verified.

Furthermore, the first discrimination condition may be a condition for determining, as a module to be verified, a module containing a signal name whose counter value is equal to or greater than a predetermined first threshold. In this case, the module identification unit 23 compares the counter value for each signal name with the first threshold within the module and between modules, determines modules containing signal names whose counter value is equal to or greater than the first threshold, and identifies the resulting module as a module to be verified. This allows the module identification unit 23 to accurately identify modules to be verified.

The first discrimination condition may be a condition for determining, as a module to be verified, a module for which the number of signal names for which the counter value is equal to or greater than a first threshold is equal to or greater than a second threshold. The second threshold is a threshold related to the number of signal names. In this case, the module identification unit 23 compares the counter value for each signal name with the first threshold within the module and between modules, and identifies the number of signal names for which the counter value is equal to or greater than the first threshold. The module identification unit 23 then compares the identified number of signal names with the second threshold, and determines modules including signal names for which the number of signal names for which the counter value is equal to or greater than the first threshold is equal to or greater than the second threshold, and identifies the determined modules as modules to be verified. This allows the module identification unit 23 to accurately identify modules to be verified.

The larger the counter value of the toggle amount of a signal, the more likely it is that a module containing a signal name corresponding to this counter value is a module to be verified in the verification pattern. The first discrimination condition is a conditionalization of this characteristic.
The module specifying unit 23 may specify one verification target module or may specify multiple verification target modules.

The signal identification unit 24 identifies the signal name whose counter value in the module to be verified satisfies a second determination condition. For example, the second determination condition is a condition that determines the signal name whose counter value is the largest in the module to be verified. In this case, the signal identification unit 24 compares the counter values for each signal name within the module to be verified and determines the signal name whose counter value is the largest.

The signal with the largest counter value is activated by executing the verification pattern, and is therefore likely to be related to the function being verified. The second discrimination condition is a condition based on this characteristic.

The second discrimination condition may also be to determine signal names in the module to be verified whose counter values are equal to or greater than a first threshold. In this case, the signal identification unit 24 identifies multiple signal names as signal names related to the function to be verified when the counter values corresponding to multiple signal names in the module to be verified are equal to or greater than the first threshold.

The keyword extraction unit 25 extracts a first keyword corresponding to the signal name identified by the signal identification unit 24 from the comment field of the circuit description of the verification pattern, and extracts a second keyword corresponding to the first keyword from the verification specification information. The comment field in the circuit description of the verification pattern is a comment field where an explanation of the signal name is written. For example, it is a description field starting with "//" at the end of each line of the circuit description and extending to the end of the line, and text information can be written there.

The first keyword is text information indicating the signal name identified by the signal identification unit 24. Since the signal name identified by the signal identification unit 24 is likely to be related to the function to be verified, the first keyword indicating this signal name is related to the function to be verified. The comment field of the circuit description contains the specific signal name identified by the signal identification unit 24. If the signal name of the signal that holds the value of register A is "regA", the comment field of the circuit description contains text information such as "register A", for example.

If the comment field in the circuit description corresponding to the signal name identified by the signal identification unit 24 is blank, the keyword extraction unit 25 may extract the first keyword from the design document information of the logic circuit. The design document information of the logic circuit is an electronic file that describes the design details of the logic circuit to be verified, and is stored in the storage unit 3 in association with the logic circuit. For example, if the comment field in the circuit description corresponding to the signal name identified by the signal identification unit 24 is blank, the keyword extraction unit 25 searches the design document information stored in the storage unit 3 using the signal name as a search word to extract the first keyword.

Verification specification information is an electronic file that describes the specifications of a verification pattern and is stored in the storage unit 3 in association with the verification pattern. For example, the keyword extraction unit 25 reads the verification specification information corresponding to the verification pattern from the storage unit 3 and searches for verification items in the verification specification information using the first keyword. When the keyword extraction unit 25 identifies a verification item that includes the first keyword from the verification specification information, it extracts a second keyword from the content of the identified verification item.

The second keyword is information written in the verification item corresponding to the first keyword in the verification specification information. For example, the verification item contains more specific information related to the function to be verified than the first keyword. If the first keyword is "A register," the verification item contains specific content related to the function to be verified, such as "check the value of A register."

The verification purpose identification unit 26 identifies the verification purpose of the verification pattern using the first keyword and the second keyword. For example, the verification purpose identification unit 26 outputs text information using the first keyword and the second keyword as information indicating the verification purpose of the verification pattern. The text information includes either the first keyword or the second keyword, or a combination of both.

The verification purpose identification unit 26 may also generate new text information including the first keyword and the second keyword. The information indicating the verification purpose of the verification pattern may be, for example, display control information for display on a display device not shown in Figures 1 and 2. The verification worker can understand the verification purpose of the verification pattern by referring to the information displayed on the display device.

FIG. 3 is a flowchart showing the operation of the verification pattern check device 2.
The signal extraction unit 21 extracts signal names for each module from the circuit description of the verification pattern (step ST1). Figure 4 shows the signal names of each module in the circuit description of the verification pattern. In Figure 4, the circuit description of the verification pattern describes module (1), module (2), and module (3).

Module (1) contains the signal names regA, regB, regC, wireD, wireE, and wireF. Module (2) contains the signal names regG, regH, wireI, and wireJ. Furthermore, module (3) contains the signal names regK, regL, regM, wireN, wireP, and wireQ.

The signal extraction unit 21 extracts regA, regB, regC, wireD, wireE, and wireF from module (1), extracts regG, regH, wireI, and wireJ from module (2), and extracts regK, regL, regM, wireN, wireP, and wireQ from module (3). The signal names extracted by the signal extraction unit 21 from the circuit description are output to the counter generation unit 22.

The counter generation unit 22 generates counters that count the toggle amounts of signals with the signal names extracted by the signal extraction unit 21 (step ST2). For example, the counter generation unit 22 generates counters for regA, regB, regC, wireD, wireE, and wireF in module (1), counters for regG, regH, wireI, and wireJ in module (2), and counters for regK, regL, regM, wireN, wireP, and wireQ in module (3). This is the pre-processing.
Next, the logic simulator 4 executes the verification pattern and starts verifying the logic circuit.

The module identification unit 23 identifies, as a module to be verified, a module whose counter value when the verification pattern is executed satisfies the first judgment condition (step ST3). Figure 5 is a diagram showing an overview of the process of counting the toggle amount of a signal indicated by a signal name. When execution of the verification pattern is complete, the counter value of module (1) counter is "50" for regA, "2" for regB, "0" for regC, "8" for wireD, "0" for wireE, and "0" for wireF. The total counter value of module (1) is "60".

When the execution of the verification pattern is complete, the counter value of module (2) counter is "0" for regG, "0" for regH, "0" for wireI, and "0" for wireJ. The sum of the counter values of module (2) is "0".

When execution of the verification pattern is complete, the counter value of module (3) counter is "1" for regK, "0" for regL, "0" for regM, "1" for wireN, "0" for wireP, and "0" for wireQ. The total counter value of module (3) is "2".

When the first judgment condition is a condition that the module to be verified is the module with the largest sum of counter values corresponding to signal names, the module identification unit 23 identifies module (1) with the largest sum of counter values corresponding to signal names, "60," as the module to be verified. The module identification unit 23 outputs information indicating the module to be verified to the signal identification unit 24.

The signal identification unit 24 identifies the signal name whose counter value in the module to be verified satisfies the second judgment condition (step ST4). FIG. 6 is a diagram showing an overview of the process of identifying the verification target function, which is the purpose of verification. If the second judgment condition is a condition to extract the signal name whose counter value in the module to be verified is the largest, the signal identification unit 24 identifies the signal name "regA" whose counter value is "50", as shown in FIG. 6. If the second judgment condition is a condition to extract the signal name whose counter value in the module to be verified is equal to or greater than a first threshold value (e.g., 8), the signal identification unit 24 identifies the signal name "regA" whose counter value is "50" and the signal name "wireD" whose counter value is "8".

The keyword extraction unit 25 extracts a first keyword corresponding to the identified signal name from the comment field 10 of the circuit description, and extracts a second keyword corresponding to the first keyword from the verification specification information 30 (step ST5). For example, if the signal identification unit 24 identifies the signal name "regA" with the largest counter value, the keyword extraction unit 25 extracts "A register" as the first keyword from the comment field 10 of the circuit description for the signal name "regA." Next, the keyword extraction unit 25 identifies verification items 11 that include the first keyword "A register" from the verification specification information 30, and extracts the second keyword "A register check" from the content of the identified verification item 11.

The verification purpose identification unit 26 identifies the verification purpose of the verification pattern using the first keyword and the second keyword (step ST6). For example, the verification purpose identification unit 26 uses the first keyword "A register" and the second keyword "A register confirmation" to generate text information "Verification to confirm the operation of register A," and outputs this as information indicating the verification purpose of the verification pattern.

The verification purpose identification unit 26 also identifies the verification purpose for each module and identifies the verification procedure for the verification pattern from the transition of the counter value. For example, the verification purpose identification unit 26 can identify the transition of the verification purpose within the verification pattern, i.e., the verification procedure for one verification pattern, by identifying the verification purpose according to the counter value when execution of one verification pattern is completed. Furthermore, the verification purpose identification unit 26 can also identify the verification procedure for each verification pattern by identifying the verification purpose according to the counter value for each verification pattern.
This allows the verification pattern check device 2 to check the verification procedure in addition to the verification purpose of each verification pattern.

The hardware configuration for realizing the functions of the verification pattern check device 2 will be described.
The functions of the signal extraction unit 21, counter generation unit 22, module identification unit 23, signal identification unit 24, keyword extraction unit 25, and verification purpose identification unit 26 included in the verification pattern check device 2 are realized by processing circuits. That is, the verification pattern check device 2 includes a processing circuit for executing the processes of steps ST1 to ST6 shown in Fig. 3. The processing circuit may be dedicated hardware, or may be a CPU (Central Processing Unit) that executes a program stored in a memory.

Figure 7 is a block diagram showing the hardware configuration that realizes the functions of the verification pattern check device 2. In Figure 7, the input interface 100 is an interface that relays information output from the storage unit 3 and logic simulator 4 to the verification pattern check device 2. The output interface 101 is an interface that relays test results and the like output from the verification pattern check device 2 to the storage unit 3.

When the processing circuit is the processor 102 shown in FIG. 7, the functions of the signal extraction unit 21, counter generation unit 22, module identification unit 23, signal identification unit 24, keyword extraction unit 25, and verification purpose identification unit 26 provided in the verification pattern check device 2 are realized by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in memory 103.

By reading and executing programs stored in memory 103, processor 102 realizes the functions of signal extraction unit 21, counter generation unit 22, module identification unit 23, signal identification unit 24, keyword extraction unit 25, and verification purpose identification unit 26 provided in verification pattern check device 2. For example, verification pattern check device 2 includes memory 103 that stores programs that, when executed by processor 102, result in the processing of steps ST1 to ST6 shown in FIG. 3 being executed. These programs cause a computer to execute the procedures or methods of the processing performed by signal extraction unit 21, counter generation unit 22, module identification unit 23, signal identification unit 24, keyword extraction unit 25, and verification purpose identification unit 26. Furthermore, memory 103 may be a computer-readable storage medium that stores programs that cause a computer to function as signal extraction unit 21, counter generation unit 22, module identification unit 23, signal identification unit 24, keyword extraction unit 25, and verification purpose identification unit 26.

Memory 103 may be, for example, non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), or EEPROM (Electrically-EPROM), as well as magnetic disks, flexible disks, optical disks, compact disks, minidisks, and DVDs.

Some of the functions of the signal extraction unit 21, counter generation unit 22, module identification unit 23, signal identification unit 24, keyword extraction unit 25, and verification purpose identification unit 26 provided in the verification pattern check device 2 may be realized by dedicated hardware, and other functions may be realized by software or firmware. For example, the signal extraction unit 21 is realized by a processing circuit that is dedicated hardware, and the counter generation unit 22, module identification unit 23, signal identification unit 24, keyword extraction unit 25, and verification purpose identification unit 26 are realized by the processor 102 reading and executing programs stored in memory 103. In this way, the processing circuit can realize the above functions by hardware, software, firmware, or a combination of these.

As described above, the verification pattern checking device 2 according to the first embodiment includes a signal extraction unit 21 that extracts signal names for each module from the circuit description of the verification pattern; a counter generation unit 22 that generates a counter that counts the toggle amount of the signal for the signal name; a module identification unit 23 that identifies, as a module to be verified, a module whose counter value satisfies a first judgment condition when the verification pattern is executed; a signal identification unit 24 that identifies a signal name in the module to be verified whose counter value satisfies a second judgment condition; a keyword extraction unit 25 that extracts a first keyword corresponding to the identified signal name from the comment field of the circuit description and extracts a second keyword corresponding to the first keyword from the verification specification information; and a verification purpose identification unit 26 that identifies the verification purpose of the verification pattern using the first keyword and the second keyword. This enables the verification pattern checking device 2 to check the verification purpose of the verification pattern.

In the verification pattern check device 2 according to the first embodiment, the signal extraction unit 21 extracts signal names from the declaration section in the circuit description. This allows the signal extraction unit 21 to accurately extract, for each module, the signal names of signals used in the circuit description of the verification pattern.

In the verification pattern check device 2 according to the first embodiment, the module identification unit 23 identifies the module containing the signal name with the largest counter value as the module to be verified. This allows the module identification unit 23 to accurately identify the module to be verified.

In the verification pattern check device 2 according to the first embodiment, the module identification unit 23 identifies, as a module to be verified, a module that includes a signal name whose counter value is equal to or greater than a predetermined first threshold. This allows the module identification unit 23 to accurately identify the module to be verified.

In the verification pattern check device 2 according to the first embodiment, the module identification unit 23 identifies, as a module to be verified, a module for which the number of signal names for which the counter value is equal to or greater than the first threshold is equal to or greater than a predetermined second threshold. This allows the module identification unit 23 to accurately identify the module to be verified.

In the verification pattern check device 2 according to the first embodiment, the keyword extraction unit 25 extracts the first keyword corresponding to the signal name with the largest counter value from the comment field of the circuit description. This allows the keyword extraction unit 25 to accurately extract the first keyword related to the verification purpose of the module to be verified.

In the verification pattern check device 2 according to the first embodiment, the keyword extraction unit 25 extracts, from the comment field of the circuit description, a first keyword corresponding to the name of a signal whose counter value is equal to or greater than a predetermined first threshold. This enables the keyword extraction unit 25 to accurately extract a first keyword related to the verification purpose of the module to be verified.

In the verification pattern check device 2 according to embodiment 1, the verification purpose identification unit 26 identifies the verification purpose for each module and identifies the verification procedure for the verification pattern from the transition of the counter value. This allows the verification pattern check device 2 to confirm the verification procedure in addition to the individual verification purposes of the verification pattern.

The program according to the first embodiment causes a computer to function as a verification pattern check device 2, and can provide a verification pattern check device that can check the verification purpose of a verification pattern.

Various aspects of the present disclosure are summarized below as appendices.
(Appendix 1)
a signal extraction unit that extracts signal names for each module from a circuit description of a verification pattern written in a hardware description language;
a counter generating unit that generates a counter that counts the toggle amount of the signal having the signal name;
a module identification unit that identifies a module as a verification target module, the module having a counter value that satisfies a first determination condition when the verification pattern is executed;
a signal identification unit that identifies the signal name for which the counter value in the module to be verified satisfies a second determination condition;
a keyword extraction unit that extracts a first keyword corresponding to the identified signal name from a comment field of the circuit description of the verification pattern, and extracts a second keyword corresponding to the first keyword from verification specification information in which specifications of the verification pattern are described;
a verification purpose specifying unit that specifies a verification purpose of the verification pattern using the first keyword and the second keyword.
(Appendix 2)
2. The verification pattern checking device according to claim 1, wherein the signal extraction unit extracts the signal name from a declaration part in a circuit description of the verification pattern.
(Appendix 3)
3. The verification pattern check device according to claim 1, wherein the module identification unit identifies a module including the signal name with the largest counter value as the module to be verified.
(Appendix 4)
3. The verification pattern check device according to claim 1, wherein the module identification unit identifies, as the verification target module, a module including the signal name for which the counter value is equal to or greater than a predetermined first threshold value.
(Appendix 5)
the module identification unit is configured to identify, as the verification target module, a module for which the number of the signal names for which the counter value is equal to or greater than the first threshold is equal to or greater than a predetermined second threshold.
(Appendix 6)
the keyword extraction unit extracts the first keyword corresponding to the signal name with the largest counter value from a comment field of the circuit description of the verification pattern.
(Appendix 7)
the keyword extraction unit extracts the first keyword corresponding to the signal name whose counter value is equal to or greater than a predetermined first threshold from a comment field of the circuit description of the verification pattern.
(Appendix 8)
8. The verification pattern checking device according to claim 1, wherein the verification purpose specifying unit specifies the verification purpose for each module and specifies a verification procedure for the verification pattern from a transition of the counter value.
(Appendix 9)
A program for causing a computer to function as the verification pattern check device according to any one of claims 1 to 8.

In addition, any of the components of the embodiments may be modified or omitted.

1 Logic verification system, 2 Verification pattern check device, 3 Storage unit, 4 Logic simulator, 10 Comment field, 11 Verification item, 21 Signal extraction unit, 22 Counter generation unit, 23 Module identification unit, 24 Signal identification unit, 25 Keyword extraction unit, 26 Verification purpose identification unit, 30 Verification specification information, 100 Input interface, 101 Output interface, 102 Processor, 103 Memory.

Claims (9)

a signal extraction unit that extracts signal names for each module from a circuit description of a verification pattern written in a hardware description language;
a counter generating unit that generates a counter that counts the toggle amount of the signal having the signal name;
a module identification unit that identifies a module as a verification target module, the module having a counter value that satisfies a first determination condition when the verification pattern is executed;
a signal identification unit that identifies the signal name for which the counter value in the module to be verified satisfies a second determination condition;
a keyword extraction unit that extracts a first keyword corresponding to the identified signal name from a comment field of the circuit description of the verification pattern, and extracts a second keyword corresponding to the first keyword from verification specification information in which specifications of the verification pattern are described;
a verification purpose specifying unit that specifies a verification purpose of the verification pattern using the first keyword and the second keyword. 2. The verification pattern checking device according to claim 1, wherein the signal extraction unit extracts the signal name from a declaration part in a circuit description of the verification pattern. 2. The verification pattern check device according to claim 1, wherein the module identification unit identifies a module including the signal name for which the counter value is the largest as the module to be verified. 2. The verification pattern check device according to claim 1, wherein the module identification unit identifies, as the verification target module, a module including the signal name for which the counter value is equal to or greater than a predetermined first threshold value. 5. The verification pattern checking device according to claim 4, wherein the module identification unit identifies, as the verification target module, a module for which the number of the signal names for which the counter value is equal to or greater than the first threshold is equal to or greater than a predetermined second threshold. 2. The verification pattern checking device according to claim 1, wherein the keyword extraction unit extracts the first keyword corresponding to the signal name with the largest counter value from a comment field of the circuit description of the verification pattern. 2. The verification pattern checking device according to claim 1, wherein the keyword extraction unit extracts the first keyword corresponding to the signal name whose counter value is equal to or greater than a predetermined first threshold value from a comment field of a circuit description of the verification pattern. 2. The verification pattern checking device according to claim 1, wherein the verification purpose specifying unit specifies the verification purpose for each module and specifies a verification procedure for the verification pattern from a transition of the counter value. A program for causing a computer to function as the verification pattern check device described in any one of claims 1 to 8.