JP7746142B2 - Antenna device and camera system - Google Patents

Description

This disclosure relates to an antenna device and a camera system that transmits or receives electromagnetic waves.

An antenna consisting of a negative differential resistance element and a resonant circuit can generate electromagnetic waves (hereinafter simply referred to as "terahertz waves") that include at least a portion of the frequency band from millimeter waves to terahertz waves (30 GHz or higher and 30 THz or lower). As an example, Patent Document 1 discloses an antenna that emits terahertz waves by integrating a negative differential resistance element and a resonant circuit on a semiconductor chip.

Patent Document 1 uses a resonant tunneling diode (RTD) as the negative differential resistance element and includes a power supply that supplies a bias voltage to the negative differential resistance element. The bias voltage from the power supply is supplied to the negative differential resistance element via a bias supply unit that includes electric wires and conductors. Parasitic low-frequency oscillations (parasitic oscillations) other than terahertz waves emitted by the antenna are often generated by the structure associated with the bias supply unit. Therefore, Patent Document 1 discloses technology that suppresses parasitic oscillations by placing a shunt element in the bias supply unit.

JP 2015-180049 A

One way to increase antenna output is to create an antenna array by arranging multiple antennas, each consisting of a negative differential resistance element and a resonant circuit. When mounting a chip integrating this antenna array on a separate substrate such as a ceramic package or printed circuit board, the chip and substrate are connected with bonding wires, and a shunt element is placed on the substrate to suppress parasitic oscillation.

The resistances and capacitances that make up these bonding wires and shunt elements have parasitic inductance. This parasitic inductance cannot be ignored when generating terahertz waves properly, and is the cause of parasitic oscillations at frequencies lower than terahertz waves (less than 30 GHz). This parasitic inductance makes it particularly likely that parasitic oscillations will occur between 10 MHz and 10 GHz. In such antenna arrays, the circuit parameters and placement of the shunt elements on the board must be optimized to properly oscillate terahertz waves, but this is not fully considered in Patent Document 1.

The present disclosure therefore aims to provide technology for suppressing parasitic oscillation in an antenna device having an antenna array consisting of a negative differential resistance element and a resonant circuit.

In order to achieve the above object, an antenna device according to the present disclosure includes:
An antenna device for transmitting or receiving electromagnetic waves,
an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged;
a voltage bias circuit for applying a voltage to the antenna array;
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series;
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series;
and
the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element ,
The antenna device includes an antenna device characterized by satisfying the following formulas (1) to (3):
Rp +1/(2π×f×Cp) < r...(1)
Rc +1/(2π×f×Cc) < r...(2)
L/(Cc×r) <Rc...(3)
Here, r is the absolute value of the resistance value of the negative differential resistance element, Rp is the resistance value of the second resistor, Cp is the capacitance value of the second capacitor, Rc is the resistance value of the first resistor, Cc is the capacitance value of the first capacitor, L is the inductance of the path connecting the first shunt element and the second shunt element, and f is a frequency less than the resonant frequency of the resonant circuit.
In order to achieve the above object, the antenna device according to the present disclosure comprises:
An antenna device for transmitting or receiving electromagnetic waves,
an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged;
a voltage bias circuit for applying a voltage to the antenna array;
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series;
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series;
and
the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element,
The inductance L of the path connecting the first shunt element and the second shunt element satisfies the following formula (4):
L≦5 nH (4)
When the path is divided into a first portion whose cross section can be approximated to a circle and a second portion whose cross section can be approximated to a rectangle, the inductance L1 of the first portion is calculated by the following formula (5), and the inductance L2 of the second portion is calculated by the following formula (6).
L1=0.2×l1×[ln(4×l1/d)-0.75]...(5)
L2=0.2×l2×[ln{2×l2/(w + h)}+0.2235×(w+h)/l2+0.5] ...(6)
where l1 is the length of the first portion, d is the cross-sectional diameter of the first portion, l2 is the length of the second portion, w is the width of the second portion, and h is the thickness of the second portion.
In order to achieve the above object, the antenna device according to the present disclosure comprises:
An antenna device for transmitting or receiving electromagnetic waves,
an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged;
a voltage bias circuit for applying a voltage to the antenna array;
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series;
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series;
and
the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element,
The antenna array includes an antenna device having a third shunt element connected in parallel to the negative differential resistance element and including at least a third capacitance.
In order to achieve the above object, the antenna device according to the present disclosure comprises:
An antenna device for transmitting or receiving electromagnetic waves,
a chip having an antenna array in which a plurality of antennas each consisting of a negative differential resistance element and a resonant circuit are arranged;
a substrate on which the chip is disposed;
a voltage bias circuit for applying a voltage to the antenna array;
The chip is
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, the first shunt element including at least a first capacitance;
a plurality of pads including at least a first pad and a second pad for supplying a predetermined voltage to the antenna array;
The substrate is
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, including at least a second capacitance, and disposed on the substrate;
the antenna array is located between the first pad and the second pad;
The antenna array includes an antenna device having a third shunt element connected in parallel to the negative differential resistance element and including at least a third capacitance.
In order to achieve the above object, the antenna device according to the present disclosure comprises:
An antenna device for transmitting or receiving electromagnetic waves,
an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged;
a voltage bias circuit for applying a voltage to the antenna array;
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series;
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series;
and
the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element,
a plurality of pairs of the first shunt element and the second shunt element are arranged;
The antenna device includes at least two sets of the first shunt element and the second shunt element, which are arranged at positions symmetrical with respect to an axis passing through the center of the antenna array.

Moreover, the antenna device according to the present disclosure includes:
An antenna device for transmitting or receiving electromagnetic waves,
a chip having an antenna array in which a plurality of antennas each consisting of a negative differential resistance element and a resonant circuit are arranged;
a substrate on which the chip is disposed;
a voltage bias circuit for applying a voltage to the antenna array;
The chip is
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, the first shunt element including at least a first capacitance;
a plurality of pads including at least a first pad and a second pad for supplying a predetermined voltage to the antenna array;
The substrate is
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, including at least a second capacitance, and disposed on the substrate;
The antenna device includes an antenna array located between the first pad and the second pad.
In addition, the camera system according to the present disclosure includes:
The antenna device;
a detection device for detecting electromagnetic waves transmitted from the antenna device;
and a processing unit for processing signals from the detection device.

The technology disclosed herein allows for the provision of an antenna device and camera system that optimizes the configuration of the shunt element, suppresses parasitic oscillation, and operates well.

1 is a plan view illustrating an example of an antenna device according to a first embodiment; 1 is a cross-sectional view of an antenna device according to a first embodiment of the present invention; 1 is a cross-sectional view of an antenna device according to a first embodiment of the present invention; FIG. 1 is an explanatory diagram showing an antenna array according to a first embodiment; 1 is an equivalent circuit diagram of an antenna device according to a first embodiment; Graph illustrating the antenna device according to the first embodiment Graph illustrating the antenna device according to the first embodiment FIG. 1 is a diagram illustrating an antenna device according to a first embodiment. FIG. 1 is a diagram illustrating an antenna device according to a first embodiment. 10 is a plan view of an antenna device according to a second embodiment of the present invention; 10 is a plan view of an antenna device according to a third embodiment of the present invention; 10 is a plan view of an antenna device according to a fourth embodiment of the present invention; 10 is a plan view of an antenna device according to a fourth embodiment of the present invention; 10 is a plan view of an antenna device according to a fourth embodiment of the present invention; 10 is a plan view of an antenna device according to a fifth embodiment of the present invention; 10 is a plan view of an antenna device according to a fifth embodiment of the present invention; 10 is an equivalent circuit diagram of an antenna device according to a sixth embodiment. FIG. 10 is an explanatory diagram showing an antenna array according to a sixth embodiment; 13 is a cross-sectional view of an antenna device according to a sixth embodiment of the present invention; FIG. 13 is an explanatory diagram showing an antenna array according to a modification of the sixth embodiment; 13 is a cross-sectional view of an antenna device according to a modification of the sixth embodiment; 10 is a plan view of an antenna device according to a fourth embodiment of the present invention; FIG. 13 is a schematic diagram for explaining a camera system according to a seventh embodiment.

Embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to the following embodiments and can be modified as appropriate without departing from the spirit of the present disclosure. Furthermore, in the drawings described below, components having the same functions will be assigned the same reference numerals, and their descriptions may be omitted or simplified.

(First embodiment)
An antenna device according to a first embodiment will be described with reference to Fig. 1 to Fig. 9. Fig. 1 is a plan view showing a schematic configuration of the antenna device according to this embodiment. Fig. 2 is a cross-sectional view taken along line AA' in Fig. 1.

As shown in Figures 1 and 2, the antenna device 100 according to this embodiment has a rectangular chip 11 mounted on a substrate 10, on which an antenna array 12 consisting of multiple antennas 121 is arranged. Figure 1 shows the configuration on the surface of the chip 11. Details of the antenna 121 will be described later, but the antenna 121 is composed of a negative differential resistance element and a resonant circuit, and transmits or receives electromagnetic waves in the terahertz frequency band. The antenna 121 generates electromagnetic waves (hereinafter simply referred to as "terahertz waves") that include at least a portion of the frequency band from millimeter waves to terahertz waves (30 GHz or higher and 30 THz or lower). Adjacent antennas 121 are capacitively coupled via a microstrip line (described later using Figure 4).

In addition to the antenna array 12, the chip 11 includes a resistive element 131 and a capacitive element 132 that constitute the first shunt element 1300, a pad 141 that applies a bias voltage to the chip 11, and a pad 142 that applies a ground voltage to the chip 11. The pads 141 and 142 are used to electrically connect the chip 11 to a circuit external to the chip 11, for example, to supply a predetermined voltage from the outside. The pads 141 and 142 are made of a conductor. Hereinafter, the term "pad" refers to a pad that is used for electrical connection to the outside. Specifically, the pad is used to receive a predetermined voltage from the outside, and can be used to supply a predetermined voltage to the outside. In this embodiment, the predetermined voltage can be a ground voltage, a power supply voltage, a voltage from a voltage bias circuit, or the like.

The antenna array 12 is placed approximately in the center of the chip 11, and the capacitive elements 132 are placed adjacent to the antenna array 12. Furthermore, by placing the capacitive elements 132 so that they surround the antenna array 12, the placement area of the capacitive elements on the chip 11 can be expanded, ensuring a large capacitance. Furthermore, the capacitive elements 132 are placed separately on each of the two opposing sides of the chip 11 (on the right and left sides of the chip 11 in the figure) so that the antenna array 12 is sandwiched between the capacitive elements 132. This allows the placement of resistive elements 131, wiring, pads, etc. in areas where the capacitive elements 132 are not placed (on the upper side of the chip 11 in the figure), thereby reducing the chip size of the chip 11.

As shown in FIG. 2, one terminal of the resistive element 131 is connected to one terminal of the capacitive element 132 via wiring 133 and via 134. The resistive element 131 and the capacitive element 132 are connected in series, and to facilitate the connection, the resistive element 131 is preferably arranged near the capacitive element 132. Alternatively, the resistive element 131 may be arranged overlapping the capacitive element 132. The other terminal of the resistive element 131 is connected to the pad 141 via the bias voltage line 130. The bias voltage line 130 is also arranged between each antenna 121 of the antenna array 12 and is commonly connected to each antenna 121, applying a bias voltage to each antenna 121. The other terminal of the capacitive element 132 is connected to the pad 142 via wiring and a via (not shown).

The capacitance element 132 can be a metal-insulator-metal (MIM) capacitor in which an insulating layer is sandwiched between metal layers. The metal layer can be a wiring layer within the chip 11, and the insulating layer can be an insulating layer or a dielectric layer forming an antenna. According to this embodiment, as shown in FIG. 2 , a ground metal layer 124 is used as one electrode of the MIM capacitance, and the ground metal layer 124 is connected to a pad 142 to which a ground voltage is applied. A metal layer 139 is formed as the other electrode of the MIM capacitance via an insulating layer. The metal layer 139 is connected to a wiring 133 via a via 134. By configuring the MIM capacitance in this manner, a capacitance can be formed within a chip using a simple manufacturing process.

In addition to the above configuration, it is also possible to form a capacitor on a substrate separate from chip 11 and attach it to the front or back of chip 11. This configuration makes it possible to provide a capacitive element with a larger capacity.

In the first shunt element 1300, the resistive element 131 is connected to a pad 141 that applies a bias voltage, and the capacitive element 132 is connected to a pad 142 that applies a ground voltage. However, the connections may be reversed, with the resistive element 131 connected to the pad 142 that applies a ground voltage, and the capacitive element 132 connected to the pad 141 that applies a bias voltage.

Preferably, 20 to 40 antennas are arranged on the chip 11 as the antennas 121 of the antenna array 12. Furthermore, the number of pads 141 for applying bias voltages and the number of pads 142 for applying ground voltages are made smaller than the number of antennas. This allows the chip 11 to be used more efficiently and made more compact. Furthermore, if the number of pairs of resistive elements 131 and capacitive elements 132 is less than or equal to the number of pads 141 for applying bias voltages or the number of pads 142 for applying ground voltages, the chip 11 can be used more efficiently and made more compact.

The substrate 10 also includes a resistive element 151 and a capacitive element 152 that constitute the second shunt element 1500, a pad 161 for connecting to the pad 141 of the chip 11, and a pad 162 for connecting to the pad 142 of the chip 11. The pads 161 and 162 are for electrically connecting the chip 11 to an external circuit. The pads 161 and 162 are made of conductive material. In this case, the external circuit is the chip 11. The substrate 10 also includes a connection terminal 181 to which a bias voltage is supplied from the voltage bias circuit 17 and a connection terminal 182 to which a ground voltage is applied. To reduce the size of the substrate 10, it is preferable to use surface-mounted components (SMDs) as the resistive element 151 and the capacitive element 152. Because the wiring arranged on the substrate 10 also has resistance, the resistance of the wiring on the substrate 10 included in the path connecting the first shunt element 1300 and the second shunt element 1500 may be used as the resistive element 151. This reduces the number of components used in chip 11, making it possible to miniaturize chip 11. Here, connection terminals 181 and 182 may be pads.

The voltage bias circuit 17 is connected from outside the substrate 10 via connection terminals 181 and 182. Alternatively, the voltage bias circuit 17 may be placed on the substrate 10 or on the chip 11.

Pad 141 on chip 11 and pad 161 on substrate 10 are connected by bonding wire 191. Pad 142 on chip 11 and pad 162 on substrate 10 are connected by bonding wire 192. To reduce the inductance of bonding wires 191 and 192, it is preferable to position pads 141 and 161, and pads 142 and 162, close to each other and shorten the lengths of bonding wires 191 and 192.

To shorten the bonding wires 191 and 192, it is recommended that pads 141 and 142 be placed at the ends of the chip 11. Pads 141 and 161 should also be placed opposite each other across an edge of the chip 11. Pads 142 and 162 should also be placed opposite each other across an edge of the chip 11.

One terminal 1512 of the resistive element 151 is connected to one terminal 1521 of the capacitive element 152 via wiring 157. In other words, the resistive element 151 and the capacitive element 152 are connected in series. Therefore, it is preferable to arrange the resistive element 151 and the capacitive element 152 in close proximity to each other. More preferably, one terminal 1512 of the resistive element 151 is arranged adjacent to one terminal 1521 of the capacitive element 152. This allows the length of the wiring 157 to be shortened, thereby reducing inductance.

The other terminal 1511 of the resistive element 151 is connected to the pad 161 via wiring 153 and to the connection terminal 181 via wiring 154. The other terminal 1522 of the capacitive element 152 is connected to the pad 162 via wiring 155 and to the connection terminal 182 via wiring 156. It is preferable that the direction in which the terminals 1511, 1512 of the resistive element 151 and the terminals 1521, 1522 of the capacitive element 152 are aligned is the same as the direction in which the pads 161 and 162 are aligned. This arrangement allows the connecting wiring to be shorter, thereby reducing inductance.

Furthermore, in the second shunt element 1500, the resistive element 151 is connected to the connection terminal 181 that applies a bias voltage, and the capacitive element 132 is connected to the connection terminal 182 that applies a ground voltage. However, the connections may be reversed, with the resistive element 131 connected to the connection terminal 182 that applies a ground voltage, and the capacitive element 132 connected to the connection terminal 181 that applies a bias voltage.

In this embodiment, an example is assumed in which the first shunt element 1300 and the second shunt element 1500 are composed of resistive elements 131, 151 and capacitive elements 132, 152, respectively. However, the first shunt element and the second shunt element may be composed of either a resistive element or a capacitive element. When the shunt element includes a capacitive element, it is possible not only to suppress parasitic oscillation but also to suppress power consumption by, for example, cutting DC current by utilizing the frequency characteristics of impedance.

The positional relationship of the components of the antenna device 100 is such that the first shunt element 1300 is disposed between the antenna array 12 and the voltage bias circuit 17, and the second shunt element 1500 is disposed between the first shunt element 1300 and the voltage bias circuit 17.

3 is a partial cross-sectional view of antenna device 100 illustrating a configuration in which a pad is formed on the back surface of chip 11 and chip 11 is connected to substrate 10 without using bonding wire 19. According to Fig. 3, wiring on the front surface of chip 11 is connected to pad 141 on the back surface of chip 11 via through electrode 135.

The through electrode 135 is formed by forming a through hole in the chip 11, forming an insulating film on the inner wall of the through hole for electrical isolation, and filling the through hole with copper or the like, which has low electrical resistance and allows for easy electrode formation by electrolytic plating or the like. The through electrode 135 is also smoothed using a CMP (Chemical Mechanical Polishing) process or the like.
After forming the through electrode 135, a pad 141 is formed on the back surface of the chip 11 so as to be electrically connected to the through electrode 135.

The pads 141 on the back surface of the chip 11 and the pads 161 on the substrate 10 are arranged so that they overlap, and are connected by solder or the like. When making an electrical connection using the through electrodes 135, no bonding wires are used, which reduces inductance and makes it easier to suppress parasitic oscillation in the antenna device 100.

Figure 4 is an explanatory diagram showing the antenna array 12 in this embodiment. Figure 4A is a top view of the antenna array 12, and Figure 4B is a cross-sectional view of the antenna array 12 taken along line B-B' in Figure 4A. The figure shows two antennas 121 and 122 included in the antenna array 12 as an example.

Typically, in an antenna array intended for power combining, the spacing between individual antennas is equal to or less than the wavelength of the oscillating electromagnetic wave converted to its wavelength in a vacuum, or an integer multiple of that wavelength, and more preferably, equal to or less than half the wavelength. In this embodiment, antennas 121 and 122 are arranged so that the spacing between the antennas is equal to or less than half the wavelength of the transmitted electromagnetic wave.

In the antenna array 12, a resonant circuit 1200 for controlling the oscillation frequency is formed by a microstrip resonator consisting of a metal layer 123, which is a first conductor forming part of the antenna, a dielectric layer 128, and a grounded metal layer 124, which is a second conductor forming part of the antenna. The antennas 121 and 122 are composed of this resonant circuit 1200 and a negative differential resistance element 127. A bias voltage line 130 is connected to the metal layer 123 via a via 134 , and a bias voltage is applied to the negative differential resistance element 127. The negative differential resistance element 127 generates electromagnetic wave gain to maintain oscillation. Since the individual antennas 121 and 122 oscillate synchronously in phase, they are designed to have an oscillation frequency close to _ω0 . Therefore, it is preferable that the shapes of the individual antennas, including the half-wave resonators, are similar to each other. It is also preferable that the negative differential resistance elements 127 have similar shapes and characteristics. The microstrip line 125 is an inter-element structure for synchronizing and oscillating the individual antennas described above in phase with each other.

The microstrip line 125, which is the transmission line of the metal portion forming the link structure, is preferably selected so that the length along the microstrip line 125 from one end to the other is 2π in electrical length at the oscillation frequency _ω0 after synchronization. The electrical length of 2π is the length equivalent to the effective oscillation wavelength _λ0 converted by the effective dielectric constant of the surrounding structure. The electrical length of 2π is selected so that the antennas 121 and 122 are synchronized and oscillated in phase. When the antennas 121 and 122 are synchronized in antiphase, the electrical length may be π or 3π. The length of the microstrip line 125 does not need to be exactly 2π to enable synchronization of the antennas 121 and 122. Although it depends on the magnitude of coupling between the elements formed by the microstrip line 125, a typical allowable range is approximately 2π±10% of the electrical length. This allowable range is wider than when coupling is performed without using the microstrip line 125. The electrical length of the microstrip line can be easily confirmed using an electromagnetic field simulator or the like.

A portion of the oscillation output of antenna 121 is input approximately in phase to adjacent antenna 122 via microstrip line 125. On the other hand, a portion of the oscillation output of antenna 122 is input approximately in phase to adjacent antenna 121 via microstrip line 125. In the antenna array of this embodiment, microstrip line 125 is introduced to achieve this mutual injection locking phenomenon between antennas 121 and 122.

The microstrip line 125 of this embodiment is characterized by being capacitively coupled to the metal layer 123 of the resonant structure. They only form a capacitance via the insulating layer 129 in the metal-insulator-metal (MIM) region 126, and are DC-open. This allows the magnitude of coupling between the antennas to be maintained as large as direct coupling in the oscillation frequency band _ω0 . Furthermore, in the low-frequency region below _ω0 , the magnitude of coupling is reduced, ensuring isolation between the antennas. The microstrip line 125 of this embodiment is preferable because it has these properties. Furthermore, in the low-frequency region below _ω0 , the open-ended microstrip line 125 becomes a capacitive element. From the perspective of the negative differential resistance element 127 on the antenna 121 side, the microstrip line 125 is a capacitive element, and the metal layer 123 of the resonant structure on the antenna 122 side is also a capacitor. Therefore, the resonant frequency itself, which is a concern in the low-frequency region, is not generated. Therefore, parasitic oscillation in the low-frequency region can be suppressed.

Figures 4A and 4B illustrate two individual antennas 121, 122, but in the antenna array 12, each antenna can be arrayed by arranging it in the same configuration as the antennas 121, 122. Furthermore, multiple metal layers 123 corresponding to the number of arrays are arranged on the ground metal layer 124, with a dielectric layer 128 interposed between them, and negative differential resistance elements 127 corresponding to the metal layers 123 are also arranged. Adjacent antennas are capacitively coupled by microstrip lines 125. Furthermore, the electrical length of each microstrip line 125 is approximately 2π. Therefore, it is possible to synchronize all negative differential resistance elements 127 in phase. Arraying antennas in this way is preferable because not only does it increase the combined power, but it also provides sharp directivity.

In addition, the multiple metal layers 123 are commonly connected inside the chip 11 via a strip conductor (not shown) and connected to pad 141, to which a bias voltage is applied, and the ground metal layer 124 is connected to pad 142 inside the chip 11. With this configuration, when a voltage is applied to pad 141 and pad 142, a bias voltage is applied to the negative differential resistance element 127.

A resonant tunneling diode lattice-matched to the InP substrate can be used as the negative differential resistance element 127. The negative differential resistance element 127 is not limited to a resonant tunneling diode, and an Esaki diode or a Gunn diode may also be used. The resonant tunneling diode is configured, for example, with a multiple quantum well structure of InGaAs/InAlAs or InGaAs/AlAs on an InP substrate, and an electrical contact layer of n-InGaAs. For example, a triple barrier structure is used as the multiple quantum well structure. More specifically, a triple barrier structure of AlAs (1.3
nm)/InGaAs (7.6 nm)/InAlAs (2.6 nm)/InGaAs (5.
The semiconductor multilayer structure is composed of InGa (1.6 nm)/AlAs (1.3 nm).
The As well layers are lattice-matched InAlAs and non-lattice-matched AlAs are barrier layers. These layers are intentionally left undoped. This multiple quantum well structure is sandwiched between electrical contact layers made of n-InGaAs with an electron concentration of 2×10 ¹⁸ cm ⁻³ . The current-voltage (I/V) characteristics of the structure between these electrical contact layers show a peak current density of 280 kA/cm ² and a negative resistance region from approximately 0.7 V to approximately 0.9 V. A mesa structure with a 2 μm diameter diode configuration achieves a peak current value of 10 mA and a negative resistance value of −20 Ω. Considering the reactance associated with the junction capacitance of the 2 μm diameter resonant tunneling diode connected to the bottom of the metal layer 123, the oscillation frequency is approximately 0.55 THz.

Next, Figure 5 shows an equivalent circuit diagram of the antenna device according to this embodiment. The equivalent circuit of the chip 11 has the resistance r (r indicates the absolute value of the resistance of the negative differential resistance element) of the negative differential resistance element that constitutes the antenna array 12. The equivalent circuit of the chip 11 also has the impedance Z of the resonant circuit 1200 that constitutes the antenna array 12, and the resistance Rc of the resistive element 131 that constitutes the first shunt element 1300. The equivalent circuit of the chip 11 also has the capacitance Cc of the capacitive element 132 that constitutes the first shunt element 1300.

The first shunt element 1300 is configured by connecting a resistance Rc and a capacitance Cc in series. Furthermore, the resistance r, the impedance Z of the resonant circuit 1200, and the first shunt element 1300 are connected in parallel with each other. More specifically, one terminal of the resistance r, one terminal of the impedance Z of the resonant circuit 1200, and one terminal of the resistance Rc are each connected to a first node n1. The other terminal of the resistance Rc is connected to one terminal of the capacitance Cc. The other terminal of the resistance r, the other terminal of the impedance Z of the resonant circuit 1200, and the other terminal of the capacitance Cc are connected to the ground voltage. The first node n1 is connected to pad 141 of the chip 11, and the ground voltage is applied via pad 142 of the chip 11.

The equivalent circuit of the substrate 10 is composed of the resistance Rp of the resistive element 151 and the capacitance Cp of the capacitive element 152 that make up the second shunt element 1500, and the inductance L of the path connecting the first shunt element 1300 and the second shunt element 1500. The inductance L includes the parasitic inductance of the wiring connecting the first shunt element 1300 and the pad 141, the bonding wire connecting the chip and the substrate, the wiring connecting the bonding wire and the second shunt element 1500, the pad, etc.

The second shunt element 1500 is configured by connecting a resistance Rp and a capacitance Cp in series. Furthermore, the chip 11 and the second shunt element 1500 are connected via an inductance L. More specifically, one terminal of the inductance L is connected to the first node n1 in the equivalent circuit of the chip 11, and the other terminal of the inductance L and one terminal of the resistance Rp are connected to the second node n2. Furthermore, the other terminal of the resistance Rp is connected to one terminal of the capacitance Cp. Furthermore, a ground voltage is applied to the other terminal of the capacitance Cp. Furthermore, the second node n2 is connected to terminal 181, and a voltage bias circuit V is connected to it. Therefore, a bias voltage is applied to the second node n2, and the bias voltage is applied to the resistance r via the inductance L.

The first shunt element 1300 (resistance Rc and capacitance Cc) is connected in parallel with the negative differential resistance element (resistance r), and is also connected in parallel with the second shunt element 1500 (resistance Rp and capacitance Cp) via inductance L. Furthermore, the first shunt element 1300 is also connected in parallel with the voltage bias circuit V.

In such an antenna device, to suppress parasitic oscillation, it is preferable that the first shunt element 1300 and the second shunt element 1500 have low impedance with reference to the resistance r of the negative differential resistance element 127. In other words, it is preferable that they are set to have low impedance as seen from the negative differential resistance element 127 in a frequency band shorter than the terahertz frequency band. In this case, the following conditional expressions (1) and (2) hold true.
Rp +1/(2π×f×Cp) < r...(1)
Rc +1/(2π×f×Cc) < r...(2)
Here, r is the absolute value of the resistance of the negative differential resistance element, Rc is the resistance of the resistor Rc, which is the first resistor, and Cc is the capacitance of the capacitor Cc, which is the first capacitor. Rp is the resistance of the resistor Rp, which is the second resistor, Cp is the capacitance of the capacitor Cp, which is the second capacitor, and L is the inductance of the path connecting the first shunt element 1300 and the second shunt element 1500. f is the frequency of the parasitic oscillation in question, and indicates a frequency less than the resonant frequency of the resonant circuit that constitutes the antenna array 12. The frequency f is specifically less than 30 GHz, but when the chip 11 is mounted on the substrate 10 as in this embodiment, it is particularly a frequency in the range of 10 MHz to 10 GHz.

However, even if equations (1) and (2) hold, LC resonance may occur between the inductance L and the capacitance Cc. To suppress this LC resonance, it is necessary to ensure Rc in order to dissipate the oscillation energy, and it is preferable to reduce L and increase Cc. Therefore, to suppress parasitic oscillation, the following conditional equation (3) also holds.
L/(Cc×r) <Rc...(3)

Figure 6 is a graph showing the frequency characteristics of the impedance seen from the negative differential resistance element 127 when the value of inductance L is changed based on the equivalent circuit of Figure 5. The dashed line shows the characteristics for L = 1 nH, the solid line for 5 nH, and the dashed-dotted line for 10 nH, and the impedance has peak values at specific frequencies. Specifically, for L = 1 nH, the peak value is 1.8 Ω at 160 MHz, for L = 5 nH, the peak value is 16.8 Ω at 50 MHz, and for L = 10 nH, the peak value is 8.5 Ω at 71 MHz.

Figure 7 is a graph showing the relationship between the inductance L and the peak value of the impedance seen from the negative differential resistance element 127, based on the frequency characteristics of Figure 6. According to Figure 7, as the inductance L increases, the peak value of the impedance increases.

At the frequency f of the parasitic oscillation to be suppressed, if the impedance of the line as seen from the negative differential resistance element 127 is 10 times or less the absolute value of the negative differential resistance, the magnitude of the loss due to the line becomes non-negligible relative to the gain of the negative differential resistance element 127. This makes it possible to suppress LC resonance oscillation. As an example, in an antenna array with a chip size of 3 mm square to 4 mm square, 20 to 40 antennas can be arranged, and the combined resistance value of the negative differential resistance 127 is at most 1 Ω, i.e., 1 Ω or less. Therefore, parasitic oscillation can be suppressed if the resistance is 10 times this resistance value, i.e., 10 Ω or less. In other words, according to the graph in FIG. 7, L≦5 nH is sufficient.

The inductance L includes the parasitic inductance of the wiring connecting the first shunt element 1300 and the pad 141, the bonding wire connecting the chip and the substrate, the wiring connecting the bonding wire and the second shunt element 1500, the pad, etc. The inductances of the path connecting the first shunt element 1300 and the second shunt element 1500 can be calculated using the following formulas (4) and (5), respectively. In the path connecting the first shunt element 1300 and the second shunt element 1500, the portion whose cross section can be approximated to a nearly circular shape is calculated using formula (4), and the portion whose cross section can be approximated to a square is calculated using formula (5).
L1=0.2×l1×[ln(4×l1/d)-0.75] [nH]...(4)
L2=0.2×l2×[ln{2×l2/(w + h)}+0.2235×(w+h)/l2+0.5] [nH]...(5)
Here, l1 is the length (mm) of the portion of the path whose cross section can be approximated as a circle, d is the diameter (mm) of the cross section, l2 is the length (mm) of the portion of the path whose cross section can be approximated as a rectangle, w is the width (mm), and h is the thickness (mm).

8 is a diagram illustrating the inductance of a path connecting the first shunt element 1300 and the second shunt element 1500 in this embodiment. The path connecting the first shunt element 1300 and the second shunt element 1500 includes a wiring (first portion P1) connecting the resistive element 131 and the pad 141 constituting the first shunt element 1300, and the pad 141 (second portion P2). The path further includes a bonding wire 19 (third portion P3), the pad 161 (fourth portion P4), and a wiring (fifth portion P5) connecting the pad 161 and the resistive element 151 constituting the second shunt element 1500.

The length of the path connecting the first shunt element 1300 and the second shunt element 1500 is preferably 4 mm or less, which is suitable for reducing parasitic inductance and suppressing parasitic oscillation. It is more preferably 2 mm or less.

Below, we will explain the dimensions of each part in the path and an example of the inductance calculated using equation (4) or equation (5).

The first portion P1 has a length of 0.3 mm, a width of 0.2 mm, and a thickness of 0.5 μm, and the inductance L1 of this region is calculated using equation (5) to be 0.1 nH.

The inductance L2 of the second portion P2 is calculated as the region from the end of the pad 141 to approximately the center of the pad 141 where the bonding wire 19 is connected. This region is 0.1 mm long, 0.2 mm wide, and 0.5 μm thick, and the inductance L2 is calculated using equation (5) to be 0.02 nH.

The third portion P3 is a bonding wire with a length of 1.0 mm and a cross-sectional diameter of 20 μm. The inductance L3 of this region is calculated using equation (4) to be 0.91 nH.

The inductance L4 of the fourth portion P4 is calculated as the region from the end of the pad 161 to approximately the center of the pad 161 where the bonding wire 19 is connected. This region is 0.6 mm long, 1.2 mm wide, and 35 μm thick, and the inductance L4 is calculated using equation (5) to be 0.11 nH.

The fifth portion P5 has a length of 0.8 mm, a width of 0.6 mm, and a thickness of 35 μm, and the inductance L5 of this region is calculated using equation (5) to be 0.26 nH.

Therefore, the inductance of the path connecting the first shunt element 1300 and the second shunt element 1500 can be calculated as the sum of inductances L1, L2, L3, L4, and L5, which is 1.4 nH.

In this embodiment, the inductance was calculated using equation (4) assuming that the cross section of the bonding wire 19 is circular, but a ribbon-shaped bonding wire with a square cross section may also be used. In the case of a ribbon-shaped bonding wire, the inductance can be calculated using equation (5). A ribbon-shaped bonding wire can have a larger cross-sectional area, which reduces the inductance.

Figures 9A and 9B are diagrams for explaining how to calculate the inductance of a wiring. Here, we will explain using wiring 153 connecting pad 161 to resistive element 151 that constitutes second shunt element 1500. The same can be considered for wiring connecting resistive element 131 that constitutes first shunt element 1300 to pad 141.

FIG. 9A is a diagram showing an example of a configuration in which wiring 153 has a bent portion. In the example shown in FIG. 9A , wiring 153 is configured with a bent portion having two 90-degree bends. The inductance of wiring 153 in the example shown in FIG. 9A can be calculated by dividing it into three rectangular portions. The three rectangular portions are a first rectangular portion RS1 connected to pad 161, a second rectangular portion RS2 connected to the first rectangular portion, and a third rectangular portion RS3 connected to the second rectangular portion. The third rectangular portion RS3 is connected to resistor element 151. The first rectangular portion RS1 has a length l21, a width w1, and a thickness h1. The second rectangular portion RS2 has a length l22, a width w2, and a thickness h2. The third rectangular portion RS3 has a length l23, a width w3, and a thickness h3. The inductance of each rectangular portion is calculated using equation (5), and the sum of the calculated inductances is the inductance of wiring 153.

Here, an example of how to determine lengths l21, l22, and l23 will be described. Point A is the intersection of line X, which passes through the center of the width of the first rectangular portion RS1 and extends in the length direction, and line Y, which passes through the center of the width of the second rectangular portion RS2 and extends in the length direction. Point B is the intersection of line Y and line Z, which passes through the center of the width of the third rectangular portion RS3 and extends in the length direction. The distance between the end of pad 161 and point A is the length l21 of the first rectangular portion, the distance between points A and B is the length l22 of the second rectangular portion RS2, and the distance between point B and the end of resistor element 151 is the length l23 of the third rectangular portion RS3.

Methods for determining length l21, length l22, and length l23 other than those described above may be used as long as they can divide wiring 153 and identify rectangular portions.

Next, Figure 9B shows an example in which wiring 153 is configured to extend linearly from resistor element 151 toward pad 161 while gradually increasing in width. Even with this type of wiring 153, the inductance of wiring 153 can be calculated using equation (5) by replacing wiring 153 with a rectangular portion RS4 as shown in the figure. Rectangular portion RS4 has a length l24, a width w4, and a thickness h4.

Next, an example of how to determine the length l24 and width w4 of rectangular portion RS4 will be explained. A center point C of portion V-V' where wiring 153 and pad 161 contact is defined, and a point D that contacts resistor element 151 at the shortest distance from point C is defined. The distance between points C and D is length l24. Furthermore, the distance between the ends of the wiring in the direction perpendicular to line segment CD, passing through center E between points C and D, is defined as width w4.

In this way, the wiring inductance can be calculated using the determination method described using Figures 9A and 9B.

According to this embodiment, parasitic oscillation can be suppressed by configuring the shunt elements to satisfy equations (1), (2), and (3). Furthermore, when calculating the inductance L of the path connecting the first shunt element 1300 and the second shunt element 1500 used in equation (3), the calculation method described using equations (4), (5), Figures 8, and 9 can be applied.

Second Embodiment
An antenna device according to a second embodiment of the present disclosure will be described with reference to Fig. 10. The second embodiment differs from the first embodiment in that pads are connected to each other by a plurality of bonding wires. Note that in this embodiment, a description of the same configuration as in the first embodiment will be omitted.

10 includes, on the chip 21, a pad 241 for applying a bias voltage and a pad 242 for applying a ground voltage. Furthermore, on the substrate 20, a pad 261 for connecting to the pad 241 of the chip 21 and a pad 262 for connecting to the pad 242 of the chip 21 are provided. Furthermore, on the substrate 20, a plurality of bonding wires 291 for connecting the pad 241 to the pad 261 and a plurality of bonding wires 292 for connecting the pad 242 to the pad 262 are provided. The other elements of the antenna device 200, such as the antenna array, the first shunt element, and the second shunt element, are the same as those of the antenna device 100 according to the first embodiment.

To reduce the inductance of bonding wires 291 and 292, it is preferable to position pads 241 and 261, and pads 242 and 262, close to each other and shorten bonding wires 291 and 292.

To shorten the bonding wires 291, 292, it is preferable to place pads 241 and 242 at the ends of the chip 21. If one side of the chip 21 across which the multiple bonding wires 291, 292 cross is defined as first side 271, pads 241 and 261 are placed opposite each other across first side 271. Pads 242 and 262 are also placed opposite each other across first side 271. Furthermore, the multiple bonding wires 291, 292 are placed side by side at intervals in a direction parallel to first side 271.

The multiple bonding wires 291 and 292 are electrically connected in parallel. The combined inductance Lm of the M bonding wires connected in parallel can be calculated by the following equation (6).
1/Lm=Σ(1/Li)(i=1,2,3,...,M)...(6)
Here, Li is the inductance of the i-th bonding wire out of M wires, and is calculated using equation (4) when the cross section of the bonding wire is circular, and is calculated using equation (5) when the cross section of the bonding wire is rectangular. Whether the cross section of the bonding wire is circular or rectangular may be determined appropriately, and the combined inductance Lm of the bonding wire may be calculated using equations (4) and (5).

By electrically connecting multiple bonding wires 291, 292 in parallel in this way, the combined inductance of the bonding wires 291, 292 can be reduced, making it easier to suppress parasitic oscillation.

In this embodiment, the areas of pads 241 and 242 are larger than pads 141 and 142 in the first embodiment, and the areas of pads 261 and 262 are larger than pads 161 and 162 in the first embodiment. This allows the number of bonding wires connecting the pads to be increased, reducing the combined inductance of multiple bonding wires.

In addition, pads 241, 242, 261, and 262 are configured so that the dimension parallel to the first side 271 of chip 21 is greater than the dimension perpendicular to the first side 271. This allows for a greater number of bonding wires to be placed, reducing the combined inductance of the bonding wires.

It is also possible to divide pads 241, 242, 261, and 262 into individual bonding wires, as in the first embodiment. In this case, the pads can be connected in a wiring layer lower than the metal layer on which they are formed. However, a configuration in which multiple bonding wires are placed on one pad, as shown in Figure 10, eliminates the need to reserve space to separate the pads, making pattern formation easier. Therefore, by adopting the configuration shown in Figure 10, an inexpensive printed circuit board or ceramic package can be used as substrate 20, reducing costs.

(Third embodiment)
An antenna device according to a third embodiment of the present disclosure will be described with reference to Fig. 11. The third embodiment differs from the first embodiment in that resistive elements and capacitive elements constituting the first shunt element and the second shunt element are added and connected in parallel. In this embodiment, descriptions of the same configuration as in the first and second embodiments will be omitted.

The antenna device 300 according to this embodiment shown in Figure 11 includes, on the chip 31, a first shunt element consisting of a resistive element 331 and a capacitive element 332, and another first shunt element consisting of a resistive element 333 and a capacitive element 332. Furthermore, the antenna device 300 includes, on the chip 31, pads 341 and 343 for applying a bias voltage and a pad 342 for applying a ground voltage. Furthermore, the substrate 30 includes, on the substrate 30, a second shunt element consisting of a resistive element 351 and a capacitive element 352, and another second shunt element consisting of a resistive element 353 and a capacitive element 354.

Substrate 30 also includes pad 361 for connection to pad 341 of chip 31, pad 362 for connection to pad 342 of chip 31, and pad 363 for connection to pad 343 of chip 31. Pad 341 and pad 361 are connected by bonding wire 391, pad 342 and pad 362 are connected by bonding wire 392, and pad 343 and pad 363 are connected by bonding wire 393. Substrate 30 also includes connection terminals 381 and 383 to which a bias voltage is supplied from voltage bias circuit 37, and connection terminal 382 to which a ground voltage is applied.

In Figure 11, pads 341, 342, and 343 of chip 31 are connected to pads 361, 362, and 363 of substrate 30 by single bonding wires 391, 392, and 393, respectively. However, as in the second embodiment, two pads may be connected by multiple bonding wires. Alternatively, as in Figure 3, two pads may be connected by through electrodes without using bonding wires 391, 392, and 393.

As in the first embodiment, the antenna array 32 is disposed approximately in the center of the chip 31, and the capacitance element 332 is disposed adjacent to the antenna array 32. One terminal of the resistance element 331 is connected to one terminal of the capacitance element 332 via wiring and a via (not shown). One terminal of the resistance element 333 is connected to one terminal of the capacitance element 332 via wiring and a via (not shown). The resistance elements 331 and 333 are preferably disposed near the capacitance element 332. Alternatively, the resistance elements 331 and 333 may be disposed overlapping the capacitance element 332. The other terminal of the resistance element 331 is connected to the pad 341 via the bias voltage line 330. The bias voltage line 330 is also disposed between the antennas 321 of the antenna array 32 and connected to each antenna 321. This applies a bias voltage to each antenna 321. The other terminal of the capacitance element 332 is connected to the pad 342 via wiring and a via (not shown). The other terminal of the resistor element 333 is connected to the pad 343 via the bias voltage line 330.

One terminal 3512 of the resistive element 351 is connected to one terminal 3521 of the capacitive element 352 via wiring. In other words, the resistive element 351 and the capacitive element 352 are connected in series. Therefore, it is preferable to arrange the resistive element 351 and the capacitive element 352 adjacent to each other. More preferably, if one terminal 3512 of the resistive element 351 is arranged adjacent to one terminal 3521 of the capacitive element 352, the wiring can be shortened, thereby reducing inductance.

The other terminal 3511 of the resistive element 351 is connected to the pad 361 via wiring, and also connected to the connection terminal 381 via wiring. The other terminal 3522 of the capacitive element 352 is connected to the pad 362 via wiring, and also connected to the connection terminal 382 via wiring.

One terminal 3532 of the resistive element 353 is connected to one terminal 3541 of the capacitive element 354 via wiring. In other words, the resistive element 353 and the capacitive element 354 are connected in series. Therefore, it is preferable to arrange the resistive element 353 and the capacitive element 354 adjacent to each other. More preferably, if one terminal 3532 of the resistive element 353 is arranged adjacent to one terminal 3541 of the capacitive element 354, the wiring can be shortened, thereby reducing inductance.

The other terminal 3531 of the resistive element 353 is connected to the pad 363 via wiring, and also connected to the connection terminal 383 via wiring. The other terminal 3542 of the capacitive element 354 is connected to the pad 362 via wiring, and also connected to the connection terminal 382 via wiring.

In FIG. 11, terminals 3511 and 3512 of resistive element 351, terminals 3521 and 3522 of capacitive element 352, terminals 3531 and 3532 of resistive element 353, and terminals 3541 and 3542 of capacitive element 354 are arranged in one direction (left and right in the figure) on substrate 30. In this embodiment, pads 361, 362, and 363 are also arranged in the same direction as terminals 3511, 3512, 3521, 3522, 3531, 3532, 3541, and 3542. By arranging the terminals and pads in this manner, the connecting wiring can be shortened, reducing inductance.

Because a bias voltage is supplied from the voltage bias circuit 37 to both connection terminals 381 and 383, the other terminal 3511 of the resistive element 351 and the other terminal 3531 of the resistive element 353 are electrically connected. Furthermore, the other terminal 3522 of the capacitive element 352 and the other terminal 3542 of the capacitive element 354 are commonly connected by wiring. Therefore, the resistive element 351 and the capacitive element 352 constituting the second shunt element are electrically connected in parallel with the resistive element 353 and the capacitive element 354 constituting another second shunt element. For example, SMDs (Surface Mount Devices) are used as the resistive elements 351 and 353 and the capacitive elements 352 and 354, but such components have not only resistive and capacitive components but also parasitic inductance. Therefore, for each pair of first and second shunt elements, the second shunt elements (resistive element 351 and capacitive element 352 and resistive element 353 and capacitive element 354) of each pair are connected in parallel. This reduces parasitic inductance and suppresses parasitic oscillation.

In addition, since bonding wires 391 and 393, which are the paths for supplying the bias voltage, are connected in parallel, the combined inductance of the bonding wires is also reduced.

Furthermore, since the wiring arranged on the substrate 30 also has a resistance value, the resistance of the wiring on the substrate 30 connecting the first shunt element and the second shunt element may be used as the resistance elements 351 and 353. This allows the number of components arranged on the substrate 30 to be reduced, which is advantageous for miniaturization.

Furthermore, in the chip 31, the elements and pads arranged on the chip 31, and the elements, pads, wiring, etc. arranged on the substrate 30 are arranged symmetrically with respect to an axis passing through the center of the antenna array 32. The axis passing through the center of the antenna array 32 can be, for example, an axis AX extending in a direction perpendicular to the surface of the substrate 30 or an axis extending in a direction parallel to the surface of the substrate 30. Here, symmetry is determined based on the axis extending in a direction parallel to the surface of the substrate. The center of the antenna array 32 can be determined based on the planar shape of the conductors of the antenna array 32. The center of the antenna array 32 may also be the center of gravity of the conductors of the antenna array 32. The center of gravity can be determined based on the cross-sectional shape and planar shape. Therefore, multiple pairs of first shunt and second shunt elements connected to each other are arranged on the substrate 30, and at least two pairs of first shunt and second shunt elements are arranged symmetrically with respect to the axis passing through the center of the antenna array. This improves the directivity of the terahertz waves generated from the antenna array 32 and increases the frontal intensity of the terahertz waves.

In this embodiment, a configuration is adopted in which bias voltage is supplied from two paths using connection terminals 381 and 383, and ground voltage is supplied from one path using connection terminal 182. However, a configuration in which ground voltage is supplied from two paths using connection terminals 381 and 383, and bias voltage is supplied from one path using connection terminal 182 may also be used.

(Fourth embodiment)
An antenna device according to a fourth embodiment of the present disclosure will be described with reference to Figures 12 to 14. The antenna device according to the fourth embodiment differs from the antenna device according to the first embodiment in that pads are arranged on both sides of the chip, i.e., the pads and chip are arranged so that the chip is sandwiched between the pads. In this embodiment, a description of the same configuration as in the above embodiments will be omitted.

The antenna device 400 according to this embodiment shown in FIG. 12 has a chip 41 that includes a pad 441 for applying a bias voltage and a pad 442 for applying a ground voltage, similar to the first embodiment. Also, unlike the first embodiment, the antenna device 400 includes a pad 443 for applying a bias voltage and a pad 444 for applying a ground voltage.

Furthermore, in chip 41, pads 441 and 442 are arranged on the side of chip 41 where first side 411 is located, as viewed from antenna array 42. Furthermore, in chip 41, pads 443 and 444 are arranged on the side of chip 41 where second side 412, which faces first side 411 of chip 41, is located, as viewed from antenna array 42. This results in a configuration in which antenna array 42 is arranged between pads 441 and 442 and pads 443 and 444. In this way, pairs of first shunt elements and second shunt elements are arranged so that the antenna array is sandwiched between the two pairs of first shunt elements and second shunt elements.

In addition, chip 41 is provided with a resistive element 431, a capacitive element 432, and a resistive element 433 that form the first shunt element.

One terminal of the resistive element 431 is connected to one terminal of the capacitive element 432 via wiring and a via (not shown). The resistive element 431 is preferably arranged near the capacitive element 432. Alternatively, the resistive element 431 may be arranged overlapping the capacitive element 432. The other terminal of the resistive element 431 is connected to the pad 441 via the bias voltage line 430. The bias voltage line 430 is also arranged between each antenna 421 of the antenna array 42 and is commonly connected to each antenna 421, applying a bias voltage to each antenna 421.

One terminal of the resistive element 433 is connected to one terminal of the capacitive element 432 via wiring and a via (not shown). The resistive element 433 is preferably placed near the capacitive element 432. Alternatively, it may be placed on top of the capacitive element 432 so as to overlap it. The other terminal of the resistive element 433 is connected to the pad 443 via the bias voltage line 430. The other terminal of the capacitive element 432 is connected to the pads 442 and 444 via wiring and a via (not shown).

In the chip 41, a resistive element 431 and a resistive element 433 are disposed between the pads 441, 442 and the pads 443, 444. The antenna array 42, which is surrounded by a capacitive element 432, is disposed between the resistive elements 431 and 433. In this manner, the pads and the first shunt elements are disposed symmetrically with respect to an axis passing through the center of the antenna array 42 (axis BX extending perpendicular to the surface of the substrate 40 in the figure). Therefore, multiple pairs of first shunt and second shunt elements connected to each other are disposed on the substrate 40, and at least two pairs of first shunt and second shunt elements are disposed symmetrically with respect to the axis passing through the center of the antenna array. This improves the directivity of the terahertz waves generated from the antenna array 42 and increases the frontal intensity of the terahertz waves.

In the substrate 40, a resistive element 451 and a capacitive element 452 constituting a second shunt element are arranged in a first region 413 (the region surrounded by a dotted line in the figure) on the side of the first side 411 of the chip 41, as in the first embodiment. Furthermore, the first region 413 is also arranged with a pad 461 connected to the pad 441 of the chip 41 by a bonding wire 491, and a pad 462 connected to the pad 442 of the chip 41 by a bonding wire 492. Furthermore, the first region 413 is also arranged with a connection terminal 481 to which a bias voltage is supplied from a voltage bias circuit 471, and a connection terminal 482 to which a ground voltage is applied.

Also, in the substrate 40, a resistive element 453 and a capacitive element 454 that constitute the second shunt element are arranged in a second region 414 (the region surrounded by a dotted line in the figure) on the side of the second side 412 of the chip 41. Furthermore, the second region 414 also has arranged therein a pad 463 connected to the pad 443 of the chip 41 by a bonding wire 493, and a pad 464 connected to the pad 444 of the chip 41 by a bonding wire 494. Furthermore, the second region 414 also has arranged therein a connection terminal 483 to which a bias voltage is supplied from the voltage bias circuit 472, and a connection terminal 484 that supplies a ground voltage.

In the above description, the voltage bias circuits 471 and 472 are separate circuits, but the substrate 40 may also be configured so that the bias voltage and ground voltage are supplied by a single voltage bias circuit.

As described above, the substrate 40 is configured such that the chip 41 is disposed between the first region 413 and the second region 414. According to this configuration, the antenna array 42 is disposed between the pads 441 and 442 and the pads 443 and 444. In other words, the first region 413, the chip 41, and the second region 414 are disposed in this order along the line connecting the side 411 and the side 412. This configuration reduces the impedance of the wiring supplying the bias voltage. Furthermore, the chip 41 is disposed between the resistive element 451 or the capacitive element 452 and the resistive element 453 or the capacitive element 454. Therefore, similar to the first shunt element, the pads and the second shunt element are disposed symmetrically with respect to an axis passing through the center of the antenna array 42. The axis passing through the center of the antenna array 42 may be, for example, an axis BX extending perpendicular to the surface of the substrate 40 or an axis extending parallel to the surface of the substrate 40. Here, symmetry is determined based on the axis extending parallel to the surface of the substrate. Therefore, multiple pairs of first shunt and second shunt elements connected to each other are arranged on the substrate 40, and at least two pairs of first shunt and second shunt elements are arranged at positions symmetrical with respect to an axis passing through the center of the antenna array 42. This improves the directivity of the terahertz waves generated from the antenna array 42 and increases the frontal intensity of the terahertz waves.

Furthermore, according to this embodiment, the bias voltage applied to the antenna array 42 is supplied from the two opposing sides 411, 412 of the chip 41. This reduces the impedance of the wiring supplying the bias voltage, thereby reducing voltage drop, compared to when the bias voltage is supplied from one side of the chip 41. As a result, the variation between antennas in the bias voltage applied to the negative differential resistance elements of each antenna is reduced, improving the uniformity of the antenna output.

Furthermore, resistive element 451 and capacitive element 452, which constitute the second shunt element, are connected in parallel with resistive element 453 and capacitive element 454. Resistive elements 451, 453 and capacitive elements 452, 454 are, for example, SMDs, but such components have not only resistive and capacitive components but also parasitic inductance. Therefore, by connecting resistive element 451 and capacitive element 452 in parallel with resistive element 453 and capacitive element 454, parasitic inductance can be reduced, and parasitic oscillation can be suppressed.

In addition, since the wiring arranged on the substrate 40 also has a resistance value, the resistance of the wiring may be used as the resistive elements 451 and 453, which reduces the number of components arranged on the substrate 40 and is advantageous for miniaturization.

Figure 13 is a diagram illustrating an antenna device according to a modified example of this embodiment. Note that in this modified example, explanations of components similar to those in the above embodiment will be omitted. The configuration of antenna device 500 shown in Figure 13 is a configuration in which the features of this embodiment are further applied to the configuration described in the third embodiment. In this modified example, components similar to those in the third embodiment will be assigned the same reference numerals, and explanations will be omitted.

In the antenna device 500, resistor elements 531 and 533 and pads 541, 542, and 543 are arranged on the chip 51 on the side where the first side 511 of the chip 51 is located, as in the third embodiment. Furthermore, resistor elements 534 and 535 and pads 544, 545, and 546 are arranged on the side where the second side 512, which faces the first side 511 of the chip 51, is located.

An antenna array 52, which includes multiple antennas 521, is arranged between the first side 511 and the second side 512 of the chip 51. Capacitive elements 532 are arranged around the antenna array 52. The capacitive elements 532 are connected to resistive elements 531, 533, 534, and 535, respectively, to form first shunt elements.

One terminal of each of the resistive elements 531, 533, 534, and 535 is connected to one terminal of the capacitive element 532 via wiring and vias (not shown). The resistive elements 531, 533, 534, and 535 are preferably arranged near the capacitive element 532. Alternatively, the resistive elements 531, 533, 534, and 535 may be arranged overlapping the capacitive element 532. The other terminal of each of the resistive elements 531, 533, 534, and 535 is connected to the pad 541 via the bias voltage line 530. The bias voltage line 530 is also arranged between the antennas 521 of the antenna array 52 and connected in common to each antenna 521, thereby applying a bias voltage to each antenna 521. The other terminal of the capacitive element 532 is connected to the pads 542 and 545 via wiring and vias (not shown).

In the chip 51, resistor elements 531, 533 and resistor elements 534, 535 are arranged between pads 541, 542, 543 and pads 544, 545, 546. Furthermore, an antenna array 52, with a capacitor element 532 arranged around it, is arranged between the resistor elements 531, 533 and the resistor elements 534, 535. In this manner, the pads and first shunt elements are arranged symmetrically with respect to an axis passing through the center of the antenna array 52. The axis passing through the center of the antenna array 52 may be, for example, an axis CX extending in a direction perpendicular to the surface of the substrate 50 or an axis extending in a direction parallel to the surface of the substrate 50. Here, symmetry is determined based on the axis extending in a direction parallel to the surface of the substrate. Therefore, multiple pairs of first shunt and second shunt elements connected to each other are arranged on the substrate 50, and at least two pairs of first shunt and second shunt elements are arranged in positions symmetrical with respect to the axis passing through the center of the antenna array. This improves the directivity of the terahertz waves generated from the antenna array 52, and increases the frontal intensity of the terahertz waves.

Also, in the substrate 50, a first region 513 (the region surrounded by a dotted line in the figure) on the first side 511 of the chip 51 has a pad 561 connected to the pad 541 of the chip 51 by a bonding wire 591, as in the third embodiment. Furthermore, the first region 513 also has a pad 562 connected to the pad 542 by a bonding wire 592, and a pad 563 connected to the pad 543 by a bonding wire 593. Furthermore, the first region 513 also has resistive elements 551 and 553 and capacitive elements 552 and 554 that constitute a second shunt element. Furthermore, the first region 513 also has connection terminals 581 and 583 to which a bias voltage is supplied from a voltage bias circuit 571, and a connection terminal 582 that applies a ground voltage. The mutual connection relationships between the pads, second shunt elements, and connection terminals are the same as those described in the third embodiment.

In the above description, the voltage bias circuits 571 and 572 are separate circuits, but the substrate 50 may also be configured so that the bias voltage and ground voltage are supplied by a single voltage bias circuit.

In addition, in the substrate 50, a pad 564 is arranged in a second region 514 (the region surrounded by a dotted line in the figure) on the side of the second edge 512 of the chip 51, and is connected to the pad 544 of the chip 51 by a bonding wire 594. Furthermore, the second region 514 also has a pad 565 connected to the pad 545 by a bonding wire 595, and a pad 566 connected to the pad 546 by a bonding wire 596. Furthermore, the second region 514 also has resistive elements 555 and 557 and capacitive elements 556 and 558 that constitute a second shunt element. Furthermore, the second region 514 also has connection terminals 584 and 586 to which a bias voltage is supplied from a voltage bias circuit 572, and a connection terminal 585 that applies a ground voltage. The connection relationships among the pads, second shunt elements, and connection terminals in the second region 514 are the same as those described in the third embodiment.

In this manner, the chip 51 is disposed between the first region 513 and the second region 514 on the substrate 50. According to this configuration, the antenna array 52 is disposed between pads 541 and 544, between pads 542 and 545, or between pads 543 and 546. Furthermore, the chip 51 is disposed between resistive elements 551 and 553 and capacitive elements 552 and 554, and between resistive elements 555, 557 and capacitive elements 556 and 558. Therefore, the pads and second shunt elements are disposed symmetrically with respect to an axis passing through the center of the antenna array 52. The axis passing through the center of the antenna array 52 can be, for example, an axis CX extending perpendicular to the surface of the substrate 50, or an axis extending parallel to the surface of the substrate 50. Here, symmetry is determined based on the axis extending parallel to the surface of the substrate. Therefore, multiple pairs of first shunt and second shunt elements connected to each other are arranged on the substrate 50, with at least two pairs of first shunt and second shunt elements arranged symmetrically with respect to an axis passing through the center of the antenna array. This improves the directivity of the terahertz waves generated from the antenna array 52 and increases the frontal intensity of the terahertz waves.

Furthermore, by supplying the bias voltage from the two opposing sides 511, 512 of the chip 51, the impedance of the wiring supplying the bias voltage is reduced, thereby reducing voltage drop. As a result, the variation between antennas in the bias voltage applied to the negative differential resistance element of each antenna is reduced, improving the uniformity of the antenna output.

Furthermore, resistive element 551 and capacitive element 552 constituting the second shunt element are connected in parallel with resistive element 553 and capacitive element 554. Similarly, resistive element 555 and capacitive element 556 constituting the second shunt element are connected in parallel with resistive element 557 and capacitive element 558. As a result, the number of resistive elements and capacitive elements connected in parallel in antenna device 500 is greater than that in antenna device 400. Therefore, the parasitic inductance contained in the resistive elements and capacitive elements can be further reduced, and parasitic oscillation can be suppressed.

In addition, since the wiring arranged on the substrate 50 also has a resistance value, the resistance of the wiring may be used as the resistive elements 551, 553, 555, and 557, which reduces the number of components arranged on the substrate 50 and is advantageous for miniaturization.

Figure 14 is a diagram illustrating an antenna device according to a modified example of this embodiment. The configuration of the antenna device 600 shown in Figure 14 is a configuration in which the features of the second embodiment are further applied to the configuration of the antenna device 500 shown in Figure 13. Therefore, the antenna device according to this modified example is characterized in that the number of bonding wires connecting the pads in the above-mentioned antenna device is different. In the configuration of the antenna device shown in Figure 14, the description of the same configuration as the configuration of the antenna device 500 shown in Figure 13 will be omitted.

As shown in FIG. 14, in the antenna device 600, pads 641, 642, and 643 are arranged on the chip 61 on the side where the first side 611 of the chip 61 is located. Furthermore, pads 644, 645, and 646 are arranged on the side where the second side 612, which faces the first side 611 of the chip 61, is located.

In addition, in the substrate 60, pads 661, 662, and 663 are arranged in a first region 613 (the region surrounded by a dotted line in the figure) on the side of the first side 611 of the chip 61, similar to the configuration shown in FIG. 13. In addition, pads 664, 665, and 666 are arranged in a second region 614 (the region surrounded by a dotted line in the figure) on the side of the second side 612 of the chip 61.

Pads 641 and 661 are connected by multiple bonding wires 691, pads 642 and 662 are connected by multiple bonding wires 692, and pads 643 and 663 are connected by multiple bonding wires 693. Furthermore, pads 644 and 664 are connected by multiple bonding wires 694, pads 645 and 665 are connected by multiple bonding wires 695, and pads 646 and 666 are connected by multiple bonding wires 696.

In this modified example, as in the second embodiment, by electrically connecting multiple bonding wires in parallel, the combined inductance of the bonding wires can be reduced, thereby suppressing parasitic oscillation.

Fifth Embodiment
Next, an antenna device according to a fifth embodiment of the present disclosure will be described with reference to Figures 15 and 16. The antenna device according to the fifth embodiment is characterized in that pads are arranged near each side of the chip. In this embodiment, a description of the same configuration as in the other embodiments will be omitted.

The antenna device 700 according to this embodiment shown in Figure 15 includes pads 741 and 743 for applying a bias voltage and a pad 742 for applying a ground voltage on a chip 71. Furthermore, the antenna device 700 includes a pad 741 for applying a bias voltage and a pad 742 for applying a ground voltage.

In the antenna device 700 according to this embodiment, a pad 741 is arranged near a first side 711 of a chip 71, and a pad 742 is arranged near a second side 712. Furthermore, in the chip 71, a pad 743 is arranged near a third side 713 opposite the first side 711, and a pad 744 is arranged near a fourth side 714 opposite the second side 712. A bias voltage is applied to the pads 741 and 743, and a ground voltage is applied to the pads 742 and 744. The pads 741, 742, 743, and 744 are arranged around the antenna array 72 so as to surround the antenna array 72.

Also arranged on the chip 71 are resistive elements 731 and 733 and a capacitive element 732, which constitute a first shunt element. One terminal of the resistive element 731 and one terminal of the resistive element 733 are connected to one terminal of the capacitive element 732 via wiring and vias (not shown). The resistive elements 731 and 733 are preferably arranged adjacent to the capacitive element 732. Alternatively, the resistive element 731 may be arranged overlapping the capacitive element 732. The other terminal of the resistive element 731 is connected to a pad 741 via a bias voltage line 730, and the other terminal of the resistive element 733 is connected to a pad 743 via the bias voltage line 730. The bias voltage line 730 is also arranged between the antennas 721 of the antenna array 72 and is commonly connected to each antenna 721 to apply a bias voltage. The other terminal of the capacitive element 732 is connected to pads 742 and 744 via wiring and vias (not shown).

In the substrate 70, a first region 715 on the first side 711 of the chip 71 is arranged with a resistive element 751 and a capacitive element 758 that constitute a second shunt element, and a pad 761 that is connected to a pad 741 of the chip 71 by a bonding wire 791. Also arranged in the first region 715 is a connection terminal 781 to which a bias voltage is supplied from a voltage bias circuit 771. One terminal of the resistive element 751 and one terminal of the capacitive element 758 are connected to the pad 761, and the pad 761 is connected to the connection terminal 781.

Similarly, in a second region 716 on the second side 712 of the chip 71, a capacitance element 752 and a resistance element 753 constituting a second shunt element, and a pad 762 connected to a pad 742 of the chip 71 by a bonding wire 792 are arranged. Also, in the second region 716, a connection terminal 782 to which a ground voltage is supplied from a voltage bias circuit 772 is arranged. One terminal of the capacitance element 752 and one terminal of the resistance element 753 are connected to the pad 762, and the pad 762 is connected to the connection terminal 782.

Similarly, in a third region 717 on the third side 713 of the chip 71, a capacitance element 754 and a resistance element 755 that constitute a second shunt element, and a pad 763 that is connected to a pad 743 of the chip 71 by a bonding wire 793 are arranged. Also, in the third region 717, a connection terminal 783 to which a bias voltage is supplied from a voltage bias circuit 773 is arranged. One terminal of the capacitance element 754 and one terminal of the resistance element 755 are connected to the pad 763, and the pad 763 is connected to the connection terminal 783.

Similarly, in a fourth region 718 on the fourth side 714 of the chip 71, a capacitive element 756 and a resistive element 757 that constitute a second shunt element, and a pad 764 that is connected to a pad 744 of the chip 71 by a bonding wire 794 are arranged. Also arranged in the fourth region 718 is a connection terminal 784 to which a ground voltage is supplied from a voltage bias circuit 774. One terminal of the capacitive element 756 and one terminal of the resistive element 757 are connected to the pad 764, and the pad 764 is connected to the connection terminal 784.

A resistive element 751 and a capacitive element 752 are arranged near a first corner 726 formed by a first side 711 and a second side 712 of the chip 71, and the other terminal of the resistive element 751 is connected to the other terminal of the capacitive element 752. Further, a resistive element 753 and a capacitive element 754 are arranged near a second corner 727 formed by a second side 712 and a third side 713 of the chip 71, and the other terminal of the resistive element 753 is connected to the other terminal of the capacitive element 754. Further, a resistive element 755 and a capacitive element 756 are arranged near a third corner 728 formed by a third side 713 and a fourth side 714 of the chip 71, and the other terminal of the resistive element 755 is connected to the other terminal of the capacitive element 756. In addition, a resistive element 757 and a capacitive element 758 are arranged near a fourth corner 729 formed by the fourth side 714 and the first side 711 of the chip 71, and the other terminal of the resistive element 757 and the other terminal of the capacitive element 758 are connected.

Due to the connection relationship between the resistive element and the capacitive element, the resistive element 751 and the capacitive element 752, the resistive element 753 and the capacitive element 754, the resistive element 755 and the capacitive element 756, and the resistive element 757 and the capacitive element 758 that make up the second shunt element are electrically connected in parallel with each other. This allows the parasitic inductance contained in each element to be further reduced, suppressing parasitic oscillation.

In FIG. 15, voltage bias circuits 771, 772, 773, and 774 are shown as separate circuits, but the substrate 70 may also be configured so that the bias voltage and ground voltage are supplied by a single voltage bias circuit.

In addition, in Figure 15, the resistive element 751 and the capacitive element 752 that constitute the second shunt element are arranged so that the direction in which the two terminals of the resistive element 751 are aligned is perpendicular to the direction in which the two terminals of the capacitive element 752 are aligned. Furthermore, the resistive element 753 and the capacitive element 754, the resistive element 755 and the capacitive element 756, and the resistive element 757 and the capacitive element 758 are also arranged in a similar manner.

Furthermore, since the wiring arranged on the substrate 70 also has a resistance value, the resistance of the wiring may be used as the resistance elements 751, 753, 755, and 757, which allows the number of components arranged on the substrate 70 to be reduced, which is advantageous for miniaturization.

As described above, in this embodiment, a pad is arranged on each of the four sides of the chip 71, and a bias voltage or ground voltage is supplied from each side. This configuration can be expressed as follows: A pad, chip 71, and a pad are arranged in this order along the line connecting two opposing sides, and a pad, chip 71, and a pad are arranged in this order along the line connecting another two opposing sides. The direction along the line connecting two opposing sides intersects with the direction along the line connecting the other two opposing sides. With the configuration of this embodiment, the impedance of the wiring supplying the bias voltage is smaller than when the bias voltage or ground voltage is supplied from the side where one or two sides of the chip 71 are located, thereby reducing voltage drop. As a result, the variation between antennas in the bias voltage applied to the negative differential resistance element of each antenna is reduced, improving the uniformity of the antenna output.

In addition, because the pads are located on each side of the chip 71, the pads can be made larger while simultaneously electrically connecting multiple bonding wires in parallel. This reduces the combined inductance of the bonding wires, further suppressing parasitic oscillation.

Furthermore, by arranging the resistive and capacitive elements of the second shunt element near each of the four corners 726 to 729 of the chip 71 on the substrate 70, the space on the substrate can be effectively utilized, reducing the substrate size and suppressing manufacturing costs.

Furthermore, the pads and second shunt elements are arranged symmetrically with respect to an axis passing through the center of the antenna array 72. The axis passing through the center of the antenna array 72 may be, for example, an axis DX extending perpendicular to the surface of the substrate 70 or an axis extending parallel to the surface of the substrate 70. Here, symmetry is determined based on the axis extending parallel to the surface of the substrate. Therefore, multiple pairs of first shunt and second shunt elements connected to each other are arranged on the substrate 70, and at least two pairs of first shunt and second shunt elements are arranged in positions symmetrical with respect to the axis passing through the center of the antenna array. This improves the directivity of the terahertz waves generated from the antenna array 72 and increases the frontal intensity of the terahertz waves.

Figure 16 is a diagram illustrating an antenna device according to a modified example of this embodiment. Note that in this modified example, the description of the same configuration as in the above embodiment will be omitted. In the antenna device 800 shown in Figure 16, resistive element 851 and capacitive element 852, resistive element 853 and capacitive element 854, resistive element 855 and capacitive element 856, and resistive element 857 and capacitive element 858 are arranged near each of corners 826 to 829 of chip 81. Resistive elements 851, 853, 855, and 857, and capacitive elements 852, 854, 856, and 858 are arranged diagonally with respect to the extension direction of each side of the chip. The two terminals of resistive element 851 and the two terminals of capacitive element 852 are aligned in the same direction, and resistive element 853 and capacitive element 854, resistive element 855 and capacitive element 856, and resistive element 857 and capacitive element 858 are arranged in a similar manner.

By arranging each element in this way, the wiring connecting the resistors, capacitors, and pads can be shortened, reducing the parasitic inductance contained in the wiring and suppressing parasitic oscillation.

Sixth Embodiment
Next, an antenna array in an antenna device according to a sixth embodiment of the present disclosure will be described with reference to Fig. 17 to Fig. 22. In this embodiment, a description of the same configuration as in the other embodiments will be omitted.

Figure 17 shows an equivalent circuit diagram of the antenna device 900 according to this embodiment. The configuration example of the equivalent circuit diagram shown in Figure 17 corresponds to the configuration of the antenna array 12 in the equivalent circuit diagram of the antenna device 100 according to the first embodiment shown in Figure 5, in which the antennas 121 are arranged in a 3 x 3 matrix. The antenna array 912 has 3 x 3 negative differential resistance elements r11, r12, r13, r21, r22, r23, r31, r32, and r33, resistive elements Rai (i = 1, 2, 3..., 12), and capacitive elements Cai (i = 1, 2, 3..., 12). The antenna array 912 is configured with a negative differential resistance element and multiple third shunt elements, each of which is connected in series with a resistive element and a capacitive element. The 3 x 3 negative differential resistance elements and multiple third shunt elements are connected in parallel with each other. One terminal of each negative differential resistance element, one terminal of the resistance element Rai in the multiple third shunt elements, and one terminal of the resistance element Rc in the first shunt element are commonly connected. The other terminal of the resistance element Rai is connected to one terminal of the capacitance element Cai. Furthermore, the other terminal of each negative differential resistance element and the other terminal of the capacitance element Cai in the multiple third shunt elements are connected to ground potential. The rest of the configuration of the antenna array 912 is the same as that in Figure 5, so a description thereof will be omitted here.

In the antenna array 912, the combined resistance of the 3 x 3 negative differential resistance elements r11, r12, r13, r21, r22, r23, r31, r32, and r33 corresponds to the resistance r shown in Figure 5. Furthermore, the combined impedance of the third shunt element and the parasitic impedance of the wiring corresponds to the impedance Z shown in Figure 5.

FIG. 18 is an example of a top view of an antenna array 912 arranged in a 3×3 matrix corresponding to the equivalent circuit diagram of FIG. 17. FIG. 19 is a cross-sectional view taken along line CC′ in FIG. 18. The configuration described with reference to FIG. 4 will not be described again, and the same reference numerals are used for components similar to those in FIG. 4. As described with reference to FIG. 4, adjacent antennas are mutually coupled by microstrip lines 125a to 125h and are mutually injection locked (mutually synchronized) at the oscillation frequency f THz of the terahertz waves. FIG. 18 illustrates a configuration in which one antenna includes two negative differential resistance elements 127a and 127b. To improve the directivity of the terahertz waves, it is preferable that the two negative differential resistance elements 127a and 127b be arranged symmetrically with respect to a line passing through the center of one antenna.

A third shunt element is provided on the bias voltage line 130 to suppress parasitic oscillation in frequency bands lower than the oscillation frequency fTHz. The third shunt element is arranged in parallel with the negative differential resistance element to short out frequency bands lower than fTHz and suppress parasitic oscillation. The third shunt element also has a resistance element, or an element with a resistance and capacitance connected in series, arranged in parallel with the negative differential resistance element. The resistance and capacitance values of the third shunt element are such that the impedance of the element is equal to or slightly lower than the absolute value of the combined negative differential resistance of multiple negative differential resistance elements arranged nearby.

In Figure 18, the area surrounded by dashed line 137' in plan view is where conductor layer 137, which is one electrode of the capacitive element that constitutes the third shunt element, is located. Furthermore, resistor 138, which is a resistive element, is located in the area surrounded by dashed line 138'. Conductor layer 137 and resistor 138 are located below the wiring layer that constitutes bias voltage line 130. The third shunt element is located around each antenna. Bias voltage line 130 is connected to metal layer 123, which is part of each antenna, to supply bias voltage. The third shunt element is preferably located near this connection, and is preferably located between the antennas. This arrangement allows for a configuration in which one third shunt element is shared by adjacent antennas. This improves layout efficiency and enables chip miniaturization. Furthermore, the increased flexibility in adjusting the size of the shunt element's capacitance and resistance makes it easier to suppress parasitic oscillation.

As shown in the cross-sectional view of Figure 19, a dielectric layer 136 is disposed on the ground metal layer 124. Note that since the dielectric layer 136 is used as the dielectric for the capacitance of the third shunt element, it is preferable to use silicon nitride (ε = 7), which has a relatively high dielectric constant, in order to miniaturize the MIM capacitance structure.

In addition, a conductor layer 137 is laminated on top of the dielectric layer 136. Therefore, the antenna array 912 has a metal-insulator-metal (MIM) capacitance structure formed by laminating the ground metal layer 124, dielectric layer 136, and conductor layer 137 in this order, which corresponds to the capacitance element of the third shunt element. This capacitance element is disposed below the bias voltage line 130, which is disposed between the antennas. The conductor layer 137 is disposed in a layer between the bias voltage line 130 and the ground metal layer 124. A resistor 138 is connected to the conductor layer 137, and the resistor 138 is connected to the bias voltage line 130. This resistor 138 corresponds to the resistance element of the third shunt element.

In this manner, in this embodiment, the ground metal layer 124 and the bias voltage line 130 are electrically connected via the capacitive and resistive elements that constitute the third shunt element. Multiple third shunt elements are arranged within the array antenna, connected to the bias voltage line 130 at various locations between the antennas. In this embodiment, the third shunt element is connected to the ground metal layer 124, but it may also be connected to another conductive layer as long as it is connected to a conductive layer at a fixed potential.

Note that a configuration in which a third shunt element is placed at a node of the high-frequency electric field with an oscillation frequency of fTHz standing in the antenna has high impedance at the frequency of fTHz, making it more suitable for selectively oscillating only high-frequency signals at the frequency of fTHz. However, there is a risk of unexpected low-frequency multimode oscillation occurring as the number of arrays in the antenna array increases or the bias voltage line is shared. For this reason, in this embodiment, the bias voltage line 130 in the array antenna is configured to have a lower impedance than the negative resistance element in low-frequency bands below the oscillation frequency of fTHz. This makes it possible to suppress other-mode oscillations even when the number of antenna arrays increases, thereby achieving stable single-frequency oscillation in the terahertz band. The third shunt element can effectively suppress parasitic oscillations, particularly in frequency bands above 10 GHz but below fTHz.

Figure 20 is a top view of antenna array 1012, which is a modified version of antenna array 912 shown in Figure 18, and Figure 21 is a cross-sectional view taken along line D-D' in Figure 20. The same components as those in Figures 18 and 19 are designated by the same reference numerals, and their description will be omitted. Antenna array 1012 differs from antenna array 912 shown in Figures 18 and 19 in that the resistive element that constitutes the third shunt element is composed of resistor 138a and resistor 138b.

As shown in Figure 20, in the antenna array 1012, resistors 138a and 138b are arranged between the antennas 1112 and 1113. These two resistors 138a,
The resistor elements 138a and 138b correspond to the resistor element of the third shunt element, and are connected in parallel and in series with the capacitor element . The resistor elements 138a and 138b are disposed near the connection between the antennas 1112 and 1113 and the bias voltage line 130, and are disposed in a space formed by patterning and removing the wiring layer that constitutes the bias voltage line 130.

As shown in the cross-sectional view of Figure 21, resistors 138a and 138b are arranged at the same height as the bias voltage line 130. One end of resistor 138a and resistor 138b is connected to the bias voltage line 130, and the other end is connected to conductor layer 137 using the same wiring layer as the bias voltage line 130.

For antenna 1111 at the end of antenna array 1012, the third shunt element arranged in region 137'' that is not sandwiched between other antennas may be configured to have either resistor 138a or resistor 138b (138a in the figure) arranged as the resistive element.

The configuration of the antenna array 1012 shown in Figures 20 and 21 can be achieved by patterning and removing the wiring layer that makes up the bias voltage line 130 at the positions where resistors 138a and 138b are to be placed, and then forming the material that will become the resistors in the resulting space. This makes it easier to fabricate than conventional antenna arrays, and also reduces the occurrence of defects.

Here, we will use Figure 22 to further explain the first shunt element, second shunt element, and third shunt element. Figure 22 illustrates a configuration in which pads are arranged on two opposing sides of the chip described in the fourth embodiment, and the pads are connected by multiple bonding wires. In the following explanation, components similar to those described in the fourth embodiment are given the same reference numerals, and detailed explanations will be omitted.

The first shunt element consists of a resistive element 531 and a capacitive element 532, and is arranged around the antenna array 52 within the chip 51. A metal-insulator-metal (MIM) capacitor is suitable for the capacitive element 532.

The second shunt element consists of a resistive element 551 and a capacitive element 552, and is placed on the substrate 50 on which the chip 51 is mounted. Surface-mounted devices (SMD) are preferably used for the resistive element 551 and the capacitive element 552, and a ceramic capacitor, for example, is used for the capacitive element 552.

The third shunt element is made up of a resistive element (not shown) and a capacitive element 541 , and is arranged in the chip 51 in the same manner as the first shunt element, and is also arranged in the antenna array 52. The capacitive element 541 is preferably an MIM capacitor.

The areas or capacitance values of the capacitance elements constituting the three shunt elements preferably increase in the order of the third shunt element, the first shunt element, and the second shunt element (capacitance element 541 < capacitance element 532 < capacitance element 552). Capacitance element 541 can be suitably arranged if it is 1 pF or more and less than 100 pF, capacitance element 532 if it is 100 pF or more and less than 10 nF, and capacitance element 552 if it is 10 nF or more and less than 100 μF. Furthermore, resistance elements of the first shunt element, second shunt element, and third shunt element can be suitably arranged if it is 0.01 Ω or more and less than 10 Ω.

The number of third shunt elements is determined by the number of antennas in the antenna array 2, but it is preferable that the number be equal to or greater than the number of first shunt elements and the number of second shunt elements, which makes it possible to suppress parasitic oscillation and improve output.

When the number of antennas in the antenna array 2 is small, for example to adjust the output to a low level, the number of third shunt elements may be less than the number of first shunt elements and second shunt elements.

If the number of second shunt elements is equal to or greater than the number of first shunt elements, the number of second shunt elements connected in parallel can be increased. As a result, the parasitic inductance of the SMD can be reduced, thereby suppressing parasitic oscillation. Furthermore, reducing the number of first shunt elements reduces the chip area, contributing to lower costs for the antenna array.

When the number of second shunt elements is less than the number of first shunt elements, the number of SMDs that make up the second shunt elements can be reduced. Because the area required to mount SMDs on a board is relatively large, reducing the number of SMDs allows for the board size to be made smaller, contributing to lower costs for the antenna array.

Ta, Ti, Mo, Mn, Al, Ni, Nb, W, Ru, etc. are preferably used as resistors forming the resistance elements of the first shunt element and third shunt element within the chip. Furthermore, alloy films, oxide films, nitride films, silicide films, etc. of these metals (e.g., TiW, TiN, TaN, WN, WSiN, TaSiN, NbN, MoN, MnO, RuO) are also preferably used as the resistors. Furthermore, polysilicon, diffused resistive films in which impurities are doped into Si, etc. are also preferably used as the resistors.

Materials for wiring and conductive layers used within a chip preferably have a resistivity of 1×10 ⁻⁶ Ω·m or less. Specifically, metals and metal compounds such as Ag, Au, Cu, W, Ni, Cr, Ti, Al, AuIn alloys, and TiN are preferably used as materials.

The dielectric layers that make up MIM capacitors are required to have insulating properties (the ability to act as an insulator and high-resistance material that does not conduct electricity when subjected to DC voltage), barrier properties (the ability to prevent the diffusion of metal materials used in the electrodes), and processability (the ability to be processed with submicron precision). Specific examples of materials that meet these requirements include inorganic insulating materials such as silicon oxide (ε = 4), silicon nitride (ε = 7), aluminum oxide, and aluminum nitride.

The negative resistance element includes an electrode and a semiconductor layer, and the electrode is a conductor ohmically connected to the semiconductor layer, which is suitable for reducing ohmic loss and RC delay due to series resistance. When an electrode is used as an ohmic electrode, the material can be, for example, Ti/Pd/Au or Ti/Pt/Au.
, AuGe/Ni/Au, TiW, Mo, ErAs, etc. are preferably used.

Seventh Embodiment
A detection system according to this embodiment will be described with reference to Fig. 23 . The detection system may be a system capable of capturing images, such as a camera system. In this embodiment, a camera system will be used as an example. Fig. 23 is a schematic diagram illustrating the configuration of a camera system 2300 using terahertz waves.

The camera system 2300 has an oscillator 2301, a detector 2302, and a processor 2303. The oscillator 2301 can be an antenna device described in each embodiment. The detector 2302 is capable of detecting electromagnetic waves transmitted from the antenna device and may be, for example, an antenna device using other semiconductor elements such as a Schottky barrier diode. The terahertz waves emitted from the oscillator 2301 are reflected by the subject 2305 and detected by the detector 2302. The processor 2303 processes the signal detected by the detector 2302. The image data generated by the processor 2303 is output from the output unit 2304. With this configuration, a terahertz image can be acquired.

The oscillator 2301 and detector 2302 may be provided with an optical unit. The optical unit may be made of at least one material that is transparent to terahertz waves, such as polyethylene, Teflon (registered trademark), high-resistivity silicon, or polyolefin resin, and may be composed of multiple layers.

The camera system described in this embodiment is merely an example, and other forms may be used. In particular, the information acquired by the system is not limited to image information, and may also be a detection system that detects signals.

Each embodiment merely illustrates a specific example of how the present invention may be implemented, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features.

12 Antenna array, 17 Voltage bias circuit, 100 Antenna device, 131, 151 Resistive element, 132, 152 Capacitive element, 1200 Resonant circuit, 1300 First shunt element, 1500 Second shunt element

Claims (31)

An antenna device for transmitting or receiving electromagnetic waves,
an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged;
a voltage bias circuit for applying a voltage to the antenna array;
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series;
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series;
and
the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element ,
An antenna device characterized in that the following formulas (1) to (3) are satisfied:
Rp +1/(2π×f×Cp) < r...(1)
Rc +1/(2π×f×Cc) < r...(2)
L/(Cc×r) <Rc...(3)
Here, r is the absolute value of the resistance value of the negative differential resistance element, Rp is the resistance value of the second resistor, Cp is the capacitance value of the second capacitor, Rc is the resistance value of the first resistor, Cc is the capacitance value of the first capacitor, L is the inductance of the path connecting the first shunt element and the second shunt element, and f is a frequency less than the resonant frequency of the resonant circuit. The inductance L of the path connecting the first shunt element and the second shunt element satisfies the following formula (4):
L≦5 nH (4)
When the path is divided into a first portion whose cross section can be approximated to a circle and a second portion whose cross section can be approximated to a rectangle, the inductance L1 of the first portion is calculated by the following formula (5), and the inductance L2 of the second portion is calculated by the following formula (6).
The antenna device according to claim 1 , wherein the calculation is performed by: L1=0.2×l1×[ln(4×l1/d)−0.75] (5)
L2=0.2×l2×[ln{2×l2/(w + h)}+0.2235×(w+h)/l2+0.5] ...(6)
where l1 is the length of the first portion, d is the cross-sectional diameter of the first portion, l2 is the length of the second portion, w is the width of the second portion, and h is the thickness of the second portion. An antenna device for transmitting or receiving electromagnetic waves,
an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged;
a voltage bias circuit for applying a voltage to the antenna array;
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series;
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series;
and
the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element,
The inductance L of the path connecting the first shunt element and the second shunt element satisfies the following formula (4):
L≦5 nH (4)
When the path is divided into a first portion whose cross section can be approximated to a circle and a second portion whose cross section can be approximated to a rectangle, an inductance L1 of the first portion is calculated by the following formula (5), and an inductance L2 of the second portion is calculated by the following formula (6),
L1=0.2×l1×[ln(4×l1/d)-0.75]...(5)
L2=0.2×l2×[ln{2×l2/(w + h)}+0.2235×(w+h)/l2+0.5] ...(6)
where l1 is the length of the first portion, d is the cross-sectional diameter of the first portion, l2 is the length of the second portion, w is the width of the second portion, and h is the thickness of the second portion. a plurality of pairs of the first shunt element and the second shunt element are arranged;
4. The antenna device according to claim 1, wherein at least two pairs of the first shunt element and the second shunt element are arranged symmetrically with respect to an axis passing through the center of the antenna array. The antenna device described in claim 4, characterized in that the two pairs of the first shunt element and the second shunt element are arranged so that the antenna array is sandwiched between the two pairs of the first shunt element and the second shunt element. the first shunt element is disposed on a chip on which the antenna array is disposed;
The chip is a square chip,
6. The antenna device according to claim 4, wherein the second shunt element of each pair of the first shunt element and the second shunt element is arranged near a corner of the chip. 5. The antenna device according to claim 4, wherein the second shunt elements of each of the two pairs of the first shunt element and the second shunt element are connected in parallel. the first shunt element is disposed on a chip on which the antenna array is disposed;
The antenna device according to claim 1 , wherein the second shunt element is disposed on a substrate on which the chip is disposed. a path connecting the first shunt element and the second shunt element includes a first pad disposed on the chip and a second pad disposed on the substrate;
9. The antenna device according to claim 8, wherein a bias voltage is supplied to the antenna array via the first pad and the second pad. the antenna device further includes a third pad disposed on the chip and a fourth pad disposed on the substrate;
a ground voltage is supplied to the antenna array via the third pad and the fourth pad;
The chip is a square chip,
a bias voltage is supplied to the antenna array from the side of the chip where the first side is located via the first pad and the second pad;
10. The antenna device according to claim 9, wherein a ground voltage is supplied to the antenna array via the third pad and the fourth pad from a side of the chip where a second side different from the first side is located. An antenna device as described in claim 9 or 10, characterized in that the first pad and the second pad are connected by multiple bonding wires connected in parallel. An antenna device described in any one of claims 8 to 10, characterized in that the second resistor is a wiring arranged on the substrate. An antenna device for transmitting or receiving electromagnetic waves,
a chip having an antenna array in which a plurality of antennas each consisting of a negative differential resistance element and a resonant circuit are arranged;
a substrate on which the chip is disposed;
a voltage bias circuit for applying a voltage to the antenna array;
The chip is
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, the first shunt element including at least a first capacitance;
a plurality of pads including at least a first pad and a second pad for supplying a predetermined voltage to the antenna array;
The substrate is
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, including at least a second capacitance, and disposed on the substrate;
The antenna device is characterized in that the antenna array is located between the first pad and the second pad. An antenna device described in any one of claims 1 to 13, characterized in that the combined resistance value of the negative differential resistance elements of the antenna array is 1 Ω or less. An antenna device described in any one of claims 1 to 14, characterized in that the length of the path connecting the first shunt element and the second shunt element is 4 mm or less. The antenna device described in claim 15, characterized in that the length of the path connecting the first shunt element and the second shunt element is 2 mm or less. An antenna device described in any one of claims 1 to 16, characterized in that the frequency band of the electromagnetic waves includes at least a portion of the frequency band from 30 GHz to 30 THz. An antenna device described in any one of claims 1 to 17, characterized in that the negative differential resistance element is a resonant tunneling diode. 19. The antenna device according to claim 1, wherein the first capacitor is a metal-insulator-metal (MIM) capacitor. An antenna device according to any one of claims 1 to 19, characterized in that the antenna array includes a third shunt element connected in parallel to the negative differential resistance element and including at least a third capacitance. The antenna device described in claim 20, characterized in that multiple third shunt elements are arranged between the antennas. The antenna device described in claim 21, characterized in that the third shunt element is shared by antennas on both sides of the third shunt element. The antenna device described in claim 20, characterized in that the area or capacitance value of the third capacitance is largest, followed by the first capacitance and the second capacitance. The antenna device described in claim 20, characterized in that the number of the third shunt elements is equal to or greater than the number of the first shunt elements and equal to or greater than the number of the second shunt elements. The antenna device described in claim 20, characterized in that the number of the third shunt elements is less than the number of the first shunt elements and less than the number of the second shunt elements. The antenna device described in any one of claims 1 to 19, characterized in that the number of the second shunt elements is equal to or greater than the number of the first shunt elements. An antenna device according to any one of claims 1 to 19, characterized in that the number of second shunt elements is less than the number of first shunt elements. An antenna device for transmitting or receiving electromagnetic waves,
an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged;
a voltage bias circuit for applying a voltage to the antenna array;
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series;
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series;
and
The first shunt element and the second shunt element have a resistance value of the negative differential resistance element.
It has low impedance based on
The antenna device further comprises a third shunt element connected in parallel to the negative differential resistance element and including at least a third capacitance, in the antenna array. An antenna device for transmitting or receiving electromagnetic waves,
a chip having an antenna array in which a plurality of antennas each consisting of a negative differential resistance element and a resonant circuit are arranged;
a substrate on which the chip is disposed;
a voltage bias circuit for applying a voltage to the antenna array;
The chip is
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, the first shunt element including at least a first capacitance;
a plurality of pads including at least a first pad and a second pad for supplying a predetermined voltage to the antenna array;
The substrate is
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit, including at least a second capacitance, and disposed on the substrate;
the antenna array is located between the first pad and the second pad;
The antenna device further comprises a third shunt element connected in parallel to the negative differential resistance element and including at least a third capacitance, in the antenna array. An antenna device for transmitting or receiving electromagnetic waves,
an antenna array in which a plurality of antennas, each of which is formed by a negative differential resistance element and a resonant circuit, are arranged;
a voltage bias circuit for applying a voltage to the antenna array;
a first shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the antenna array and the voltage bias circuit, the first shunt element having a first resistance and a first capacitance connected in series;
a second shunt element connected in parallel to the negative differential resistance element and the voltage bias circuit between the first shunt element and the voltage bias circuit, the second shunt element having a second resistance and a second capacitance connected in series;
and
the first shunt element and the second shunt element have low impedance with respect to the resistance value of the negative differential resistance element,
a plurality of pairs of the first shunt element and the second shunt element are arranged;
An antenna device, characterized in that at least two pairs of the first shunt element and the second shunt element are arranged at positions symmetrical with respect to an axis passing through the center of the antenna array. an antenna device according to any one of claims 1 to 30 ;
a detection device for detecting electromagnetic waves transmitted from the antenna device;
a processing unit for processing signals from the detection device.