JP7746737B2 - Rectifier circuit and power receiving control device - Google Patents

Description

The present invention relates to a rectifier circuit, a power receiving control device, etc.

Rectifier circuits that rectify AC voltages and output a rectified voltage are known. A known example of such a rectifier circuit is the circuit disclosed in Patent Document 1. The rectifier circuit in Patent Document 1 uses a Schottky diode as the rectifier element on the upper side (high potential side), and an N-type transistor as the rectifier element on the bottom side (low potential side).

JP 2013-255392 A

However, although Patent Document 1 discloses the circuit configuration of the rectifier circuit, it does not disclose the layout arrangement of the rectifier circuit. In particular, it does not propose a layout arrangement that can reduce power loss during power reception.

One aspect of the present disclosure is a rectifier circuit that receives a first AC voltage and a second AC voltage that is opposite in phase to the first AC voltage, and outputs a first rectified voltage on the high potential side and a second rectified voltage on the low potential side, the rectifier circuit comprising: a first input line to which the first AC voltage is supplied and that is wired along a first direction; a second input line to which the second AC voltage is supplied and that is wired along the first direction on the second direction side of the first input line, where a direction perpendicular to the first direction is defined as a second direction; a first output line that is an output line for the first rectified voltage and that is wired along the second direction; and a second output line for the second rectified voltage that is wired along the second direction on the first direction side of the first output line. The present invention relates to a rectifier circuit including an output line, a first rectifier element arranged in a plan view corresponding to the intersection of the first input line and the first output line and connected between the first input line and the first output line, a second rectifier element arranged in a plan view corresponding to the intersection of the second input line and the first output line and connected between the second input line and the first output line, a third rectifier element arranged in a plan view corresponding to the intersection of the first input line and the second output line and connected between the first input line and the second output line, and a fourth rectifier element arranged in a plan view corresponding to the intersection of the second input line and the second output line and connected between the second input line and the second output line.

Another aspect of the present disclosure relates to a power receiving control device that includes a power receiving circuit that includes the rectifier circuit described above, and a power supply circuit that supplies power based on the power received by the power receiving circuit.

3 shows an example of the configuration of a rectifier circuit according to the present embodiment. 3 shows an example of a layout of a rectifier circuit according to the present embodiment. 3 shows a detailed layout example of the rectifier circuit of the present embodiment. 1 shows a first configuration example of a rectifier circuit according to the present embodiment. 10 shows a second configuration example of the rectifier circuit of the present embodiment. 10 shows a third configuration example of the rectifier circuit of the present embodiment. FIG. 4 is a diagram illustrating the operation of the rectifier circuit of the first configuration example. FIG. 4 is a diagram illustrating the operation of the rectifier circuit of the first configuration example. FIG. 10 is a signal waveform diagram illustrating the operation of the rectifier circuit of the second configuration example. FIG. 10 is a signal waveform diagram illustrating the operation of the rectifier circuit of the third configuration example. 3 shows a detailed layout example of the rectifier circuit of the present embodiment. 3 shows a detailed layout example of the rectifier circuit of the present embodiment. FIG. 10A and 10B are cross-sectional views of different aspects of a rectifier circuit. 10A and 10B are diagrams illustrating the operation of a rectifier circuit according to a different embodiment. 2 shows an example of the configuration of a power receiving control device according to the present embodiment. 2 shows an example of the configuration of a power receiving control device according to the present embodiment.

A preferred embodiment of the present invention will be described in detail below. Please note that the embodiment described below does not unduly limit the content of the present invention as set forth in the claims, and not all of the configurations described in the embodiment are necessarily essential as a solution to the present invention.

1. Rectifier Circuit FIG. 1 shows an example of the configuration of a rectifier circuit 10 according to this embodiment. The rectifier circuit 10 receives AC voltages VC1 and VC2 as input and outputs rectified voltages VCC and VSS. The AC voltage VC1 is a first AC voltage, and the AC voltage VC2 is a second AC voltage that is out of phase with the AC voltage VC1. The rectified voltage VCC is a first rectified voltage on the high potential side, and the rectified voltage VSS is a second rectified voltage on the low potential side. Specifically, the rectifier circuit 10 receives the first AC voltage VC1 and the second AC voltage VC2 that is out of phase with VC1, and outputs the first rectified voltage VCC on the high potential side and the second rectified voltage VSS on the low potential side, for example, by full-wave rectification. In FIG. 1, the AC voltages VC1 and VC2 are supplied from an AC power source 12.

The rectifier circuit 10 includes rectifier elements RF1, RF2, RF3, and RF4. RF1 is the first rectifier element, RF2 is the second rectifier element, RF3 is the third rectifier element, and RF4 is the fourth rectifier element. As described below, diodes can be used as the rectifier elements, and more preferably, Schottky diodes can be used. Transistors may also be used as the rectifier elements. Rectifier element RF1 is provided between node N1, which is the input node for AC voltage VC1, and node NH, which is the output node for rectified voltage VCC. The forward direction of the rectifier element is from node N1 toward node NH. The forward direction is the rectification direction. Rectifier element RF2 is provided between node N2, which is the input node for AC voltage VC2, and node NH. The forward direction of the rectifier element is from node N2 toward node NH. Rectifier element RF3 is provided between node NL, which is the output node for rectified voltage VSS, and node N1, and is a rectifier element whose forward direction is from node NL to node N1. Rectifier element RF4 is provided between node NL and node N2, and is a rectifier element whose forward direction is from node NL to node N2. Note that the rectifier circuit 10 of this embodiment is not limited to the configuration shown in FIG. 1, and modifications such as the addition of other components are possible.

Figure 2 shows an example layout of the rectifier circuit 10 of this embodiment. Figure 2 shows the layout of circuit elements and wiring when viewed in a plan view perpendicular to the semiconductor substrate on which the rectifier circuit 10 is formed. In Figure 1, the direction perpendicular to direction DR1 is direction DR2, the direction opposite direction DR1 is direction DR3, and the direction opposite direction DR2 is direction DR4. Directions DR1, DR2, DR3, and DR4 are the first direction, second direction, third direction, and fourth direction, respectively. Note that in Figure 2, directions DR1, DR2, DR3, and DR4 are respectively right, down, left, and up on the page, but this embodiment is not limited to this. For example, various modifications are possible, such as directions DR1 and DR3 being left and right, respectively, or directions DR2 and DR4 being up and down, respectively.

The rectifier circuit 10 includes the rectifier elements RF1, RF2, RF3, and RF4 described in FIG. 1, input lines I1 and I2, and output lines Q1 and Q2. The input line I1 is the first input line, the input line I2 is the second input line, the output line Q1 is the first output line, and the output line Q2 is the second output line.

The first input line, input line I1, is supplied with a first AC voltage, VC1, and is wired along direction DR1. That is, input line I1 is wired with direction DR1 as its longitudinal direction. Direction DR1 is the first direction. The second input line, input line I2, is wired along direction DR1 on the direction DR2 side of input line I1, where direction DR2 is the direction perpendicular to direction DR1. That is, input line I2 is placed on the direction DR2 side of input line I1 and wired with direction DR1 as its longitudinal direction. Direction DR2 is the second direction. The first output line, output line Q1, is an output line for VCC, the first rectified voltage on the high potential side, and is wired along direction DR2. That is, output line Q1 is wired with direction DR2 as its longitudinal direction, and outputs the rectified voltage VCC rectified by rectifier circuit 10. The second output line, output line Q2, outputs VSS, a second rectified voltage on the low potential side, and is wired along direction DR2 on the direction DR1 side of output line Q1. That is, output line Q2 is positioned on the direction DR1 side of output line Q1, is wired with direction DR2 as its longitudinal direction, and outputs the rectified voltage VSS rectified by rectifier circuit 10.

The first rectifier element RF1 is arranged corresponding to the intersection of the input line I1 and the output line Q1 in a plan view, and is connected between the input line I1 and the output line Q1. That is, as shown in FIG. 1, the rectifier element RF1 is connected between the input line I1 of the AC voltage VC1 corresponding to the node N1 and the output line Q1 of the rectified voltage VCC corresponding to the node NH, and performs rectification operation with the direction from the input line I1 to the output line Q1 as the forward direction. The rectifier element RF1 is arranged, for example, in a region corresponding to the intersection region of the input line I1 and the output line Q1. Note that the plan view is, for example, a plan view perpendicular to the semiconductor substrate on which the rectifier circuit 10 is formed.

The second rectifier element RF2 is arranged corresponding to the intersection of the input line I2 and the output line Q1 in a plan view, and is connected between the input line I2 and the output line Q1. That is, as shown in FIG. 1, the rectifier element RF2 is connected between the input line I2 for the AC voltage VC2 corresponding to the node N2 and the output line Q1 for the rectified voltage VCC corresponding to the node NH, and performs rectification operation with the direction from the input line I2 to the output line Q1 as the forward direction. The rectifier element RF2 is arranged, for example, in the area corresponding to the intersection of the input line I2 and the output line Q1.

The third rectifier element RF3 is arranged corresponding to the intersection of the input line I1 and the output line Q2 in a plan view, and is connected between the input line I1 and the output line Q2. That is, as shown in FIG. 1, the rectifier element RF3 is connected between the input line I1 of the AC voltage VC1 corresponding to the node N1 and the output line Q2 of the rectified voltage VSS corresponding to the node NL, and performs rectification operation with the direction from the output line Q2 to the input line I1 as the forward direction. The rectifier element RF3 is then arranged, for example, in the area corresponding to the intersection region of the input line I1 and the output line Q2.

The fourth rectifier element RF4 is arranged corresponding to the intersection of the input line I2 and the output line Q2 in a plan view, and is connected between the input line I2 and the output line Q2. That is, as shown in FIG. 1, the rectifier element RF4 is connected between the input line I2 of the AC voltage VC2 corresponding to the node N2 and the output line Q2 of the rectified voltage VSS corresponding to the node NL, and performs rectification operation with the direction from the output line Q2 to the input line I2 as the forward direction. The rectifier element RF4 is then arranged, for example, in the area corresponding to the intersection region of the input line I2 and the output line Q2.

In this embodiment, the input lines I1 and I2 for the AC voltages VC1 and VC2 are wired along direction DR1, and the output lines Q1 and Q2 for the rectified voltage VCC are wired along direction DR2, which is perpendicular to direction DR1. Rectifier elements RF1 and RF2 are arranged in the region corresponding to the intersection of the input lines I1 and I2 with the output line Q1, and rectifier elements RF3 and RF4 are arranged in the region corresponding to the intersection of the input lines I1 and I2 with the output line Q2. This reduces parasitic resistance between the input line I1 and one end of the rectifier element RF1, and between the other end of the rectifier element RF1 and the output line Q1, and also reduces parasitic resistance between the input line I2 and one end of the rectifier element RF2, and between the other end of the rectifier element RF2 and the output line Q1. Similarly, parasitic resistance can be reduced between the input line I1 and one end of the rectifying element RF3, and between the other end of the rectifying element RF3 and the output line Q2, and between the input line I2 and one end of the rectifying element RF4, and between the other end of the rectifying element RF4 and the output line Q2. Reducing parasitic resistance in this way lowers impedance during rectification, reducing power loss in the rectifying circuit 10. Furthermore, efficient layout arrangement of the rectifying elements RF1, RF2, RF3, and RF4, as well as efficient layout wiring of the input lines I1 and I2 and the output lines Q1 and Q2, can be achieved, and the layout area of the rectifying circuit 10 can also be reduced.

Figure 3 shows a detailed layout example of the rectifier circuit 10 of this embodiment. In Figure 3, the rectifier circuit 10 includes an input line group GI1 including input line I1, an input line group GI2 including input line I2, an output line group GQ1 including output line Q1, and an output line group GQ2 including output line Q2. The input line group GI1 is the first input line group, the input line group GI2 is the second input line group, the output line group GQ1 is the first output line group, and the output line group GQ2 is the second output line group.

As shown in Figure 3, each input line of input line group GI1 is arranged along direction DR1, and each input line of input line group GI2 is arranged along direction DR1 on the direction DR2 side of input line group GI1. Furthermore, each output line of output line group GQ1 is arranged along direction DR2 perpendicular to direction DR1, and each output line of output line group GQ2 is wired along direction DR2 on the direction DR1 side of output line group GQ1. For example, output line group GQ1 is wired so as to intersect with input line groups GI1 and GI2, and output line group GQ2 is wired so as to intersect with input line groups GI1 and GI2 on the direction DR1 side of output line group GQ1. In this way, AC voltages VC1 and VC2 can be input to rectifier circuit 10 via multiple input lines in input line groups GI1 and GI2, and rectified voltages VCC and VSS can be output from rectifier circuit 10 via multiple output lines in output line groups GQ1 and GQ2. This makes it possible to reduce power receiving losses by reducing parasitic resistance, and to achieve proper layout wiring, for example.

Also in FIG. 3, the rectifier circuit 10 includes a rectifier element group GRF1 including rectifier element RF1 and a rectifier element group GRF2 including rectifier element RF2. The rectifier element group GRF1 is the first rectifier element group, and the rectifier element group GRF2 is the second rectifier element group. The rectifier element group GRF1 is arranged corresponding to the intersection of the input line group GI1 and the output line group GQ1, and the rectifier element group GRF2 is arranged corresponding to the intersection of the input line group GI2 and the output line group GQ1. For example, the rectifier element group GRF1 is arranged in a region corresponding to the intersection region of the input line group GI1 and the output line group GQ1, and the rectifier element group GRF2 is arranged in a region corresponding to the intersection region of the input line group GI2 and the output line group GQ1. Specifically, the rectifier element group GRF1 includes, for example, a plurality of rectifier elements arranged in parallel, and the rectifier element group GRF2 includes, for example, a plurality of rectifier elements arranged in parallel. For example, the rectifying elements of the rectifying element group GRF1 are arranged in areas corresponding to the intersections of the input lines of the input line group GI1 and the output lines of the output line group GQ1. Furthermore, the rectifying elements of the rectifying element group GRF2 are arranged in areas corresponding to the intersections of the input lines of the input line group GI2 and the output lines of the output line group GQ1. In this way, the rectifying operation of the rectifying circuit 10 can be performed by the rectifying element group GRF1, which includes multiple rectifying elements, and the rectifying element group GRF2, which also includes multiple rectifying elements. This further reduces the power receiving loss of the rectifying circuit 10, enabling efficient rectifying operation.

The rectifier circuit 10 also includes a rectifier element group GRF3 including rectifier element RF3, and a rectifier element group GRF4 including rectifier element RF4. The rectifier element group GRF3 is the third rectifier element group, and the rectifier element group GRF4 is the fourth rectifier element group. The rectifier element group GRF3 is arranged corresponding to the intersection of the input line group GI1 and the output line group GQ2, and the rectifier element group GRF4 is arranged corresponding to the intersection of the input line group GI2 and the output line group GQ2. For example, the rectifier element group GRF3 is arranged in a region corresponding to the intersection region of the input line group GI1 and the output line group GQ2, and the rectifier element group GRF4 is arranged in a region corresponding to the intersection region of the input line group GI2 and the output line group GQ2. Specifically, the rectifier element group GRF3 includes, for example, a plurality of rectifier elements arranged in parallel, and the rectifier element group GRF4 includes, for example, a plurality of rectifier elements arranged in parallel. For example, each rectifying element of the rectifying element group GRF3 is arranged in an area corresponding to the intersection of each input line of the input line group GI1 and each output line of the output line group GQ2. Furthermore, each rectifying element of the rectifying element group GRF4 is arranged in an area corresponding to the intersection of each input line of the input line group GI2 and each output line of the output line group GQ2.

2. Detailed Configuration Example of Rectifier Circuit FIG. 4 shows a first configuration example of the rectifier circuit 10. In FIG. 4, diodes D1 and D2 are provided as the rectifier elements RF1 and RF2 in FIG. 1. Diode D1 is the first diode, specifically a first Schottky barrier diode. Diode D2 is the second diode, specifically a second Schottky barrier diode. Also in FIG. 4, diodes D3 and D4 are provided as the rectifier elements RF3 and RF4. Diode D3 is the third diode, specifically a third Schottky barrier diode. Diode D4 is the fourth diode, specifically a fourth Schottky barrier diode. Schottky barrier diodes utilize a Schottky barrier created by a junction between a metal and a semiconductor. Schottky barrier diodes operate using majority carriers, and therefore have the characteristics of a smaller forward voltage drop and faster switching speed than PN junction diodes. Note that a modified implementation using PN junction diodes as diodes D1, D2, D3, and D4 is also possible. A PN junction diode is a diode formed by the junction of a P-type semiconductor region and an N-type semiconductor region.

Diodes D1 and D2 have a cathode at node NH, which is the output node of rectified voltage VCC. Diode D1 has an anode at node N1, which is the input node of AC voltage VC1, and diode D2 has an anode at node N2, which is the input node of AC voltage VC2. Diodes D3 and D4 have an anode at node NL, which is the output node of rectified voltage VSS. Diode D3 has a cathode at node N1, and diode D4 has a cathode at node N2. In FIG. 4 and FIGS. 5 and 6, AC voltage VC1 is output from one end of coil L, which receives power, and AC voltage VC2 is output from the other end of coil L. Coil L, for example, is the secondary coil L2 in the non-contact power transmission shown in FIG. 17, which will be described later, and receives transmitted power from power transmission device 70.

Figure 5 shows a second configuration example of the rectifier circuit 10. In Figure 5, diodes D1 and D2 are provided as rectifier elements RF1 and RF2, and transistors T1 and T2 are provided as rectifier elements RF3 and RF4. In Figure 5, diodes D1 and D2 are Schottky barrier diodes, but a modification in which they are PN junction diodes is also possible. Transistor T1 is the first transistor, and transistor T2 is the second transistor. Transistors T1 and T2 are, for example, N-type transistors, such as MOS N-type transistors. The gate of transistor T1 is connected to node N2, which is the input node for AC voltage VC2, and the gate of transistor T2 is connected to node N1, which is the input node for AC voltage VC1. That is, in Figures 2 and 3, the gate of transistor T1, which is the first transistor, is connected to input line I2, which is the second input line. The gate of transistor T2, which is the second transistor, is connected to input line I1, which is the first input line. Additionally, a parasitic diode DP1 is formed between the drain and source of transistor T1, and this parasitic diode DP1 also functions as a rectifying element RF3. Additionally, a parasitic diode DP2 is formed between the drain and source of transistor T2, and this parasitic diode DP2 also functions as a rectifying element RF4. Parasitic diodes DP1 and DP2 are formed by PN junctions between the drain and source of transistors T1 and T2, and are also called body diodes.

Figure 6 shows a third configuration example of the rectifier circuit 10. In Figure 6, diodes D1 and D2 are provided as rectifier elements RF1 and RF2. Rectifier element RF3 includes transistor T1, which is a first transistor, and diode D3, which is connected in parallel to transistor T1. Diode D3 is a third Schottky barrier diode. Rectifier element RF4 includes transistor T2, which is a second transistor, and diode D4, which is connected in parallel to transistor T2. Diode D4 is a fourth Schottky barrier diode. The gate of transistor T1 is connected to node N2, which is connected to input line I2 in Figures 2 and 3. The gate of transistor T2 is connected to node N1, which is connected to input line I1 in Figures 2 and 3. Note that a variation in which PN junction diodes are provided as diodes D1, D2, D3, and D4 is also possible.

Figures 7 and 8 are diagrams illustrating the operation of the rectifier circuit 10 of the first configuration example of Figure 4. As shown in Figure 7, current ID1 from node N1 of AC voltage VC1 flows to load 14 via diode D1, and then flows from load 14 via diode D4 to node N2 of AC voltage VC2. Current ID2 from node N2 of AC voltage VC2 flows to load 14 via diode D2, and then flows from load 14 via diode D3 to node N1 of AC voltage VC1. The paths along which currents ID1 and ID2 flow are similar in the rectifier circuits 10 of the second and third configuration examples of Figures 5 and 6. In Figure 7, a capacitor 16 for smoothing the rectified voltages VCC and VSS is provided between node NH of rectified voltage VCC and node NL of rectified voltage VSS.

Figure 8 shows the waveforms of the forward voltage VF and current ID1 of diode D1 in Figure 7. When diode D1 is a Schottky barrier diode, as shown in B1 of Figure 8, the forward voltage VF when forward current ID1 flows through diode D1 can be reduced to, for example, approximately 0.4 V. On the other hand, when diode D1 is a PN junction diode, as shown in B2, the forward voltage VF when forward current ID1 flows through diode D1 is higher than that of a Schottky barrier diode, for example, approximately 0.7 V. Furthermore, when a reverse voltage is applied to diode D1, the power loss can be reduced with a Schottky barrier diode, as shown in B3, but with a PN junction diode, the power loss is increased, as shown in B4. Thus, using Schottky barrier diodes for diodes D1 to D4 is advantageous over using PN junction diodes in that it allows for a lower forward voltage VF and reduces power loss.

Figure 9 is a signal waveform diagram illustrating the operation of the rectifier circuit 10 of the second configuration example shown in Figure 5. The period indicated by E1 in Figure 9 is when a forward voltage is applied to diode D1, turning on transistor T2, and a reverse voltage is applied to diode D2, turning off transistor T1. Specifically, when AC voltage VC1 exceeds the threshold voltage of transistor T2, transistor T2 turns on. When AC voltage VC1 exceeds rectified voltage VCC, forward current flows through diode D1. As a result, as in Figure 7, current ID1 from node N1 of AC voltage VC1 flows through diode D1, load 14, and transistor T2 to node N2 of AC voltage VC2. At this time, because the forward voltage VF of the Schottky barrier diode is small, AC voltage VC1 is clamped at a voltage lower than rectified voltage VCC, as shown by E2. Furthermore, even when AC voltage VC1 is lower than the threshold voltage of transistor T2 and transistor T2 is still off, a forward current flows through parasitic diode DP2, causing AC voltage VC2 to become lower than rectified voltage VSS by the forward voltage VF of parasitic diode DP2, as shown in E3. These regions above rectified voltage VCC shown in E2 and below rectified voltage VSS shown in E3 are regions where power is lost.

The period indicated by E4 in Figure 9 is when a reverse voltage is applied to diode D1, turning off transistor T2, and when a forward voltage is applied to diode D2, turning on transistor T1. Specifically, when AC voltage VC2 exceeds the threshold voltage of transistor T1, transistor T1 turns on, and when AC voltage VC2 exceeds rectified voltage VCC, forward current flows through diode D2. As a result, as in Figure 7, current ID2 from node N2 of AC voltage VC2 flows to node N1 of AC voltage VC1 via diode D2, load 14, and transistor T1. In this case, too, the regions indicated by E5 and E6 are regions of power loss.

Figure 10 is a signal waveform diagram illustrating the operation of the rectifier circuit 10 of the third configuration example shown in Figure 6. The period indicated by F1 in Figure 10 is when a forward voltage is applied to diodes D1 and D4, turning on transistor T2, and a reverse voltage is applied to diodes D2 and D3, turning off transistor T1. Specifically, when AC voltage VC1 exceeds the threshold voltage of transistor T2, transistor T2 turns on. When AC voltage VC1 exceeds rectified voltage VCC, forward current flows through diode D1. As a result, as in Figure 7, current ID1 from node N1 of AC voltage VC1 flows to node N2 of AC voltage VC2 via diode D1, load 14, transistor T2, and diode D4. At this time, because the forward voltage VF of the Schottky barrier diode is small, AC voltage VC1 is clamped at a voltage lower than rectified voltage VCC, as shown by F2. Furthermore, even when AC voltage VC1 is lower than the threshold voltage of transistor T2 and transistor T2 is still off, current flows through diode D4 connected in parallel to transistor T2, causing AC voltage VC2 to be lower than rectified voltage VSS by the forward voltage VF of diode D4, as shown at F3. In this case, diode D4 is a Schottky barrier diode with a low forward voltage VF, so the voltage drop from rectified voltage VSS is smaller at F3 in FIG. 10 than at E3 in FIG. 9. Therefore, the rectifier circuit 10 of the third configuration example shown in FIGS. 6 and 10 can reduce power loss compared to the rectifier circuit 10 of the second configuration example shown in FIGS. 5 and 9.

The period indicated by F4 in FIG. 10 is a period during which a reverse voltage is applied to diodes D1 and D4, turning off transistor T2, and a forward voltage is applied to diodes D2 and D3, turning on transistor T1. Specifically, when AC voltage VC2 exceeds the threshold voltage of transistor T1, transistor T1 turns on. When AC voltage VC2 exceeds rectified voltage VCC, forward current flows through diode D2. As a result, as in the case of FIG. 7, current ID2 from node N2 of AC voltage VC2 flows to node N1 of AC voltage VC1 via diode D2, load 14, transistor T1, and diode D3. In this case, the regions indicated by F5 and F6 are also power loss regions, but the power loss is smaller than in the regions indicated by E5 and E6 in FIG. 9. Therefore, the rectifier circuit 10 of the third configuration example in FIGS. 6 and 10 can reduce power loss compared to the rectifier circuit 10 of the second configuration example in FIGS. 5 and 9.

As described above, in the rectifier circuit 10 of Figures 4, 5, and 6, the rectifier element RF1 of Figure 1 is provided with a first diode, diode D1, and the rectifier element RF2 is provided with a second diode, diode D2. This allows the rectifier circuit 10 to operate at higher speeds than when transistors are used as the rectifier elements RF1 and RF2. As a result, even when the AC voltages VC1 and VC2 have high frequencies, the rectifier circuit 10 can properly rectify the AC voltages VC1 and VC2 and output the rectified voltages VCC and VSS. In other words, when transistors are used as the rectifier elements RF1 and RF2, gate control of the transistors is required using feedback control. However, such feedback control introduces delays, making it difficult to operate the rectifier circuit 10 at high speeds. This makes it difficult to accommodate high frequencies of the AC voltages VC1 and VC2, for example. In contrast, if diodes D1 and D2 are used as rectifying elements RF1 and RF2, this feedback control becomes unnecessary, allowing the rectifier circuit 10 to operate at high speed and to handle high frequencies of the AC voltages VC1 and VC2.

In addition, in Figures 4, 5, and 6, diode D1 is a Schottky barrier diode, and diode D2 is also a Schottky barrier diode. By using Schottky barrier diodes as diodes D1 and D2 in this way, as explained in B1 and B2 of Figure 8, the forward voltage VF can be reduced compared to when PN junction diodes are used. By reducing the forward voltage VF in this way, the area in which the AC voltages VC1 and VC2 exceed the rectified voltage VCC can be reduced, as shown, for example, in E2 and E5 of Figure 9 and F2 and F5 of Figure 10. Therefore, power loss can be reduced compared to PN junction diodes, and the power receiving efficiency of rectifier circuit 10 can be improved.

In Figures 5 and 6, the rectifying element RF3 is a first transistor, T1, whose gate is connected to the input line I2 for the AC voltage VC2. The rectifying element RF4 is a second transistor, T2, whose gate is connected to the input line I1 for the AC voltage VC1. This configuration allows the transistor T1 to function as the rectifying element RF3 by inputting the AC voltage VC2 from the input line I2 to the gate of the transistor T1 and turning the transistor T1 on and off. Furthermore, the transistor T2 can function as the rectifying element RF4 by inputting the AC voltage VC1 from the input line I1 to the gate of the transistor T2 and turning the transistor T2 on and off. In other words, the transistors T1 and T2 can function as the rectifying elements RF3 and RF4 without the need for a gate control circuit to control the transistor gates. Another advantage is that the drain-source voltage when the transistors T1 and T2 are on can be made smaller than the forward voltage VF of the diode, thereby reducing forward loss.

In addition, in FIG. 6, the rectifying element RF3 further includes a third Schottky barrier diode, diode D3, connected in parallel to transistor T1, and the rectifying element RF4 further includes a fourth Schottky barrier diode, diode D4, connected in parallel to transistor T2. This configuration reduces power loss, as described in F3 and F6 of FIG. 10, compared to the configuration in FIG. 5, which does not include Schottky barrier diodes D3 and D4. In other words, in the configuration in FIG. 5, as shown in E3 and E6 of FIG. 9, the AC voltages VC1 and VC2 fall below the rectified voltage VSS by the forward voltage VF of the parasitic diodes DP1 and DP2, which are PN junction diodes. In contrast, by providing Schottky barrier diodes D3 and D4 as shown in FIG. 6, the region in which the AC voltages VC1 and VC2 fall below the rectified voltage VSS can be reduced, as shown in F3 and F6 of FIG. 10, thereby reducing power loss and enabling efficient rectification.

In addition, in Figures 4 and 6, diode D3, which is a third Schottky barrier diode, is provided as rectifying element RF3, and diode D4, which is a fourth Schottky barrier diode, is provided as rectifying element RF4. By providing diodes D3 and D4, which are Schottky barrier diodes in this way, the forward voltage VF can be made smaller and power loss can be reduced compared to when PN junction diodes are provided, making it possible to achieve efficient rectification operation.

11 and 12 show a detailed layout example of the rectifier circuit 10 of this embodiment. Fig. 11 and 12 show a more detailed layout example of the layout described in Fig. 3. Specifically, Fig. 11 and 12 show a layout example of the rectifier circuit 10 of the third configuration example of Fig. 6.

In Figures 11 and 12, the rectifier circuit 10 includes an input line group GI1 in which the input lines are wired along direction DR1, and an input line group GI2 in which the input lines are wired along direction DR1 on the direction DR2 side of the input line group GI1. Also, as shown in Figure 12, the rectifier circuit 10 includes an output line group GQ1 in which the output lines are wired along direction DR2 perpendicular to direction DR1, and an output line group GQ2 in which the output lines are wired along direction DR2 on the direction DR1 side of the output line group GQ1. Note that Figure 12 is a layout diagram that adds the arrangement of output line groups GQ1 and GQ2 to Figure 11.

In the rectifier circuit 10 of Figures 11 and 12, the rectifier element group GRF1 of Figure 1 is provided with a diode group GD1, which is the first diode group, and the rectifier element group GRF2 is provided with a diode group GD2, which is the second diode group. The rectifier element group GRF3 is provided with a diode group GD3, which is the third diode group, and the rectifier element group GRF4 is provided with a diode group GD4, which is the fourth diode group. The diode group GD1 is provided corresponding to the intersection of the input line group GI1 and the output line group GQ1, and the diode group GD2 is provided corresponding to the intersection of the input line group GI2 and the output line group GQ1. The diode group GD3 is provided corresponding to the intersection of the input line group GI1 and the output line group GQ2, and the diode group GD4 is provided corresponding to the intersection of the input line group GI2 and the output line group GQ2. For example, diode group GD1 is provided in the intersection region of input line group GI1 and output line group GQ1, and diode group GD2 is provided in the intersection region of input line group GI2 and output line group GQ1. Diode group GD3 is provided in the intersection region of input line group GI1 and output line group GQ2, and diode group GD4 is provided in the intersection region of input line group GI2 and output line group GQ2. Note that the numbers of wires and diodes shown in Figures 11 and 12 are examples, and in reality the number of wires and diodes can be even greater.

Specifically, in Figures 11 and 12, diodes Di, Di+1, and Di+2 are provided as diode group GD1, and diodes Dj, Dj+1, and Dj+2 are provided as diode group GD2. Diodes Di, Di+1, and Di+2 are the i-th, i+1st, and i+2nd diodes, respectively, and diodes Dj, Dj+1, and Dj+2 are the j-th, j+1st, and j+2nd diodes, respectively. Diodes Dp, Dp+1, and Dp+2 are provided as diode group GD3, and diodes Dq, Dq+1, and Dq+2 are provided as diode group GD4. Diodes Dp, Dp+1, and Dp+2 are the p-th, p+1st, and p+2nd diodes, respectively, and diodes Dq, Dq+1, and Dq+2 are the q-th, q+1st, and q+2nd diodes, respectively. Note that i, j, p, and q are different integers, for example, greater than or equal to 1.

Specifically, the diode group GD1 includes a diode Di and a diode Di+1 adjacent to the diode Di in the direction DR2. The i-th diode, Di, and the i+1-th diode, Di+1, are arranged side by side along the direction DR2, with the direction DR1 being the longitudinal direction, for example. The diode group GD1 also includes a diode Di+2 adjacent to the diode Di+1 in the direction DR2.

Diode group GD2 also includes diode Dj and diode Dj+1 adjacent to diode Dj in direction DR2. Diode Dj, the jth diode, and diode Dj+1, the j+1th diode, are arranged side by side along direction DR2, with direction DR1 as the longitudinal direction, for example. Diode group GD2 also includes diode Dj+2 adjacent to diode Dj+1 in direction DR2.

In this way, diode Di is placed below the input line corresponding to diode Di in input line group GI1, and diode Di+1 is placed below the input line corresponding to diode Di+1 in input line group GI1. For example, diodes Di and Di+1 can be placed below each corresponding input line along the longitudinal direction of each input line, allowing AC voltage VC1 to be supplied from each input line. Note that "downward" refers to the direction from the circuit formation area of the semiconductor substrate toward the semiconductor substrate. Furthermore, diode Dj is placed below the input line corresponding to diode Dj in input line group GI2, and diode Dj+1 is placed below the input line corresponding to diode Dj+1 in input line group GI2. For example, diodes Dj and Dj+1 can be placed below each corresponding input line along the longitudinal direction of each input line, allowing AC voltage VC2 to be supplied from each input line. Therefore, multiple diodes of the diode group GD1 can be efficiently arranged in the intersection region between the input line group GI1 and the output line group GQ1, and multiple diodes of the diode group GD2 can be efficiently arranged in the intersection region between the input line group GI2 and the output line group GQ1, thereby realizing a small layout area for the rectifier circuit 10. Furthermore, because multiple diodes connected in parallel are provided between the input line group GI1 and the output line group GQ1, and multiple diodes connected in parallel are provided between the input line group GI2 and the output line group GQ1, the current flowing through the rectifier elements can be increased, enabling efficient rectification operation of the rectifier circuit 10.

In addition, in Figures 11 and 12, a shared cathode CCAi shared by anode ANi and anode ANi+1 is provided between anode ANi of diode Di and anode ANi+1 of diode Di+1. Furthermore, a shared cathode CCAi+1 shared by anode ANi+1 and anode ANi+2 is provided between anode ANi+1 and anode ANi+2 of diode Di+2. Anodes ANi, ANi+1, and ANi+2 are the i-th anode, i+1-th anode, and i+2-th anode, respectively. Shared cathodes CCAi and CCAi+1 are the i-th shared cathode and i+1-th shared cathode, respectively.

In addition, in Figures 11 and 12, a shared cathode CCAj shared by anode ANj and anode ANj+1 is provided between anode ANj of diode Dj and anode ANj+1 of diode Dj+1. Furthermore, a shared cathode CCAj+1 shared by anode ANj+1 and anode ANj+2 is provided between anode ANj+1 and anode ANj+2 of diode Dj+2. Anodes ANj, ANj+1, and ANj+2 are the jth anode, j+1th anode, and j+2th anode, respectively. Shared cathodes CCAj and CCAj+1 are the jth shared cathode and j+1th shared cathode, respectively.

In this way, for two anodes arranged along direction DR2, the cathode arranged between the two anodes can be used as a shared cathode for the two anodes. Therefore, the length of each diode group area in direction DR2 can be reduced while maintaining the rectified current of each diode, thereby achieving both improved efficiency in the rectification operation of rectifier circuit 10 and a smaller area.

In Figures 11 and 12, cathode CA1 is provided to surround each of anodes ANi, ANi+1, and ANi+2, and cathode CA2 is provided to surround each of anodes ANj, ANj+1, and ANj+2. In this way, current flows from each of anodes ANi, ANi+1, and ANi+2 to cathode CA1 in the up, down, left, and right directions, and current flows from each of anodes ANj, ANj+1, and ANj+2 to cathode CA2 in the up, down, left, and right directions. This makes it possible to efficiently flow current from the anodes to the cathodes, enabling efficient rectification by the rectifier circuit 10.

In the rectifier circuit 10 of Figures 11 and 12, a diode group GD3 is provided as the rectifier element group GRF3, and a diode group GD4 is provided as the rectifier element group GRF4. The diode group GD3, which is the third diode group, includes a diode Dp and a diode Dp+1 adjacent to diode Dp in direction DR2. Diode Dp, which is the pth diode, and diode Dp+1, which is the p+1th diode, are arranged side by side along direction DR2, with direction DR1 as the longitudinal direction, for example. The diode group GD3 also includes a diode Dp+2 adjacent to diode Dp+1 in direction DR2.

Diode group GD4 also includes diode Dq and diode Dq+1 adjacent to diode Dq in direction DR2. Diode Dq, the qth diode, and diode Dq+1, the q+1th diode, are arranged side by side along direction DR2, with direction DR1 as the longitudinal direction, for example. Diode group GD4 also includes diode Dq+2 adjacent to diode Dq+1 in direction DR2.

In this manner, diodes Dp and Dp+1 are arranged below each input line corresponding to diodes Dp and Dp+1 in the input line group GI1, and AC voltage VC1 is supplied. Furthermore, diodes Dq and Dq+1 are arranged below each input line corresponding to diodes Dq and Dq+1 in the input line group GI2, and AC voltage VC2 is supplied. Therefore, multiple diodes of diode group GD3 can be efficiently arranged in the intersection region between input line group GI1 and output line group GQ2, and multiple diodes of diode group GD4 can be efficiently arranged in the intersection region between input line group GI2 and output line group GQ2, thereby achieving a reduced layout area for rectifier circuit 10. Furthermore, multiple parallel-connected diodes are provided between input line group GI1 and output line group GQ2, and multiple parallel-connected diodes are provided between input line group GI2 and output line group GQ2, thereby increasing the current flowing through the rectifier elements and enabling efficient rectification operation of rectifier circuit 10.

In addition, in Figures 11 and 12, a shared cathode CCAp shared by anode ANp and anode ANp+1 is provided between anode ANp of diode Dp and anode ANp+1 of diode Dp+1. Furthermore, a shared cathode CCAp+1 shared by anode ANp+1 and anode ANp+2 is provided between anode ANp+1 and anode ANp+2 of diode Dp+2. Anodes ANp, ANp+1, and ANp+2 are the pth anode, p+1th anode, and p+2nd anode, respectively. Shared cathodes CCAp and CCAp+1 are the pth shared cathode and p+1th shared cathode, respectively.

In addition, in Figures 11 and 12, a shared cathode CCAq shared by anode ANq and anode ANq+1 is provided between anode ANq of diode Dq and anode ANq+1 of diode Dq+1. Furthermore, a shared cathode CCAq+1 shared by anode ANq+1 and anode ANq+2 is provided between anode ANq+1 and anode ANq+2 of diode Dq+2. Anodes ANq, ANq+1, and ANq+2 are the qth anode, q+1th anode, and q+2nd anode, respectively. Shared cathodes CCAq and CCAq+1 are the qth shared cathode and q+1th shared cathode, respectively.

In this way, when two anodes are arranged along direction DR2, the cathode arranged between the two anodes can be used as a shared cathode for the two anodes, thereby achieving both improved efficiency in the rectification operation of rectifier circuit 10 and a smaller area.

In Figures 11 and 12, cathode CA3 is provided to surround each of anodes ANp, ANp+1, and ANp+2, and cathode CA4 is provided to surround each of anodes ANq, ANq+1, and ANq+2. In this way, current flows from each of anodes ANp, ANp+1, and ANp+2 to cathode CA3 in the vertical and horizontal directions, and current flows from each of anodes ANq, ANq+1, and ANq+2 to cathode CA4 in the vertical and horizontal directions. This makes it possible to efficiently flow current from the anodes to the cathodes, enabling efficient rectification by the rectifier circuit 10.

Furthermore, in Figures 11 and 12, the anode ANi and the shared cathode CCAp are arranged side by side along the direction DR1, and the anode ANj and the shared cathode CCAq are arranged side by side along the direction DR1.

That is, the anode ANi of diode Di in diode group GD1, the anode ANp of diode Dp in diode group GD3, and the shared cathode CCAp of anode ANp+1 of diode Dp+1 are arranged side by side in direction DR1. Similarly, the anode ANi+1 of diode group GD1 and the shared cathode CCAp+1 of diode group GD3 are arranged side by side in direction DR1.

Furthermore, the anode ANj of diode Dj of diode group GD3, the anode ANq of diode Dq of diode group GD4, and the shared cathode CCAq of anode ANq+1 of diode Dq+1 are arranged side by side along direction DR1. Similarly, the anode ANj+1 of diode group GD2 and the shared cathode CCAq+1 of diode group GD4 are arranged side by side along direction DR1.

11 and 12 corresponds to the anode of diode D1 in FIG. 6, and shared cathode CCAp corresponds to the cathode of diode D3. A contact is provided where anode ANi and the input line corresponding to anode ANi overlap in a planar view, and by connecting anode ANi to the input line via the contact, node N1 of AC voltage VC1 is connected to anode ANi, which is the anode of diode D1. A contact is also provided where shared cathode CCAp and the input line overlap in a planar view, and by connecting shared cathode CCAp to the input line via the contact, node N1 of AC voltage VC1 is connected to shared cathode CCAp, which is the cathode of diode D3. Therefore, by arranging the anode ANi and the shared cathode CCAp side by side in the direction DR1, it is possible to connect the anode of diode D1 and the cathode of diode D3 in Figure 6 via a short-path connection path via the input line and contact. This reduces parasitic resistance in the connection path, and reduces power loss caused by parasitic resistance.

The anode ANj in Figures 11 and 12 corresponds to the anode of diode D2 in Figure 6, and the shared cathode CCAq corresponds to the cathode of diode D4. A contact is provided where the anode ANj and the input line corresponding to anode ANj overlap in a planar view, and by connecting the anode ANj to the input line via the contact, node N2 of AC voltage VC2 is connected to anode ANj, which is the anode of diode D2. A contact is provided where the shared cathode CCAq and the input line overlap in a planar view, and by connecting the shared cathode CCAq to the input line via the contact, node N2 of AC voltage VC2 is connected to shared cathode CCAq, which is the cathode of diode D4. Therefore, by arranging the anode ANj and the shared cathode CCAq side by side in the direction DR1, it is possible to connect the anode of diode D2 and the cathode of diode D4 in Figure 6 via a short-path connection path via the input line and contact. This reduces parasitic resistance in the connection path, thereby reducing power loss caused by parasitic resistance.

In Figures 11 and 12, transistor T1 is arranged on the DR1 side of diode group GD3. For example, transistor T1 is arranged adjacent to diode group GD3 on the DR1 side so that the longitudinal direction of the source S, gate G, and drain D constituting transistor T1 is aligned with direction DR2. Transistor T2 is also arranged on the DR1 side of diode group GD4. For example, transistor T2 is arranged adjacent to diode group GD4 on the DR1 side so that the longitudinal direction of the source S, gate G, and drain D constituting transistor T2 is aligned with direction DR2. This enables efficient arrangement of not only diode groups GD1, GD2, GD3, and GD4, but also transistors T1 and T2 in a compact layout. The AC voltage VC2 from input line group GI2 is supplied to the gate G of transistor T1 via the wiring indicated by H1 in Figure 11. In addition, the AC voltage VC1 from the input line group GI1 is supplied to the gate G of transistor T2 via the wiring shown in H2.

The layout of the rectifier circuit 10 of this embodiment is not limited to that shown in FIGS. 11 and 12, and various modifications are possible. For example, in the case of the rectifier circuit 10 of the first configuration example shown in FIG. 4, the layout of the transistors T1 and T2 shown in FIGS. 11 and 12 is unnecessary. Furthermore, in the case of the rectifier circuit 10 of the second configuration example shown in FIG. 5, the layout of the diode groups GD3 and GD4 shown in FIGS. 11 and 12 is unnecessary.

Figure 13 is a cross-sectional view of the rectifier circuit 10 at the portion indicated by the dotted line Y in Figure 12. As shown in Figure 13, the input lines of the input line groups GI1 and GI2 are formed from metal layers ALB and ALC, and the output lines of the output line groups GQ1 and GQ2 are formed from metal layers ALD and ALE, which are located above the metal layers ALB and ALC. This allows the output line groups GQ1 and GQ2 to be wired so that they intersect with the input line groups GI1 and GI2 in the direction DR1. Note that a metal layer ALA is provided below the metal layer ALB for connection to diodes, etc. The metal layers ALA to ALE are formed from a metal such as aluminum.

In FIG. 13, a P-type well 20 and an N-type well 22 are formed in a semiconductor substrate, and an N-type well 24 is formed in the N-type well 22. The N-type well 22 is, for example, a high-voltage N-type well with a high breakdown voltage, and the N-type well 24 is, for example, a low-voltage N-type well with a low breakdown voltage. An N-type diffusion layer 26 formed on the N-type well 24 serves as the cathode electrode of a Schottky barrier diode. A P-type buried layer 34 is formed in the N-type well 22, a P-type diffusion layer 32 is formed on the P-type buried layer 34, and a metal layer 30 is formed on the P-type diffusion layer 32. This metal layer 30 serves as the anode electrode of the Schottky barrier diode. The metal layer 30 is made of, for example, cobalt or a cobalt alloy. Specifically, cobalt silicide is used. However, titanium or a titanium alloy may also be used for the metal layer 30. For example, a Schottky barrier diode is realized by the Schottky barrier formed by the junction between the metal layer 30 and the N-type well 22. In Figure 13, the relationship between P-type impurity concentrations is P+>P>P-, and the relationship between N-type impurity concentrations is N+>N>N-. The structure of the Schottky barrier diode is not limited to that shown in Figure 13, and various modifications are possible. For example, a structure in which multiple P-type diffusion layers or electrodes are separated and arranged in an N-type well is also possible. In this embodiment, it is desirable to use Schottky barrier diodes as diodes D1 to D4, but modifications using PN junction diodes are also possible. In this case, for example, a P-type diffusion layer that serves as the anode of the PN junction diode and an N-type diffusion layer that serves as the cathode of the PN junction diode can be formed in the N-type well. The diffusion layers are impurity layers.

FIG. 14 is a cross-sectional view of a different embodiment of the rectifier circuit 10, and corresponds to FIG.
In the diode configuration of FIG. 13, an N-type diffusion region 27 may be provided between the two N-type wells 24, as shown in FIG. 14. The N-type diffusion region 27 is a region with a high impurity concentration, and is provided to connect the two N-type wells 24. The N-type diffusion region 27 has a higher impurity concentration than the N-type well 22 region, and therefore has a low electrical resistance. In a preferred example, the impurity concentration of the N-type diffusion region 27 is the same impurity concentration N+ as the N-type diffusion layer 26. However, the impurity concentration is not limited to this, and it is sufficient that the impurity concentration be higher than the N-type well 22 region (impurity concentration N−) of the base.

FIG. 15 is a correlation diagram between the forward voltage VF of the diode and the current ID1, and corresponds to FIG.
14, the diode configuration with the N-type diffusion region 27 provides a lower connection resistance between the two N-type wells 24 than the configuration of FIG. 13, allowing for a lower forward voltage VF. Specifically, as shown in FIG. 15, a voltage B5 can be set that is lower than the voltage B1 representing the forward voltage VF of the diode of FIG. 13. Furthermore, a current B6 can be set that is lower than the current B3 representing the reverse current ID1 of the diode of FIG. 13. In other words, the diode configuration of FIG. 14 allows for a further reduction in power loss.

16 shows an example of the configuration of a power receiving control device 40 of this embodiment. As shown in FIG. 16 , the power receiving control device 40 of this embodiment includes a power receiving circuit 50 including the rectifier circuit 10 of this embodiment, and a power feeding circuit 60 that feeds power based on the power received by the power receiving circuit 50. For example, the power receiving circuit 50 rectifies an AC voltage from an AC power source 12 using the rectifier circuit 10 to generate rectified voltages VCC and VSS, and supplies a receiving voltage based on the rectified voltages VCC and VSS to the power feeding circuit 60 as received power. The power feeding circuit 60 feeds power to a load 14 based on the power received by the power receiving circuit 50. The AC power source 12 may be, for example, an AC power source or an AC power source using a secondary coil for contactless power transmission.

Figure 17 shows another example configuration of the power receiving control device 40 of this embodiment. In Figure 17, the power receiving control device 40 receives power through contactless power transmission. Specifically, the power receiving circuit 50 of the power receiving control device 40 receives the transmitted power from the power transmitting device 70 contactlessly. In other words, power is received wirelessly. For example, a primary coil L1 is provided on the power transmitting device 70 side, and a secondary coil L2 is provided on the power receiving control device 40 side. Then, the power transmitting driver of the power transmitting device 70 applies an AC voltage to the primary coil L1, thereby transmitting power from the primary coil L1 to the secondary coil L2. The power receiving circuit 50 receives power from the power transmitting device 70. Specifically, the power receiving circuit 50 converts the AC induced voltage of the secondary coil L2 into a DC rectified voltage VCC using the rectifier circuit 10. The power supply circuit 60 charges the battery 15, which is the load 14, based on the received voltage derived from the rectified voltage VCC.

The power receiving control device 40 of this embodiment can be incorporated into electronic devices. The electronic device into which the power receiving control device 40 is incorporated is preferably a hearable device such as an earphone or a wearable device, but this embodiment is not limited to this. Examples of electronic devices that can be considered include head-mounted displays, portable communication terminals such as smartphones and mobile phones, wristwatches, biometric information measuring devices, shavers, electric toothbrushes, wrist computers, handheld terminals, and on-board equipment for automobiles.

As described above, the rectifier circuit of this embodiment receives a first AC voltage and a second AC voltage that is opposite in phase to the first AC voltage as inputs, and outputs a first rectified voltage on the high potential side and a second rectified voltage on the low potential side. The rectifier circuit includes a first input line that receives the first AC voltage and is wired along a first direction, and a second input line that receives the second AC voltage and is wired along the first direction on the second direction side of the first input line, where the second direction is a direction perpendicular to the first direction. The rectifier circuit also includes a first output line that is an output line for the first rectified voltage and is wired along the second direction, and a second output line that is an output line for the second rectified voltage and is wired along the second direction on the first direction side of the first output line. The rectifier circuit also includes a first rectifier element arranged in a plan view corresponding to the intersection of the first input line and the first output line and connected between the first input line and the first output line, a second rectifier element arranged in a plan view corresponding to the intersection of the second input line and the first output line and connected between the second input line and the first output line, a third rectifier element arranged in a plan view corresponding to the intersection of the first input line and the second output line and connected between the first input line and the second output line, and a fourth rectifier element arranged in a plan view corresponding to the intersection of the second input line and the second output line and connected between the second input line and the second output line.

In this embodiment, a first input line for a first AC voltage and a second input line for a second AC voltage are wired along a first direction, and a first output line for a first rectified voltage and a second output line for a second rectified voltage are wired along a second direction perpendicular to the first direction. The first and second rectifier elements are arranged corresponding to the intersections of the first and second input lines and the first output line, and the third and fourth rectifier elements are arranged corresponding to the intersections of the first and second input lines and the second output line. This reduces parasitic resistance between each rectifier element and each input line or output line, thereby reducing power loss in the rectifier circuit. It also enables efficient layout arrangement of the rectifier elements and efficient layout wiring of the input and output lines, thereby reducing the layout area of the rectifier circuit.

This embodiment may also include a first input line group including first input lines, a second input line group including second input lines, a first output line group including first output lines, and a second output line group including second output lines. Each input line of the first input line group may be wired along a first direction, each input line of the second input line group may be wired along the first direction on the second direction side of the first input line group, each output line of the first output line group may be wired along the second direction, and each output line of the second output line group may be wired along the second direction on the first direction side of the first output line group.

In this way, the first AC voltage and the second AC voltage can be input to the rectifier circuit via multiple input lines, the first input line group and the second input line group, and the first rectified voltage and the second rectified voltage can be output from the rectifier circuit via multiple output lines, the first output line group and the second output line group. This makes it possible to reduce power receiving losses by reducing parasitic resistance, for example.

Furthermore, this embodiment may include a first rectifying element group including first rectifying elements and a second rectifying element group including second rectifying elements, where the first rectifying element group is arranged corresponding to the intersection of the first input line group and the first output line group, and the second rectifying element group is arranged corresponding to the intersection of the second input line group and the first output line group.

In this way, rectification can be performed by the rectifier circuit using, for example, a first rectifier element group including multiple rectifier elements and a second rectifier element group including multiple rectifier elements, thereby further reducing the power reception loss of the rectifier circuit and achieving efficient rectification operation.

In addition, in this embodiment, a first diode group is provided as the first rectifying element group, and a second diode group is provided as the second rectifying element group, and the first diode group may include the i-th diode and the i+1-th diode adjacent to the i-th diode in the second direction, and the second diode group may include the j-th diode and the j+1-th diode adjacent to the j-th diode in the second direction.

In this way, it is possible to place the i-th diode and the i+1-th diode at the location of each corresponding input line of the first input line group, and the j-th diode and the j+1-th diode at the location of each corresponding input line of the second input line group. This makes it possible to efficiently place multiple diodes in the first diode group corresponding to the intersections of the first input line group and the first output line group, and efficiently place multiple diodes in the second diode group corresponding to the intersections of the second input line group and the first output line group.

In addition, in this embodiment, an i-th shared cathode shared by the i-th anode and the i+1-th anode may be arranged between the i-th anode of the i-th diode and the i+1-th anode of the i+1-th diode, and a j-th shared cathode shared by the j-th anode and the j+1-th anode may be arranged between the j-th anode of the j-th diode and the j+1-th anode of the j+1-th diode.

In this way, when two anodes are arranged along the second direction, the cathode arranged between the two anodes can be used as a shared cathode for the two anodes.

In addition, in this embodiment, a third diode group is provided as the third rectifying element group, and a fourth diode group is provided as the fourth rectifying element group. The third diode group may include a pth diode and a p+1th diode adjacent to the pth diode in the second direction, and the fourth diode group may include a qth diode and a q+1th diode adjacent to the qth diode in the second direction.

In this way, the pth and p+1th diodes can be placed at the locations of the corresponding input lines of the first input line group, and the qth and q+1th diodes can be placed at the locations of the corresponding input lines of the second input line group. This makes it possible to efficiently place multiple diodes in the third diode group corresponding to the intersections of the first input line group and the second output line group, and efficiently place multiple diodes in the fourth diode group corresponding to the intersections of the second input line group and the second output line group.

In addition, in this embodiment, a p-th shared cathode shared by the p-th anode and the p+1-th anode may be arranged between the p-th anode of the p-th diode and the p+1-th anode of the p+1-th diode, and a q-th shared cathode shared by the q-th anode and the q+1-th anode may be arranged between the q-th anode of the q-th diode and the q+1-th anode of the q+1-th diode. The i-th anode and the p-th shared cathode may be arranged side by side along the first direction, and the j-th anode and the q-th shared cathode may be arranged side by side along the first direction.

In this way, when two anodes are arranged along the second direction, the cathode arranged between the two anodes can be used as a shared cathode for the two anodes. In this embodiment, the i-th anode and p-th shared cathode are arranged side by side along the first direction, and the j-th anode and q-th shared cathode are arranged side by side along the first direction. This makes it possible to connect the anode of the i-th diode and the cathode of the p-th diode with a short-path signal line, and to connect the anode of the j-th diode and the cathode of the q-th diode with a short-path signal line.

In this embodiment, a first diode may be provided as the first rectifying element, and a second diode may be provided as the second rectifying element.

In this way, the rectifier circuit can operate at higher speeds than when transistors are used as the first and second rectifier elements. For example, even when the frequencies of the first and second AC voltages are high, the first and second AC voltages can be properly rectified and the first and second rectified voltages can be output.

In this embodiment, the first diode may be a first Schottky barrier diode, and the second diode may be a second Schottky barrier diode.

By using a Schottky barrier diode in this way, the forward voltage can be made smaller than when a PN junction diode is used, thereby reducing power loss and improving the power receiving efficiency of the rectifier circuit.

In this embodiment, a first transistor having a gate connected to the second input line may be provided as the third rectifier element, and a second transistor having a gate connected to the first input line may be provided as the fourth rectifier element.

In this way, by inputting the second AC voltage from the second input line to the gate of the first transistor and turning the first transistor on and off, it is possible to operate the first transistor as a third rectifier element. Furthermore, by inputting the first AC voltage from the first input line to the gate of the second transistor and turning the second transistor on and off, it is possible to operate the second transistor as a fourth rectifier element.

In this embodiment, a third Schottky barrier diode connected in parallel to the first transistor may be further provided as the third rectifying element, and a fourth Schottky barrier diode connected in parallel to the second transistor may be further provided as the fourth rectifying element.

This reduces power loss compared to a configuration that does not include the third and fourth Schottky barrier diodes.

In addition, in this embodiment, a third Schottky barrier diode may be provided as the third rectifying element, and a fourth Schottky barrier diode may be provided as the fourth rectifying element.

By using a Schottky barrier diode in this way, the forward voltage can be made smaller and power loss can be reduced compared to when using a PN junction diode.

This embodiment also relates to a power receiving control device that includes a power receiving circuit that includes the rectifier circuit described above, and a power supply circuit that supplies power based on the power received by the power receiving circuit.

While this embodiment has been described in detail above, those skilled in the art will readily understand that many modifications are possible that do not substantially deviate from the novel features and effects of the present invention. Therefore, all such modifications are intended to fall within the scope of the present invention. For example, a term that appears at least once in the specification or drawings together with a different, broader or synonymous term may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also within the scope of the present invention. Furthermore, the configurations and operations of the rectifier circuit and power receiving control device are not limited to those described in this embodiment, and various modifications are possible.

10...Rectifier circuit, 12...AC power supply, 14...Load, 15...Battery, 16...Capacitor, 20...P-type well, 22...N-type well, 24...N-type well, 26...N-type diffusion layer, 27...N-type diffusion region, 30...Metal layer, 32...Diffusion layer, 34...Buried layer, 40...Power receiving control device, 50...Power receiving circuit, 60...Power supply circuit, 70...Power transmitting device, ALA to ALD...Metal layer, ANi...Anode, ANj...Anode, ANp, ANq...Anode, CA1, CA2, CA3, CA4...Cathode, CCAi, CCAj, CCAp, CCAq...Shared cathode, D1, D2, D3, D4...Diode, DP1, DP2...Parasitic Diodes, DR1, DR2, DR3, DR4...direction, Di...diode, Dj, Dp...diode, Dq...diode, GD1, GD2, GD3, GD4...diode group, GI1, GI2...input line group, GQ1...output line group, GQ2...output line group, GRF1, GRF2, GRF3, GRF4...rectifier element group, I1, I2...input line, ID1...current, ID2...current, L...coil, L1...primary coil, L2...secondary coil, Q1, Q2...output line, RF1, RF2, RF3, RF4...rectifier elements, T1, T2...transistor, VC1, VC2...AC voltage, VCC, VSS...rectified voltage, VF...forward voltage.

Claims (9)

a rectifier circuit that receives a first AC voltage and a second AC voltage that is in phase opposite to the first AC voltage, and outputs a first rectified voltage on a high potential side and a second rectified voltage on a low potential side,
a first input line to which the first AC voltage is supplied and which is wired along a first direction;
a second input line to which the second AC voltage is supplied, the second input line being wired along the first direction on the second direction side of the first input line when a direction orthogonal to the first direction is defined as a second direction;
a first output line that is an output line of the first rectified voltage and is wired along the second direction;
a second output line that is an output line of the second rectified voltage and is wired along the second direction on the first direction side of the first output line;
are arranged corresponding to intersections of the first input lines and the first output lines in a plan view,
a first rectifying element connected between the input line and the first output line;
a second rectifying element disposed at a position corresponding to an intersection of the second input line and the first output line in the plan view and connected between the second input line and the first output line;
a third rectifying element that is arranged corresponding to an intersection of the first input line and the second output line in the plan view and is connected between the first input line and the second output line;
a fourth rectifying element that is arranged corresponding to an intersection of the second input line and the second output line in the plan view and is connected between the second input line and the second output line;
a first input line group including the first input lines;
a second input line group including the second input lines;
a first output line group including the first output lines;
a second output line group including the second output lines;
Including,
each input line of the first input line group is wired along the first direction;
Each input line of the second input line group is arranged on the second direction side of the first input line group.
Wired in one direction,
each output line of the first output line group is wired along the second direction,
Each output line of the second output line group is arranged on the first direction side of the first output line group.
Wired in two directions,
a first rectifying element group including the first rectifying element;
a second rectifying element group including the second rectifying element;
Including,
The first rectifying element group is arranged corresponding to the intersection of the first input line group and the first output line group.
Re,
The second rectifying element group is arranged corresponding to the intersection of the second input line group and the first output line group.
R,
a first diode group is provided as the first rectifying element group,
a second diode group is provided as the second rectifying element group,
The first diode group includes:
A first diode;
a second diode adjacent to the first diode in the second direction;
Including,
The second diode group includes:
A third diode;
a fourth diode adjacent to the third diode in the second direction;
A rectifier circuit comprising: 2. The rectifier circuit according to claim 1 ,
The first diode is connected between the anode of the first diode and the anode of the second diode .
a first shared cathode is disposed which is shared by the cathode of the diode and the cathode of the second diode ;
The third diode is connected between the anode of the third diode and the anode of the fourth diode .
A rectifier circuit comprising a second shared cathode that is shared by the cathode of the diode and the cathode of the fourth diode . 3. The rectifier circuit according to claim 2 ,
a third rectifying element group including the third rectifying element;
a fourth rectifying element group including the fourth rectifying element;
Including,
a third diode group is provided as the third rectifying element group,
a fourth diode group is provided as the fourth rectifying element group,
The third diode group includes:
A fifth diode;
a sixth diode adjacent to the fifth diode in the second direction;
Including,
The fourth diode group includes:
A seventh diode; and
an eighth diode adjacent to the seventh diode in the second direction;
A rectifier circuit comprising: 4. The rectifier circuit according to claim 3 ,
Between the anode of the fifth diode and the anode of the sixth diode,
a third shared cathode is disposed which is shared by the cathode of the diode and the cathode of the sixth diode ;
Between the anode of the seventh diode and the anode of the eighth diode ,
a fourth shared cathode is disposed which is shared by the cathode of the diode and the cathode of the eighth diode ;
the anode of the first diode and the third shared cathode are arranged side by side along the first direction;
A rectifier circuit, characterized in that the anode of the second diode and the fourth shared cathode are arranged side by side along the first direction. 2. The rectifier circuit according to claim 1 ,
The rectifier circuit is characterized in that the first diode, the second diode, the third diode, and the fourth diode are Schottky barrier diodes. 6. The rectifier circuit according to claim 5 ,
a first transistor having a gate connected to the second input line is provided as the third rectifying element;
A rectifier circuit, characterized in that a second transistor having a gate connected to the first input line is provided as the fourth rectifier element. 7. The rectifier circuit according to claim 6 ,
a Schottky barrier diode connected in parallel to the first transistor is further provided as the third rectifying element,
a Schottky barrier diode connected in parallel to the second transistor, as the fourth rectifying element; 2. The rectifier circuit according to claim 1 ,
The rectifier circuit according to claim 1, wherein the third rectifier element and the fourth rectifier element are Schottky barrier diodes. a power receiving circuit including the rectifier circuit according to any one of claims 1 to 8 ;
a power supply circuit that supplies power based on the received power of the power receiving circuit;
A power receiving control device comprising: