JP7748873B2 - display device - Google Patents

Description

This disclosure relates to a display device.

Organic EL elements are known as electro-optical elements used in self-luminous display devices. Organic EL elements are electro-optical elements that utilize the phenomenon of light emission when an electric field is applied to an organic thin film, and the color gradation is achieved by controlling the amount of current flowing through the organic EL element. For this reason, organic EL display devices that use organic EL elements are provided with a pixel circuit for each pixel, which includes a drive transistor for controlling the amount of current through the organic EL element, a storage capacitor for storing the control voltage of the drive transistor, and a sampling transistor (write transistor) for writing the control voltage to the storage capacitor (see Patent Document 1).

JP 2013-057947 A

However, off-leakage of a switching transistor such as a write transistor reduces the charge held in the storage capacitor, thereby reducing the light-emitting current flowing through a light-emitting element such as an organic EL element, making it impossible to maintain the desired brightness; in other words, off-leakage can cause brightness to change. Patent Document 1 does not disclose how to suppress changes in brightness caused by off-leakage of a write transistor.

This disclosure therefore provides a display device that can suppress changes in brightness due to off-leakage of switching transistors.

A display device according to one aspect of the present disclosure is a display device comprising a plurality of pixels arranged two-dimensionally, each of the plurality of pixels comprising a light-emitting element, a storage capacitor for storing a data signal supplied via a data signal line, a drive transistor for supplying a current corresponding to the data signal to the light-emitting element, and a write transistor connected between the data signal line and a gate electrode of the drive transistor, the write transistor having one of its source electrode and drain electrode connected to the data signal line, and the storage capacitor comprising a gate electrode of the drive transistor and a first electrode layer connected to the write transistor, and a first insulating layer covering the first electrode layer. a second electrode layer connected to the source electrode of the driving transistor and having a first opposing portion disposed on the first insulating layer opposite the first electrode layer; a second insulating layer covering the first insulating layer and the second electrode layer; and a third electrode layer connected to the source electrode of the driving transistor and at least a portion of which is formed on the second insulating layer, the third electrode layer having a second opposing portion disposed opposite the first electrode layer, the first opposing portion and the second opposing portion being formed in positions that do not overlap each other in a plan view of the display device, and the first electrode layer being formed to overlap each of the first opposing portion and the second opposing portion in the plan view.

A display device according to one aspect of the present disclosure can suppress changes in luminance due to off-leakage of the switching transistor.

FIG. 1 is a plan view schematically showing the configuration of a pixel circuit of a display device according to a comparative example. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, and schematically showing the configuration of a pixel circuit of a display device according to a comparative example. FIG. 3 is a block diagram showing a functional configuration of the display device according to the first embodiment. FIG. 4 is a circuit diagram showing the configuration of a pixel circuit of the display device according to the first embodiment. FIG. 5 is a plan view schematically showing the configuration of a pixel circuit of the display device according to the first embodiment. FIG. 6 is a cross-sectional view taken along the line VI-VI in FIG. 5, and schematically showing the configuration of a pixel circuit of the display device according to the first embodiment. FIG. 7 is a cross-sectional view taken along the line VII-VII in FIG. 5, and schematically showing the configuration of a pixel circuit of the display device according to the first embodiment. FIG. 8 is a diagram for explaining the effect of the display device according to the first embodiment. FIG. 9 is a timing chart of various gate control signals of the display device according to the first embodiment. FIG. 10 is a cross-sectional view schematically showing a first example of the configuration of a pixel circuit of a display device according to the second embodiment, taken along a cutting line corresponding to cutting line VI-VI in FIG. FIG. 11 is a cross-sectional view schematically showing a second example of the configuration of a pixel circuit of a display device according to the second embodiment, taken along a cutting line corresponding to cutting line VI-VI in FIG. FIG. 12 is a cross-sectional view schematically showing the configuration of a pixel circuit of a display device according to the second embodiment, taken along a line corresponding to the line VII-VII in FIG. FIG. 13 is a diagram for explaining a manufacturing method of the display device according to the second embodiment. FIG. 14 is a plan view schematically showing the configuration of a pixel circuit of a display device according to the third embodiment. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14, showing a schematic configuration of a pixel circuit of a display device according to the third embodiment.

(Background to this disclosure)
Prior to describing the present disclosure, the background to the present disclosure will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view schematically showing the configuration of a pixel circuit 1011 of a display device according to a comparative example. FIG. 2 is a cross-sectional view schematically showing the configuration of the pixel circuit 1011 of the display device according to the comparative example, taken along the II-II cutting line in FIG. 1. Note that, hereinafter, the circuit and the region in which the circuit is formed may be referred to by the same reference numeral.

As shown in FIG. 1, the sub-pixel circuits 1011R, 1011G, and 1011B are formed in three sub-pixel regions 1011R, 1011G, and 1011B, respectively, which are obtained by dividing the pixel region 1011. The sub-pixel circuits 1011R, 1011G, and 1011B have the same configuration.

The pixel circuit 1011 is formed, for example, by a first wiring layer, a semiconductor layer, and a second wiring layer arranged in this order on a substrate 110. The first wiring layer is mainly used as control signal lines INI, REF, WS, reference voltage lines VINI, VREF, one electrode of storage capacitors _CsR , _CsG , and _CsB (e.g., the lower electrode 210 shown in FIG. 2), and the gate electrodes of each transistor. The semiconductor layer is used as a channel region of each transistor. The second wiring layer is mainly used as data signal lines _VdatR , _VdatG , and _VdatB , a positive power supply line VCC, the other electrodes of storage capacitors _CsR , _CsG , and _CsB (e.g., the first upper electrode 220 shown in FIG. 2), and the source and drain electrodes of each transistor. Different layers are connected to each other by vias. The positive power supply line VCC is an example of a power supply line.

The light-emitting elements EL _R , EL _G , and EL _B included in the pixel circuit 1011 emit light at luminances corresponding to the data signals (data voltages) Vdat _R , Vdat _G , and Vdat _B held in the storage capacitors Cs _R , Cs _G , and Cs _B at the same timing in accordance with the same control signals INI, REF, and WS. Charges for determining a potential difference Vgs between the gate and source of each of the drive transistors TD _R , TD _G , and TD _B described later are accumulated in the storage capacitors Cs _R , Cs _G , and Cs _B via the data signal lines Vdat _R , Vdat _G , and Vdat _B , respectively.

Although not shown, a planarization layer is provided to cover the substrate, the first wiring layer, the semiconductor layer, and the second wiring layer, and the light-emitting elements EL _R , EL _G , and EL _B are formed on the planarization layer.

In the above, "R", "G", and "B" are attached to the reference numerals of the components according to the sub-pixel circuit, but hereinafter, when there is no need to distinguish between the three sub-pixel circuits, the reference numerals may be attached without the "R", "G", and "B" notation. Taking the storage capacitors _CsR , _CsG , and _CsB as an example, they may also be referred to as storage capacitors Cs.

2, the pixel circuit 1011 has, in cross section, a substrate 110, a first undercoat layer 120, a second undercoat layer 130, a first insulating layer 140, a second insulating layer 150, metal layers 160 and 180, a light-emitting layer 170, a fourth insulating layer 200, a lower electrode 210, a first upper electrode 220, a positive power supply line VCC, and a data signal line Vdat _G. In the example of FIG. 2, the display device is a top-emission display device. That is, light emitted from the light-emitting elements EL _R , EL _G , and EL _B is emitted toward the surface of the substrate 110 (the positive direction of the Z axis).

The substrate 110 is, for example, a glass substrate or a glass film. A plurality of pixels (pixel circuits 1011) are formed on the substrate 110.

The first undercoat layer 120 is provided to cover the surface of the substrate 110. The first undercoat layer 120 is, for example, an insulating layer (silicon nitride layer) made of a silicon nitride film.

The second undercoat layer 130 is provided to cover the surface of the first undercoat layer 120. The second undercoat layer 130 is, for example, an insulating layer (silicon oxide layer) made of a silicon oxide film. The first wiring layer is formed by electrodes formed on the second undercoat layer 130.

The undercoat layer is not limited to SiO or SiN, and can be any thin film with barrier properties. Its thickness can also be changed as appropriate.

The lower electrode 210 is part of the electrode formed on the second undercoat layer 130 and functions as one electrode for forming the storage capacitance Cs_conv. The lower electrode 210 is connected to the gate electrodes of the write transistor T3 and the drive transistor TD.

The first insulating layer 140 is provided to cover the second undercoat layer 130, on which one or more electrodes (first wiring layer) including the lower electrode 210 are formed. The first insulating layer 140 is filled between the lower electrode 210 and the first upper electrode 220. The first insulating layer 140 is, for example, a silicon oxide film, but may also be composed of an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film. The second wiring layer is formed by electrodes formed on the first insulating layer 140. Note that the storage capacitance Cs_conv shown in FIG. 2 corresponds to the storage capacitance Cs shown in FIG. 1.

The first upper electrode 220, the positive power supply line VCC, and the data signal line Vdat are part of electrodes formed on the first insulating layer 140. In this embodiment, the first upper electrode 220 has a portion (first opposing portion) that faces the lower electrode 210, and functions as the other electrode for forming the storage capacitance Cs_conv. The first opposing portion is the portion of the first upper electrode 220 that overlaps with the lower electrode 210 in a planar view. Note that "A" and "B" being opposed to each other means that no other metal layer is formed in at least a portion between "A" and "B".

The positive power supply line VCC is connected to the drain electrode of the drive transistor TD and the power supply 30 (see Figure 3), and is elongated in the X-axis direction in a plan view.

The data signal line Vdat _G is a data signal line of the sub-pixel circuit 1011G adjacent to the sub-pixel circuit 1011B. The positive power supply line VCC and the data signal line Vdat _G are provided at positions that do not overlap the lower electrode 210 (the lower electrode 210 of the pixel circuit 1011R) in a plan view.

The second insulating layer 150 is provided so as to cover the first insulating layer 140 on which a plurality of electrodes (second wiring layer) including the first upper electrode 220 and the data signal line Vdat _G are formed. The second insulating layer 150 has a thickness (length in the Z-axis direction) greater than that of the first insulating layer 140, for example. The second insulating layer 150 is, for example, a silicon oxide film, but may also be composed of an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film. The second insulating layer 150 may also be composed of an inorganic insulating film and an organic insulating film. The organic insulating film functions, for example, as a planarizing layer for planarizing the surface of the substrate 110.

The metal layer 160 is an electrode for forming the EL layer, such as an anode. The metal layer 160 is formed for each subpixel.

The light-emitting layer 170 is provided in each region partitioned by the third insulating layer 190, and emits light in response to a light-emitting current that corresponds to the amount of charge stored in the storage capacitor Cs.

Metal layer 180 is an electrode for forming the EL layer, for example, a cathode. Metal layer 180 is connected to the negative power supply line VCATH. Metal layer 180 is formed so as to cover multiple pixels collectively. Metal layer 180 is an example of a fourth electrode layer.

The third insulating layer 190 is a bank (partition) that divides the substrate 110 to form the light-emitting layer 170. The third insulating layer 190 is formed from a photosensitive thermosetting resin.

The EL layer is formed by the light-emitting layer 170, the third insulating layer 190, and the metal layers 160 and 180.

In addition, a protective film, sealing resin, and sealing substrate may be laminated on the EL layer in this order (not shown).

The lower electrode 210, first upper electrode 220, positive power supply line VCC, and data signal line Vdat are made of metals such as molybdenum (Mo), tungsten (W), aluminum (Al), copper (Cu), silver (Ag), and titanium (Ti), or alloys.

As described above, in the pixel circuit according to the comparative example, the storage capacitance Cs_conv is formed by the lower electrode 210, the first upper electrode 220, and the first insulating layer 140 between the lower electrode 210 and the first upper electrode 220.

Polysilicon semiconductor TFTs (Thin Film Transistors) are generally used for switching transistors such as the compensation transistor T2 and write transistor T3 shown in Figure 1, as they emphasize high-speed operation. However, polysilicon semiconductor TFTs have a relatively large off-leakage current due to leakage caused by crystal defects, etc., and as the charge held in the storage capacitor Cs_conv is released, the potential difference Vgs between the gate and source of the drive transistor TD decreases, reducing the light-emitting current flowing through the light-emitting element EL. This makes it impossible to display at the desired brightness (desired gradation value) or to maintain the desired brightness.

The off-leakage current of polysilicon semiconductor TFTs tends to be highly dependent on process control (control of Si crystallinity) during manufacturing, and existing technology has limitations in how much it can be reduced. Examples of factors that cause off-leakage current include subthreshold leakage current (drain-source leakage), gate leakage current (gate insulating film leakage), GIDL (Gate-Induced-Drain-Leakage current), and junction leakage current (crystalline defect leakage current).

The inventors of the present application therefore conducted extensive research into display devices that can suppress changes in brightness due to off-leakage of switching transistors, and devised the display device described below.

Each embodiment of the present disclosure will be described below with reference to the drawings. Note that each embodiment described below represents a specific example of the present disclosure. Therefore, the numerical values, shapes, materials, components, component placement and connection configurations, etc. shown in each of the following embodiments are merely examples and are not intended to limit the present disclosure. Therefore, among the components in each of the following embodiments, any component not recited in an independent claim of the present disclosure will be described as an optional component.

Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Furthermore, in each figure, substantially identical components are assigned the same reference numerals, and redundant explanations are omitted or simplified.

In addition, in this specification and drawings, the X-axis, Y-axis, and Z-axis represent the three axes of a right-handed three-dimensional Cartesian coordinate system. In each embodiment, the Z-axis direction is the stacking direction of each layer. In this specification, "planar view" means when the pixel circuit is viewed along the thickness direction of the pixel circuit.

In addition, in this specification, terms indicating the relationship between elements, such as identical or parallel, terms indicating the shape of elements, such as rectangular or elongated, as well as numerical values and numerical ranges, are not expressions that express only the strict meaning, but also expressions that include a substantially equivalent range, for example, a difference of about a few percent (e.g., about 10%).

(Embodiment 1)
[1-1. Configuration of display device]
First, the schematic configuration of the display device 1 according to this embodiment will be described with reference to Figures 3 to 5. Figure 3 is a block diagram showing the functional configuration of the display device 1 according to this embodiment. In the following description, for simplicity, signals and the wiring that transmits the signals may be referred to by the same reference numerals.

As shown in FIG. 3, the display device 1 includes a display module 10, a control unit 20, and a power supply 30. The display module 10 includes a display panel 12 (display unit), a gate driver 13, and a data driver 14.

The display panel 12 is configured by arranging multiple pixel circuits 11 (pixels) in a two-dimensional array (matrix). That is, the display panel 12 has multiple pixel rows L. Each pixel circuit 11 has sub-pixel circuits 11R, 11G, and 11B (sub-pixels) corresponding to the emitted colors R, G, and B, respectively. In this embodiment, an example is described in which each of the multiple pixels constituting the multiple pixel rows L has an organic EL element as its light-emitting element, but this is not limited to this. The display panel 12 may also have QLED (Quantum-dot Light Emitting Diode) elements as its light-emitting elements.

Each row of the matrix is provided with three control signal lines INI, REF, and WS that are connected to the multiple pixel circuits 11 arranged in the same row. The control signal lines INI, REF, and WS transmit the control signals INI, REF, and WS supplied from the gate driver 13 to the pixel circuits 11. Note that the number of control signal lines and the control signals are merely examples and are not limited to this example. The control signal lines INI, REF, and WS are also examples of scan lines.

Scanning lines are arranged for each of multiple pixel rows L and are provided to select the pixel row L to which a data signal corresponding to a video signal is written.

Each column of the matrix is provided with three data signal lines Vdat _R , Vdat _G , and Vdat _B connected to the pixel circuits 11 arranged in the same column. The data signal lines Vdat R, Vdat G, and Vdat _B transmit data signals Vdat _R , Vdat _G , and Vdat _B related to the emission brightness of R, _G , and _B supplied from the data driver 14 to the pixel circuits 11, respectively.

In FIG. 3, the gate driver 13 is arranged on one side of the display panel 12, but it may be arranged on both sides. Furthermore, the data driver 14 may be mounted on the display panel 12 using COG (chip on glass) or COF (chip on film).

The control unit 20 controls each component of the display module 10. The control unit 20 receives a video signal from an external device and supplies control signals to the gate driver 13 and data driver 14 to display an image of each frame of the video signal on the display panel 12.

The power supply 30 supplies operating power to the display panel 12, gate driver 13, data driver 14, and control unit 20. The power supply 30 supplies, for example, reference voltages VINI and VREF, a positive power supply voltage VCC, and a negative power supply voltage VCATH to the display panel 12.

The detailed configuration of the pixel circuit 11 will now be described with reference to Figures 4 to 7. Figure 4 is a circuit diagram showing the configuration of the pixel circuit 11 of the display device 1 according to this embodiment.

As shown in FIG. 4, the sub-pixel circuits 11R, 11G, and 11B that make up the pixel circuit 11 have the same configuration. Below, the configuration of the pixel circuit 11 will be explained, focusing on the sub-pixel circuit 11R.

The sub-pixel circuit 11R includes an initialization transistor _T1R , a compensation transistor _T2R , a write transistor _T3R , a storage capacitor _CsR , a drive transistor TD _R , and a light-emitting element EL _R. The sub-pixel circuit 11R also includes control signal lines INI, REF, WS, reference voltage lines VINI, VREF, a data signal line Vdat _R , a positive power supply line VCC, and a negative power supply line VCATH. Note that the initialization transistor _T1R and the compensation transistor _T2R are not essential components.

The initialization transistor _T1R is turned on in accordance with the control signal INI, and sets the source node of the drive transistor _TDR to a reference voltage (standard voltage) VINI.

The compensation transistor _T2R is turned on in accordance with the control signal REF and supplies the reference voltage VREF to the gate electrode (gate node) of the drive transistor _TDR . This corresponds to initializing the potential of the electrode (e.g., anode) of the light-emitting element _ELRR .

The write transistor _T3R is turned on in response to the control signal WS, and causes the voltage of the data signal _VdatR to be held in the holding capacitor _CsR . The write transistor _T3R is connected between the data signal line _VdatR and the gate electrode of the drive transistor _TDR . Specifically, one of the source electrode and the drain electrode of the write transistor _T3R is connected to the data signal line _VdatR , and the other of the source electrode and the drain electrode is connected to one of the source electrode and the drain electrode of the compensation transistor _T2R and the gate electrode of the drive transistor _TDR .

The drive transistor TD _R has one of its source electrode and drain electrode connected to the positive power supply line VCC, and the other of its source electrode and drain electrode connected to the anode of the light-emitting element EL _R , and supplies a light-emitting current to the light-emitting element EL _R according to the data signal Vdat _R held in the storage capacitor Cs _R. This causes the light-emitting element EL _R to emit light with a luminance according to the data signal Vdat _R.

The storage capacitor _CsR stores the data signal _VdatR supplied via the data signal line _VdatR . As will be described in detail later, the storage capacitor _CsR according to the present disclosure has a larger capacitance than the storage capacitor _CsR according to the comparative example. The storage capacitor _CsR according to the present disclosure is realized by a combined capacitance of the storage capacitor Cs_conv shown in the comparative example and the storage capacitor Cs_add (see FIG. 6 ).

The light-emitting element EL _R is a self-luminous light-emitting element, and in this embodiment, is an organic EL (Electro Luminescence) element. The anode electrode of the light-emitting element EL _R is connected to one of the source electrode and the drain electrode of the drive transistor TD _R. A cathode voltage (negative power supply voltage VCATH) is applied to the cathode electrode of the light-emitting element EL _R via a cathode power supply line (negative power supply line VCATH).

4 indicates the potential of the gate electrode of _the driving transistor _TDR , and the source potential _VsR indicates the potential of the source electrode of the driving transistor _TDR .

Note that each of the transistors described above is, for example, an n-type thin film transistor (n-type TFT), but may also be a p-type thin film transistor (p-type TFT). Furthermore, each of the transistors described above may be, for example, a polysilicon semiconductor TFT, but is not limited to this.

The cross-sectional configuration of the pixel circuit 11 will now be described with reference to Figures 5 to 7. Figure 5 is a plan view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to this embodiment. Figure 6 is a cross-sectional view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to this embodiment, taken along the VI-VI cutting line in Figure 5. Figure 7 is a cross-sectional view schematically showing the configuration of the pixel circuit 11 of the display device 1 according to this embodiment, taken along the VII-VII cutting line in Figure 5.

As shown in Figures 5 to 7, the pixel circuit 11 according to this embodiment has a lower electrode 310 instead of the lower electrode 210 of the pixel circuit 1011 according to the comparative example, and further has a second upper electrode 320 and a fourth insulating layer 200.

The lower electrode 310 is connected to the gate electrode of the drive transistor _TDR and the write transistor _T3R , and functions as one electrode for forming the storage capacitors Cs_conv and Cs_add. The lower electrode 310 has a larger area in a planar view than the lower electrode 210 according to the comparative example. The lower electrode 310 is formed, for example, to cover a portion of the first upper electrode 220 and the second upper electrode 320 in a planar view. For example, the lower electrode 310 is arranged to overlap a first opposing portion of the first upper electrode 220 and a second opposing portion of the second upper electrode 320 in a planar view. For example, the lower electrode 310 is formed across the positive power supply line VCC. Note that the lower electrode 310 does not overlap a data signal line (the data signal line _VdatG in the example of FIG. 6) of an adjacent subpixel circuit in a planar view.

In a plan view, the lower electrode 310 has a first electrode portion 310a which is a portion facing the first upper electrode 220, a second electrode portion 310b facing the first electrode portion 320a, a third electrode portion 310c facing the second electrode portion 320b, and a fourth electrode portion 310d connected to the gate electrode of the driving transistor TD _R. The lower electrode 310 covers the first upper electrode 220 (for example, a first facing portion described later), the first electrode portion 320a, and the second electrode portion 320b.

The first electrode portion 310a is, for example, rectangular, while the second electrode portion 310b and the third electrode portion 310c are elongated. For example, the second electrode portion 310b and the third electrode portion 310c are elongated along the positive power supply line VCC. In a plan view, the lower electrode 310 has a configuration in which the positive power supply line VCC is sandwiched between the second electrode portion 310b and the third electrode portion 310c. The first electrode portion 310a corresponds to the lower electrode 210 shown in the comparative example. The fourth electrode portion 310d is an example of a first wiring portion.

In plan view, the portion of the lower electrode 310 that overlaps with the first upper electrode 220 and the second upper electrode 320, i.e., the portion of the lower electrode 310 that covers the first upper electrode 220 and the second upper electrode 320, is an example of a third opposing portion. In addition, in plan view, the portion of the first upper electrode 220 that overlaps with the lower electrode 310 is an example of a first opposing portion. It can also be said that the first upper electrode 220 has a first opposing portion that is disposed opposite the lower electrode 310 on the first insulating layer 140. The first upper electrode 220 is an example of a second electrode layer.

As shown in Figures 6 and 7, the pixel circuit 11 has a second upper electrode 320 and a third insulating layer 190 between the second insulating layer 150 and the metal layer 160.

The first insulating layer 140 is formed to cover the second undercoat layer 130 on which one or more electrodes (first wiring layer) including the lower electrode 310 are formed. It can also be said that the first insulating layer 140 is formed to cover the lower electrode 310.

The second insulating layer 150 is formed to cover the first insulating layer 140 on which one or more electrodes (second wiring layer) including the first upper electrode 220 are formed. It can also be said that the second insulating layer 150 covers the first upper electrode 220 and the first insulating layer 140.

At least a portion of the second upper electrode 320 is formed on the second insulating layer 150, and functions as the other electrode for forming the storage capacitor Cs_add. The second upper electrode 320 is connected to one of the source electrode and drain electrode of the drive transistor _TDR via a connection portion 330. In other words, the second upper electrode 320 is electrically connected to the first upper electrode 220 and has the same potential. In this embodiment, the second upper electrode 320 is also connected to one of the source electrode and drain electrode of the initialization transistor _T1R via the connection portion 330. The second upper electrode 320 is an example of a third electrode layer.

The connection section 330 connects the first upper electrode 220 to one of the source electrode and the drain electrode of the driving transistor _TDR . The connection section 330 is an example of a second wiring section.

As shown in FIG. 7 , the connection between the connection portion 330 and the second upper electrode 320 is realized at contact portion C. A through-hole 151 is formed in the second insulating layer 150 at a position where the connection portion 330 and the second upper electrode 320 (e.g., third electrode portion 320c) overlap, and the connection portion 330 and the second upper electrode 320 are connected via this through-hole 151. For example, the through-hole 151 connects the connection portion 330 formed directly on the first insulating layer 140 to the second upper electrode 320. It can also be said that the second upper electrode 320 is electrically connected to the source electrode of the drive transistor TD via the connection portion 330.

The second upper electrode 320 has a first electrode portion 320a, a second electrode portion 320b, and a third electrode portion 320c. In this embodiment, the second upper electrode 320 is formed directly on the second insulating layer 150.

The first electrode portion 320a has a portion facing the second electrode portion 310b and is provided closer to the data signal line Vdat _R than the positive power supply line VCC. The first electrode portion 320a is elongated in the X-axis direction along the positive power supply line VCC. The first electrode portion 320a is a portion that overlaps with the lower electrode 310 (e.g., the second electrode portion 310b) in a plan view.

The second electrode portion 320b has a portion facing the third electrode portion 310c, and is provided between the positive power supply line VCC and the data signal line of the adjacent subpixel (the data signal line Vdat _G in the example of FIG. 5 ). The first electrode portion 320a is elongated in the X-axis direction along the positive power supply line VCC. The second electrode portion 320b is a portion that overlaps with the lower electrode 310 (for example, the third electrode portion 310c) in a plan view.

The first electrode portion 320a and the second electrode portion 320b are provided at positions that do not overlap with the first opposing portion in a planar view. The first electrode portion 320a and the second electrode portion 320b are formed to sandwich the positive power supply line VCC in a planar view. The first electrode portion 320a and the second electrode portion 320b may be provided parallel to each other in a planar view. Furthermore, the length of the second electrode portion 320b in the X-axis direction may be the same as the length of the first electrode portion 320a in the X-axis direction. The first electrode portion 320a and the second electrode portion 320b are an example of a second opposing portion.

The third electrode portion 320c is elongated in a direction intersecting (e.g., perpendicular to) the longitudinal direction (X-axis direction) of the first electrode portion 320a and the second electrode portion 320b in a plan view, and is provided to electrically connect the first electrode portion 320a and the second electrode portion 320b to the connection portion 330. The third electrode portion 320c is formed, for example, to cover the inner surface of the through-hole 151. Furthermore, the third electrode portion 320c intersects with the fourth electrode portion 310d in a plan view, and overlaps with a portion of the fourth electrode portion 310d.

In order to prevent an increase in the parasitic capacitance of existing wiring, the second upper electrode 320 is preferably formed in an area where there are no signal lines or the like below.

The fourth insulating layer 200 is provided to cover the second insulating layer 150 on which one or more electrodes (third wiring layer) including the second upper electrode 320 are formed. The fourth insulating layer 200 is, for example, a silicon oxide film, but may also be composed of an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film.

The constituent material of each electrode layer described above may be, for example, a simple substance or alloy containing one of titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), molybdenum (Mo), silver (Ag), neodymium (Nd), and copper (Cu). Alternatively, it may be a compound containing at least one of these, or a laminated film containing two or more of these. Alternatively, a transparent conductive film such as ITO may be used.

As described above, in the pixel circuit 11 according to the present embodiment, in addition to the storage capacitance Cs_conv shown in the pixel circuit 1011 according to the comparative example, the storage capacitance Cs_add is formed by the lower electrode 310, the second upper electrode 320, and the first insulating layer 140 and second insulating layer 150 between the lower electrode 310 and the second upper electrode 320. Specifically, the storage capacitance Cs_add is formed by the combined capacitance of the first auxiliary storage capacitance between the second electrode portion 310b and the first electrode portion 320a, the second auxiliary storage capacitance between the third electrode portion 310c and the second electrode portion 320b, and the third auxiliary storage capacitance between the fourth electrode portion 310d and the third electrode portion 320c.

The storage capacitance Cs_add can be calculated using the following formula (1), where S is the area where the lower electrode 310 and the second upper electrode 320 overlap in a plan view, and d1 is the distance between the lower electrode 310 and the second upper electrode 320.

Cs_add=ε0×εx×S/d1 (Formula 1)

Note that ε0 represents the dielectric constant of a vacuum, and εx represents the relative dielectric constant. Furthermore, the total storage capacitance Cs of the pixel circuit 11 can be calculated using the following (Equation 2):

Cs=Cs_conv+Cs_add...(Formula 2)

The storage capacitance Cs is greater than the storage capacitance Cs_conv.

In this way, the display device 1 according to this embodiment can make the storage capacitance Cs larger than the storage capacitance Cs_conv described in the comparative example.

In addition, in a plan view, the area where the second electrode portion 310b and the first electrode portion 310a overlap, and the area where the third electrode portion 310c and the second electrode portion 310b overlap, may be equal, for example. In other words, the storage capacitance Cs_add formed by the second electrode portion 310b and the first electrode portion 310a may be equal to the storage capacitance Cs_add formed by the third electrode portion 310c and the second electrode portion 310b. Note that the two storage capacitances Cs_add are not limited to being equal, and may be different from each other.

[1-2. Effect of increasing storage capacitance]
The effect of increasing the storage capacitance Cs will be described with reference to FIG. 8 . FIG. 8 is a diagram for explaining the effect of the display device 1 according to the present embodiment. The vertical axis of FIG. 8 represents the degree of decrease in pixel current (light-emitting current), and the horizontal axis represents time. FIG. 8 shows a comparison of the degree of decrease in pixel current over one frame between the display device 1 and a display device of the prior art, based on the value of the pixel current at the start of one frame. Note that the prior art refers to a display device in which the storage capacitance of the pixel circuit is formed only by the storage capacitance Cs_conv, out of the storage capacitances Cs_conv and Cs_add.

As shown in Figure 8, the display device 1 according to this embodiment reduces the decrease in pixel current over one frame compared to display devices of the prior art (see "Improved -ΔIpix" in Figure 8). The display device 1 has a larger storage capacitance Cs than conventional display devices, and therefore a larger amount of accumulated charge. On the other hand, the amount of pixel current lost due to off-leakage is constant regardless of storage capacitance Cs. In other words, the display device 1 has a small ratio of the amount of charge reduction due to off-leakage to the amount of accumulated charge. Therefore, as shown in Figure 8, the display device 1 according to this embodiment reduces the degree of decrease in pixel current, thereby reducing the decrease in light-emitting current and suppressing changes in brightness due to off-leakage.

For example, if the combined storage capacitance of the storage capacitance Cs_conv and the storage capacitance Cs_add is 1.5 times the storage capacitance of the storage capacitance Cs_conv alone, the decrease in the potential difference Vgs between the gate and source of the drive transistors TD _R , TD _G , and TD _B can be suppressed to approximately 0.67 times, thereby suppressing the decrease in the pixel current Ipix.

Note that the display device 1 according to this embodiment has a configuration in which a combined storage capacitance Cs of the storage capacitance Cs_conv and the storage capacitance Cs_add is formed, and therefore the pixel current increases as the storage capacitance increases. Therefore, in the display device 1, the data signal may be adjusted so that the pixel current flowing through the light-emitting element EL for the same pixel value matches that in a configuration in which the storage capacitance Cs is formed only by the storage capacitance Cs_conv (for example, a configuration according to a comparative example).

[1-3. Operation of pixel circuit]
The operation of the pixel circuit 11 will be described with reference to Fig. 9. Fig. 9 is a timing chart showing various gate control signals (control signals INI, REF, WS) of the display device 1 according to the present embodiment.

As shown in Figure 9, the period from time t1 to time t4 is the off period. At time t1, the control signal REF changes from low to high, turning on the compensation transistors _T2R , _T2G , and _T2B , thereby starting the off period. From time t2 to time t3, the control signal REF is at low level, the control signal INI is at high level, and an initialization period is performed during which an initialization operation is performed. From time t3 to time t4, the control signal REF is at high level, the control signal INI is at low level, and a threshold compensation period (Vth compensation period) is performed during which a threshold compensation operation is performed.

Between time t4 and time t5, the control signal WS is at a high level, so the write transistors _T3R , _T3G , and _T3B are turned on, and the data signals held in the data signal lines _VdatR , _VdatG , and _VdatB are written to the storage capacitors _CsR , _CsG , and _CsB , respectively. The period from time t4 to time t5 is a data write period. Between time t4 and time t5, for example, charge is stored simultaneously in the storage capacitors Cs_conv and Cs_add.

Then, at time t5, the control signal WS goes to low level, causing the light-emitting elements EL _R , EL _G , and EL _B to emit light.

The off period is a period for initial setting, and more specifically, a period during which the subpixel circuit is not lit (i.e., black display). If there are n pixel rows and one horizontal period is 1H, the off period is, for example, a period defined by n x H. Note that "black display" is not limited to complete black (non-emission), but also includes substantially black, and may include, for example, a brightness below a predetermined level.

[1-4. Effects, etc.]
The effects of the display device 1 will be described below, but for convenience, the light-emitting elements EL _R , EL _G , and EL _B will be referred to as light-emitting elements EL, the data signal lines and data signals Vdat _R , Vdat _G , and Vdat _B will be referred to as data signal lines and data signals Vdat, the storage capacitors Cs _R , Cs _G , and Cs _B will be referred to as storage capacitors Cs, the drive transistors TD _R , TD _G , and TD _B will be referred to as drive transistors TD, and the write transistors T3 _R , T3 _G , and T3 _B will be referred to as write transistors T3.

As described above, the display device 1 according to this embodiment is a display device including a plurality of pixels (pixel circuits 11) arranged two-dimensionally. Each of the plurality of pixels includes a light-emitting element EL, a storage capacitor Cs that holds a data signal supplied via a data signal line Vdat, a drive transistor TD that supplies a current corresponding to the data signal Vdat to the light-emitting element EL, and a write transistor T3 connected between the data signal line Vdat and the gate electrode of the drive transistor TD, with one of its source electrode and drain electrode connected to the data signal line Vdat. The storage capacitor Cs includes a lower electrode 310 (an example of a first electrode layer) connected to the gate electrode of the drive transistor TD and the write transistor T3, a first insulating layer 140 covering the lower electrode 310, a first upper electrode 220 connected to the source electrode of the drive transistor TD and having a first opposing portion disposed on the first insulating layer 140 opposite the lower electrode 310, a second insulating layer 150 covering the first insulating layer 140 and the lower electrode 310, and a second insulating layer 150 connected to the source electrode of the drive transistor TD and having a small The display device 1 is formed of a second upper electrode 320 (an example of a third electrode layer) at least a portion of which is formed on the second insulating layer 150, the second upper electrode 320 having a second opposing portion (e.g., a first electrode portion 320a and a second electrode portion 320b) arranged opposite the lower electrode 310, the first opposing portion and the second opposing portion being formed in positions that do not overlap each other in a planar view of the display device 1, and the lower electrode 310 being formed so as to overlap each of the first opposing portion and the second opposing portion in a planar view.

As a result, in addition to the storage capacitance Cs_conv formed by the lower electrode 310, the first upper electrode 220 (first opposing portion), and the first insulating layer 140, a storage capacitance Cs_add formed by the lower electrode 310, the second upper electrode 320 (second opposing portion), and the first insulating layer 140 (or the first insulating layer 140 and the second insulating layer 150) is formed. In other words, in the display device 1, the storage capacitance Cs is larger than in the past in each of the multiple pixels. As described in FIG. 8, this display device 1 accumulates a larger amount of charge than in the past, and is therefore less susceptible to the effects of off-leakage. Therefore, the display device 1 according to this embodiment can suppress changes in luminance due to off-leakage of the writing transistor T3 (switching transistor).

In addition, the second opposing portion is formed directly on the second insulating layer 150.

As a result, a storage capacitance Cs_add is formed by the second opposing portion (e.g., the first electrode portion 320a and the second electrode portion 320b) formed directly on the second insulating layer 150 and the lower electrode 310, thereby increasing the storage capacitance Cs for each pixel.

The lower electrode 310 also has a third opposing portion that covers the first opposing portion and the second opposing portion, and a fourth electrode portion 310d that connects the third opposing portion to the gate electrode of the drive transistor TD, and the second upper electrode 320 overlaps a portion of the fourth electrode portion 310d (an example of a first wiring portion) in a plan view.

This allows capacitance to be formed in the area where the second upper electrode 320 and the fourth electrode portion 310d overlap, further increasing the storage capacitance Cs_add.

Furthermore, the first opposing portion is rectangular in plan view, and the second opposing portion is elongated in plan view.

As a result, the first opposing portion and the second opposing portion are formed with different shapes, so even if there is a limit to the layout area in which the first opposing portion and the second opposing portion can be provided, the storage capacitance Cs_add can be effectively increased.

In addition, the second insulating layer 150 has a through-hole 151 formed in a position where, in a plan view, the second upper electrode 320 overlaps with a connection section 330 (an example of a second wiring section) that connects the first upper electrode 220 and the source electrode of the driving transistor TD, and the second upper electrode 320 is electrically connected to the source electrode of the driving transistor TD via the through-hole 151.

This allows the second upper electrode 320 to be formed wider, further increasing the storage capacitance Cs_add.

Furthermore, the second opposing portion is provided with a positive power supply line VCC (an example of a power supply line) that is connected to the drain electrode of the drive transistor TD and is formed in an elongated shape in a planar view, and is formed so as to sandwich the positive power supply line VCC in a planar view.

This allows the storage capacitance Cs_add to be effectively increased by utilizing the space around the positive power supply line VCC in a plan view.

(Embodiment 2)
The display device according to the present embodiment will be described below with reference to FIGS. 10 to 13. The following description will focus on differences from the first embodiment, and descriptions of content that is the same as or similar to the first embodiment will be omitted or simplified. In the present embodiment, an example will be described in which the other electrode that forms the storage capacitor Cs_add is formed at a position below the upper surface of the second insulating layer 150. A configuration in which the other electrode is formed in a through-hole in the second insulating layer 150 will be described using FIG. 10, and a configuration in which the other electrode is formed in a bottomed recess in the second insulating layer 150 will be described using FIG. 11.

[2-1. Configuration of display device]
FIG. 10 is a cross-sectional view schematically showing a first example of the configuration of the pixel circuit 11 of the display device 1 according to the present embodiment, taken along a cutting line corresponding to cutting line VI-VI in FIG.

As shown in FIG. 10, the first electrode portion 320a and the second electrode portion 320b of the second upper electrode 320 are formed not on the second insulating layer 150 but in through holes 152 and 153 formed in the second insulating layer 150. In the example of FIG. 10, the through holes 152 and 153 are recesses that penetrate the second insulating layer 150 in the Z-axis direction. In other words, the second insulating layer 150 has recesses (through holes 152 and 153) that penetrate toward the first insulating layer 140 (negative Z-axis side) at positions that overlap the first electrode portion 320a and the second electrode portion 320b in a plan view.

In this case, the first electrode portion 320a and the second electrode portion 320b are formed on the first insulating layer 140. In other words, the first electrode portion 320a and the second electrode portion 320b and the first upper electrode 220 are formed on the same layer (second wiring layer), and the distance d2 to the lower electrode 310 is equal. Distance d2 is smaller than distance d1.

In a cross-sectional view, the first electrode unit 320a is arranged between the first upper electrode 220 and the positive power supply line VCC so as not to contact each other, and the second electrode unit 320b is arranged between the positive power supply line VCC and the data signal line Vdat _G so as not to contact each other. In other words, the first electrode unit 320a and the second electrode unit 320b are electrically isolated from the first upper electrode 220, the positive power supply line VCC, and the data signal line Vdat _G. The first electrode unit 320a and the second electrode unit 320b have a portion (first portion) facing the lower electrode 310.

The storage capacitance Cs_add can be calculated using the following formula (3), where S is the area where the lower electrode 310 and the second upper electrode 320 overlap in a planar view, and d2 is the distance between the lower electrode 310 and the second upper electrode 320.

Cs_add=ε0×εx×S/d2 (Formula 3)

Furthermore, the first electrode portion 320a is formed so as to cover the inner surface 152a of the through hole 152, and the second electrode portion 320b is formed so as to cover the inner surface 153a of the through hole 153. The through holes 152 and 153 are formed at positions that do not overlap with the electrodes of the second wiring layer (the first upper electrode 220, the positive power supply line VCC, and the data signal line Vdat _G ) in a planar view. The through hole 152 is formed in an elongated shape along the positive power supply line VCC between the first upper electrode 220 and the positive power supply line VCC in a planar view, and the through hole 153 is formed in an elongated shape along the positive power supply line VCC between the positive power supply line VCC and the data signal line Vdat _G in a planar view. For example, the through holes 152 and 153 are parallel through grooves in a planar view.

The portion of the first electrode portion 320a formed on the inner surface 152a of the through-hole 152 (an example of the second portion) and the portion of the second electrode portion 320b formed on the inner surface 153a of the through-hole 153 (an example of the second portion) extend along the positive power supply line VCC in a planar view. By forming electrodes on the inner surfaces 152a and 153a, capacitance is formed between the electrodes and the lower electrode 310. In other words, by forming electrodes on the inner surfaces 152a and 153a, it is expected that the effect of further increasing the storage capacitance Cs_add will be achieved. The second portion is connected to the first portion.

The number of through holes 152 and 153 formed in the second insulating layer 150 is not limited to two, and may be one, three, or more, as long as they are formed in the area where the lower electrode 310 and the second upper electrode 320 overlap in a plan view. Furthermore, the through holes 152 and 153 are not limited to being through grooves, and may be realized by multiple cylindrical through holes.

Figure 11 is a cross-sectional view schematically showing a second example of the configuration of a pixel circuit 11 of a display device 1 according to this embodiment, taken along a cutting line corresponding to cutting line VI-VI in Figure 5.

As shown in FIG. 11, the first electrode portion 320a and the second electrode portion 320b of the second upper electrode 320 are formed in recesses 154 and 155 formed in the second insulating layer 150. In the example of FIG. 11, the recesses 154 and 155 are bottomed (open) grooves that do not penetrate the second insulating layer 150 in the Z-axis direction. In other words, the second insulating layer 150 has bottomed recesses 154 and 155 formed in a plan view at positions that overlap the first electrode portion 320a and the second electrode portion 320b and are recessed toward the first insulating layer 140 (negative Z-axis side).

Since the recesses 154 and 155 are bottomed grooves, the first electrode portion 320a and the second electrode portion 320b are formed on the bottom surfaces of the recesses 154 and 155. In other words, the first electrode portion 320a and the second electrode portion 320b are formed between the second wiring layer and the third wiring layer, and the distance to the lower electrode 310 is distance d3. Distance d3 is smaller than distance d1 and larger than distance d2 (see Figure 10).

The recesses 154 and 155 are formed at the same positions in a plan view as the through holes 152 and 153.

The storage capacitance Cs_add can be calculated using the following equation (4), where S is the area where the lower electrode 310 and the second upper electrode 320 overlap in a plan view, and d3 is the distance between the lower electrode 310 and the second upper electrode 320.

Cs_add = ε0 × εx × S/d3 ... (Equation 4)

Furthermore, the first electrode portion 320a is formed to cover the inner surface of the recess 154, and the second electrode portion 320b is formed to cover the inner surface of the recess 155.

Figure 12 is a cross-sectional view schematically showing the configuration of a pixel circuit 11 of a display device 1 according to this embodiment, taken along a cutting line corresponding to cutting line VII-VII in Figure 5.

As shown in FIG. 12, the second upper electrode 320 overlaps with the third electrode portion 310c in a planar view, so a storage capacitance Cs_add is also formed between the second upper electrode 320 and the third electrode portion 310c. This makes it possible to further increase the storage capacitance Cs. Also, in the example of FIG. 12, no recess is formed above the third electrode portion 310c. The area above the third electrode portion 310c is the area where the third electrode portion 310c and the fourth electrode portion 310d overlap in a planar view. Because this area is physically close to the drive transistor TD, no recess is formed in this area in consideration of the impact on the operation of the drive transistor TD.

In this case, the area where the second electrode portion 310b and the first electrode portion 320a overlap in a planar view is S1, the storage capacitance formed by the second electrode portion 310b and the first electrode portion 320a is Cs_add_1 (the storage capacitance Cs_add between the second electrode portion 310b and the first electrode portion 320a in FIG. 12), the area where the fourth electrode portion 310d and the third electrode portion 320c overlap in a planar view is S2, and the storage capacitance formed by the second electrode portion 310b and the first electrode portion 320a is Cs_add_2 (the storage capacitance Cs_add between the fourth electrode portion 310d and the third electrode portion 320c in FIG. 12), the relationship shown in Equation 5 below holds.

Cs_add_2/S2<Cs_add_1/S1 (Formula 5)

The second insulating layer 150 may have a bottomed recess formed above the third electrode portion 310c, the recess having a depth that does not affect the operation of the drive transistor TD, and the second upper electrode 320 may be formed on the bottom surface of the recess. The depth of such a recess can be obtained, for example, by experimentation.

The number of recesses 154 and 155 formed in the second insulating layer 150 is not limited to two, and may be one, or three or more, as long as they are formed in an area that overlaps with the lower electrode 310 in a plan view. Furthermore, the recesses 154 and 155 are not limited to being groove-shaped recesses, and may be realized as multiple cylindrical recesses.

[2-2. Display device manufacturing method]
Next, a method for manufacturing the through-hole 151, recess 154, and recess 155 shown in FIGS. 11 and 12 will be described with reference to FIG. 13 . FIG. 13 is a diagram for explaining a manufacturing method of the display device 1 according to the present embodiment. FIG. 13 schematically shows an exposure process for forming the through-hole 151, recess 154, and recess 155. Note that the amount of light (e.g., UV light) incident on the photomask 500 is, for example, uniform in plan view. Furthermore, the resin used as the material for the second insulating layer 150 is assumed to be a positive photosensitive resin, but is not limited to this.

The second insulating layer 150 is formed by forming a first wiring layer including the lower electrode 310 on the first insulating layer 140, applying a positive photosensitive resin to form the second insulating layer 150, hardening it (temporarily hardening) by pre-baking, exposing it to light using a photomask 500 shown in Figure 13, removing the resin in the etched areas with a developer, and finally hardening it (mainly hardening) by post-baking.

As shown in FIG. 13, through-holes 151, recesses 154, and recesses 155 are formed by an exposure process using photomask 500. Photomask 500 has a light-shielding portion 510, a transparent portion 520, and a halftone portion 530. Photomask 500 is a multi-tone mask configured to have two or more transparent portions with different light transmittances in addition to light-shielding portion 510.

The light-shielding portion 510 is provided in areas where the through-holes 151, recesses 154, and recesses 155 are not formed (for example, areas including the areas where the third electrode portions 310c are formed), and blocks light from entering the photomask 500.

The transparent portion 520 is provided in the area where the through-hole 151 is formed, and is a portion that transmits light incident on the photomask 500.

The halftone section 530 is provided in the area where the bottomed grooves are formed (for example, the area where the first electrode section 310a and the second electrode section 310b are formed), and is a section that transmits a portion of the light incident on the photomask 500. The halftone section 530 has a lower transmittance than the transmitting section 520 and a higher transmittance than the light-shielding section 510. The halftone section 530 is provided in an elongated shape in the X-axis direction.

By using such a photomask 500, grooves of different depths (for example, through-hole grooves and non-through-hole grooves) can be formed with a single exposure. When forming the through-holes 152 and 153 shown in Figure 10, a photomask in which the halftone portions 530 are replaced with transmissive portions 520 can be used.

[2-3. Effects, etc.]
As described above, the second insulating layer 150 of the display device 1 according to this embodiment has bottomed recesses 154 and 155 formed on the first insulating layer 140 side (negative Z-axis side) at positions that overlap the lower electrode 310 (an example of a first electrode layer) in a planar view, and the second opposing portions (e.g., the first electrode portion 320a and the second electrode portion 320b) may be formed on the bottom surfaces of the recesses 154 and 155.

This allows the distance between the first electrode portion 320a and the second electrode portion 320b and the lower electrode 310 to be reduced, further increasing the storage capacitance Cs_add. Furthermore, the second insulating layer 150 is present between the first electrode portion 320a and the second electrode portion 320b and the underlying signal lines. Therefore, the display device 1 can increase the storage capacitance Cs while preventing the first electrode portion 320a and the second electrode portion 320b from shorting out with other signal lines.

In addition, through holes 152 and 153 (examples of recesses) that penetrate toward the first insulating layer 140 are formed in the second insulating layer 150 at positions that overlap the lower electrode 310 in a plan view, and the second opposing portion is formed directly on the first insulating layer 140.

This allows the distance between the first electrode portion 320a and the second electrode portion 320b and the lower electrode 310 to be reduced to the distance d2 between the first upper electrode 220 and the lower electrode 310, thereby further increasing the storage capacitance Cs_add. Therefore, the display device 1 can further increase the storage capacitance Cs.

The second opposing portion is composed of a first portion that faces the lower electrode 310 and a second portion that is formed on the inner surface of the recess (e.g., the inner surfaces 152a and 153a of the through holes 152 and 153).

This forms a capacitance between the second portion and the lower electrode 310, further increasing the storage capacitance Cs_add.

(Embodiment 3)
The display device according to the present embodiment will be described below with reference to FIGS. 14 and 15. The following description will focus on differences from the first embodiment, and descriptions of the same or similar aspects as those of the first embodiment will be omitted or simplified. The present embodiment will describe a case where a VCC auxiliary line 410 and a VCATH auxiliary line 420 are formed in a pixel circuit 11. While FIG. 14 illustrates an example in which both the VCC auxiliary line 410 and the VCATH auxiliary line 420 are formed in the pixel circuit 11, it is sufficient that at least one of the VCC auxiliary line 410 and the VCATH auxiliary line 420 is formed.

[3-1. Configuration of display device]
Fig. 14 is a plan view schematically showing the configuration of a pixel circuit 11 of a display device 1 according to the present embodiment. Fig. 15 is a cross-sectional view schematically showing the configuration of a pixel circuit 11 of a display device 1 according to the present embodiment, taken along the XV-XV cutting line in Fig. 14.

As shown in Figures 14 and 15, the pixel circuit 11 of the display device 1 according to this embodiment includes a VCC auxiliary line 410 and a VCATH auxiliary line 420 in addition to the pixel circuit 11 according to embodiment 1. The VCC auxiliary line 410 is an example of a first auxiliary line, and the VCATH auxiliary line 420 is an example of a second auxiliary line.

The VCC auxiliary line 410 is electrically connected to the positive power supply line VCC and is provided in the pixel circuit 11 to suppress a voltage drop of the positive power supply voltage VCC in the display area. The VCC auxiliary line 410 is, for example, a metal line having a lower resistance than the positive power supply line VCC. For example, the VCC auxiliary line 410 is a metal line. Furthermore, the VCC auxiliary line 410 is, for example, formed in an elongated shape along the data signal line Vdat (the data signal line Vdat _R in the example of FIG. 14 ) so as to overlap at least a portion of the data signal line Vdat in a plan view, but does not have to overlap the data signal line Vdat. The VCC auxiliary line 410 is provided in each pixel, for example.

The VCATH auxiliary line 420 is electrically connected to the metal layer 180 and is a line provided in the pixel circuit 11 to suppress a voltage drop of the negative power supply voltage VCATH in the display area. The VCATH auxiliary line 420 is, for example, a metal line having a lower resistance than the metal layer 180. For example, the VCATH auxiliary line 420 is a metal line. Furthermore, the VCATH auxiliary line 420 is, for example, formed in an elongated shape along the data signal line Vdat so that at least a portion of the VCATH auxiliary line 420 overlaps with the data signal line Vdat (the data signal line Vdat _B in the example of FIG. 14 ) in a plan view, but does not have to overlap with the data signal line Vdat. The VCATH auxiliary line 420 is provided in each pixel, for example.

Such VCC auxiliary lines 410 and VCATH auxiliary lines 420 are formed on the second insulating layer 150, and the pixel circuits 11 including the VCC auxiliary lines 410 and VCATH auxiliary lines 420 are formed on the fourth insulating layer 200. The VCC auxiliary lines 410 and VCATH auxiliary lines 420 are arranged in positions that do not overlap the lower electrodes 310 and connection portions 330 in a plan view.

Therefore, in a pixel circuit 11 having a VCC auxiliary line 410 and a VCATH auxiliary line 420, the second upper electrode 320 can be formed in an area other than the area where the VCC auxiliary line 410 and the VCATH auxiliary line 420 are formed in a plan view without forming an additional layer.

If the distance between the data signal line Vdat _R and the auxiliary VCC line 410 is d4, and the distance between the data signal line Vdat _R and the first electrode unit 320a and the second electrode unit 320b is d5, the following (Equation 6) holds.

d4>d5...(Formula 6)

This makes it possible to prevent a short circuit between the data signal line Vdat _R and the VCC auxiliary line 410, since the insulating layer (second insulating layer 150) below the VCC auxiliary line 410 is thick. In other words, the insulation between the data signal line Vdat _R and the VCC auxiliary line 410 can be maintained.

Although the VCATH auxiliary line 420 is not shown in FIG. 15, the distance between the data signal line Vdat _R and the VCATH auxiliary line 420 is also the distance d4.

In addition, at least a portion of the second electrode portion 320b and the third electrode portion 320c are located closer to the lower electrode 310 (negative Z-axis side) than the VCC auxiliary line 410 and the VCATH auxiliary line 420 in a cross-sectional view.

[3-2. Effects, etc.]
As described above, the display device 1 according to the present embodiment includes a positive power supply line VCC that is connected to the drain electrode of the drive transistor TD and that is formed in a long shape in a plan view, and a VCC auxiliary line 410 (an example of a first auxiliary line) that is connected to the positive power supply line VCC and has a lower resistance than the positive power supply line VCC. The VCC auxiliary line 410 may be formed on the second insulating layer 150. The display device 1 according to the present embodiment also includes a metal layer 180 (an example of a fourth electrode layer) that is connected to the cathode electrode of the light-emitting element EL and covers a plurality of pixels, and a VCATH auxiliary line 420 (an example of a second auxiliary line) that is connected to the metal layer 180 and has a lower resistance than the metal layer 180. The VCATH auxiliary line 420 may be formed on the second insulating layer 150.

As a result, in a display device 1 provided with at least one of the VCC auxiliary line 410 and the VCATH auxiliary line 420, the second upper electrode 320 can be formed on the second insulating layer 150 provided for forming the at least one auxiliary line. In other words, the display device 1 does not need to be provided with a dedicated insulating layer for forming the second upper electrode 320. Therefore, a display device 1 that can suppress changes in brightness due to off-leakage can be realized at low cost.

(Other embodiments)
While the display device according to the present disclosure has been described above based on each embodiment, the display device according to the present disclosure is not limited to the above-described each embodiment. The present disclosure also includes other embodiments realized by combining any of the components in each embodiment, modifications obtained by applying various modifications to each embodiment that would occur to those skilled in the art without departing from the spirit of the present disclosure, and various devices incorporating a display device according to the present embodiment.

For example, one of the grooves (grooves for forming a storage capacitor) formed in the second insulating layer may be a through groove and the other may be a bottomed groove.

The present disclosure may also be realized as a display panel alone. The present disclosure may also be realized in a configuration that does not include a power supply or a control unit. Such a display panel includes a plurality of pixels arranged two-dimensionally, each of which includes a light-emitting element, a storage capacitor that stores a data signal supplied via a data signal line, a drive transistor that supplies a current corresponding to the data signal to the light-emitting element, and a write transistor connected between the data signal line and the gate electrode of the drive transistor, the write transistor having one of its source and drain electrodes connected to the data signal line. The storage capacitor is formed by: a first electrode layer connected to the gate electrode of the drive transistor and the write transistor; a first insulating layer formed on the first electrode layer; a second electrode layer connected to the source electrode of the drive transistor and having a first electrode portion disposed on the first insulating layer opposite the first electrode layer; a second insulating layer formed on the first insulating layer; and a third electrode layer connected to the source electrode of the drive transistor, at least a portion of which is formed on the second insulating layer, the third electrode layer having a second electrode portion disposed opposite the first electrode layer. The first electrode portion and the second electrode portion are positioned so that they do not overlap each other when viewed from above, and the first electrode layer covers the first electrode portion and the second electrode portion. Note that the IC that constitutes the control portion may be mounted on the display panel.

The present disclosure may also be realized as an active matrix substrate alone. The present disclosure may also be realized in a configuration that does not include a power source, a control unit, or an EL layer (e.g., a light-emitting layer and electrode layers sandwiching the light-emitting layer). Such an active matrix substrate is an active matrix substrate used in a display device having a plurality of pixels arranged two-dimensionally, and a pixel circuit for forming each of the plurality of pixels includes a light-emitting element, a storage capacitor for storing a data signal supplied via a data signal line, a drive transistor for supplying a current corresponding to the data signal to the light-emitting element, and a write transistor connected between the data signal line and a gate electrode of the drive transistor, the write transistor having one of its source electrode and drain electrode connected to the data signal line. The storage capacitor is formed by: a first electrode layer connected to the gate electrode of the drive transistor and the write transistor; a first insulating layer formed on the first electrode layer; a second electrode layer connected to the source electrode of the drive transistor and having a first electrode portion arranged on the first insulating layer opposite the first electrode layer; a second insulating layer formed on the first insulating layer; and a third electrode layer connected to the source electrode of the drive transistor, at least a portion of which is formed on the second insulating layer, the third electrode layer having a second electrode portion arranged opposite the first electrode layer. The first electrode portion and the second electrode portion are arranged in positions that do not overlap each other when viewed in a plan view of the active matrix substrate, and the first electrode layer covers the first electrode portion and the second electrode portion.

Furthermore, in each of the above embodiments, the display panel has been described as a top-emission structure display panel, but it may also be a bottom-emission structure display panel.

Furthermore, the control unit and data driver in each of the above embodiments may be implemented as a single IC, or may be implemented as separate ICs.

In addition, in each of the above embodiments, the function and configuration of the initialization transistors _T1G and _T1B may be the same as, for example, the initialization transistor _T1R , the function and configuration of the compensation transistors _T2G and _T2B may be the same as, for example, the compensation transistor _T2R , the function and configuration of the write transistors _T3G and _T3B may be the same as, for example, the write transistor _T3R , and the function and configuration of the drive transistors _TDG and _TDB may be the same as, for example, the drive transistor _TDR .

Furthermore, the functions and configurations of the light-emitting elements _ELLG and _ELLB in the above-described embodiments may be the same as, for example, the light-emitting element _ELLR .

Furthermore, the functions and configurations of the storage capacitors _CsG and _CsB in the above-described embodiments may be the same as those of the storage capacitor _CsR , for example.

Furthermore, while the display devices in the above embodiments have been described as displaying color images, this is not limited to this and, for example, may also display monochrome images.

This disclosure is useful, for example, for display devices using organic EL elements, etc.

REFERENCE SIGNS LIST 1 display device 10 display module 11 pixel circuit 11B, 11G, 11R sub-pixel circuit 12 display panel 13 gate driver 14 data driver 20 control unit 30 power supply 110 substrate 120 first undercoat layer 130 second undercoat layer 140 first insulating layer 150 second insulating layer 151 through-hole 152, 153 through-hole (recess)
152a, 153a: inner surfaces 154, 155: recesses 160: metal layer 180: metal layer (fourth electrode layer)
170 Light-emitting layer 190 Third insulating layer 200 Fourth insulating layer 220 First upper electrode (second electrode layer)
310 Lower electrode (first electrode layer)
310a First electrode part 310b Second electrode part 310c, 320c Third electrode part 310d Fourth electrode part (first wiring part)
320 Second upper electrode (third electrode layer)
320a First electrode part (second opposing part)
320b Second electrode part (second opposing part)
330 Connection section (second wiring section)
410 VCC auxiliary line (1st auxiliary line)
420 VCATH auxiliary line (second auxiliary line)
500 Photomask 510 Light-shielding portion 520 Transparent portion 530 Halftone portion C Contact portion Cs, Cs _B , Cs _G , Cs _R , Cs_add, Cs_conv Storage capacitance d1, d2, d3, d4, d5 Distance EL _B , EL _G , EL _R Light-emitting element INI Initialization signal line, control signal L Pixel row REF Reference signal line, control signal t1, t2, t3, t4, t5 Time T1 _B , T1 _G , T1 _R Initialization transistor T2 _B , T2 _G , T2 _R Compensation transistor T3 _B , T3 _G , T3 _R Write transistor TD _B , TD _G , TD _R Drive transistor VCATH Negative power supply line, negative power supply voltage VCC Positive power supply line (power supply line), positive power supply voltage Vdat _B , Vdat _G , Vdat _R Data signal line, data signal WS Write signal line, control signal

Claims (11)

A display device comprising a plurality of pixels arranged two-dimensionally,
Each of the plurality of pixels is
A light-emitting element;
a storage capacitor that stores a data signal supplied via a data signal line;
a driving transistor that supplies a current corresponding to the data signal to the light emitting element;
a write transistor connected between the data signal line and the gate electrode of the drive transistor, one of a source electrode and a drain electrode of the write transistor being connected to the data signal line;
The retention capacity is
a first electrode layer connected to a gate electrode of the drive transistor and the write transistor;
a first insulating layer covering the first electrode layer;
a second electrode layer connected to a source electrode of the driving transistor and having a first opposing portion disposed on the first insulating layer so as to oppose the first electrode layer;
a second insulating layer covering the first insulating layer and the second electrode layer;
a third electrode layer connected to the source electrode of the driving transistor, at least a portion of which is formed on the second insulating layer, the third electrode layer having a second opposing portion disposed opposite to the first electrode layer;
the first opposing portion and the second opposing portion are formed at positions that do not overlap with each other in a plan view of the display device,
the first electrode layer is formed so as to overlap with each of the first opposing portion and the second opposing portion in the plan view. The display device according to claim 1 , wherein the second opposing portion is formed directly on the second insulating layer. a recess having a bottom recessed toward the first insulating layer at a position overlapping the first electrode layer in the plan view;
The display device according to claim 1 , wherein the second opposing portion is formed on a bottom surface of the recess. a recessed portion that penetrates the second insulating layer toward the first insulating layer at a position that overlaps the first electrode layer in the plan view,
The display device according to claim 1 , wherein the second opposing portion is formed on the first insulating layer. The display device according to claim 3 , wherein the second opposing portion is configured by a first portion opposing the first electrode layer and a second portion formed on an inner surface of the recess. moreover,
a power supply line connected to a drain electrode of the driving transistor and formed in an elongated shape in the plan view;
a first auxiliary line connected to the power supply line and having a lower resistance than the power supply line;
The display device according to any one of claims 1 to 5, wherein the first auxiliary lines are formed on the second insulating layer. moreover,
a fourth electrode layer connected to a cathode electrode of the light-emitting element and covering the plurality of pixels;
a second auxiliary line connected to the fourth electrode layer and having a lower resistance than the fourth electrode layer;
The display device according to claim 1 , wherein the second auxiliary lines are formed on the second insulating layer. The first electrode layer is
a third opposing portion covering the first opposing portion and the second opposing portion;
a first wiring portion connected to the gate electrode of the driving transistor;
The display device according to claim 1 , wherein the third electrode layer overlaps a part of the first wiring portion in the plan view. The first opposing portion has a rectangular shape in the plan view,
The display device according to claim 8 , wherein the second opposing portion has an elongated shape in the plan view. a through hole is formed in the second insulating layer at a position where, in the plan view, a second wiring portion that connects the second electrode layer and the source electrode of the driving transistor and the third electrode layer overlaps with each other;
The display device according to any one of claims 1 to 9, wherein the third electrode layer is electrically connected to the source electrode of the driving transistor via the through hole. further comprising a power supply line connected to a drain electrode of the driving transistor and formed in an elongated shape in the plan view,
The display device according to claim 1 , wherein the second opposing portions are formed so as to sandwich the power line in the plan view.