JP7749436B2 - printed wiring board - Google Patents

Description

The disclosed technology relates to printed wiring boards.

A large number of components, such as semiconductors and integrated circuits (hereafter referred to as "ICs"), are mounted on the printed wiring boards built into electronic devices. The widely used and mainstream BGA (Ball Grid Array) is a well-known packaging format for semiconductors and ICs. In recent years, in response to trends toward smaller and thinner mobile communication devices, for example, there has been a demand for packaging methods that allow for even higher density component mounting.

In addition to BGA, other known packaging techniques include non-leaded packages without external lead terminals, such as QFN (Quad Flat Non-Leaded Package) and SON (Small Outline Non-Leaded Package). QFN and SON use electrodes on the bottom of the package as terminals for connection to a printed wiring board. Because QFN and SON do not have protruding lead terminals, they require a small mounting area and are suitable for high-density mounting. Furthermore, many QFN and SON packages have a ground electrode in the center of the bottom of the package, which serves the role of heat dissipation. QFNs and SONs with such ground electrodes have superior heat dissipation capabilities compared to components with other package shapes. Due to these excellent properties, QFNs and SONs have become increasingly common on printed wiring boards for mobile communication devices in recent years.
Both QFN and SON packages have electrode pads instead of lead terminals as connection terminals. While QFN has electrode pads arranged on all four sides of the package, SON has electrode pads arranged on only two sides of the package.

Mounting a QFN or SON (hereafter collectively referred to as "QFN, etc.") on a printed wiring board involves several steps. The first required step is to print solder paste on the peripheral pads that correspond to the package's peripheral terminals and the pads that correspond to the bottom electrodes, both of which are mounted on the printed wiring board. The next required steps are to align the QFN, etc. with the pads in the mounting position, and to perform reflow soldering (hereafter simply referred to as the "reflow step"). Through these steps, the package's peripheral terminals are soldered to the corresponding peripheral pads, and the bottom electrodes are also soldered to the corresponding pads.

When soldering by reflow, the cream solder melted by heating tends to become round due to surface tension as it aggregates. If too much cream solder is supplied to the pads corresponding to the bottom electrodes, the QFN or other package will end up on top of the rounded solder, causing the package to float. If the package floats, the peripheral terminals located on the periphery of the package will not make contact with the corresponding peripheral pads, resulting in an open defect.

Several countermeasures have been disclosed to eliminate open defects caused by an inappropriate amount of cream solder. For example, Patent Document 1 discloses a technique in which the pads corresponding to the bottom electrodes are divided into multiple regions, for example, four, using solder resist. By printing and melting cream solder of the same size and thickness in each of the four regions, four vertices of the melted solder are created. When a QFN or other package is placed in the designated mounting position on the printed wiring board, the center of gravity of the QFN or other package is located in the center of the region formed by the four vertices. This principle allows the QFN or other package to be stably supported by the molten solder, preventing the QFN or other package from being mounted at an angle to the printed wiring board.

JP 2013-89795 A

Some printed wiring boards have multiple through-holes arranged within the mounting pads of the heat dissipation electrode section to improve thermal conductivity to the backside. However, providing through-holes creates the risk of solder leaking to the backside of the printed wiring board through the through-holes. Solder leaks can lower the solder height of the heat dissipation bottom electrode section, crushing the solder on the peripheral electrode section and ultimately causing a short circuit in the external electrode section.

The disclosed technology aims to prevent short circuits that occur on the mounting pads of external electrodes on printed wiring boards that mount QFNs or other devices with two or more rows of peripheral electrodes.

The printed wiring board according to the disclosed technology is a printed wiring board on which a package 1a including first peripheral bottom electrodes 11 and second peripheral bottom electrodes 12 is mounted. The printed wiring board according to the disclosed technology includes first peripheral mounting pads 21 corresponding to the first peripheral bottom electrodes 11 and second peripheral mounting pads 22 corresponding to the second peripheral bottom electrodes 12, with first peripheral bottom electrode solder 31 and second peripheral bottom electrode solder 32 applied so as to be encompassed within the first peripheral mounting pads 21 and the second peripheral mounting pads 22, respectively, the first peripheral mounting pads 21 having a first peripheral buffer area 21a that expands in the direction toward the outer edge of the package 1a, and the second peripheral mounting pads 22 having a second peripheral buffer area 22a that expands in the direction toward the outer edge of the package 1a and includes a portion that expands into the region between two adjacent first peripheral mounting pads 21 , resulting in an overall convex shape.

The printed wiring board according to the disclosed technology has the above-mentioned configuration, which has the effect of suppressing short-circuit defects that occur on the mounting pads of the external electrodes, even when mounting QFNs or other devices with two or more rows of peripheral electrodes.

FIG. 1 is a bottom view showing an example of a general appearance of a QFN mounted on a printed wiring board according to a first embodiment. FIG. 2 is an enlarged top view of a part of the top surface of the printed wiring board according to the first embodiment, showing the positions and shapes of the mounting pads and solders. FIG. 3 is a comparative reference diagram showing the positions and shapes of the mounting pads and solder when no buffer area is provided. FIG. 4 is a cross-sectional view of the printed wiring board according to the first embodiment after mounting, taken along the line AA' in FIG. FIG. 5 is a cross-sectional view of the prior art, which is compared with FIG. 4, showing the problem of the solder being crushed by the bottom surface of the component. FIG. 6 is a second cross-sectional view of the prior art compared with FIG. 4, showing the problem of the electronic component being tilted. FIG. 7 is a cross-sectional view taken along the line BB' in FIG. 5 or 6, showing a defect in which a short circuit occurs between adjacent electrodes. FIG. 8 is an enlarged top view of a part of the top surface of a printed wiring board according to the second embodiment, showing the positions and shapes of the mounting pads, solder, and silk printing. FIG. 9 is a cross-sectional view of the printed wiring board according to the second embodiment after mounting, taken along the line AA' in FIG.

Embodiment 1.
FIG. 1 is a bottom view showing an example of a typical appearance of a QFN mounted on a printed wiring board 2 according to the first embodiment. As shown in FIG. 1 , the QFN is an electronic component 1 mounted on a printed wiring board 2. The electronic component 1 is shown in the form of a package 1a, and includes a central heat-dissipating bottom electrode 10 located at the center of the bottom surface, first peripheral bottom electrodes 11 located on the outermost sides of each of the four sides, and second peripheral bottom electrodes 12 located in the second row from the outside of each of the four sides. The central heat-dissipating bottom electrode 10, the first peripheral bottom electrode 11, and the second peripheral bottom electrode 12 are sometimes referred to as electrode pads to emphasize that they are not lead terminals.
Although FIG. 1 shows a QFN package 1a, the package 1a mounted on the printed wiring board 2 according to the disclosed technique may be a SON package.

2 is a partially enlarged top view of the top surface of printed wiring board 2 according to embodiment 1, showing the positions and shapes of the mounting pads and solder. As shown in Fig. 2, on the top surface of printed wiring board 2 according to embodiment 1, central mounting pad 20, first peripheral mounting pad 21 including first peripheral buffer area 21a, second peripheral mounting pad 22 including second peripheral buffer area 22a, solder resist 23, application areas of solder 30 for heat dissipation bottom electrodes, application areas of solder 31 for first peripheral bottom electrodes, and application areas of solder 32 for second peripheral bottom electrodes can be seen.
FIG. 3 is a comparative reference diagram showing the positions and shapes of the mounting pads and solder when no buffer area is provided.
Comparing FIG. 2 with FIG. 3, as shown in FIG. 2, the first peripheral mounting pads 21 of the printed wiring board 2 are enlarged in the direction toward the outer edge (i.e., outer rim) of the package 1a, compared to the conventional first peripheral mounting pads 21 shown in FIG. 3, and a first peripheral buffer area 21a is provided.
2 in comparison with Fig. 3, as shown in Fig. 2, the second peripheral mounting pads 22 of the printed wiring board 2 are expanded in the direction toward the adjacent second peripheral mounting pads 22 and in the direction toward the outer edge of the package 1a into the region between two adjacent first peripheral mounting pads 21, thereby providing second peripheral buffer areas 22a, compared to the conventional second peripheral mounting pads 22 shown in Fig. 3. In other words, the shape of the second peripheral mounting pads 22 according to the first embodiment is convex in the direction toward the outer edge of the package 1a.

2 and 3, the first peripheral bottom electrode solder 31 and the second peripheral bottom electrode solder 32 are applied so as to be enclosed within the first peripheral mounting pad 21 and the second peripheral mounting pad 22, respectively. The application of the first peripheral bottom electrode solder 31 and the second peripheral bottom electrode solder 32 may be achieved by printing cream solder. Also, as shown in FIG. 2, the second peripheral bottom electrode solder 32 according to embodiment 1 does not need to be applied up to the second peripheral buffer area 22a.
Cream solder is also called solder paste.

FIG. 4 is a cross-sectional view of the printed wiring board 2 after mounting according to the first embodiment, taken along the line AA' in FIG.
As shown in Figure 4, the printed wiring board 2 of embodiment 1 is composed of, from the inside out, a wiring layer including a central mounting pad 20, a first peripheral mounting pad 21, and a second peripheral mounting pad 22, and an insulating film layer made of solder resist 23.

The electronic component 1 may be mounted on the printed wiring board 2 according to the first embodiment by a reflow process (mounting by the reflow process will be referred to as "reflow mounting"). Reflow mounting is performed through several steps.
The first required step is to apply the heat dissipating bottom electrode solder 30, the first peripheral bottom electrode solder 31, and the second peripheral bottom electrode solder 32. As described above, the heat dissipating bottom electrode solder 30, the first peripheral bottom electrode solder 31, and the second peripheral bottom electrode solder 32 may be cream solder. The printing of the cream solder may be achieved using a metal mask jig.
The next necessary step is to mount the electronic component 1 on the printed wiring board 2. Mounting of the electronic component 1 can be achieved by an automatic mounting machine.
The next required step is the reflow process. In the reflow process, the printed wiring board 2 on which the electronic components 1 are mounted is placed in a reflow furnace. In the reflow furnace, the printed wiring board 2 is preheated, and then heated to melt the cream solder. By this heating, the heat dissipation bottom electrode solder 30, the first peripheral bottom electrode solder 31, and the second peripheral bottom electrode solder 32 each melt and spread over the central mounting pad 20, the first peripheral mounting pad 21, and the second peripheral mounting pad 22, respectively.

In order to improve thermal conductivity to the back surface of printed wiring board 2 according to embodiment 1, multiple penetrating through-holes may be provided in central mounting pad 20. In the reflow process, heat dissipating bottom electrode solder 30 flows out to the back surface of printed wiring board 2 through the penetrating through-holes. This flow to the back surface reduces the solder height of heat dissipating bottom electrode solder 30.
Even if no through-holes are provided, if the amount of solder supplied is less than the designed amount, the solder height will be low.

Reflow mounting involves several steps after the actual heating in the reflow furnace.
The next step required after this heating is a cooling step to solidify the cream solder. During the cooling step, the heat dissipation bottom electrode solder 30 generally begins to solidify earlier than the first peripheral bottom electrode solder 31 and the second peripheral bottom electrode solder 32. This is thought to be because the central mounting pad 20 has a higher thermal conductivity than the first peripheral mounting pad 21 and the second peripheral mounting pad 22, and therefore dissipates heat more easily.
The fact that the solder 30 for the heat dissipating bottom electrode solidifies first means that the height at which the solder 30 for the heat dissipating bottom electrode solidifies is governed by the height at which the solder 30 for the heat dissipating bottom electrode solidifies, and affects the solder heights of the solder 31 for the first outer peripheral bottom electrode and the solder 32 for the second outer peripheral bottom electrode.
When the heat dissipation bottom electrode solder 30 solidifies first and the first and second peripheral bottom electrode solders 31 and 32 are still molten, there is room for the excess solder and flux of the first and second peripheral bottom electrode solders 31 and 32 to spread to the first and second peripheral buffer areas 21a and 22a of the first and second peripheral mounting pads 21 and 22, respectively. In the printed wiring board 2 according to the technology disclosed herein, there is room for the excess solder and flux to spread, thereby suppressing short circuit defects.
The above are the steps required for reflow mounting and the phenomena that occur in each step.

Figure 5 is a cross-sectional view of the prior art compared to Figure 4, showing the problem of the solder being crushed by the bottom surface of the component. Figure 6 is a cross-sectional view of the prior art compared to Figure 4, showing the problem of the electronic component being fixed at an angle. Figure 7 is a cross-sectional view taken along the line B-B' in Figure 5 or Figure 6, showing the problem of a short circuit occurring between adjacent electrodes. The line B-B' is also shown as B-B' in Figure 2 when viewed from above.
As mentioned above, the solder height of the first outer peripheral bottom electrode solder 31 and the second outer peripheral bottom electrode solder 32 is governed by the solder height of the heat dissipation bottom electrode solder 30 that solidified earlier, and if there is not enough room for the first outer peripheral bottom electrode solder 31, the second outer peripheral bottom electrode solder 32, and their respective fluxes to spread, the problems shown in Figures 5 to 7 may occur.

To avoid the problems shown in Figures 5 to 7, it is possible to reduce the amount of solder for the first peripheral bottom electrode solder 31 and the second peripheral bottom electrode solder 32. However, reducing the amount of solder would require a smaller package 1a, which would require a very small printing opening in the metal mask used to print the solder paste. This would also reduce the area of the first peripheral mounting pads 21 and second peripheral mounting pads 22 onto which the solder paste is applied, making it more likely that the solder paste will stick to the metal mask and remain. As a result, the required amount of solder cannot be applied to the printed wiring board 2, and reducing the amount of solder is likely to result in poor soldering.

As described above, the printed wiring board 2 according to embodiment 1 has the above configuration, which has the effect of suppressing short-circuit defects that occur on the mounting pads of the external electrodes, even when mounting QFNs or the like with two or more rows of peripheral electrodes.

In addition, the presence or absence of solder defects on printed wiring boards is generally inspected by checking X-ray images. As mentioned above, the second peripheral mounting pads 22 according to embodiment 1 have a convex shape. Because the technology disclosed herein utilizes the convex shape of these mounting pads, using image processing technology to check the X-ray images makes it easy to identify solder and flux that has spread into the second peripheral buffer area 22a, making it easier to determine the connection status of the connection.

Embodiment 2.
Silk printing may be used in the printed wiring board 2 according to the present disclosure. The printed wiring board 2 according to the second embodiment includes a configuration in which silk printing is used in addition to the configuration shown in the first embodiment. In the second embodiment, the same reference numerals as those used in the first embodiment are used unless otherwise specified. Furthermore, in the second embodiment, explanations that overlap with those in the first embodiment are omitted as appropriate.

8 is an enlarged top view of a portion of the top surface of the printed wiring board 2 according to embodiment 2, showing the positions and shapes of the mounting pads, solder, and silk prints. As shown in FIG. 8, when the printed wiring board 2 without electronic components 1 mounted thereon is viewed from above, in addition to what is shown in FIG. 2 according to embodiment 1, pattern 24a, solid ground 24b, silk prints 25a, and silk prints 25b can be seen. Note that because pattern 24a and solid ground 24b are located under the solder resist 23 layer, their outlines are shown by dashed lines indicating hidden lines (see also FIG. 9).
In Fig. 8, the solid ground 24b is shown to be slightly larger than the central mounting pad 20. In Fig. 8, the silkscreen prints 25a and 25b are shown by dark hatching with a high fill ratio.

Figure 9 is a cross-sectional view of the printed wiring board 2 after mounting according to embodiment 2, taken along the line A-A' in Figure 2. As shown in Figure 9, the pattern 24a and the solid ground 24b are provided on the same wiring layer as the central mounting pad 20, the first peripheral mounting pad 21, and the second peripheral mounting pad 22. Also, as shown in Figure 9, the silkscreen prints 25a and 25b are printed on the solder resist 23.

The patterns 24a shown in Figures 8 and 9 are patterns extending from the first peripheral mounting pads 21 and the second peripheral mounting pads 22 of the printed wiring board 2 toward the outer edge. When viewed from above as if the electronic component 1 were not present, the patterns 24a extending from the second peripheral mounting pads 22 extend between the two adjacent first peripheral mounting pads 21 to a position outside the electronic component 1.

The silkscreen print 25a shown in Figures 8 and 9 is printed in a position that overlaps a portion of the pattern 24a when the printed wiring board 2 is viewed from above. Furthermore, the silkscreen print 25a shown in Figures 8 and 9 is printed so as to create a wall between two adjacent first peripheral bottom electrodes 11.

The silkscreen print 25b shown in Figures 8 and 9 is printed in a position that overlaps a portion of the periphery of the solid ground 24b when the printed wiring board 2 is viewed from above. Furthermore, the silkscreen print 25b shown in Figures 8 and 9 is printed so as to create a wall between the central heat dissipation bottom electrode 10 and the second peripheral bottom electrode 12.

The silkscreen prints 25a and 25b are supports for mounting the electronic component 1 with a predetermined clearance and in a position parallel to the upper surface of the printed wiring board 2. In other words, mounting the electronic component 1 on the printed wiring board 2 according to the second embodiment is achieved by actively bringing the electronic component 1 into contact with the silkscreen prints 25a and 25b.
Therefore, the silk print 25a is not limited to being located at a position overlapping the pattern 24a when the printed wiring board 2 is seen through from above, but may be located at a position overlapping a copper foil such as GND.

When the printed wiring board 2 according to the second embodiment is reflow mounted, the following phenomenon occurs after the main heating in the reflow furnace.
As described above, in the cooling process, the heat dissipating bottom electrode solder 30 generally begins to solidify earlier than the first outer peripheral bottom electrode solder 31 and the second outer peripheral bottom electrode solder 32. In the second embodiment, due to the supporting effect of the silk screen printing 25b, the solder height of the heat dissipating bottom electrode solder 30 does not become smaller than the sum of the thickness of the solder resist 23 and the thickness of the silk screen printing 25b.
As mentioned above, when the solder 30 for the heat dissipation bottom electrode solidifies first and the solder 31 for the first peripheral bottom electrode and the solder 32 for the second peripheral bottom electrode are still molten, the excess solder and flux of the solder 31 for the first peripheral bottom electrode and the solder 32 for the second peripheral bottom electrode have enough room to spread to the first peripheral buffer area 21a and the second peripheral buffer area 22a of the first peripheral mounting pad 21 and the second peripheral mounting pad 22, respectively.

As described above, the printed wiring board 2 according to embodiment 2 has the above configuration, which has the effect of suppressing short-circuit defects that occur on the mounting pads of the external electrodes, even when mounting QFNs or the like with two or more rows of peripheral electrodes.

This disclosed technology can be applied to printed wiring boards that mount QFNs and other devices with two or more rows of peripheral electrodes, and has industrial applicability.

1 Electronic component, 1a Package, 2 Printed wiring board, 10 Central heat dissipation bottom electrode, 11 First peripheral bottom electrode, 12 Second peripheral bottom electrode, 20 Central mounting pad, 21 First peripheral mounting pad, 21a First peripheral buffer area, 22 Second peripheral mounting pad, 22a Second peripheral buffer area, 23 Solder resist, 24a Pattern, 24b Solid ground, 25a Silk printing, 25b Silk printing, 30 Solder for heat dissipation bottom electrode, 31 Solder for first peripheral bottom electrode, 32 Solder for second peripheral bottom electrode.

Claims (3)

A printed wiring board on which a package having a first outer periphery bottom electrode and a second outer periphery bottom electrode is mounted,
first peripheral mounting pads corresponding to the first peripheral bottom electrodes;
second peripheral mounting pads corresponding to the second peripheral bottom electrodes;
solder for the first peripheral bottom electrodes and solder for the second peripheral bottom electrodes are applied so as to be enclosed within the first peripheral mounting pads and the second peripheral mounting pads, respectively;
the first peripheral mounting pads have a first peripheral buffer area that is enlarged in a direction toward the outer edge of the package;
The second peripheral mounting pads have a second peripheral buffer area including a portion that extends toward the outer edge of the package and into the region between two adjacent first peripheral mounting pads , and have an overall convex shape.
Printed wiring board. 2. The printed wiring board according to claim 1, wherein the package is a QFN or SON package. 2. The printed wiring board according to claim 1, wherein a silk print is formed to be sandwiched between the solder resist and the package when the package is mounted.