JP7749810B2 - Semiconductor device incorporating a substrate recess - Google Patents

Description

This disclosure relates to semiconductor devices, and more particularly to improved semiconductor structures and related manufacturing methods for semiconductor devices.

STATEMENT OF U.S. GOVERNMENT INTEREST This invention was made with Government support under Contract No. N000164-19-C-WP50 awarded by the Under Secretary of Defense for Research and Design (OUSD R&E), Defense Manufacturing Science and Technology (DMS&T). The Government has certain rights in the invention.

Metals such as silicon (Si) and gallium arsenide (GaAs) have found wide application in semiconductor devices for low-power and, in the case of Si, low-frequency applications. However, these materials may be less suitable for high-power and/or high-frequency applications due, for example, to their relatively small bandgaps (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and relatively small breakdown voltages.

For high-power, high-temperature, and/or high-frequency applications and devices, wide-bandgap semiconductor materials such as silicon carbide (SiC) (e.g., 4H—SiC has a bandgap of approximately 3.2 eV at room temperature) and Group III nitrides (e.g., gallium nitride (GaN) has a bandgap of approximately 3.36 eV at room temperature). As used herein, the term "Group III nitrides" refers to semiconductor compounds formed between nitrogen (N) and elements from Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In). The term refers to binary, ternary, and quaternary compounds such as GaN, AlGaN, and AlInGaN. These compounds have empirical formulas where one mole of nitrogen is combined with one mole of the total Group III elements. These materials may have higher electric field breakdown strengths and higher electron saturation velocities compared to GaAs and Si.

Semiconductor devices fabricated from SiC and/or Group III nitrides may include power transistor devices such as field effect transistors (FETs), including MOSFETs (metal oxide semiconductor field effect transistors), DMOS (double-diffused metal oxide semiconductor) transistors, HEMTs (high electron mobility transistors), MESFETs (metal semiconductor field effect transistors), LDMOS (laterally diffused metal oxide semiconductor) transistors, etc.

According to some embodiments of the present invention, a semiconductor device includes a substrate, the upper surface of which includes a recessed region; a semiconductor structure on the substrate, a portion of the semiconductor structure being within the recessed region; and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recessed region does not vertically overlap the drain contact or the source contact.

In some embodiments, the semiconductor structure comprises a high electron mobility transistor (HEMT) or a field effect transistor (FET).

In some embodiments, the FET comprises a metal-oxide-semiconductor FET (MOSFET) or a metal-semiconductor FET (MESFET).

In some embodiments, the substrate includes an impurity region adjacent to the recessed region.

In some embodiments, the impurity region includes p-type impurities.

In some embodiments, the impurity region is located on at least one sidewall and/or bottom surface of the recessed region.

In some embodiments, a portion of the semiconductor structure within the recessed region is doped with a p-type dopant.

In some embodiments, the recessed region is on a portion of the semiconductor structure that extends from beneath the source contact to beneath the gate contact.

In some embodiments, the recessed region is on a portion of the semiconductor structure that extends from beneath the drain contact to beneath the gate contact.

In some embodiments, the gate contact includes a first gate contact, the semiconductor device further includes a second gate contact, and the recessed region is below the first gate contact.

In some embodiments, the first and second gate contacts extend in a first direction on the semiconductor structure, and the recessed region has a longitudinal axis extending in the first direction.

In some embodiments, a first threshold voltage of the first transistor associated with the first gate contact is different from a second threshold voltage of the second transistor associated with the second gate contact.

In some embodiments, the gate contact has a longitudinal axis extending in a first direction, and the recessed region includes a plurality of recessed regions disposed below the gate contact and spaced apart from one another along the first direction.

In some embodiments, the semiconductor structure includes a Group III nitride.

According to some embodiments of the present invention, a semiconductor device includes a substrate, an impurity region in the substrate, a semiconductor structure on the substrate, and a gate contact, a drain contact, and a source contact on the semiconductor structure. A first thickness of a first portion of the semiconductor structure above the impurity region is greater than a second thickness of a second portion of the semiconductor structure.

In some embodiments, the impurity region is on at least one sidewall and/or bottom surface of the recessed region in the substrate.

In some embodiments, the recessed region is over a source access region of the semiconductor structure and/or over a drain access region of the semiconductor structure.

In some embodiments, the recessed region does not overlap the source contact and/or the drain contact in a direction perpendicular to the bottom surface of the substrate.

In some embodiments, the impurity region includes p-type impurities.

In some embodiments, the gate contact includes a first gate contact, the semiconductor device further includes a second gate contact, and the first portion of the semiconductor structure is between the first gate contact and the substrate.

In some embodiments, a first threshold voltage of the first transistor associated with the first gate contact is different from a second threshold voltage of the second transistor associated with the second gate contact.

In some embodiments, the gate contact has a longitudinal axis extending in the first direction, and the impurity region is on at least one sidewall and/or bottom surface of a respective one of a plurality of recessed regions disposed along the first direction in the substrate below the gate contact.

In some embodiments, the gate contact has a longitudinal axis extending in the first direction, and the impurity region is on at least one sidewall and/or bottom surface of a continuous trench in the substrate having a longitudinal axis extending in the first direction.

According to some embodiments of the present invention, a semiconductor device includes a substrate, the top surface of which includes a recessed region; an impurity region in the substrate on at least one sidewall and/or bottom surface of the recessed region; and a semiconductor structure on the recessed region and the impurity region.

In some embodiments, a first thickness of a first portion of the semiconductor structure above the recessed region is greater than a second thickness of a second portion of the semiconductor structure away from the recessed region.

In some embodiments, the semiconductor device further comprises a gate contact, a drain contact, and a source contact on the semiconductor structure. The recessed region is on a source access region of the semiconductor structure and/or a drain access region of the semiconductor structure.

In some embodiments, the recessed region does not overlap the source contact and/or the drain contact in a direction perpendicular to the bottom surface of the substrate.

In some embodiments, the gate contact includes a first gate contact, the semiconductor device further includes a second gate contact, and the recessed region is between the first gate contact and the substrate.

In some embodiments, a first threshold voltage of the first transistor associated with the first gate contact is different from a second threshold voltage of the second transistor associated with the second gate contact.

In some embodiments, the gate contact has a longitudinal axis extending in a first direction, and the recessed region includes a plurality of recesses below the gate contact and spaced apart along the first direction.

In some embodiments, the gate contact has a longitudinal axis extending in the first direction, and the recessed region comprises a continuous trench in the substrate having a longitudinal axis extending in the first direction.

In some embodiments, the impurity region includes p-type impurities.

Other devices, apparatus, and/or methods according to some embodiments will become apparent to one of ordinary skill in the art upon examination of the following drawings and detailed description. All such additional embodiments, as well as any and all combinations of the above embodiments, are intended to be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1A and 1B are cross-sectional views illustrating examples of semiconductor devices according to some embodiments of the present disclosure. 1A and 1B are cross-sectional views illustrating examples of semiconductor devices according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 illustrates an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 10A-10C illustrate embodiments utilizing variations in recessed areas in accordance with some embodiments of the present disclosure. 10A-10C illustrate embodiments utilizing variations in recessed areas in accordance with some embodiments of the present disclosure. 10A-10C illustrate embodiments utilizing variations in recessed areas in accordance with some embodiments of the present disclosure. 1 is a cross-sectional view of an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 is a cross-sectional view of an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1 is a cross-sectional view of an exemplary embodiment of a semiconductor device according to some embodiments of the present disclosure. 1A and 1B are cross-sectional views illustrating examples of semiconductor devices according to some embodiments of the present disclosure. 1A and 1B are cross-sectional views illustrating examples of semiconductor devices according to some embodiments of the present disclosure. 1 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 1 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 1 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 1 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 1 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 1 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 1 illustrates a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 10A-10C illustrate methods for constructing additional semiconductor devices according to some embodiments of the present disclosure. 10A-10C illustrate methods for constructing additional semiconductor devices according to some embodiments of the present disclosure. 10A-10C illustrate methods for constructing additional semiconductor devices according to some embodiments of the present disclosure. 10A-10C illustrate methods for constructing additional semiconductor devices according to some embodiments of the present disclosure. 1A-1C are schematic cross-sectional views of alternative transistor device structures according to some embodiments of the present disclosure. 1A-1C are schematic cross-sectional views of alternative transistor device structures according to some embodiments of the present disclosure. 1A-1C are schematic cross-sectional views illustrating several exemplary ways in which semiconductors may be packaged according to embodiments of the present disclosure. 1A-1C are schematic cross-sectional views illustrating several exemplary ways in which semiconductors may be packaged according to embodiments of the present disclosure. 1A-1C are schematic cross-sectional views illustrating several exemplary ways in which semiconductors may be packaged according to embodiments of the present disclosure.

DETAILED DESCRIPTION [0023] Exemplary embodiments of the inventive concepts are described in more detail below with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the inventive concepts may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concepts to those skilled in the art. Like numbers refer to like elements throughout.

The present disclosure provides semiconductor devices in which the on-resistance of the device is reduced and/or the gate threshold of the device is adjusted. The reduction in device resistance and/or the adjustment in gate threshold is achieved, in part, through the use of recessed regions in the substrate of the semiconductor device. The location of the recessed regions may be varied to provide various advantageous improvements to the device.

In the context of HEMT devices, the present disclosure may arise from the recognition of the effect of GaN buffer thickness on HEMT device characteristics (e.g., threshold voltage). The GaN buffer may be monolithically integrated by including GaN-filled trench and/or recessed regions in selective regions of the HEMT device. In some embodiments, the GaN-filled trench and/or recessed regions may be located below the source access region to reduce depletion resulting from the adjacent gate field. The reduced depletion in this region reduces the resistance of the HEMT device. In some embodiments, the use of GaN-filled trenches and/or recesses may be combined with buried P regions used in trapping reduction.

FIGS. 1A-1C illustrate an exemplary embodiment of a semiconductor device 300 according to some embodiments of the present disclosure. FIGS. 1A-1C are intended to depict structures for identification and explanation purposes and are not intended to depict the structures to physical scale.

With reference to FIG. 1A, semiconductor device 300 includes a substrate 322 and a semiconductor structure 390 on substrate 322. The semiconductor structure 390 of FIG. 1A is a schematic illustration shown as a generic semiconductor structure 390 that may incorporate many types and/or configurations of semiconductor elements, as further described herein.

The semiconductor structure 390 may be provided on a substrate 322, such as a silicon carbide (SiC) substrate or a sapphire substrate. The substrate 322 may be a _semi -insulating SiC substrate. However, embodiments of the present disclosure may utilize any suitable substrate, such as sapphire ( _Al2O3 ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), etc. The substrate 322 may be a SiC wafer, and the semiconductor device 300 may be formed, at least in part, through wafer-level processing, which may then be diced or otherwise singulated to provide dies including a plurality of unit cell transistor structures. The term "semi-insulating" is used descriptively herein, not in an absolute sense. In some embodiments, the substrate 322 may be doped to have n-type conductivity.

The semiconductor structure 390 may be SiC-based and/or III-nitride-based material in some embodiments. A portion of the semiconductor structure 390 may define a channel region of the semiconductor device 300. The channel region may extend between the source region 215 and the drain region 205 of the semiconductor device 300. Conduction in the channel region may be controlled by a signal provided to the gate contact 310. The signal may be provided to the source region 215 via the source contact 315 and to the drain region 205 via the drain contact 305. The portion of the semiconductor structure 390 from below the source contact 315 to below the gate contact 310 may be referred to as the source access region (SAR), and the portion of the semiconductor structure 390 from below the drain contact 305 to below the gate contact 310 may be referred to as the drain access region (DAR).

Although not shown in FIG. 1A, semiconductor device 300 may include other elements, such as insulating layers, passivation layers, metal transmission lines, etc. These elements are not shown in FIG. 1A to focus on other portions of the device, but as will be understood by those skilled in the art, these other elements may be present as necessary for the functionality of semiconductor device 300.

From a general perspective, semiconductor device 300 operates according to the principle of electrons flowing between source region 215 and drain region 205 under the control of gate contact 310. As explained further herein, the configuration of semiconductor structure 390 can affect the mechanism by which this operation is established. Each of the regions defined by the placement of the source, drain, and gate of semiconductor device 300 can affect the resistance of semiconductor device 300, each of which is shown in FIG. 1A. Such regions include source contact resistance region 380, source access region resistance region 382, gate contact resistance region 384, drain access region resistance region 386, and drain contact resistance region 388.

Source contact resistance region 380 is the region of semiconductor structure 390 that vertically overlaps source contact 315. Gate contact resistance region 384 is the region of semiconductor structure 390 that vertically overlaps gate contact 310. Drain contact resistance region 388 is the region of semiconductor structure 390 that vertically overlaps drain contact 305. As used herein, "element A vertically overlapping element B" (or similar expression) is understood to mean that there is at least one vertical line that intersects both elements A and B. The vertical direction may be perpendicular to the bottom surface of the substrate (e.g., the Z direction).

The source recessed region resistance region 382 extends between the source contact resistance region 380 and the gate contact resistance region 384. The source access region resistance region 382 may vertically overlap the source access region (SAR). The drain access region resistance region 386 extends between the drain contact resistance region 388 and the gate contact resistance region 384. The drain access region resistance region 386 may vertically overlap the drain access region (DAR). Configuration and/or operation of the semiconductor device 300 may form a first depletion region 342 in the source access region (SAR) and a second depletion region 344 in the drain access region (DAR).

The locations of the source contact resistance region 384, the source access region resistance region 382, the gate contact resistance region 384, the drain access region resistance region 386, and the drain contact resistance region 388 are approximate and are not intended to limit the present disclosure.

A recessed region 360 may be formed in the substrate 322. The recessed region 360 may provide the substrate 322 with a non-linear upper surface 322A. For example, the height 322A of the upper surface of the substrate above the bottom surface 322B of the substrate within the recessed region 360 may be less than the height of the upper surface 322A of the substrate 322 above the bottom surface 322B of the substrate outside the recessed region 360. In some embodiments, the depth Dr of the recessed region 360 may be between 0.05 μm and 0.4 μm. In some embodiments, the width of the trench (e.g., in the X direction in FIG. 1A) may be between 0.5 μm and 7 μm.

As a result of the recessed region 360, the first depth D1 of the semiconductor structure 390 in the source access region (SAR) (e.g., above the recessed region 360) may be greater than the second depth D2 of the semiconductor structure 390 in the drain access region (DAR). Here, the depth of the semiconductor structure 390 refers to the distance between the top surface 390A of the semiconductor structure 390 and the top surface 322A of the substrate 322 in the vertical direction (e.g., perpendicular to the bottom surface 322B of the substrate 322, i.e., the Z direction in FIG. 1A).

The increased depth D1 may result in less charge storage and reduced depletion within the first depletion region 342 compared to a device that does not include the recess 360. The reduced charge storage may lower the on-resistance of the semiconductor device 300.

In some embodiments, the recessed region 360 may be positioned so as not to overlap the source contact 315. More specifically, an interface 315A may exist between the source contact 315 and the source region 215. The recessed region 360 may be formed so as not to overlap the interface 315A between the source contact 315 and the source region 215 in the vertical direction (e.g., not to overlap in the Z direction). In some embodiments, increasing the depth/thickness of the semiconductor structure 390 below the source contact interface 315A (e.g., in the source contact resistance region 380) may increase the source resistance of the device. However, embodiments of the present disclosure are not limited to such embodiments in which the recessed region 360 does not overlap the source contact 315. In some embodiments, a portion of the recessed region 360 may overlap the interface between the source contact 315 and the source region 215 in the vertical direction (e.g., overlap in the Z direction).

The recessed region 360 may be formed to have a longitudinal axis extending parallel to the longitudinal direction (e.g., the Y direction in FIG. 1A) of the source contact 315 and/or the gate contact 310. FIG. 1B shows a plan view of a semiconductor device 300 according to some embodiments of the present disclosure. FIG. 1A corresponds to a cross section taken along line A-A in FIG. 1B.

Referring to FIG. 1B, in some embodiments, a device may include a plurality of source contacts 315, drain contacts 305, and gate contacts 310 on a substrate 322. The plurality of drain contacts 305 and source contacts 315 may be arranged in an alternating pattern on the substrate 322. A gate contact 310 may be arranged between adjacent drain contacts 305 and source contacts 315 to form a plurality of transistor unit cells, examples of which are shown as TC1 and TC2 in FIG. 1B. Each of the transistor unit cells TC1, TC2 may include a source contact 315, a drain contact 305, and a gate contact 310. 1A and 1B show a subset of the source contacts 315, drain contacts 305, and gate contacts 310 for ease of explanation, it will be understood that the semiconductor device 300 may have additional structures, including additional source contacts 315, drain contacts, and gate contacts 310 not shown in FIGS. 1A and 1B. As will be understood by those skilled in the art, a transistor may be formed by the active region between the source contacts 315 and drain contacts 305 under the control of the gate contact 310 between the source contacts 315 and drain contacts 305.

Not shown in FIG. 1B are structures such as metal wiring layers, insulating layers, and/or vias for providing additional electrical connections and other structures for semiconductor device 300.

As shown in FIG. 1B , in some embodiments, recessed region 360 may extend as a continuous trench having a longitudinal axis in the source access region (SAR) parallel to the longitudinal axis (e.g., Y direction) of source contact 315, drain contact 305, and/or gate contact 310. Recessed region 360 may have opposite termination points 360A, 360B at opposite ends of recessed region 360. In some embodiments, termination points 360A, 360B may be formed such that recessed region 360 extends along a majority of the length of source contact 315, e.g., greater than 80%. In some embodiments, the length of recessed region 360 (e.g., in the Y direction in FIG. 1B ) may be greater than the length of source contact 315. For example, in some embodiments, one or more of the endpoints 360A, 360B may extend beyond the opposite end of the source contact 315.

Figure 1C illustrates additional embodiments of recessed regions 360. As shown in Figure 1C, the recessed regions 360 may be formed by trenches arranged along a direction substantially parallel to the source contacts 315 (e.g., the Y direction in Figure 1C). In the source access region (SAR), the recessed regions 360 may be spaced apart from one another by a third distance D3. In some embodiments, the third distance D3 may be between 0.5 μm and 7 μm.

Figure 2 is a cross-sectional view illustrating an example of a semiconductor device 300' according to some embodiments of the present disclosure. Elements in Figure 2 that are substantially the same as elements in Figures 1A-1C will not be described.

Referring to FIG. 2 , in some embodiments, impurity region 375 may be formed in substrate 322. In some embodiments, impurity region 375 may be formed on the opposite sidewall of the trench that forms recessed region 360. In some embodiments, impurity region 375 may be formed deeper in substrate 322 such that impurity region 375 is disposed below recessed region 360.

In some embodiments, impurity region 375 may be formed from a p-type material. For example, impurity region 375 may be formed by doping (e.g., via ion implantation) with aluminum (Al), boron (B), gallium (Ga), indium (In), and/or thallium (Tl), or any other material capable of forming a p-type layer. In some embodiments, the p-type conductivity of impurity region 375 may differ from the n-type conductivity of substrate 322. In some embodiments, impurity region 375 may be configured to have a varying doping and/or implantation profile perpendicular to top surface 322A of substrate 322. In some embodiments, impurity region 375 may not extend laterally across the entire active region. For example, impurity region 375 may not vertically overlap one or more of drain contact 305, source contact 315, and/or gate contact 310.

In some embodiments, the presence of impurity region 375 in substrate 322 may reduce trapping in semiconductor device 300'. In some embodiments, a portion of the voltage from drain region 205 to source region 215 may be dropped in impurity region 375. This may also laterally deplete the channel. Lateral depletion may reduce the lateral electric field and increase the breakdown voltage. In some embodiments, a more compact structure may be obtained for the required breakdown voltage. Impurity region 375 may eliminate the need to have doping (e.g., C or Fe) in semiconductor structure 390 used to sustain the applied drain voltage. Elimination of deep doping levels may lead to reduced current flow (e.g., the absence or reduction of trapping) under operating conditions. Additionally, in some aspects, impurity region 375 supports an electric field.

Figure 3 is a cross-sectional view illustrating an example of a semiconductor device 300'' according to some embodiments of the present disclosure. Elements in Figure 3 that are substantially identical to elements in Figures 1A-1C will not be described.

3, in some embodiments, an impurity region 375' may be formed in the semiconductor structure 390 within the recessed region 360. In some embodiments, the impurity region 375' may be formed in one or more of the bottom and/or sidewalls of the trench forming the recessed region 360. In some embodiments, the impurity region 375' may completely fill the recessed region 360, although the disclosure is not limited thereto. The impurity region 375' may include aluminum (Al), boron (B), gallium (Ga), or any other material capable of forming a p-type layer. In some embodiments, the impurity region 375' may be configured to have a doping and/or implantation profile that varies vertically or laterally within the recessed region 360. The use of a p-type layer as shown in FIG. 3 may provide the same advantages to the semiconductor device 300'' as those described herein with respect to FIG. 2. In some embodiments, the impurity conductivity type of impurity region 375' may be different from the portion of semiconductor structure 390 immediately adjacent to impurity region 375'. For example, in some embodiments, impurity region 375' may be a p-type region, and the portion of semiconductor structure 390 immediately adjacent to impurity region 375' may be doped to be n-type. In some embodiments, impurity region 375' and the portion of semiconductor structure 390 immediately adjacent to impurity region 375' may have the same conductivity type (e.g., both p-type), but the concentration of dopant in impurity region 375' may be higher than that of the portion of semiconductor structure 390 immediately adjacent to impurity region 375'.

While Figures 1A-1C, 2, and 3 illustrate an embodiment in which recessed region 360 is formed in source access region resistor region 382, the present disclosure is not so limited. Figures 4A-4E are cross-sectional views of an exemplary embodiment incorporating recessed region 360' in drain access region resistor region 386 (see Figure 1A). A description of Figures 4A-4E, which are substantially identical to those in previously described figures, will be omitted.

Referring to FIG. 4A , the semiconductor device 400 may include a recessed region 360' disposed in the drain access region resistor region 386 to vertically overlap at least a portion of the drain access region (DAR). As a result of the recessed region 360', a second depth D2' of the semiconductor structure 390 in the drain access region (DAR) (e.g., above the recessed region 360') may be greater than a first depth D1' of the semiconductor structure 390 in the source access region (SAR). The dimensions (e.g., length or depth) of the recessed region 360' may be similar to those described herein in FIG. 1A with respect to the recessed region 360.

As with the semiconductor device 300 illustrated in FIG. 1A, the difference in thickness of the semiconductor structure 390 as a result of the recessed region 360' can affect the charge storage of the device. For example, as a result of the recessed region 360', the depletion in the second depletion region 344 may be lower than that in the first depletion region 342, and the resistance of the semiconductor device 300' may be reduced.

As shown in FIG. 4A , an interface 305A may exist between the drain contact 305 and the drain region 205. In some embodiments, the recessed region 360' may be positioned so as not to overlap the interface 305A between the drain contact 305 and the drain region 205 in the vertical direction (e.g., in the Z direction). However, embodiments of the present disclosure are not limited to such embodiments in which the recessed region 360' does not overlap the drain contact 305. In some embodiments, a portion of the recessed region 360' may overlap the interface 305A between the drain contact 305 and the drain region 205 in the vertical direction (e.g., overlap in the Z direction).

Figure 4B shows a semiconductor device 400' in which an impurity region 475 is formed in the substrate 322. In some embodiments, the impurity region 475 may be formed in one or more of the sidewalls of the trench forming the recessed region 360'. In some embodiments, the impurity region 475 may be formed deeper in the substrate 322 such that the impurity region 475 is disposed below the recessed region 360'.

In some embodiments, impurity region 475 may be formed from a p-type material. For example, impurity region 475 may be formed by doping (e.g., ion implantation) with aluminum (Al), boron (B), gallium (Ga), or any other material capable of forming a p-type layer. In some embodiments, impurity region 475 may be configured to have a varying doping and/or implantation profile perpendicular to top surface 322A of substrate 322. In some embodiments, impurity region 475 may not extend laterally across the entire active region. For example, impurity region 475 may not vertically overlap one or more of drain contact 305, source contact 315, and/or gate contact 310.

Figure 4C is a cross-sectional view illustrating a semiconductor device 400' according to some embodiments of the present disclosure. Referring to Figure 4C, in some embodiments, an impurity region 475' may be formed in the semiconductor structure 390 within the recessed region 360'. In some embodiments, the impurity region 475' may be formed on one or more of the bottom and/or side surfaces of the trench forming the recessed region 360'. In some embodiments, the impurity region 475' may completely fill the recessed region 360', although the present disclosure is not limited thereto. The impurity region 475' may include aluminum (Al), boron (B), gallium (Ga), or any other material capable of forming a p-type layer. In some embodiments, the impurity region 475' may be configured to have a doping and/or implantation profile that varies vertically or laterally within the recessed region 360'.

Figures 4D and 4E are plan views showing an exemplary embodiment of recessed region 360'. Figures 4A-4C correspond to cross-sectional views taken along line A-A in Figures 4D and 4E.

Referring to FIG. 4D , recessed region 360' may, in some embodiments, extend as a continuous trench with its longitudinal axis in the drain access region parallel (e.g., in the Y direction) to the longitudinal axes of source contact 315, drain contact 305, and/or gate contact 310. Recessed region 360' may extend along a majority of the length of drain contact 305, e.g., greater than 80%. In some embodiments, the length of recessed region 360' (e.g., in the y direction in FIG. 4D ) may be greater than the length of drain contact 305. For example, in some embodiments, one or more of the endpoints of recessed region 360' may extend beyond the opposite endpoint of drain contact 305.

Figure 4E shows an additional embodiment in which the recessed regions 360' may be formed as multiple trenches arranged along a direction substantially parallel to the drain contact 305 (e.g., the Y direction in Figure 4E). In the drain access region (DAR), the recessed regions 360' may be spaced apart from one another by a fourth distance D4. In some embodiments, the fourth distance D4 may be between 0.5 μm and 7 μm.

Figures 5A-5E are cross-sectional views of an exemplary embodiment incorporating recessed region 360'' in gate contact resistor region 384 (see Figure 1A). Descriptions of elements in Figures 5A-5E that are substantially similar to previously described elements are omitted.

Referring to FIG. 5A , the semiconductor device 500 includes a recessed region 360″ disposed in the gate contact resistance region 384 to vertically overlap at least a portion of the gate contact 310. As a result of the recessed region 360″, a fifth depth D5 of the semiconductor structure 390 below the gate contact 310 (e.g., above the recessed region 360″) may be greater than a first depth D1″ of the semiconductor structure 390 in the source access region (SAR) and a second depth D2″ of the semiconductor structure 390 in the drain access region (DAR).

The difference in thickness of the semiconductor structure 390 as a result of the recessed regions 360" may alter the threshold voltage of the semiconductor device 300". For example, by varying the depth and/or width of the recessed regions 360", the threshold voltage of the semiconductor device 300" may differ from the threshold voltage of a similarly configured semiconductor device without such recessed regions 360". While this disclosure is not bound by a particular theory of operation, the altered threshold voltage may be due to altered charge storage in the device or may be the result of an altered carrier concentration in the thicker regions. For example, a more concentrated carrier distribution may occur in the recessed regions 360". In some embodiments, the presence of the recessed regions 360" may increase the threshold voltage of the resulting semiconductor device 500 compared to the threshold voltage of a transistor device without such recessed regions 360".

FIG. 5B shows a semiconductor device 500' in which impurity regions 575 are formed in the substrate 322. In some embodiments, the impurity regions 575 may be formed in one or more of the sidewalls of the trenches forming the recessed regions 360". In some embodiments, the impurity regions 575 may be formed deeper in the substrate 322 such that the impurity regions 575 are disposed below the recessed regions 360".

In some embodiments, the impurity region 575 may be formed from a p-type material. For example, the impurity region 575 may be formed by doping (e.g., ion implantation) with aluminum (Al), boron (B), gallium (Ga), or any other material capable of forming a p-type layer. In some embodiments, the impurity region 575 may be configured to have a varying doping and/or implantation profile perpendicular to the top surface 322A of the substrate 322. In some embodiments, the impurity region 575 may not extend laterally across the entire active region. For example, the impurity region 575 may not vertically overlap one or more of the drain contact 305, the source contact 315, and/or the gate contact 310.

5C is a cross-sectional view illustrating a semiconductor device 500" according to some embodiments of the present disclosure. Referring to FIG. 5C, in some embodiments, an impurity region 575' may be formed in the semiconductor structure 390 within the recessed region 360". In some embodiments, the impurity region 575' may be formed in one or more of the bottom and/or sidewalls of the trench forming the recessed region 360". In some embodiments, the impurity region 575' may completely fill the recessed region 360", although the present disclosure is not limited thereto. The impurity region 575' may include aluminum (Al), boron (B), gallium (Ga), or any other material capable of forming a p-type layer. In some embodiments, the impurity region 575' may be configured to have a doping and/or implantation profile that varies vertically or laterally within the recessed region 360".

Figures 5D and 5E are plan views showing an exemplary embodiment of recessed region 360''. Figures 5A-5C correspond to cross sections taken along line A-A in Figures 5D and 5E.

Referring to FIG. 5D , recessed region 360″, in some embodiments, may extend as a continuous trench beneath gate contact 310 and parallel to the longitudinal axis of gate contact 310 (e.g., the Y direction in FIG. 5D ). Recessed region 360″ may extend along a majority (e.g., greater than 80%) of gate contact 310. In some embodiments, the length of recessed region 360″ (e.g., in the Y direction) may be greater than the length of gate contact 310. For example, in some embodiments, one or more of the endpoints of recessed region 360″ may extend beyond the opposite end of gate contact 310.

Figure 5E shows an additional embodiment in which the recessed regions 360'' may be formed as trenches arranged along a direction substantially parallel to the gate contact 310 (e.g., the Y direction in Figure 5E). The recessed regions 360'' may be spaced apart from one another by a sixth distance D6. In some embodiments, the sixth distance D6 may be between 0.5 μm and 7 μm.

In some embodiments, recessed regions 360" below the gate contact 310 may be provided in some, but not all, unit transistor cells of a semiconductor device. As previously discussed, the presence of recessed regions 360" below the gate contact 310 may increase the voltage threshold of the device. Providing some unit cell transistors with a first threshold voltage and some unit cell transistors with a second threshold voltage that is different from the first threshold voltage may enable the configuration of different types of semiconductor behavior. For example, by designing a semiconductor device to have different threshold voltages in different regions of the device, different portions of the channel of the semiconductor device (e.g., the 2DEG channel in a HEMT device) may turn on at different degrees or levels in response to the application of a gate voltage. In other words, the channels of different unit cells of the semiconductor device may turn on at different levels of current. In some embodiments, a semiconductor device formed in a wide bandgap semiconductor material system, such as a gallium nitride-based semiconductor, may exhibit rapid turn-on behavior, in which all unit cells turn on at approximately the same time. Because tertiary transconductance tends to peak at turn-on, multi-cell semiconductor devices formed in such material systems can experience large spikes in tertiary transconductance at device turn-on because the unit cells turn on simultaneously. By varying the threshold voltage so that different portions of the device have different threshold voltages, the degree to which the channel is turned on at any given time varies across the device. This can result, for example, in a reduction in the magnitude of the spike in tertiary transconductance. Techniques for varying threshold voltages in semiconductor devices are described, for example, in commonly owned U.S. Patent No. 10,615,273, filed June 21, 2021, the entire contents of which are incorporated herein by reference.

Figures 6A-6C illustrate embodiments utilizing variations of recessed region 360'' according to some embodiments of the present disclosure. Figure 6A is a plan view of a semiconductor device 600 according to some embodiments of the present disclosure, while Figure 6B is a cross-sectional view of semiconductor device 600 of Figure 6A taken along lines B-B and B'-B'. Figure 6C is a schematic circuit diagram of semiconductor device 600 of Figure 6A. Descriptions of elements in Figures 6A-6C previously described will be omitted.

Referring to FIG. 6A, a plan view of a semiconductor device 600 similar to that of FIG. 5D is shown. That is, multiple gate contacts 310, source contacts 315, and drain contacts 305 may be disposed on a semiconductor structure 390 that is further disposed on a substrate 322. The semiconductor device 600 may include multiple unit cell transistors TC_A, TC_B electrically connected in parallel. In some embodiments, the parallel connection may be achieved by a gate bus 345 connected to each of the gate contacts 310 and a drain bus 347 connected to each of the drain contacts 305. Each of the gate contacts 310 may be part of a unit cell transistor TC_A, TC_B. While only a subset of the unit cell transistors is shown in FIGS. 6A-6C, it will be understood that additional unit cell transistors may be present.

6A-6B, a first unit cell transistor TC_A may incorporate a gate contact 310 having a recessed region 360'' in the substrate 322 below the gate contact 310. The presence of the recessed region 360'' may result in the first unit cell transistor TC_A having a first voltage threshold V _TH-A .

The second unit cell transistor TC_B of the semiconductor device 600 may incorporate the gate contact 310, but may not have a recessed region below the gate contact 310. As a result, the second unit cell transistor TC_B has a second voltage threshold V _TH-B that is different from the first voltage threshold V _TH-A .

In FIG. 6A, the number of first unit cell transistors TC_A and second unit cell transistors TC_B is merely an example, and embodiments of the present disclosure are not limited thereto. The configuration of the first and second unit cell transistors TC_A, TC_B may result in a parallel connection of unit cell transistors having different voltage thresholds, as shown in FIG. 6C. As a result of the parallel connection of various unit cell transistors, different portions of the device may turn on at different applied gate voltages, providing improved linearity.

While FIG. 6A illustrates an embodiment in which recessed region 360'' is implemented as a continuous trench, embodiments of the present invention are not limited in this respect. In some embodiments, recessed region 360'' may be provided as a series of separated trenches in a manner similar to FIG. 5E.

While the previous figures show embodiments in which recessed regions 360, 360', 360" are provided in the source access region, in the drain access region, or under the gate contact, embodiments of the present disclosure are not so limited. In some embodiments, two or more of the previously shown recessed regions 360, 360', 360" may be combined. For example, a semiconductor device may include a recessed region 360 under the source access region and a recessed region 360' under the drain access region, or other combinations of recessed regions 360, 360', 360" described herein.

The previous figures illustrate variations in the use of recessed regions 360, 360', 360" in substrate 322 incorporated as part of semiconductor structure 390. As will be appreciated by those skilled in the art, recessed regions 360, 360', 360" may be applied to many different semiconductor structures without departing from the embodiments of the present disclosure.

For example, Figures 7A-7C are cross-sectional views illustrating examples of semiconductor devices 300A, 300A', and 300A" implemented as HEMTs, according to some embodiments of the present disclosure. The cross-sections shown in Figures 7A-7C are taken along line A-A in Figure 1B or Figure 1C. Figures 7A-7C are intended to depict structures for identification and explanation purposes, and are not intended to depict the structures to physical scale.

Referring to semiconductor device 300A in FIG. 7A, a semiconductor structure 390, such as a semiconductor structure for a III-nitride semiconductor HEMT, may be formed on a substrate 322, such as a silicon carbide (SiC) substrate or a sapphire substrate. Substrate 322 may be a semi-insulating silicon carbide (SiC) substrate, which may be, for example, a 4H polytype of silicon carbide. Other candidate silicon carbide polytypes may include the 3C, 6H, and 15R polytypes. The substrate may be a high-purity semi-insulating (HPSI) substrate available from Cree, Inc.

In some embodiments, the silicon carbide bulk crystal of substrate 322 may have a resistivity of about 1× ¹⁰ ohm-cm or greater at room temperature. Exemplary SiC substrates that may be used in some embodiments of the present disclosure are manufactured, for example, by Cree, Inc. of Durham, North Carolina, the assignee of the present disclosure, and methods for manufacturing such substrates are described, for example, in U.S. Reissue Patent Application No. Re. 34,861, U.S. Pat. No. 4,946,547, U.S. Pat. No. 5,200,022, and U.S. Pat. No. 6,218,680, the disclosures of which are incorporated herein by reference in their entireties. Although silicon carbide may be used as the substrate material, embodiments of the present disclosure may utilize any suitable substrate, such as _sapphire ( _Al2O3 ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), indium phosphide (InP), etc. The substrate 322 may be a silicon carbide wafer, and the HEMT device 300A may be formed, at least in part, via wafer-level processing, and the wafer may then be diced to provide a plurality of individual high electron mobility transistors 300A.

The substrate 322 may have a bottom surface 322B and a top surface 322A. In some embodiments, the substrate 322 of the HEMT device 300A may be a thin substrate 322. In some embodiments, the thickness of the substrate 322 (e.g., in the vertical Z direction in FIG. 7A ) may be 100 μm or less. In some embodiments, the thickness of the substrate 322 may be 75 μm or less. In some embodiments, the thickness of the substrate 322 may be 50 μm or less.

A recessed region 360 may be formed in the substrate 322. The characteristics of the recessed region 360 may be similar to those shown and described herein with respect to FIG. 1A, and as a result, a redundant description thereof will be omitted. The recessed region 360 may be formed as a continuous trench similar to that of FIG. 1B, or as a series of separate trenches similar to that of FIG. 1C.

The channel layer 324 is formed on the upper surface 322A of the substrate 322 (or on an optional layer described further herein) and in the recessed region 360, and the barrier layer 326 is formed on the upper surface of the channel layer 324. The channel layer 324 and the barrier layer 326 may each be formed by epitaxial growth in some embodiments. Techniques for epitaxial growth of Group III nitrides are described, for example, in U.S. Pat. Nos. 5,210,051, 5,393,993, and 5,523,589, the disclosures of which are incorporated herein by reference in their entireties. The channel layer 324 may have a bandgap smaller than that of the barrier layer 326, and the channel layer 324 may also have a greater electron affinity than the barrier layer 326. The channel layer 324 and the barrier layer 326 may comprise a Group III nitride-based material. In some embodiments, the wafer thickness (e.g., the thickness of the substrate 322, the channel layer 324, and the barrier layer 326) may be between 40 μm and 100 μm. In some embodiments, the wafer thickness may be between 40 μm and 80 μm. In some embodiments, the wafer thickness may be approximately 75 μm.

In some embodiments, the channel layer 324 may be a Group III nitride, such as Al _x Ga _1-x N, where 0≦x<1, if the energy of the conduction band edge of the channel layer 324 is less than the energy of the conduction band edge of the barrier layer 326 at the interface between the channel layer 324 and the barrier layer 326. In certain embodiments of the present disclosure, x=0 indicates that the channel layer 324 is GaN. The channel layer 324 may also be other Group III nitrides, such as InGaN, AlInGaN, etc. The channel layer 324 may be undoped (“unintentionally doped”) and grown to a thickness greater than about 0.002 μm. The channel layer 324 may also be a multi-layer structure, such as a superlattice or combination of GaN, AlGaN, etc. The channel layer 324 may be under compressive strain in some embodiments.

The material of the channel layer 324 may be on or within the recessed region 360. In some embodiments, the material of the channel layer 324 may completely fill the recessed region 360, although embodiments of the present disclosure are not limited thereto.

In some embodiments, the barrier layer 326 is AlN, AlInN, AlGaN, or AlInGaN, or a combination of these layers. The barrier layer 326 may include one layer or may be a multi-layer structure. In some embodiments, the barrier layer 326 may be a thin AlN layer directly on the channel layer 324 with one or more AlGaN layers on top of that. In certain embodiments of the present disclosure, the barrier layer 326 may be sufficiently thick and have a sufficiently high aluminum (Al) composition and doping to induce a significant carrier concentration at the interface between the channel layer 324 and the barrier layer 326 through the polarization effect when the barrier layer 326 is buried under the ohmic contact metal. The barrier layer 326 may be, for example, about 0.1 nm to about 30 nm thick, but not so thick as to cause cracking or substantial defect formation therein. In some embodiments, the barrier layer thickness is 13-18 nm. In certain embodiments, the barrier layer 326 is undoped or doped with an n-type dopant to a concentration of less than about 10 ¹⁹ cm ⁻³ . In some embodiments, the barrier layer 326 is Al _x Ga _1-x N, where 0<x<1. In particular embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present disclosure, the barrier layer 326 comprises AlGaN with an aluminum concentration of about 5% to less than about 100%. In certain embodiments of the present disclosure, the aluminum concentration is greater than about 10%. The channel layer 324 and/or the barrier layer 326 may be deposited by, for example, metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). As described herein, a 2DEG layer is induced in the channel layer 324 at the junction between the channel layer 324 and the barrier layer 326. The 2DEG layer acts as a highly conductive layer that allows conduction between the source and drain regions of the device underlying source contact 315 and drain contact 305, respectively. Channel layer 324 and barrier layer 326 form semiconductor structure 390.

Although the semiconductor structure 390 is shown with the channel layer 324 and the barrier layer 326 for illustrative purposes, the semiconductor structure 390 may include additional layers/structures/elements, such as a buffer and/or nucleation layer between the channel layer 324 and the substrate 322, and/or a cap layer on the barrier layer 326. HEMT structures including substrates, channel layers, barrier layers, and other layers are described, for example, in U.S. Pat. Nos. 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774, and 7,709,269, the disclosures of which are incorporated herein by reference in their entireties. For example, an AlN buffer layer may be formed on the upper surface 322A of the substrate 322 to provide a suitable crystal structure transition between the silicon carbide substrate 322 and the remainder of the HEMT device 300A. In addition, a strain-balancing transition layer may additionally and/or alternatively be provided as described in commonly assigned U.S. Patent No. 7,030,428, the disclosure of which is incorporated herein by reference as if fully set forth herein. The optional buffer/nucleation/transition layer may be deposited by MOCVD, MBE, and/or HVPE. If present, at least a portion of the buffer/nucleation/transition layer may be within the recessed region 360, although embodiments of the present disclosure are not limited thereto.

The source contact 315 and the drain contact 305 may be formed on the upper surface 326A of the barrier layer 326 and may be laterally spaced apart from one another. The gate contact 310 may be formed on the upper surface 236A of the barrier layer 326 between the source contact 315 and the drain contact 305. The material of the gate contact 310 may be selected based on the composition of the barrier layer 326 and, in some embodiments, may be a Schottky contact. Conventional materials capable of forming a Schottky contact to a gallium nitride-based semiconductor material may be used, such as nickel (Ni), platinum (Pt), nickel silicide (NiSix), copper (Cu), palladium (Pd), chromium (Cr), tungsten (W), and/or tungsten silicon nitride (WSiN).

The source contact 315 and the drain contact 305 may include a metal capable of forming an ohmic contact to the gallium nitride-based semiconductor material. Suitable metals may include refractory metals such as Ti, W, titanium tungsten (TiW), silicon (Si), titanium tungsten nitride (TiWN), tungsten silicide (WSi), rhenium (Re), niobium (Nb), Ni, gold (Au), aluminum (Al), tantalum (Ta), molybdenum (Mo), NiSi x , titanium silicide (TiSi), titanium nitride (TiN), WSiN, and Pt. In some embodiments, the source contact 315 may be an ohmic source contact 315. Thus, the source contact 315 and the drain contact 305 may include an ohmic contact portion in direct contact with the barrier layer 326. In some embodiments, the source contact 315 and/or the drain contact 305 may be formed from multiple layers to form an ohmic contact, which may be provided as described, for example, in commonly assigned U.S. Patent Nos. 8,563,372 and 9,214,352, the disclosures of which are incorporated herein by reference in their entireties.

The source contact 315 may be coupled to a reference signal, such as a ground voltage. In some embodiments, the coupling to the reference signal may be provided by a via (not shown) extending from the lower surface 322B of the substrate 322 through the substrate 322 to the upper surface 326A of the barrier layer. A back metal layer 335 may be formed on the lower surface 322B of the substrate 322. In some embodiments, the back metal layer 335 may be in direct contact with the source contact 315 (e.g., through the use of a via not shown in FIG. 7A ). In some embodiments, the back metal layer 335 may be indirectly electrically connected to the source contact 315 via an additional conductive path. Thus, the back metal layer 335 and the signal coupled to the back metal layer 335 may be electrically connected to the source contact 315.

In some embodiments, recessed region 360 may be positioned within substrate 322 such that recessed region 360 does not vertically overlap source contact 315 (e.g., in the Z direction in FIG. 7A ). For example, recessed region 360 may not vertically overlap interface 315A between source contact 315 and barrier layer 326. In some embodiments, recessed region 360 may not vertically overlap interface 310A between gate contact 310 and barrier layer 326. However, embodiments of the present disclosure are not limited to such configurations. In some embodiments, a portion of recessed region 360 may vertically overlap source contact 315.

7A , a first insulating layer 350_1 may be formed on the barrier layer 326, and a second insulating layer 350_2 may be formed on the first insulating layer 350_1. In some embodiments, the first insulating layer 350_1 and/or the second insulating layer 350_2 may include silicon nitride (SixNy), aluminum nitride (AlN), silicon dioxide (SiO ₂ ), and/or other suitable protective materials. The thickness of the first insulating layer 350_1 may affect the gate-to-source capacitance and the gate-to-drain capacitance, which may affect the switching speed of the semiconductor device 300A. Similarly, the thickness of the second insulating layer 350_2 may affect the gate-to-drain capacitance, which may affect the switching speed and gain of the semiconductor device 300A.

The source contact 315 and the drain contact 305 may be formed in the first insulating layer 350_1, with respective portions thereof underlying the first insulating layer 350_2. It will be understood that the present invention is not limited to the particular shape of the gate contact 310 shown in FIG. 7A , and other shapes of the gate contact 310 and other elements of the semiconductor device 300A are possible without departing from the embodiments described herein. In some embodiments, the gate contact 310 may be closer to the source contact 315 than to the drain contact 305. In some embodiments, the gate contact 310 may be formed as a T-gate and/or a gamma gate, the formation of which is described, for example, in U.S. Pat. Nos. 8,049,252, 7,045,404, and 8,120,064, the disclosures of which are incorporated herein by reference in their entireties. A second insulating layer 350_2 may be formed over the first insulating layer 350_1 and over portions of the drain contact 305, gate contact 310, and source contact 315.

A field plate 312 may be formed on the second insulating layer 350_2. At least a portion of the field plate 312 may be on the gate contact 310. At least a portion of the field plate 312 may be on a portion of the second insulating layer 350_2 between the gate contact 310 and the drain contact 305. The field plate 312 may reduce the peak electric field in the HEMT device 300A, resulting in an increased breakdown voltage and reduced charge trapping. The reduced electric field may also result in other benefits, such as reduced leakage current and improved reliability. Field plates and techniques for forming field plates are described, for example, in U.S. Pat. No. 8,120,064, the disclosure of which is incorporated herein by reference in its entirety. The field plate 312 is optional and may be omitted in some embodiments. For ease of illustration, the first and second insulating layers 350_1, 350_2 and the field plate 312 are not shown in Figures 1A, 1B, and 1C.

The configuration of the recessed region 360 of the HEMT device 300A is not limited to that of FIG. 7A. FIGS. 7B and 7C show examples of HEMT devices 300A', 300A'' that include recessed regions 360 similar to those described herein in FIGS. 2 and 3.

With reference to semiconductor device 300A' of FIG. 7B, impurity regions 375 may be formed in substrate 322 at one or more of the bottom and/or side surfaces of the trenches forming recessed region 360. In some embodiments, impurity regions 375 may be doped with impurities (e.g., by ion implantation) to be p-type. The characteristics of impurity regions 375 may be similar to those shown and described herein with respect to FIG. 2, and as a result, a redundant description thereof will be omitted.

Referring to semiconductor device 300A'' of FIG. 7C, the portion of channel layer 324 (and/or other optional layers described herein) within recessed region 360 may be doped to form impurity region 375'. In some embodiments, the impurity conductivity type of impurity region 375' may be different from that of channel layer 324. For example, in some embodiments, impurity region 375' may be a p-type region, and channel layer 324 may be doped to be n-type. In some embodiments, impurity region 375' and channel layer 324 may have the same conductivity type (e.g., both p-type), but the concentration of dopant in impurity region 375' may be higher than that of channel layer 324. The characteristics of impurity region 375' may be similar to those shown and described herein with respect to FIG. 3, and as a result, a repeated description thereof will be omitted.

Figures 7A-7C show examples of HEMT devices 300A, 300A', 300A" in which a recessed region 360 is provided below the source access region. However, embodiments of the present disclosure are not so limited. Figures 8A and 8B show cross-sectional views of examples of semiconductor devices 400A, 500A implemented as HEMTs, according to some embodiments of the present disclosure. The cross-section shown in Figure 8A is taken along line A-A in Figure 4D or Figure 4E. The cross-section shown in Figure 8B is taken along line A-A in Figure 5D or Figure 5E. Figures 8A and 8B are intended to depict structures for identification and explanation purposes and are not intended to depict the structures to physical scale.

For example, FIG. 8A shows an embodiment of a HEMT device 400A in which a recessed region 360' is provided below the drain access region in a manner similar to that of FIGS. 4A-4C. The recessed region 360' may be formed as a continuous trench similar to that of FIG. 4D or as a series of separated trenches similar to that of FIG. 4E. Although not shown in FIG. 8A, the HEMT 400A may also include an impurity region 475, such as that shown in FIG. 4B, or an impurity region 475', such as that shown in FIG. 4C.

Figure 8B shows an embodiment of a HEMT device 500A in which a recessed region 360' is provided below the drain access region in a manner similar to that of Figures 5A-5C. The recessed region 360'' may be formed as a continuous trench similar to that of Figure 5D or as a series of separated trenches similar to that of Figure 5E. Although not shown in Figure 8B, the HEMT device 500A may also include an impurity region 575, such as that shown in Figure 5B, or an impurity region 575', such as that shown in Figure 5C.

Figures 9A-9G illustrate a method of fabricating a semiconductor device, such as HEMT device 300A of Figure 7A, according to an embodiment of the present disclosure. Figures 9A-9G are views along line CC of Figure 1B.

Now referring to FIG. 9A, a substrate 122 is provided upon which a semiconductor structure may be formed. The substrate 122 may be, for example, a semi-insulating silicon carbide (SiC) substrate, which may be the 4H polytype of silicon carbide. Other candidate silicon carbide polytypes may include the 3C, 6H, and 15R polytypes. The thickness of the substrate 122 may be 100 μm or greater.

Silicon carbide has a significantly closer crystal lattice match to Group III nitrides (which may be employed in the channel layer 324 and/or barrier layer 326) than sapphire (Al ₂ O ₃ ), which may be a common substrate material for Group III nitride devices. The closer lattice match may result in higher quality Group III nitride films than those typically available on sapphire. Silicon carbide also has a relatively high thermal conductivity, such that the total output power of Group III nitride devices formed on silicon carbide may not be limited by the heat dissipation of the substrate as much as similar devices formed on sapphire and/or silicon. Additionally, semi-insulating silicon carbide substrates may provide device isolation and reduced parasitic capacitance.

Although silicon carbide may be employed as the substrate, embodiments of the present invention may utilize any suitable substrate for substrate 122, such as sapphire _{( Al2O3} ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), etc.

Optional buffer, nucleation, and/or transition layers (not shown) may also be provided on the substrate 122. For example, an AlN buffer layer may be provided to provide a suitable crystal structure transition between the silicon carbide substrate and the remainder of the device. In addition, a strain-balancing transition layer may also be provided.

Recessed regions 360 may be formed in the upper surface of substrate 122. Recessed regions 360 may be provided, for example, by forming a mask on the upper surface of substrate 122 and patterning the mask to expose portions of the upper surface of substrate 122 where the location of recessed regions 360 is desired, such as beneath a source access region, beneath a drain access region, or in a region intended to be beneath the gate of the resulting device. The exposed portions of the upper surface of substrate 122 may then be etched using the patterned mask to form recessed regions 360.

Referring to FIG. 9B , a channel layer 324 is provided on the substrate 122 and within the recessed region 360. The channel layer 324 may be deposited on the substrate 122 using buffer, transition, and/or nucleation layers as described above. The channel layer 324 may be under compressive strain. Furthermore, the channel layer 324 and/or the buffer, nucleation, and/or transition layers may be deposited by MOCVD, MBE, and/or HVPE. In some embodiments of the present invention, the channel layer 324 may be a Group III nitride layer.

9B, a barrier layer 326 may be formed on the channel layer 324. The barrier layer 326 may be a Group III nitride layer. In some embodiments of the present invention, the barrier layer 326 may be a highly doped n-type layer. For example, the barrier layer 326 may be doped to a concentration of less than about 10 ¹⁹ cm ⁻³ .

In some embodiments of the present invention, the barrier layer 326 may have a thickness, Al composition, and/or doping sufficient to induce a significant carrier concentration at the interface between the channel layer 324 and the barrier layer 326 due to polarization effects when the barrier layer 326 is buried under an ohmic contact metal. The barrier layer 326 may also be thick enough to reduce or minimize scattering of electrons in the channel by ionized impurities deposited at the interface between the barrier layer 326 and a subsequently formed first protective layer.

In some embodiments, the channel layer 324 and the barrier layer 326 may have different lattice constants. For example, the barrier layer 326 may be a relatively thin layer having a smaller lattice constant than the channel layer 324, such that the barrier layer 326 "stretches" at the interface between them. Thus, a pseudomorphic HEMT (pHEMT) device may be provided.

9D , a first protective layer 410 is formed on the barrier layer 326. The first protective layer 410 may be a dielectric material, such as silicon nitride (SixNy), aluminum nitride (AlN), silicon dioxide ( _SiO2 ), and/or other suitable protective materials. Other materials may also be utilized for the first protective layer 410. For example, the first protective layer 410 may include magnesium oxide, scandium oxide, aluminum oxide, and/or aluminum oxynitride. The first protective layer 410 may be a single layer or may include multiple layers of uniform and/or non-uniform composition.

The first protective layer 410 may be a blanket layer formed on the barrier layer 326. For example, the first protective layer 410 may be a silicon nitride (SiN) layer formed by high-quality sputtering and/or plasma-enhanced chemical vapor deposition (PECVD). The first protective layer 410 may be sufficiently thick to protect the underlying barrier layer 326 during subsequent annealing of the ohmic contact.

Referring to FIG. 9E, the first protective layer 410 (see FIG. 9D) may be patterned to form openings for the source contact 315, the gate contact 310, and the drain contact 305. For example, the first protective layer 410 may be patterned to form windows that expose the barrier layer 326 for placement of the source contact 315 and the drain contact 305. The windows may be etched using a patterned mask and a low-damage etch on the barrier layer 326. Ohmic contacts may be formed in the exposed portions of the barrier layer 326. The ohmic contacts may be annealed to provide the source contact 315 and the drain contact 305.

The first protective layer 410 may be patterned to provide the gate contact 310. The first protective layer 410 may be etched to form a window exposing the barrier layer 326 for placement of the gate contact 310. The gate contact 310 may be formed in the etched window and may extend through the first protective layer 410 to contact the exposed portion of the barrier layer 326. The appropriate gate material may depend on the composition of the barrier layer 326. However, in certain embodiments, conventional materials capable of forming a Schottky contact with nitride-based semiconductor materials may be used, such as Ni, Pt, NiSix, Cu, Pd, Cr, TaN, W, and/or WSiN. A portion of the gate contact 310 may extend above the surface of the first protective layer 410. Formation of the source contact 315, gate contact 310, and drain contact 305 may result in patterning of the first protective layer 410 of FIG. 9D to form the first insulating layer 350_1.

Although the source contact 315 is shown in FIG. 9E as being on top of the barrier layer 326, it will be understood that in some embodiments, the source contact 315, gate contact 310, and/or drain contact 305 may be formed within a recess in the top surface of the barrier layer 326.

Referring to FIG. 9F, a second protective layer 420 may be formed over the first insulating layer 350, the source contact 315, the gate contact 310, and the drain contact 305. The second protective layer 420 may be a dielectric layer. In some embodiments, the second protective layer 420 may have a different dielectric constant than the first insulating layer 350_1.

Referring to FIG. 9G, a field plate 312 may be formed on the second protective layer 420. The field plate 312 may overlap the gate contact 310 (e.g., in the Z direction of FIG. 9F) and may extend a predetermined distance over the region between the gate and drain (i.e., the gate-drain region). The overlap of the field plate 312 on the gate contact 310 and/or the distance the field plate 312 extends over the gate-drain region may be varied for optimal results. In some embodiments, the field plate 312 may be electrically connected to the gate contact 310 or the source contact 315, and it is understood that field plate structures other than those shown may be used without departing from the invention. In some embodiments, the field plate 312 may be omitted.

7A, the substrate 122 (see FIG. 9F) may be thinned to form a thin substrate 322. In some embodiments, the thickness of the substrate 322 is reduced using a grinder, such as an in-feed or creep feed grinder. In other embodiments, the thickness of the substrate 322 is reduced using lapping, with or without grinding, chemical or reactive ion etching, or a combination of these approaches. In still other embodiments, etching may be used to treat the backside of the substrate 322 to reduce damage to the substrate 322 that may occur during the thinning process. Methods for thinning wafers may be described, for example, in commonly assigned U.S. Patent Nos. 7,291,529, 7,932,111, 7,259,402, and 8,513,686, the disclosures of which are incorporated herein by reference in their entireties.

In some embodiments according to the invention, substrate 322 is thinned to a thickness of about 40 μm to about 100 μm. Substrate 322 is thinned to a thickness of about 40 μm to about 75 μm. In some embodiments, thinning of substrate 122 is omitted, and substrate 122 is effectively identical to substrate 322.

A backmetal layer 335 may be deposited on the lower surface 322B of the substrate 322. The backmetal layer 335 may include a conductive metal such as titanium, platinum, and/or gold. The backmetal layer 335 may be electrically connected to the source contact 315 (e.g., by a conductive via or other conductive path).

10A-10D illustrate methods for constructing additional semiconductor devices according to some embodiments of the present disclosure. For example, FIGS. 10A and 10B illustrate methods for forming impurity regions 375, for example, to construct semiconductor device 300' of FIG. 2. Referring to FIG. 10A, doped regions 1075 may be formed in substrate 122. Doped regions 1075 may be formed, for example, by ion implantation into substrate 122. In some embodiments, substrate 122 may be n-type, and doped regions 1075 may be formed to be p-type.

10B, recessed region 360' may be formed in the upper surface of substrate 122 and doped region 1075. Recessed region 360' may be provided, for example, by forming a mask on the upper surface of substrate 122 and patterning the mask to expose portions of the upper surface of substrate 122 and doped region 1075 where recessed region 360' is desired, such as in an area intended to underlie a source access region of the resulting device. Etching recessed region 360' may be performed such that the depth of recessed region 360' (e.g., from the upper surface of substrate 122) and/or the width of recessed region 360' do not exceed that of doped region 1075. After etching recessed region 360', impurity region 375 may be formed on the sidewalls and/or bottom surface of recessed region 360'. The processes of FIGS. 9B-9G may then be performed to form a device incorporating recessed region 360'.

Figures 10C and 10D illustrate a method for forming impurity region 375' to construct, for example, semiconductor device 300'' of Figure 3.

10C may be performed after the step shown in FIG. 9A. Referring to FIG. 10C, impurity region 375' may be formed in recessed region 360. For example, impurity region 375' may be formed by ion implantation. In some embodiments, impurity region 375' may be deposited within recessed region 360 in substrate 122. For example, impurity region 375' may be deposited by MOCVD, MBE, and/or HVPE. In some embodiments, impurity region 375' may be a Group III nitride layer, such as GaN. Impurity region 375' may be doped to be p-type after or during its formation.

Referring to FIG. 10D, a channel layer 324 is provided on the substrate 122 and the impurity region 375'. The channel layer 324 may be deposited on the substrate 122 and the impurity region 375' using buffer, transition, and/or nucleation layers, as described above. The channel layer 324 may be under compressive strain. Furthermore, the channel layer 324 and/or the buffer, nucleation, and/or transition layers may be deposited by MOCVD, MBE, and/or HVPE. In some embodiments of the present invention, the channel layer 324 may be a Group III nitride layer. In some embodiments, the material of the channel layer 324 may be the same as that of the impurity region 375'. The steps of FIGS. 9C-9G may then be performed to form a device incorporating the recessed region 360'.

While Figures 9A-9G and 10A-10D illustrate embodiments in which recessed regions 360 are formed in the source access region, embodiments of the present disclosure are not so limited. As will be understood by those skilled in the art, the methods of Figures 9A-9G and 10A-10D may be similarly applied, mutatis mutandis, to form devices having recessed regions 360' in the drain access region (such as devices 400, 400', and 400" shown in Figures 4A-4E) and devices having recessed regions 360" under the gate contact (such as devices 500, 500', and 500" shown in Figures 5A-5E).

Additionally, although semiconductor structures embodied as HEMT devices 300A, 300A", 300A"" are shown in Figures 9A-9G and 10A-10D, the semiconductor structure 390 described herein may be provided using other types of semiconductor devices. In other words, other types of semiconductor devices may be used, and the methods for forming recessed regions 360 may be applied to semiconductor devices without departing from the scope of the present disclosure. Figures 11A and 11B show exemplary semiconductor devices 300B and 300C that may include recessed regions 360, 360', 360" described herein. Duplicate descriptions of elements in Figures 11A and 11B previously described will be omitted. Figures 11A and 11B are generally viewed along line A-A in Figures 1B and 1C.

Figure 11A shows a metal-semiconductor field-effect transistor (MESFET) device 300B in which the region of semiconductor structure 390 between source and drain regions 215 and 205 provides the conductive channel or channel region of MESFET 300B. MESFET 300B may be formed on a substrate 322.

FIG. 11B shows a metal oxide semiconductor field effect transistor (MOSFET) device 300C in which the region of semiconductor structure 390 between source and drain regions 215 and 205 provides the channel region of MOSFET 300C, and gate contact 310 is separated from the channel region by gate oxide layer 110. MOSFET 300C may be formed on a substrate 322.

Each semiconductor device 300B, 300C may include a recessed region 360 in the substrate 322. While FIGS. 11A and 11B show an embodiment in which the recessed region 360 is formed in the source access region, embodiments of the present invention are not limited in this respect. The semiconductor devices 300B, 300C of FIG. 11A may also be embodied with a recessed region 360' in the drain access region (such as devices 400, 400', 400" shown in FIGS. 4A-4E) and/or with a recessed region 360" under the gate contact (such as devices 500, 500', 500" shown in FIGS. 5A-5E).

12A, 12B, and 12C are schematic cross-sectional views illustrating several exemplary ways in which semiconductor device 300A according to embodiments of the present disclosure may be packaged to provide packaged transistor devices 600A-600C, respectively. While FIGS. 12A-12C show semiconductor device 300A of FIG. 7A being packaged, it will be appreciated that any of semiconductor devices 300A, 300A', 300A", 300B, and 300C according to embodiments of the present disclosure may be packaged in the packages illustrated in FIGS. 12A-12C.

Figure 12A is a schematic side view of a packaged transistor device 600A. As shown in Figure 12A, the packaged transistor device 600A includes a semiconductor device 300A packaged in an open cavity package 610A. The package 610A includes a metal gate lead 622A, a metal drain lead 624A, a metal submount 630, sidewalls 640, and a lid 642.

The submount 630 may include a material configured to aid in thermal management of the packaged transistor device 600A. For example, the submount 630 may include copper and/or molybdenum. In some embodiments, the submount 630 may be comprised of multiple layers and/or may include vias/interconnects. In an exemplary embodiment, the submount 630 may be a multi-layer copper/molybdenum/copper metal flange including a core molybdenum layer with copper cladding layers on each major surface thereof. In some embodiments, the submount 630 may include a metal heat sink that is part of a lead frame or metal slug. The sidewalls 640 and/or the lid 642 may be formed from or include an insulating material in some embodiments. For example, the sidewalls 640 and/or the lid 642 may be formed from or include a ceramic material. In some embodiments, the sidewalls 640 and/or the lid ₆₄₂ may be formed from, for example, _Al2O3 . The lid 642 may be adhered to the sidewall 640 using epoxy glue. The sidewall 640 may be attached to the submount 630 by brazing, for example. The gate lead 622A and the drain lead 624A may be configured to extend through the sidewall 640, although embodiments of the present invention are not limited in this respect.

The semiconductor device 300A is mounted on the top surface of the metal submount 630 within an air-filled cavity 612 defined by the metal submount 630, ceramic sidewalls 640, and ceramic lid 642. The gate and drain terminals 632, 634 of the semiconductor device 300 may be on the top side of the semiconductor device 300A, while the source terminal 636 may be on the bottom side of the semiconductor device 300A. The source terminal 636 may be attached to the metal submount 630 using, for example, a conductive die attach material (not shown). The metal submount 630 may provide an electrical connection to the source terminal 636 and may act as a heat dissipation structure to dissipate heat generated in the semiconductor device 300A. Heat is primarily generated in the top portion of the semiconductor device 300A, where, for example, a relatively high current density is generated in the channel regions of the unit cell transistors. This heat can be transferred through the semiconductor structure 390 to the source terminal 636 and then to the metal submount 630.

An input matching circuit 650 and/or an output matching circuit 652 may also be mounted within the package 610A. The matching circuits 650, 652 may include impedance matching and/or harmonic termination circuits. The impedance matching circuit may be used to match the impedance of the fundamental element of the RF signal input to or output from the packaged transistor device 600A to the impedance at the input or output, respectively, of the semiconductor device 300A. The harmonic termination circuit may be used to ground harmonics of the fundamental RF signal that may be present at the input or output of the semiconductor device 300A. Two or more input matching circuits 650 and/or output matching circuits 652 may be provided. As shown schematically in FIG. 12A, the input and output matching circuits 650, 652 may be mounted on a metal submount 630. The gate lead 622A may be connected to an input matching circuit 650 by one or more bond wires 654, which may be connected to the gate terminal 632 of the semiconductor device 300A by one or more additional bond wires 654. Similarly, the drain lead 624A may be connected to an output matching circuit 652 by one or more bond wires 654, which may be connected to the drain terminal 634 of the semiconductor device 300A by one or more additional bond wires 654. The bond wires 654, which are inductive elements, may form part of the input and/or output matching circuits 650, 652.

Figure 12B is a schematic side view of a packaged transistor device 600B that includes the semiconductor device 300A of Figure 7A packaged in a printed circuit board-based package 610B. The packaged transistor device 600B is very similar to the packaged transistor device 600A of Figure 12A, except that the gate and drain leads 622A, 624A of package 610A have been replaced with printed circuit board-based leads 622B, 624B in package 610B.

Package 610B includes a submount 630, a ceramic sidewall 640, and a ceramic lid 642, each of which may be substantially the same as the like-numbered elements of package 610A described above. Package 610B also includes a printed circuit board 620. Conductive traces on the printed circuit board 620 form a metal gate lead 622B and a metal drain lead 624B. The printed circuit board 620 may be attached to the submount 630 by, for example, conductive glue. The printed circuit board 620 includes a central opening, and the semiconductor device 300 is mounted within this opening on the submount 630. The other components of packaged transistor device 600B may be the same as the like-numbered elements of packaged transistor device 600A, and therefore further description thereof will be omitted.

12C shows a schematic side view of another packaged transistor device 600C. Packaged transistor device 600C differs from packaged transistor device 600A in that it includes a different package 610C. Package 610C includes a metal submount 630 (which may be similar or identical to the like-numbered submount 630 of package 610) and metal gate and drain leads 622C, 624C. Packaged transistor device 600C also includes a plastic overmold 660 that at least partially encloses semiconductor device 300A, leads 622C, 624C, and metal submount 630. Other components of packaged transistor device 600C may be the same as the like-numbered components of transistor device 600A, and therefore further description thereof will be omitted.

The various embodiments of the present invention described above illustrate the gate, source, and drain contacts as all being on the top surface of the semiconductor structure (i.e., the surface opposite the surface that contacts the substrate). In this case, such contacts may be referred to as "top-side" contacts. However, it will be appreciated that semiconductor devices according to embodiments of the present invention are not limited to having only top-side source, gate, and drain contacts. For example, as described above with respect to FIG. 7A , conductive source vias (not shown) may be provided that extend through the semiconductor structure 390 and the substrate 322. These source vias may include, for example, metal-plated or metal-filled vias (openings) that may be used to electrically connect the top-side source contacts 315 to a first backside metal layer that may be provided on the bottom surface of the substrate 322. The first backside metal layer may serve as the backside source contacts.

In other embodiments, a gate via may be provided extending through the semiconductor structure 390 and the substrate 322 to electrically connect the top-side gate contact 310 to a second backside metal pattern that may be provided on the underside of the substrate 322, which may serve as a backside gate contact, and/or a drain via may be provided extending through the semiconductor structure 390 and the substrate 322 to electrically connect the drain contact 305 to a third backside metal pattern that may be provided on the underside of the substrate 322, which may serve as a backside drain contact. The use of backside source, gate, and/or drain contacts may provide a convenient method for connecting the semiconductor device to external circuitry, for example, reducing or eliminating any need for bond wire connections between the semiconductor device and external circuitry.

It will be appreciated that semiconductor devices according to embodiments of the present invention may include any combination of backside source, drain, and gate contacts (and their associated vias). For example, in some embodiments, backside source and gate contacts (and their associated vias) may be provided, while in other embodiments, backside source and drain contacts (and their associated vias) may be provided. In still other embodiments, backside source, gate, and drain contacts (and their associated vias) may be provided. Other combinations are possible. It will also be appreciated that the top-side source, gate, and drain contacts 305, 310, 315 may or may not be connected to (or may or may not include) bond pads or other structures that facilitate forming electrical connections from external sources to the top-side source, gate, and drain contacts 305, 310, 315. Thus, semiconductor devices according to embodiments of the present invention can be configured with top-side only, back-side only, or both top-side and back-side contact structures for connecting to external circuitry for each of the source, gate, and drain contacts.

U.S. Patent Application No. 17/211,281 (the "'281 Application"), filed March 24, 2021, discloses an RF transistor amplifier having backside source, gate, and/or drain contacts. The entire contents of the '281 Application are incorporated herein by reference. It will be appreciated that any of the backside and top-side source, gate, and drain contact arrangements disclosed in the '281 Application may be used in any of the semiconductor devices according to embodiments of the invention disclosed herein. It will also be appreciated that semiconductor devices according to embodiments of the invention may be mounted such that the substrate is mounted on an underlying mounting substrate, or alternatively, may be mounted in a flip-chip configuration where the top-side contacts are mounted on an underlying mounting substrate.

Although terms such as first, second, etc. may be used herein to describe various elements, it will be understood that these elements are not to be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including," as used herein, specify the presence of stated features, integers, steps, processes, elements, and/or components, but do not exclude the presence or addition of one or more other features, integers, steps, processes, elements, components, and/or groups thereof.

Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms used herein should be interpreted as having a meaning consistent with their meaning in the context of the present specification and the relevant art, and it will be further understood that they should not be interpreted in an idealized or overly formal sense unless expressly defined otherwise herein.

When an element, such as a layer, region, or substrate, is described as being "on" or extending "on" another element, it will be understood that the element can be directly on or extending directly onto the other element, or intervening elements may be present. In contrast, when an element is described as being "directly on" or "extending directly onto" another element, there are no intervening elements. When an element is described as being "connected" or "coupled" to another element, it will also be understood that the element can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

Relative terms such as "lower" or "upper" or "upper" or "bottom" or "horizontal" or "lateral" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, deviations from the shapes of the illustrations are to be expected as a result, for example, of manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be construed as limited to the specific shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. Similarly, it will be understood that dimensional variations are to be expected based on standard deviations in manufacturing procedures. As used herein, unless otherwise specified, "about" and/or "substantially" include values within 10% of the nominal value.

The same numbers refer to the same elements throughout. Thus, the same or similar numbers may be described with respect to other drawings even if they are not mentioned or described in the corresponding drawing. Also, elements not indicated by a reference number may be described with respect to other drawings.

Some embodiments of the invention are described in terms of semiconductor layers and/or regions characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration in the layer and/or region. Thus, N-type material has a majority equilibrium concentration of negatively charged electrons, while P-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated by a "+" or "-" (e.g., N+, N-, P+, P-, N++, N--, P++, P--) to indicate a relatively greater ("+") or lesser ("-") concentration of majority carriers compared to another layer or region. However, such designations do not imply the presence of a particular concentration of majority or minority carriers in the layer or region.

In the drawings and specification, exemplary embodiments of the invention are disclosed and, although specific terms are used, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being indicated in the following claims.

Claims (14)

A semiconductor device comprising:
a substrate, the top surface of the substrate comprising a recessed region;
a semiconductor structure on the substrate, a portion of the semiconductor structure within the recessed region; and
a gate contact, a drain contact, and a source contact on the semiconductor structure;
the recessed region does not vertically overlap either the drain contact or the interface between the gate contact and the semiconductor structure in a direction perpendicular to the bottom surface of the substrate ;
the portion of the semiconductor structure within the recessed region is an undoped Group III nitride layer. The semiconductor device of claim 1, wherein the substrate includes an impurity region adjacent to the recessed region. The semiconductor device of claim 2, wherein the impurity region contains p-type impurities. The semiconductor device of claim 3, wherein the impurity region is located on at least one sidewall and/or bottom surface of the recessed region. 5. The semiconductor device of claim 1, wherein the recessed region is on a portion of the semiconductor structure that extends from beneath the source contact to beneath the gate contact. 5. The semiconductor device of claim 1 , wherein the recessed region is on a portion of the semiconductor structure that extends from beneath the drain contact to beneath the gate contact. the gate contact includes a first gate contact;
the semiconductor device further includes a second gate contact;
The semiconductor device of claim 1 , wherein the recessed region underlies the first gate contact. the first and second gate contacts extend in a first direction on the semiconductor structure;
The semiconductor device of claim 7 , wherein the recessed region has a longitudinal axis extending in the first direction. 8. The semiconductor device of claim 7, wherein a first threshold voltage of a first transistor associated with the first gate contact is different from a second threshold voltage of a second transistor associated with the second gate contact. the gate contact has a longitudinal axis extending in a first direction;
8. The semiconductor device of claim 7 , wherein the recessed region comprises a plurality of recessed regions disposed below the gate contact and spaced apart from one another along the first direction. A semiconductor device comprising:
a substrate, the top surface of the substrate comprising a recessed region;
a semiconductor structure on the substrate, a portion of the semiconductor structure within the recessed region; and
a gate contact, a drain contact, and a source contact on the semiconductor structure;
the substrate and the portion of the semiconductor structure within the recessed region form a heterojunction;
the semiconductor device is configured such that a two-dimensional electron gas (2DEG) layer extending continuously from beneath the source contact to beneath the drain contact is injected into the semiconductor structure during operation in an on-state;
the recessed region does not vertically overlap any of the source contact, the gate contact, or the drain contact;
A semiconductor device, wherein a portion of the substrate including the sidewalls and bottom of the recessed region is implanted with a dopant of a first conductivity type. The semiconductor device of claim 11 , wherein the portion of the semiconductor structure within the recessed region is an undoped Group III-nitride layer. 12. The semiconductor device of claim 11 , wherein the portion of the substrate having the sidewalls and bottom in the recessed region and implanted with the first conductivity type dopant overlaps only vertically with a portion of the source contact. 12. The semiconductor device of claim 11 , wherein the portion of the substrate having the sidewalls and bottom in the recessed region and implanted with the first conductivity type dopant overlaps only vertically with a portion of the gate contact.