JP7750109B2 - Semiconductor device and ignition system - Google Patents

Description

The present invention relates to a semiconductor device that controls the switching of a semiconductor switch and an ignition system that controls the ignition of an engine.

In recent years, the automotive industry has seen progress in the development of highly functional ignition systems. In ignition systems, a semiconductor device called an igniter controls the ignition of an automotive engine, and discharges (ignites) the spark plug via an ignition coil under control of an ECU (Electronic Control Unit).

13 is a diagram showing the configuration of a conventional ignition system. The ignition system 100 includes an igniter 110, an ignition coil 2, a spark plug 3, and a capacitor _CVB . The ignition coil 2 includes a primary coil L1, a secondary coil L2, and a diode Da.

The primary coil L1 of the ignition coil 2 is connected to terminal a1 of the igniter 110, which acts as a switch that turns the current on and off, and the secondary coil L2 is connected to the spark plug 3.

A terminal a2 of the igniter 110 is connected to ground (GND), and a terminal a3 of the igniter 110 is connected to the ECU 4. A capacitor _CVB is connected between the power supplies of the ignition system 100 to suppress the propagation of noise and surges from the ignition coil 2 to the battery Ba side.

The ECU 4, ignition coil 2, and spark plug 3 are supplied with power through battery Ba, and the ignition system 100 operates when a signal from the ECU 4 is input to terminal a3 of the igniter 110. The ignition system 100 and battery Ba are connected via a harness h1 (wiring cable).

Figure 14 shows the circuit configuration of a conventional igniter. The igniter 110 includes an IGBT (Insulated Gate Bipolar Transistor) as a power semiconductor switch, and the gate terminal, collector terminal, and emitter terminal are connected to the IGBT as input/output terminals via resistor Rg. The collector terminal, emitter terminal, and gate terminal correspond to terminals a1, a2, and a3 shown in Figure 13, respectively.

Connected between the gate terminal, to which the signal from the ECU 4 is input, and resistor Rg are a Zener diode GEZD (gate-emitter Zener diode) for surge removal and a pull-down resistor Rpull for drawing the voltage Vg applied to the gate terminal to the emitter terminal when the signal is off. The signal recognition circuit 11a is also connected between the gate terminal and emitter terminal, operates using voltage Vg as its power source, and recognizes the signal sent from the ECU 4 to instruct the IGBT to turn on/off.

The output of the signal recognition circuit 11a is input to the gate of the pull-down MOS 13 via inverter IN1. The pull-down MOS 13 is, for example, an NMOS transistor, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The pull-down MOS 13 is used as a pull-down MOS that discharges the gate voltage Vge applied to the gate of the IGBT and pulls out the gate charge.

The drain of the pull-out MOS 13 is connected to the gate of the IGBT via resistor Rp, and the source of the pull-out MOS 13 is connected to the emitter terminal. A Zener diode group CGZD (multiple collector-gate Zener diodes) is connected between the collector terminal and the gate of the IGBT to perform clamping when high voltages are generated.

In a normal configuration, a fixed voltage supplied from battery Ba is used as the driving voltage, but as described above, igniter 110 uses the voltage of the signal from ECU 4 input to the gate terminal (gate terminal voltage Vg) as the driving voltage. Therefore, if the signal level input to the gate terminal falls below the operating power supply voltage of signal recognition circuit 11a, igniter 110 enters a non-driving state, and operation of the entire ignition system 100 stops.

Here, when an ON signal to turn on the IGBT is input from ECU 4 to the gate terminal, signal recognition circuit 11a outputs an H level, and inverter IN1 outputs an L level to the gate of pull-out MOS 13, turning it off.

Furthermore, when an OFF signal is received from the ECU 4 while the IGBT is in the ON state, the signal recognition circuit 11a switches the output signal from H level to L level. At this time, the output logic of the inverter IN1 is inverted (from L level to H level), causing the extraction MOS 13 to turn ON and begin conducting current, extracting gate charge from the gate of the IGBT and discharging the gate voltage Vge.

However, if the gate terminal voltage Vg falls below the operating power supply voltage of the signal recognition circuit 11a, this function is lost. Meanwhile, the IGBT's gate voltage Vge is also discharged via resistor Rg and pull-down resistor Rpull. This discharge of the gate voltage Vge causes the IGBT to transition to the off state.

FIG. 15 is a time chart showing the operating waveforms of a conventional igniter.
[Period from time t0 to time t1] Assume that the IGBT transitions to the off state from time t0. The gate terminal voltage Vg drops because it is discharged by the pull-down resistor Rpull. Furthermore, the gate voltage Vge is discharged by the pull-down MOS 13 and the pull-down resistor Rpull, and the gate voltage Vge drops to the mirror voltage.

Note that the igniter 110 is configured to turn the IGBT off by gradually discharging the gate terminal voltage Vg and gate voltage Vge, so the gate terminal voltage Vg and gate voltage Vge do not drop suddenly.

[Period from time t1 to time t2] Residual charge at the gate terminal is discharged through pull-down resistor Rpull, causing the gate terminal voltage Vg to gradually decrease. Meanwhile, the IGBT collector voltage Vce increases, but Miller capacitance feeds back from the IGBT collector to the gate.

Therefore, even if the gate voltage Vge is discharged by the pull-down resistor Rpull, the increased collector voltage Vce is fed back to the gate, so the decrease and increase cancel each other out, and the gate voltage Vge becomes close to a flat state. The period in which this phenomenon occurs (the period from time t1 to time t2) is called the mirror region.

[Period from time t2 to time t3] The period from time t2 onwards is the period after the end of the mirror region, and from time t2 onwards the IGBT approaches a fully off state (complete shutdown of the IGBT). As the gate voltage Vge decreases, the collector current Ice decreases. In addition, the collector voltage Vce rises to a clamp voltage determined by the breakdown voltage of the Zener diode group CGZD.

[Period from time t3 to time t4] When the Zener diode group CGZD breaks down, charge is supplied from the collector terminal to the gate voltage Vge, slowing the rate at which the gate voltage Vge falls.

As the rate of decline of the gate voltage Vge slows, the rate of decline of the collector current Ice also slows, and the collector current Ice continues to decline until the stored energy in the ignition coil 2 connected to the collector terminal is released.

[Period from time t4 to time t5] Charge is no longer supplied from the collector terminal to the IGBT gate, accelerating the decline of the gate voltage Vge. The collector current Ice also becomes zero. However, because the gate terminal voltage Vg has fallen to a voltage at which the signal recognition circuit 11a cannot operate, no current is drawn by the pull-down MOS 13, and current is slowly drawn only by the pull-down resistor Rpull. The gate voltage Vge at time t4 is the operating threshold voltage of the IGBT.

Related technologies include, for example, a technique in which, when an IGBT transitions from an on to an off state, the first and second switches are closed simultaneously to extract gate charge from the IGBT gate, and when the rate of rise of the collector voltage is high, the second switch is opened to mitigate the extraction of gate charge.

Japanese Patent Application Laid-Open No. 2021-103849

With the igniter 110 configured as described above, the IGBT collector current Ice also drops sharply as the gate voltage Vge drops sharply after the mirror region ends, and this increases dI/dt (change in current over time), which is the rate of current change corresponding to the IGBT's switching speed. From the perspective of IGBT switching loss, it is considered that the greater the dI/dt, the lower the switching loss.

However, because the collector current Ice flows from the emitter terminal to GND via the harness h1, if dI/dt is too large, an induced voltage will be generated at the emitter terminal due to the parasitic inductance of the harness h1 connecting the ignition system 100 and the battery Ba.

Furthermore, since a capacitor _CVB is connected to the emitter terminal to prevent noise and surges from propagating to the battery Ba, when an induced voltage is generated, resonance occurs between the parasitic inductance component of the harness h1 and the capacitance component of the capacitor _CVB , generating resonance noise, which can cause the ignition system 100 to malfunction due to, for example, the IGBT being turned on erroneously.

The above describes the generation of resonant noise when the IGBT is turned off in the ignition system 100. However, in general, a sudden drop in the collector current Ice when the IGBT is turned off increases the likelihood of noise being generated in the area around the IGBT. For this reason, there is a demand for technology that can effectively prevent noise that may be generated when the IGBT is turned off while maintaining the IGBT's switching time.

In one aspect, the present invention aims to provide a semiconductor device and an ignition system that prevent noise generation and ensure stable operation of the device.

To solve the above problem, a semiconductor device is provided. The semiconductor device has a semiconductor switch and a control circuit. The control circuit is driven by the voltage of a signal that instructs the semiconductor switch to be on or off. The control circuit also has a first extraction circuit and a second extraction circuit. When an instruction to turn the semiconductor switch off is detected, the first extraction circuit extracts gate charge from the gate of the semiconductor switch with a first sink capacity. When a voltage generated from the collector voltage of the semiconductor switch is equal to or higher than a predetermined voltage, the second extraction circuit extracts gate charge with a second sink capacity higher than the first sink capacity.

An ignition system is also provided to solve the above problem. The ignition system includes an igniter, an ignition coil, a spark plug, and a capacitor. The igniter includes a semiconductor switch, a first extraction circuit that extracts gate charge from the gate of the semiconductor switch with a first sink capacity when an instruction to turn the semiconductor switch off is detected, and a second extraction circuit that extracts gate charge with a second sink capacity higher than the first sink capacity when a voltage generated from the collector voltage of the semiconductor switch is equal to or higher than a predetermined voltage. The igniter is powered by the voltage of a signal output from an electronic control unit that instructs the semiconductor switch to turn on or off. The ignition coil is connected to an external power source via a harness and amplifies the voltage generated by the semiconductor switch. The spark plug discharges based on the negative voltage output from the ignition coil. The capacitor is connected to the power source and ground within the system and to the emitter of the semiconductor switch via a harness.

According to one aspect, it is possible to prevent noise generation and ensure stable operation of the device.

1A and 1B are diagrams illustrating a semiconductor device according to the present invention; FIG. 1 is a diagram illustrating an example of the overall configuration of an ignition system. FIG. 2 is a diagram illustrating an example of the configuration of an ECU. 3 is a time chart showing the overall operation of the ignition system. FIG. 2 is a diagram illustrating an example of a circuit configuration of an igniter. FIG. 2 is a diagram illustrating an example of a configuration of a logic circuit. FIG. 2 is a diagram illustrating the operation logic of a logic circuit. FIG. 2 is a diagram for explaining generation of a power supply voltage supplied to a logic circuit. 4 is a time chart showing the operation of an igniter. 10A and 10B are diagrams illustrating waveform comparison between the operation of the present invention and the conventional operation. FIG. 10 is a diagram showing a modified example of the igniter. FIG. 10 is a diagram illustrating a modified example of a logic circuit. FIG. 1 is a diagram showing the configuration of a conventional ignition system. FIG. 1 is a diagram showing a circuit configuration of a conventional igniter. 10 is a time chart showing the operating waveforms of a conventional igniter.

The present embodiment will be described below with reference to the drawings.
1 is a diagram illustrating a semiconductor device according to the present invention. The semiconductor device 1 includes a semiconductor switch 1a and a control circuit 1b. The control circuit 1b is driven by a voltage signal ct that indicates whether the semiconductor switch 1a is on or off. The semiconductor switch 1a is, for example, an IGBT.

Control circuit 1b includes extraction circuit 1b1 (first extraction circuit) and extraction circuit 1b2 (second extraction circuit). Extraction circuit 1b1 extracts gate charge from the gate of semiconductor switch 1a with a first sink capacity when it detects an instruction to turn semiconductor switch 1a off from signal ct. Extraction circuit 1b2 extracts gate charge with a second sink capacity higher than the first sink capacity when the voltage generated from the collector voltage of semiconductor switch 1a is equal to or higher than a predetermined voltage. Semiconductor switch 1a and control circuit 1b, which includes extraction circuits 1b1 and 1b2, are integrated on the same chip.

Here, in semiconductor device 1, extraction circuits 1b1 and 1b2 are used to extract the gate charge of semiconductor switch 1a in two stages. During the first period t11 of the first stage, extraction circuit 1b1 slowly extracts gate charge from the gate of semiconductor switch 1a using the first sink capacity, easing the decline of collector current Ice so that the collector current Ice has a current change rate that does not trigger noise.

On the other hand, maintaining the switching time ts is also important in terms of switching loss, so during the second period t12 of the second stage, the extraction circuit 1b2 extracts the gate charge with a second sink capacity that is higher than during the first period t11, thereby maintaining the specified switching time ts.

This configuration of semiconductor device 1 prevents noise caused by the sudden switching operation of semiconductor switch 1a when semiconductor switch 1a is turned off, enabling stable operation. Furthermore, the switching time of semiconductor switch 1a is kept within a specified time, making it possible to suppress switching losses.

Next, as an example of an application in which the semiconductor device 1 is used, the application of the semiconductor device 1 to an ignition system will be described in detail below. Note that, hereinafter, components that have already been described will be assigned the same reference numerals, and descriptions of the same components may be omitted.

<Overall configuration of ignition system>
2 is a diagram showing an example of the overall configuration of an ignition system 1-1. The ignition system 1-1 includes an igniter 10 having the function of the semiconductor device 1, an ignition coil 2, a spark plug 3, and a capacitor _CVB .

The igniter 10 includes an IGBT, an IC 10a having the function of a control circuit 1b, a resistor R10, a resistor Rg, a pull-down resistor Rpull, a diode D _B3 , a Zener diode group CGZD, and a Zener diode GEZD, and the gate terminal (Gate), collector terminal (Collector), and emitter terminal (Emitter) are connected to the IGBT as input/output terminals.

The igniter 10 generates a high voltage using the IGBT, which is then amplified by the ignition coil 2 to several tens of kV, sparking the spark plug 3 and igniting it when the IGBT switches from on to off. The igniter 10 also uses the voltage of a signal from the ECU 4 input to its gate terminal as its driving voltage.

The ECU 4, ignition coil 2, and spark plug 3 are supplied with power through battery Ba, and the ignition system 1-1 operates when a signal from the ECU 4 is input to the gate terminal of the igniter 10. The ignition system 1-1 and battery Ba are connected via a harness h1.

As described above, the igniter 10 uses the voltage of the signal input to the gate terminal from the ECU 4 (gate terminal voltage Vg) as its driving voltage. Therefore, if the signal level input to the gate terminal falls below the operating power supply voltage of IC 10a, the igniter 10 enters a non-driving state, causing the ignition system 1-1 as a whole to stop operating.

The connections of the peripheral components of the igniter 10 will now be described. The positive power terminal of the battery Ba is connected to the power terminal of the ECU 4, one end of the capacitor _CVB , one end of the primary coil L1, and the cathode of the diode Da. The other end of the primary coil L1 is connected to the collector terminal of the igniter 10. The anode of the diode Da is connected to one end of the secondary coil L2, the other end of which is connected to one end of the spark plug 3, the other end of which is connected to GND.

The negative power supply terminal of the battery Ba is connected to the reference power supply terminal of the ECU 4, the other end of the capacitor _CVB , the emitter terminal of the igniter 10, and GND. The signal output terminal of the ECU 4 is connected to the gate terminal of the igniter 10. Details of the internal circuit configuration of the igniter 10 will be described later with reference to FIG. 5.

<Configuration of ECU>
3 is a diagram showing an example of the configuration of an ECU 4. The ECU 4 includes a regulator 40, a PNP transistor 41, a resistor R41, and a capacitor C41. A PMOS transistor, which is a P-channel MOSFET, may be used instead of the PNP transistor 41.

The power supply terminal of regulator 40 is connected to the positive power supply terminal of battery Ba, and battery voltage Vb is applied. The output terminal of regulator 40 is connected to the emitter of PNP transistor 41, and the collector of PNP transistor 41 is connected to one end of resistor R41.

The other end of resistor R41 is connected to one end of capacitor C41 and the gate terminal of igniter 10, and the other end of capacitor C41 and the reference power supply terminal of regulator 40 are connected to GND. A signal for controlling the IGBT on/off, sent from a processor or the like (not shown), is input to the base of PNP transistor 41.

Here, regulator 40 outputs a voltage of 5V from battery voltage Vb (approximately 12V to 14V) input from battery Ba. PNP transistor 41 turns on when turning on the IGBT inside igniter 10, and gate terminal voltage Vg is applied to the gate terminal of igniter 10.

Furthermore, when the IGBT is turned off, the PNP transistor 41 is turned off. In this case, when the PNP transistor 41 is turned off, the charge stored in the capacitor C41 flows to GND via the pull-down resistor Rpull inside the igniter 10. Therefore, the pull-down resistor Rpull shown in Figure 2 has both the function of consuming the charge stored in the capacitor C41 of the ECU 4 and the function of drawing out the gate charge when the IGBT is turned off.

<Overall operation of the ignition system>
4 is a time chart showing the overall operation of the ignition system, which shows the operation when the IGBTs in the igniter 10 are switched.

[Period from time T0 to time T1] When the gate terminal voltage Vg becomes high due to an on signal from the ECU 4, the gate voltage Vge of the IGBT inside the igniter 10 becomes high, and the IGBT begins to conduct electricity, causing the collector current Ice to flow.

The collector current Ice does not rise sharply because the IGBT load is the ignition coil 2. The collector current Ice rises at a gradual rate due to the influence of the inductance of the L load of the ignition coil 2.

In addition, the collector voltage Vce is approximately equal to the battery voltage Vb before the gate terminal voltage Vg reaches the level of the ON signal. When the ON signal from the ECU 4 is input to the gate terminal and the IGBT begins to conduct electricity, the collector voltage Vce drops from a voltage approximately equal to the battery voltage Vb to the ON voltage of the IGBT. In addition, the secondary voltage V2 applied to the secondary coil L2 of the ignition coil 2 outputs a voltage proportional to the change in the collector current Ice over time.

Note that during the period from time T0 to time T1, the collector current Ice rises gradually at first, then rises sharply midway. This steep rise in collector current Ice is due to magnetic saturation of the ignition coil 2, which reduces the impedance of the coil and makes it easier for the collector current Ice to flow.

[Period from time T1 to time T2] The current limiting function built into the igniter 10 controls (throttles) the gate voltage Vge to limit the collector current Ice, and the collector current Ice is maintained at a constant value (I _CL ). Furthermore, since the collector current Ice is constant, the collector voltage Vce is also constant.

[Period from time T2 to time T3] In response to an OFF signal from the ECU 4, the gate terminal voltage Vg begins to transition to the L level, and the gate voltage Vge also begins to decrease. At time T2, the IGBT begins to cut off, causing the collector current Ice to decrease. The collector voltage Vce increases in proportion to the change in the collector current Ice over time (proportional to the cut-off speed of the IGBT), but is clamped by the Zener diode group CGZD inside the igniter 10, so the increasing level stops at the clamp voltage _VCL .

For example, if the breakdown voltage of the Zener diode group CGZD is 400 V, the Zener diode group CGZD will break down when the collector voltage Vce rises to 400 V, and the collector voltage Vce will be fixed at the clamp voltage _VCL of 400 V. Thereafter, the IGBT consumes the inductive energy stored in the primary coil L1 of the ignition coil 2 through such active clamp operation.

[Period after time T3] Once the collector current Ice has run out, the collector voltage Vce begins to return to the battery voltage Vb. Note that time period T3a corresponds to the discharge duration specific to the ignition coil 2. During time period T3a, the coil energy is fed back to the igniter 10, causing the collector voltage Vce to rise slightly for a few milliseconds. After time period T3a, the collector voltage Vce settles down to the level of the battery voltage Vb.

On the other hand, the secondary voltage V2 of the ignition coil 2 generates a voltage proportional to the winding ratio with respect to the primary coil L1, but when the IGBT is cut off at time T2, the energy stored in the secondary coil L2 is released, generating a negative voltage of, for example, about minus several tens of kV. When this negative voltage reaches the spark voltage _Vspark , the insulation between the spark plug 3 and GND breaks down, causing a discharge (ignition).

The above series of operations is an ideal state, and in reality, as mentioned above, there is a possibility that resonant noise may occur due to the sudden switching operation of the IGBT due to the parasitic inductance component of harness h1.

Therefore, the present invention suppresses sudden changes in the collector current Ice when the IGBT is turned off, preventing the generation of resonant noise, maintaining the ignition performance of the spark plug 3 and enabling stable operation of the ignition system 1-1.

<Igniter configuration>
5 is a diagram showing an example of the circuit configuration of an igniter. Igniter 10 includes an IGBT that turns current on and off, an IC 10a that controls the IGBT, a group of clamping Zener diodes CGZD that protect the device from a high collector voltage that occurs when the current is off, a Zener diode GEZD for surge removal, a pull-down resistor Rpull that pulls out the gate voltage Vge when the IGBT is off, a resistor R10, and a diode D _B3 . Hereinafter, the group of Zener diodes CGZD may be represented by Zener diodes CGZD1 and CGZD2.

The IC 10a includes an extraction circuit 11 (first extraction circuit), an extraction circuit 12 (second extraction circuit), and diodes D _B1 and D _B2 . The extraction circuit 11 includes a detection circuit 11-1, an extraction MOS 11b (first extraction transistor), and a resistor Rp1 (first resistive element), and the detection circuit 11-1 includes a signal recognition circuit 11a and an inverter IN1.

The extraction circuit 12 includes a logic circuit 12a, an extraction MOS 12b (second extraction transistor), a resistor Rp2 (second resistive element), and a capacitor C2. NMOS transistors are used for the extraction MOSs 11b and 12b.

In the extraction circuit 11, the detection circuit 11-1 operates using the gate terminal voltage Vg as its power source, and the signal recognition circuit 11a recognizes signals sent from the ECU 4 that instruct the IGBT to turn on or off. The output voltage V1 of the signal recognition circuit 11a is inverted via the inverter IN1, and the output voltage Mg1 (first drive signal) of the inverter IN1 is input to the gate of the extraction MOS 11b.

In the extraction circuit 12, the logic circuit 12a operates using voltage Vs as a power supply, compares the voltage generated from the IGBT collector voltage with a predetermined voltage, and generates an output voltage Mg2 (second drive signal) based on the comparison result, which is input to the gate of extraction MOS 12b.

The connection relationships of the components will be described below: The gate terminal is connected to the cathode of the Zener diode GEZD, one end of the pull-down resistor Rpull, one end of the resistor Rg, the anode of the diode D _B1 , and the power supply terminal of the signal recognition circuit 11a.

The collector terminal is connected to the collector of the IGBT, the cathode of the Zener diode CGZD1, one end of the resistor R10, and one input terminal of the logic circuit 12a, and the anode of the Zener diode CGZD1 is connected to the anode of the Zener diode CGZD2. The other end of the resistor Rg is connected to one end of the resistor Rp1, one end of the resistor Rp2, the cathode of the Zener diode CGZD2, the anode of the diode _DB2 , and the gate of the IGBT.

The other end of the resistor R10 is connected to the anode of a diode _{D_B3} , the cathode of which is connected to _the cathode of diode _{D_B1} , the cathode of diode _{D_B2} , the power supply terminal of the logic circuit 12a, and one end of a capacitor C2.

The output terminal of the signal recognition circuit 11a is connected to the input terminal of the inverter IN1 and the other input terminal of the logic circuit 12a. The output terminal of the inverter IN1 is connected to the gate of the pull-out MOS 11b, and the other end of the resistor Rp1 is connected to the drain of the pull-out MOS 11b. The output terminal of the logic circuit 12a is connected to the gate of the pull-out MOS 12b, and the other end of the resistor Rp2 is connected to the drain of the pull-out MOS 12b.

The emitter terminal is connected to the anode of the Zener diode GEZD, the other end of the pull-down resistor Rpull, the reference power supply terminal of the signal recognition circuit 11a, the source of the pull-down MOS 11b, the other end of the capacitor C2, the reference power supply terminal of the logic circuit 12a, the source of the pull-down MOS 12b, and the emitter of the IGBT.

<Sink capacity of the extraction circuit>
As described above, the steep switching operation of an IGBT with a conventional configuration when it is turned off generates resonant noise, so the igniter 10 of the present invention uses an IC 10a including extraction circuits 11 and 12 to extract the gate charge of the IGBT in two stages, thereby suppressing the generation of resonant noise.

Here, when the dI/dt (rate of change of current) during the drop in the collector current when the IGBT is off is equal to or greater than a predetermined value, an induced voltage is generated at the emitter of the IGBT, generating noise. Therefore, the extraction circuit 11, which has a first sink capacity, extracts gate charge from the gate of the IGBT at a first extraction speed at which dI/dt is less than a predetermined value (a change in extraction speed does not trigger noise generation). Furthermore, the extraction circuit 12, which has a second sink capacity, extracts gate charge at a second extraction speed at which the IGBT turns off within the IGBT's predetermined switching time (a change from the first extraction speed to the second extraction speed in this case is also a change in extraction speed that does not trigger resonant noise generation).

That is, during the first period of the first stage, the extraction circuit 11 gently extracts gate charge from the IGBT gate to slow the decline of the collector current Ice so that the collector current Ice has a dI/dt that does not trigger the generation of resonant noise. On the other hand, during the second period of the second stage, the extraction circuit 12 extracts gate charge more strongly than during the first period to maintain the specified switching time.

In this way, the gate charge is extracted during the first period by extraction circuit 11, which includes resistor Rp1 and extraction MOS 11b, and the gate charge is extracted during the second period by extraction circuit 12, which includes resistor Rp2 and extraction MOS 12b. The extraction operation is described in more detail below.

Let's assume that extraction MOS 11b and 12b are the same size. In this case, in extraction circuit 11, we want to extract gate charge so that the fall of collector current Ice during the first period is more gradual than in the conventional igniter 110 shown in Figure 13, so resistor Rp1 is set to a higher impedance (higher resistance value) than resistor Rp shown in Figure 13.

Furthermore, in the extraction circuit 12, it is desired to extract gate charge so that the fall of the collector current Ice during the second period is steeper than that of the igniter 110 of the conventional configuration shown in FIG. 13. Therefore, resistor Rp2 is set to a lower impedance (lower resistance value) than resistor Rp shown in FIG. 13. The relationship in magnitude between the resistance values of resistors Rp, Rp1, and Rp2 is Rp2<Rp<Rp1.

In this way, when the pull-out MOSs 11b and 12b are the same size, the resistor Rp1 in the pull-out circuit 11 has a high impedance relative to the resistor Rp, and the resistor Rp2 in the pull-out circuit 12 has a low impedance. This makes it possible to set the first sink capacity of the pull-out circuit 11 lower than the sink capacity of the igniter 110 of the conventional configuration, and the second sink capacity of the pull-out circuit 12 higher than the first sink capacity of the pull-out circuit 11.

On the other hand, a configuration is assumed in which resistors Rp1 and Rp2 are not provided. In this configuration in which resistors Rp1 and Rp2 are not provided, the drains of pull-out MOS 11b and pull-out MOS 12b are connected to the gates of the IGBTs.

In this case, the extraction circuit 11 is intended to extract gate charge so that the fall of the collector current Ice during the first period is more gradual than in the igniter 110 of the conventional configuration shown in FIG. 13. Therefore, the size of the extraction MOS 11b is set smaller than the size of the extraction MOS 13 shown in FIG. 13, and the on-resistance of the extraction MOS 11b is set larger than the on-resistance of the extraction MOS 13.

Furthermore, in the extraction circuit 12, it is desired to extract gate charge so that the fall of the collector current Ice during the second period is steeper than that of the igniter 110 of the conventional configuration shown in FIG. 13. Therefore, the size of extraction MOS 12b is set larger than the size of extraction MOS 13, and the on-resistance of extraction MOS 12b is set smaller than the on-resistance of extraction MOS 13. The size relationship between extraction MOS 13, 11b, and 12b is (size of extraction MOS 11b) < (size of extraction MOS 13) < (size of extraction MOS 12b).

In this way, when resistors Rp1 and Rp2 are not provided (or resistors Rp1 and Rp2 may have the same resistance value), the size of pull-out MOSFET 11b is made smaller and the size of pull-out MOSFET 12b is made larger relative to the size of pull-out MOSFET 13. This makes it possible to set the first sink capacity of pull-out circuit 11 lower than the sink capacity of the igniter 110 in a conventional configuration, and the second sink capacity of pull-out circuit 12 higher than the first sink capacity of pull-out circuit 11.

As described above, by adjusting the resistance values of resistors Rp1 and Rp2 or adjusting the sizes of pull-out MOSs 11b and 12b, the sink capabilities of both pull-out circuits 11 and 12 can be flexibly adjusted.

<Configuration and operation of logic circuit>
6 is a diagram showing an example of the configuration of a logic circuit 12a. The logic circuit 12a includes a logic element group 12a-1 including a two-input, one-output AND element ad and an inverter in0, a comparator cmp, resistors R0, R1, and R2, a diode D0, and a reference power supply unit Vref.

One end of resistor R0 is connected to the collector terminal, and the other end of resistor R0 is connected to one end of resistor R1 and the cathode of diode D0. The non-inverting input terminal of comparator cmp is connected to the other end of resistor R1 and one end of resistor R2 and receives voltage _VD , while the inverting input terminal of comparator cmp is connected to the positive power supply terminal of reference power supply Vref and receives a predetermined voltage _VR . The anode of diode D0 is connected to the other end of resistor R2, the negative power supply terminal of reference power supply Vref, and the emitter terminal.

The input terminal of inverter in0 is connected to the output terminal of signal recognition circuit 11a, and voltage V1 is input. The output terminal of inverter in0 is connected to one input terminal of AND element ad.

The output terminal of the comparator cmp is connected to the other input terminal of the AND element ad, and the output terminal of the AND element ad is connected to the gate of the extraction MOS 12b, from which voltage Mg2 is output. The power supply for each component element in the logic circuit 12a (AND element ad, inverter in0, comparator cmp) is supplied with voltage Vs, as shown in Figure 5.

As described above, the comparator cmp compares the voltage _VD of the resistor-divided voltage between the collector terminal and the emitter terminal with the predetermined voltage _VR output by the reference power supply unit Vref. Then, the voltage Mg2, which is the output signal of the logic element group 12a-1 determined based on the logic of the output of the comparator cmp and the output (voltage V1) of the signal recognition circuit 11a, is input to the gate of the extraction MOS 12b.

Figure 7 shows the operating logic of the logic circuit. In logic table 5, when the output voltage of comparator cmp is low and the output voltage V1 of signal recognition circuit 11a (corresponding to the level indicating the on/off state of the signal from ECU 4) is low, the output of AND element ad (output voltage Mg2 of logic circuit 12a) becomes low, and pull-out MOS 12b turns off. Also, when the output voltage of comparator cmp is low and the output voltage V1 of signal recognition circuit 11a is high, the output voltage Mg2 of logic circuit 12a becomes low, and pull-out MOS 12b turns off.

When the output voltage of the comparator cmp is H level and the output voltage V1 of the signal recognition circuit 11a is L level, the output voltage Mg2 of the logic circuit 12a becomes H level and the pull-out MOS 12b turns on (at this time, gate charge is pulled out). Also, when the output voltage of the comparator cmp is H level and the output voltage V1 of the signal recognition circuit 11a is H level, the output voltage Mg2 of the logic circuit 12a becomes L level and the pull-out MOS 12b turns off.

<Power supply voltage for logic circuits>
8 is a diagram for explaining the generation of the power supply voltage supplied to the logic circuit. The voltage Vs is maintained at a constant potential regardless of whether the IGBT is on or off and is supplied to the logic circuit 12a. The igniter 10 is configured to maintain the voltage Vs from a point that becomes a high potential even in states st1, st2, and st3, thereby providing a stable power supply to the logic circuit 12a. The fact that the voltage Vs is maintained at a constant value will be explained below.

[State st1] This is the case when the signal potential Vg of the gate terminal is OFF. At this time, the gate terminal voltage Vg and the gate voltage Vge are approximately equal to 0 V (Vg ≒ Vge ≒ 0 V). Meanwhile, the collector terminal voltage Vc (collector terminal voltage) is approximately equal to the battery voltage Vb (Vc ≒ Vb). Therefore, a predetermined voltage Vs (a voltage that allows the logic circuit 12a to operate normally) is generated and secured via resistor R10 and diode _DB3 and supplied to the logic circuit 12a.

[State st2] This is the case when the signal potential Vg of the gate terminal is ON. At this time, an H-level signal is input from the ECU 4, so the gate terminal voltage Vg is 5 V, and the gate voltage Vge is a potential within the range of 0 V to the gate terminal voltage Vg (Vg ≈ 5 V, 0 V << Vge < Vg). Furthermore, since the IGBT is ON, the collector terminal voltage Vc is the collector-emitter saturation voltage Vcesat in the ON state, which drops to, for example, 1 V (Vc = Vcesat ≈ 1 V). Therefore, a predetermined voltage Vs is generated and maintained via the diode D _B1 and supplied to the logic circuit 12a.

[State st3] This is the state immediately after the gate terminal signal potential Vg transitions from on to off (when the IGBT begins to turn off). At this time, the signal potential from the ECU 4 is in an off state, but the IGBT is still maintained in an on state. That is, the gate terminal voltage Vg is decreasing, but the gate voltage Vge has not yet decreased completely, and the IGBT is on. Therefore, the gate terminal voltage Vg is smaller than or equal to the gate voltage Vge, and the collector terminal voltage Vc is equal to the collector-emitter saturation voltage Vcesat (Vg≦Vge, Vc=Vcesat). Therefore, a predetermined voltage Vs is generated and maintained via diode _DB2 and supplied to the logic circuit 12a.

As described above, the power supply voltage for the logic circuit 12a is supplied from the gate terminal side ₍ gate terminal voltage Vg), gate voltage Vge side, and collector terminal side (collector terminal voltage Vc) via the backflow prevention diodes D _B1 , D B2 , and _{D B3} , respectively.

As a result, regardless of the switching operation of the IGBTs in the igniter 10, a stable voltage Vs can be ensured and supplied to the logic circuit 12a, ensuring operation of the logic circuit 12a. Note that a capacitor C2 is connected in close proximity to the logic circuit 12a to reduce transient fluctuations in the voltage Vs, but in case the voltage Vs rises too much, a protective diode may be added in parallel with the capacitor C2.

<Igniter operation>
9 is a time chart showing the operation of the igniter. In the following description, it is assumed that the sizes of the pull-out MOSFETs 11b and 12b are adjusted to provide different sink capabilities.

[Period from time t0 to time t1] The IGBT off signal from the ECU 4 is recognized by the signal recognition circuit 11a, which then inputs a high-level voltage Mg1 to the gate of the pull-out MOS 11b. The pull-out MOS 11b then turns on and pulls out the gate charge from the IGBT gate. Note that because the first sink capability of the pull-out MOS 11b is reduced compared to the sink capability of the pull-out MOS 13 in the conventional configuration, the period (period from time t0 to time t1) until the gate voltage Vge reaches the mirror voltage is extended accordingly.

[Period from time t1 to time t2] The period from time t1 to time t2, which corresponds to the mirror region, is extended by the amount that the first sink capability of pull-out MOS 11b is lower than the sink capability of pull-out MOS 13. Also, the dV/dt of the rise in collector voltage Vce is gentler than in Figure 14.

[Period from time t2 to time ta] The mirror region ends and the collector current Ice begins to fall, but because the first sink capability of pull-out MOS 11b is lower than that of pull-out MOS 13 shown in Figure 13, dI/dt changes more gradually than in Figure 14. Also, the collector voltage Vce begins to rise more rapidly from time t2, but dV/dt is gradually suppressed by the amount that the first sink capability of pull-out MOS 11b is reduced.

[Period from time ta to time t3] In the logic circuit 12a, the collector voltage Vce is divided by resistors, and the rise in the collector voltage _Vce is detected through the divided voltage VD. Furthermore, since the divided voltage _VD is a voltage obtained by dividing the collector voltage Vce by resistors, it behaves in the same way as the change in the collector voltage Vce over time. That is, Vce = {(R0 + R1 + R2) / R2} x _VD .

In the logic circuit 12a, when the divided voltage _VD exceeds a predetermined voltage _VR , the output of the comparator cmp is inverted from L level to H level, and the output voltage Mg2 of the logic circuit 12a changes from L level to H level. At this timing (time ta), the extraction MOS 12b is turned on and starts extracting the gate charge from the IGBT.

On the other hand, the second sink capability of the pull-out MOSFET 12b is set higher than the first sink capability of the pull-out MOSFET 11b. Therefore, the collector voltage Vce rises sharply at a dV/dt greater than the dV/dt during the gradual rise from time t2 to time ta, with the transition point p1 as the boundary. Vcep1, which is the collector voltage Vce at this transition point p1, is a value determined by the resistor division ratio of the logic circuit 12a with respect to a predetermined voltage _VR , as described above. That is, in the case of the logic circuit 12a of FIG. 6, Vcep1 = {(R0 + R1 + R2) / R2} × _VR . Ideally, Vcep1 is a voltage value lower than the battery voltage Vb, but it may be set to adjust the operation timing of the pull-out MOSFET 12b and the cut-off time of the collector current. In this case, Vcep1 may be higher than the battery voltage Vb.

Furthermore, the collector current Ice drops sharply from change point p2 with a larger dI/dt than the dI/dt during the gradual drop from time t2 to time ta. However, the drop in collector current Ice at this time is not as large as the dI/dt immediately after the mirror region as shown in Figure 14, so resonant noise caused by the steep dI/dt can be suppressed.

In the logic circuit 12a, clamp control is performed by the diode D0. Without such clamp control, the divided voltage _VD may rise to the voltage division ratio of the collector voltage Vce, as shown by the dotted line waveform A0 in FIG. 9, and may exceed the upper input limit level of the comparator cmp.

For this reason, the logic circuit 12a is provided with a clamping diode D0 to protect the input of the comparator cmp. The clamp voltage _VCL is calculated as the breakdown voltage of the diode D0×R2/(R1+R2).

[Period from time t3 to time t4] When the Zener diode group CGZD breaks down, charge is supplied from the collector terminal to the gate voltage Vge, slowing the rate at which the gate voltage Vge falls. As the rate at which the gate voltage Vge falls slows, the rate at which the collector current Ice falls also slows, and the collector current Ice continues to fall until the energy stored in the coil of the load connected to the collector terminal is released.

[Period from time t4 to time tb] Charge supply from the collector terminal ceases, accelerating the decline of gate voltage Vge. As mentioned above, voltage Vs can be maintained as the internal circuit power supply, so extraction MOS 12b is in a driven state and the rise in gate voltage Vge is suppressed. This prevents the IGBT from turning on again even if external noise, such as discharge noise from spark plug 3, occurs.

[Period from time tb to time t5] The collector voltage Vce stops decreasing and becomes constant, the gate terminal voltage Vg and the gate voltage Vge become 0 V, and the IGBT is completely shut off.
Here, when the signal from the ECU 4 is off, the signal recognition circuit 11a does not operate. In such a case, if the gate voltage of the IGBT is only pulled down by the pull-down resistor Rpull, the gate voltage Vge may rise momentarily due to noise or a surge, causing the IGBT to malfunction and turn on again.

Therefore, in order to prevent such re-on of the IGBT, the collector voltage Vce=Vcep1 when the divided voltage _VD in the logic circuit 12a becomes a predetermined voltage _VR is set to be lower than the battery voltage Vb, which is the voltage of the external power supply. As a result, even if the signal recognition circuit 11a does not operate and the extraction MOS 11b is off when the signal is off, the extraction MOS 12b can be turned on and operated, so that the IGBT can be reliably turned off and the IGBT can be prevented from being re-on due to noise or surges.

If the predetermined voltage V _R is set to a value higher than the battery voltage Vb, the pull-out MOS 12 b operates only at a high collector terminal voltage when the L load of the ignition coil 2 is off. In this case, the effect of preventing re-on may be reduced, but it is possible to vary the position of the change point of the collector current Ice (change point p2 at time ta shown in FIG. 9 ).

<Comparison of the present invention and the prior art>
Figure 10 is a diagram comparing waveforms of the operation of the present invention and the operation of the conventional technique. The dotted waveforms are the conventional operation waveforms shown in Figure 14, and the solid waveforms are the operation waveforms of the present invention shown in Figure 9. In the conventional operation waveforms, during period T11, the collector current Ice drops sharply as the gate terminal voltage Vg drops.

On the other hand, in the operating waveforms of the present invention, during the first half of period T11a, the gate charge is extracted by the extraction circuit 11, which has low sink capacity, so the gate voltage Vge falls slowly, the mirror region is longer, and the collector current Ice also falls slowly, suppressing the generation of resonant noise.

In addition, in the latter half of period T11a, the gate charge is extracted by the extraction circuit 12, which has high sink capacity, with a strength that is not enough to trigger the generation of resonant noise, so the gate voltage Vge drops sharply and the collector current Ice also drops sharply.

Because periods T11 and T11a have the same switching time interval, the present invention achieves two-stage gate charge extraction while suppressing the generation of resonance noise and maintaining the switching time.

<Modification of Igniter>
5, a resistor R10, which is a high-impedance resistive element, is connected between the collector terminal and the backflow prevention diode D _B3 . By connecting such a high-resistance resistor R10, it is possible to prevent a large current from flowing into the igniter 10 even if the collector terminal voltage rises for some reason. Alternatively, a depletion-type power semiconductor switch can be used instead of the high-resistance resistor R10.

Figure 11 shows a modified igniter. Igniter 10-1 uses a dep-IGBT 14, a depletion-type power semiconductor switch, instead of resistor R10.

The collector of the dep-IGBT 14 is connected to the collector terminal, the cathode of the Zener diode CGZD1, and one input terminal of the logic circuit 12a. The gate of the dep-IGBT 14 is connected to the emitter of the dep-IGBT 14 and the anode of the diode D _B3 . The other configurations are the same as those in FIG. 5.

The dep-IGBT 14 is a depression-type IGBT with a breakdown voltage roughly equal to that of the main IGBT in the igniter 10. It has a high pinch-off voltage that is higher than the battery voltage Vb by shorting the gate and emitter, and can function similarly to the high-resistance resistor R10.

<Modification of logic circuit>
Fig. 12 is a diagram showing a modification of the logic circuit. In Fig. 6, the resistor R0 to which the collector voltage is supplied from one end is a high-impedance resistive element, but in the logic circuit 12a1, a dep-IGBT 15, which is a depletion-type power semiconductor switch, is used instead of the resistor R0 with a high resistance value, as in Fig. 11.

As described above, according to the present invention, when a command to turn off the semiconductor switch is detected, the first extraction circuit extracts gate charge from the gate of the semiconductor switch with a first sink capacity, and when the voltage generated from the collector voltage of the semiconductor switch is equal to or higher than a predetermined voltage, the second extraction circuit extracts gate charge with a second sink capacity higher than the first sink capacity.

This configuration prevents noise generation and enables stable device operation. Furthermore, in the two-stage gate charge extraction, the storage time delay caused by reducing the sink capacity of the first extraction circuit is eliminated by extracting the gate charge using the second extraction circuit, which has a higher sink capacity, thereby shortening the fall time and eliminating the delay. This allows the IGBT to be turned off within the desired switching time, thereby suppressing switching losses.

Furthermore, even if the operation of the first extraction circuit stops when the signal from the ECU is turned off, the second extraction circuit continues to operate, making it possible to prevent the IGBT from being erroneously turned back on due to external noise.

The above are examples of embodiments, but the configuration of each part shown in the embodiments can be replaced with other parts that have similar functions. Any other components or processes may also be added. Furthermore, any two or more of the configurations (features) of the above-mentioned embodiments may be combined.

1 Semiconductor device 1a Semiconductor switch 1b Control circuit 1b1 Extraction circuit (first extraction circuit)
1b2 Extraction circuit (second extraction circuit)
ct: signal that commands the semiconductor switch to be on or off; Ice: collector current; t11: time required for the gate charge to be drawn by the first sink capacity; t12: time required for the gate charge to be drawn by the second sink capacity; ts: switching time;

Claims (14)

A semiconductor switch;
a control circuit including: a first extraction circuit that extracts gate charge from the gate of the semiconductor switch with a first sink capacity when an instruction to turn off the semiconductor switch is detected; and a second extraction circuit that extracts the gate charge with a second sink capacity higher than the first sink capacity when a voltage generated from a collector voltage of the semiconductor switch is equal to or higher than a predetermined voltage, and that is driven by a voltage of a signal that instructs the semiconductor switch to be turned on or off;
A semiconductor device having: When the rate of change of the collector current falling when the semiconductor switch is turned off is equal to or greater than a predetermined value, an induced voltage is generated in the semiconductor switch, causing noise.
the first extraction circuit having the first sink capability extracts the gate charge at a first extraction speed at which the current change rate is less than the predetermined value;
the second extraction circuit having the second sink capability extracts the gate charge at a second extraction rate at which the semiconductor switch is turned off within a predetermined switching time of the semiconductor switch;
The semiconductor device according to claim 1. the first extraction circuit includes a detection circuit that detects whether the signal is on or off, a first resistance element, and a first extraction transistor, one end of the first resistance element is connected to the gate of the semiconductor switch, the other end of the first resistance element is connected to the drain of the first extraction transistor, a first drive signal from the detection circuit is input to the gate of the first extraction transistor, and a source of the first extraction transistor is connected to the emitter of the semiconductor switch and a reference power supply;
the second pull-out circuit includes a logic circuit that compares a voltage generated from the collector voltage with the predetermined voltage when the signal is off, a second resistance element, and a second pull-out transistor, one end of the second resistance element is connected to the gate of the semiconductor switch, the other end of the second resistance element is connected to the drain of the second pull-out transistor, a second drive signal from the logic circuit is input to the gate of the second pull-out transistor, and a source of the second pull-out transistor is connected to the emitter of the semiconductor switch and the reference power supply.
The semiconductor device according to claim 1. a size of the first pull-out transistor and a size of the second pull-out transistor are made the same, an impedance of the second resistive element is made lower than an impedance of the first resistive element, and the second sink capability is set higher than the first sink capability;
4. The semiconductor device according to claim 3. a resistance value of the first resistance element and a resistance value of the second resistance element are set to be the same, and a size of the second pull-out transistor is set to be larger than a size of the first pull-out transistor, so that the second sink capability is set to be higher than the first sink capability;
4. The semiconductor device according to claim 3. the first pull-out circuit includes a detection circuit that detects whether the signal is on or off, and a first pull-out transistor, the drain of the first pull-out transistor is connected to the gate of the semiconductor switch, a first drive signal from the detection circuit is input to the gate of the first pull-out transistor, and the source of the first pull-out transistor is connected to the emitter of the semiconductor switch and a reference power supply;
the second pull-out circuit includes a logic circuit that compares a voltage generated from the collector voltage with the predetermined voltage when the signal is off, and a second pull-out transistor, the drain of the second pull-out transistor is connected to the gate of the semiconductor switch, a second drive signal from the logic circuit is input to the gate of the second pull-out transistor, and the source of the second pull-out transistor is connected to the emitter of the semiconductor switch and the reference power supply,
a size of the second pull-out transistor is set larger than a size of the first pull-out transistor, and the second sink capability is set higher than the first sink capability;
The semiconductor device according to claim 1. the second extraction circuit includes a logic circuit that compares a voltage generated from the collector voltage with the predetermined voltage when the signal is off,
The power supply for the logic circuit is
When the input potential of the signal is off, a predetermined power supply voltage is supplied from the voltage of the collector terminal of the semiconductor switch,
When the input potential of the signal is on, a predetermined power supply voltage is supplied from the voltage of the signal,
When the input potential of the signal transitions from on to off, a predetermined power supply voltage is supplied from the gate voltage of the semiconductor switch.
The semiconductor device according to claim 1. The semiconductor device of claim 7, wherein a resistor is provided between the power supply input terminal of the logic circuit and the collector terminal to suppress current flowing through the logic circuit when the voltage of the collector terminal exceeds a predetermined value. The semiconductor device according to claim 8, wherein the resistor portion is a high-impedance resistor element or a depletion-type power semiconductor switch. The semiconductor device of claim 3 or 6, wherein the logic circuit comprises a group of resistors that generates a divided voltage of the collector voltage, a reference power supply unit, a comparator, and a group of logic elements that generate the second drive signal by taking the logic of the output result of the comparator and a level indicating the on/off state of the signal, and the collector voltage when the divided voltage becomes the predetermined voltage output by the reference power supply unit is set lower than the voltage of an external power supply that supplies the voltage to the collector terminal of the semiconductor switch. The semiconductor device of claim 10, wherein one of the resistors that generates a divided voltage of the collector voltage and has one end to which the collector voltage is supplied is a high-impedance resistor or a depletion-type power semiconductor switch. The semiconductor device of claim 1, wherein the semiconductor switch and the control circuit including the first pull-out circuit and the second pull-out circuit are integrated on the same chip. an igniter comprising: a semiconductor switch; a first extraction circuit that extracts gate charge from the gate of the semiconductor switch with a first sink capacity when an instruction to turn off the semiconductor switch is detected; and a second extraction circuit that extracts the gate charge with a second sink capacity higher than the first sink capacity when a voltage generated from a collector voltage of the semiconductor switch is equal to or higher than a predetermined voltage, the igniter being driven by a voltage of a signal that is output from an electronic control unit and instructs the semiconductor switch to be turned on or off;
an ignition coil connected to an external power source via a harness and amplifying the voltage generated by the semiconductor switch;
a spark plug that discharges based on the negative voltage output from the ignition coil;
a capacitor connected to a power supply and a ground in the system and to the emitter of the semiconductor switch via the harness;
An ignition system having: When the rate of change of the collector current falling when the semiconductor switch is turned off is equal to or greater than a predetermined value, an induced voltage is generated in the emitter of the semiconductor switch, and the induced voltage generates resonance noise due to the parasitic inductance of the harness and the capacitance of the capacitor.
the first extraction circuit having the first sink capability extracts the gate charge at a first extraction speed at which the current change rate is less than the predetermined value;
the second extraction circuit having the second sink capability extracts the gate charge at a second extraction rate at which the semiconductor switch is turned off within a predetermined switching time of the semiconductor switch;
14. The ignition system of claim 13.