JP7750658B2 - Semiconductor memory device and method for manufacturing the same - Google Patents

Description

This disclosure relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device.

CMOS (Complementary MOS) circuits, consisting of n-type field-effect transistors (nMOSFETs) and p-type field-effect transistors (pMOSFETs) mounted on the same substrate, are known for their low power consumption, high-speed operation, and ease of miniaturization and high integration.

For this reason, CMOS circuits are used in many LSI (Large Scale Integration) devices. In recent years, such LSI devices have been commercialized as SoCs (System on a Chip), which combine analog circuits, memory, logic circuits, and other components on a single chip.

Memory installed in LSI devices typically uses static random access memory (SRAM), for example. In recent years, in order to further reduce the cost and power consumption of LSI devices, the use of dynamic RAM (DRAM), magnetic RAM (MRAM), or ferroelectric RAM (FeRAM) instead of SRAM has been considered.

Here, FeRAM is a semiconductor memory device that stores information using the direction of remanent polarization of a ferroelectric. One example of an FeRAM structure is one in which a ferroelectric capacitor is formed inside a contact hole under wiring or a damascene structure (see, for example, Patent Document 1).

Japanese Patent Application Laid-Open No. 2001-7304

In such FeRAMs, it is desirable to obtain sufficient operating margins by further increasing the capacitance of the ferroelectric capacitor. Specifically, in order to increase the capacitance of the ferroelectric capacitor, a ferroelectric capacitor structure that allows for a larger area and a method for forming the ferroelectric capacitor are desired.

Therefore, it is desirable to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can provide sufficient margin for operation.

A semiconductor memory device according to one embodiment of the present disclosure includes a field-effect transistor provided on a semiconductor substrate, an interlayer insulating film provided on the semiconductor substrate, a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field-effect transistor, a first wiring layer provided on the contact, a first insulating layer provided on the interlayer insulating film and burying the first wiring layer, an opening provided in the first insulating layer and the interlayer insulating film from above the first wiring layer, and a ferroelectric capacitor provided inside the opening and electrically connected to the source of the field-effect transistor.

A semiconductor memory device according to one embodiment of the present disclosure includes a field-effect transistor provided on a semiconductor substrate, an interlayer insulating film provided on the semiconductor substrate, an opening including a first opening formed in the interlayer insulating film and a second opening formed within the first opening and having a smaller diameter than the first opening, and a ferroelectric capacitor provided within the opening and electrically connected to the source of the field-effect transistor.

A semiconductor memory device according to one embodiment of the present disclosure includes a field-effect transistor provided on a semiconductor substrate, an interlayer insulating film provided on the semiconductor substrate, a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field-effect transistor, and a ferroelectric capacitor that is provided at least inside an opening that penetrates the interlayer insulating film at a different height from the contact and is electrically connected to the source of the field-effect transistor.

A method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure includes forming a field-effect transistor on a semiconductor substrate, forming an interlayer insulating film on the semiconductor substrate, forming a contact that penetrates the interlayer insulating film and electrically connects to the drain of the field-effect transistor, forming a first wiring layer on the contact, forming a first insulating layer on the interlayer insulating film that embeds the first wiring layer, forming an opening in the first insulating layer and the interlayer insulating film from above the first wiring layer, and forming a ferroelectric capacitor inside the opening that electrically connects to the source of the field-effect transistor.

A method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure includes forming a field-effect transistor on a semiconductor substrate, forming an interlayer insulating film on the semiconductor substrate, forming a first opening in the interlayer insulating film, forming a second opening within the first opening, the second opening having a smaller diameter than the first opening, and forming a ferroelectric capacitor electrically connected to the source of the field-effect transistor within an opening including the first opening and the second opening.

In accordance with a semiconductor memory device and a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure, the capacitor included in the semiconductor memory device is formed within the memory cell in a three-dimensional structure that allows for a larger area to be secured. This allows, for example, the semiconductor memory device to increase the area of the capacitor without increasing the area of the memory cell, thereby further increasing the capacitance of the capacitor.

FIG. 2 is a circuit diagram showing an equivalent circuit of the semiconductor memory device according to the first embodiment of the present disclosure. 2A and 2B are schematic diagrams showing a planar configuration and a cross-sectional configuration of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. FIG. 2 is a cross-sectional view schematically showing a cross section of the semiconductor memory device according to the same embodiment taken along an active region. 10A and 10B are schematic diagrams showing a planar configuration and a cross-sectional configuration of a semiconductor memory device according to a second embodiment of the present disclosure. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. FIG. 10 is a schematic diagram showing a cross-sectional configuration of a semiconductor memory device according to a third embodiment of the present disclosure. FIG. 2 is a schematic diagram showing a planar layout of the semiconductor memory device according to the same embodiment. 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. FIG. 10 is a schematic diagram showing a cross-sectional configuration of a semiconductor memory device according to a first modified example of the embodiment. 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. FIG. 10 is a schematic diagram showing a cross-sectional configuration of a semiconductor memory device according to a second modification of the embodiment. FIG. 10 is a schematic diagram showing a cross-sectional configuration of a semiconductor memory device according to a third modification of the embodiment. 10A and 10B are schematic diagrams showing a planar configuration and a cross-sectional configuration of a semiconductor memory device according to a fourth embodiment of the present disclosure. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. FIG. 2 is a cross-sectional view schematically showing a cross section of the semiconductor memory device according to the same embodiment taken along an active region. 10A and 10B are schematic diagrams showing a planar configuration and a cross-sectional configuration of a semiconductor memory device according to a fifth embodiment of the present disclosure. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 13A and 13B are schematic diagrams showing a planar configuration and a cross-sectional configuration of a semiconductor memory device according to a sixth embodiment of the present disclosure. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 13A and 13B are schematic diagrams showing a planar configuration and a cross-sectional configuration of a semiconductor memory device according to a seventh embodiment of the present disclosure. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment.

Embodiments of the present disclosure will be described in detail below with reference to the drawings. The embodiment described below is a specific example of the present disclosure, and the technology of the present disclosure is not limited to the following aspects. Furthermore, the arrangement, dimensions, dimensional ratios, etc. of each component of the present disclosure are not limited to the aspects shown in the drawings.

The explanation will be given in the following order.
1. First Embodiment 1.1. Overview 1.2. Configuration Example 1.3. Manufacturing Method 1.4. Operation Example 2. Second Embodiment 2.1. Configuration Example 2.2. Manufacturing Method 3. Third Embodiment 3.1. Configuration Example 3.2. Manufacturing Method 3.3. Modification 4. Fourth Embodiment 4.1. Configuration Example 4.2. Manufacturing Method 4.3. Operation Example 5. Fifth Embodiment 5.1. Configuration Example 5.2. Manufacturing Method 6. Sixth Embodiment 6.1. Configuration Example 6.2. Manufacturing Method 7. Seventh Embodiment 7.1. Configuration Example 7.2. Manufacturing Method

1. First embodiment
(1.1. Overview)
First, an overview of a semiconductor memory device according to a first embodiment of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an equivalent circuit of the semiconductor memory device according to this embodiment.

As shown in FIG. 1, the semiconductor memory device 10 according to this embodiment includes a capacitor 11 that stores information and a transistor 21 that controls the selection and deselection of the capacitor 11.

Capacitor 11 is a ferroelectric capacitor that includes a pair of electrodes and a ferroelectric film sandwiched between the pair of electrodes. Capacitor 11 can store one bit of information depending on the direction of remanent polarization of the ferroelectric film. Capacitor 11 is electrically connected to source line SL at one of the pair of electrodes, and electrically connected to the source of transistor 21 at the other of the pair of electrodes.

Transistor 21 is a field-effect transistor that controls the application of voltage to capacitor 11. Transistor 21 is electrically connected to the other electrode of capacitor 11 at its source and electrically connected to bit line BL at its drain. Transistor 21 is also electrically connected to word line WL at its gate, and the state of its channel can be controlled by the voltage applied from word line WL.

When writing information to capacitor 11, in the semiconductor memory device 10, a voltage is first applied to the word line WL, causing the channel of transistor 21 to transition to the ON state. Then, a potential is applied to each of the source line SL and bit line BL, applying an electric field corresponding to the information to be written to the ferroelectric film of capacitor 11. This allows the semiconductor memory device 10 to write information to capacitor 11 by controlling the direction of the remanent polarization of the ferroelectric film of capacitor 11 with an external electric field.

On the other hand, when reading information from capacitor 11, in the semiconductor memory device 10, a voltage is first applied to the word line WL, causing the channel of transistor 21 to transition to the ON state. Then, a predetermined potential is applied to each of the source line SL and bit line BL, causing the polarization direction of the ferroelectric film of capacitor 11 to transition to a predetermined direction. At this time, the magnitude of the current flowing into capacitor 11 during the transition changes depending on the polarization direction of the ferroelectric film before the transition. Therefore, the semiconductor memory device 10 can read the information stored in capacitor 11 by measuring the magnitude of the current flowing into capacitor 11.

Therefore, the semiconductor memory device 10 according to this embodiment can operate as an FeRAM (Ferroelectric Random Access Memory) that stores information in a capacitor 11 that includes a ferroelectric film.

In the semiconductor memory device 10 according to this embodiment, the capacitor 11 is provided inside a deeper opening. Specifically, in the semiconductor memory device 10, an opening is formed above the first wiring layer provided on the interlayer insulating film in which the transistor 21 is embedded, and the capacitor 11 is provided inside the opening. This allows the capacitance of the capacitor 11 to be increased, making it possible for the semiconductor memory device 10 to obtain a signal with sufficient margin for operation.

(1.2. Configuration example)
Next, a specific configuration example of the semiconductor memory device 10 according to this embodiment will be described with reference to Fig. 2. Fig. 2 is a schematic diagram showing the planar configuration and cross-sectional configuration of the semiconductor memory device 10 according to this embodiment.

In the plan view in the upper left of Figure 2, the planarization film 200 and first insulating layer 300, which are formed over the entire surface of the semiconductor substrate 100, are omitted to clarify the arrangement of each component. Each cross-sectional view in Figure 2 shows a cross section taken along line A-A, line B-B, or line C-C, respectively, shown in the plan view in the upper left.

Furthermore, in the following, "first conductivity type" refers to either "p-type" or "n-type", and "second conductivity type" refers to the other of "p-type" or "n-type" that is different from the "first conductivity type".

As shown in FIG. 2, the semiconductor memory device 10 is provided on a semiconductor substrate 100. The semiconductor memory device 10 is a semiconductor memory capable of storing large amounts of information by arranging a large number of memory cells on the semiconductor substrate 100.

The capacitor 11 is provided inside an opening 110 formed above the source or drain region 151, penetrating the planarization film 200 and the first insulating layer 300. Specifically, the capacitor 11 includes a lower electrode 111 provided along the inside of the opening 110, a ferroelectric film 113 provided on the lower electrode 111 along the opening 110, and an upper electrode 115 provided on the ferroelectric film 113 so as to fill the opening 110. The lower electrode 111 is electrically connected to the source or drain region 151 (e.g., the source) of the transistor 21, and the upper electrode 115 is electrically connected to a second wiring layer (not shown) that functions as a source line SL.

The transistor 21 includes a gate insulating film 140 provided on the semiconductor substrate 100, a gate electrode 130 provided on the gate insulating film 140, and a source or drain region 151 provided in an active region 150 of the semiconductor substrate 100. One of the source or drain regions 151 (e.g., the source) is connected to the lower electrode 111 and thereby electrically connected to the capacitor 11, and the other of the source or drain region 151 (e.g., the drain) is electrically connected via a contact 210 to a first wiring layer 310 that functions as a bit line BL. The gate electrode 130 is provided across multiple active regions 150, straddling the element isolation layer 105, and functions as a word line WL.

In the semiconductor memory device 10, the first wiring layer 310 is provided extending in a first direction within the plane of the semiconductor substrate 100, and the gate electrode 130 is provided extending in a second direction perpendicular to the first direction. The active region 150 is provided extending in a strip-like shape in a third direction obliquely intersecting both the first and second directions. This allows the semiconductor memory device 10 to efficiently arrange the capacitors 11 and transistors 21, thereby preventing an increase in the area occupied by the semiconductor memory device 10.

Here, an example of a structure in which a capacitor is constructed by embedding a dielectric and an electrode in an opening provided in the planarization film 200 or the semiconductor substrate 100, etc., is a stacked cylindrical DRAM (Dynamic Random Access Memory). However, in a DRAM that stores information using electric charge accumulated in a capacitor, a capacitor capacitance of approximately 20 fF is required, for example, compared to a bit line capacitance of 100 fF, in order to read the stored information with sufficient accuracy.

For example, if the dielectric constant of the dielectric used in a capacitor is 25, and the width of the dielectric film is 60 nm and the film thickness is 5 nm, the depth of the opening to form a capacitor with a capacitance of 20 fF would be approximately 8 μm. An opening of this depth is extremely difficult to process, making it difficult to miniaturize and increase the integration density of DRAM.

The semiconductor memory device 10 according to this embodiment functions as an FeRAM that stores information using the remnant polarization of a ferroelectric material. Because the operating principle of an FeRAM differs from that of a DRAM, even if the bit line capacitance is 100 fF, if the remnant polarization of the ferroelectric material is approximately 25 μC/ ^cm² , information can be read with sufficient accuracy by forming a capacitor 11 in an opening approximately 200 nm deep. Therefore, the semiconductor memory device 10 according to this embodiment can be more easily miniaturized and highly integrated.

The following describes each component of the semiconductor memory device 10 in more detail.

The semiconductor substrate 100 is made of a semiconductor material and is a substrate on which the capacitor 11 and the transistor 21 are formed. The semiconductor substrate 100 may be a silicon substrate, or may be an SOI (Silicon On Insulator) substrate in which an insulating film such as _SiO2 is sandwiched between a silicon substrate. The semiconductor substrate 100 may also be a substrate formed of other elemental semiconductors such as germanium, or may be a substrate formed of a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC).

The element isolation layer 105 is made of an insulating material and electrically isolates each of the transistors 21 provided on the semiconductor substrate 100 from one another. The element isolation layers 105 are provided in strip-shaped regions that are spaced apart from one another and extend in a third direction (e.g., from the upper left to the lower right when viewed from the front of FIG. 2). The third direction is a direction that intersects obliquely with both the first direction in which the first wiring layer 310 extends (e.g., the horizontal direction when viewed from the front of FIG. 2) and the second direction in which the gate electrode 130 extends (e.g., the vertical direction when viewed from the front of FIG. 2). For example, the element isolation layer 105 may be made of an insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON).

For example, the element isolation layer 105 can be formed by using an STI (Shallow Trench Isolation) method to remove a portion of the semiconductor substrate 100 in a predetermined region by etching or the like, and then filling the opening formed by etching or the like with silicon oxide (SiO _x ). Alternatively, the element isolation layer 105 may be formed by thermally oxidizing the semiconductor substrate 100 in a predetermined region by a LOCOS (Local Oxidation of Silicon) method.

The strip-shaped regions separated from each other by the element isolation layer 105 function as active regions 150 in which the transistors 21 are provided. A first conductivity type impurity (e.g., a p-type impurity such as boron (B) or aluminum (Al)) is introduced into the active region 150.

As shown in FIG. 2, the element isolation layer 105 and the active region 150 can be provided in a strip shape extending in the third direction. This allows the semiconductor memory device 10 to efficiently arrange the capacitors 11 and transistors 21, thereby preventing an increase in the area occupied by the semiconductor memory device 10.

The gate insulating film 140 is made of an insulating material and is provided on the active region 150 of the semiconductor substrate 100. The gate insulating film 140 may be made of an insulating material known as a gate insulating film for a field effect transistor. For example, the gate insulating film 140 may be made of an oxide such as silicon oxide (SiO _x ).

The gate electrode 130 is made of a conductive material and is provided on the gate insulating film 140. Specifically, multiple gate electrodes 130 are provided at predetermined intervals in a second direction perpendicular to the first direction in which the first wiring layer 310 extends, and extend in the first direction obliquely intersecting the third direction in which the element isolation layer 105 extends. The gate electrodes 130 are provided extending beyond the element isolation layer 105 into multiple active regions 150, and function as word lines WL that electrically connect the gates of the transistors 21 of each memory cell.

For example, the gate electrode 130 may be formed of polysilicon or the like, or may be formed of a metal, alloy, metal compound, or alloy of a metal (such as Ni) and polysilicon (so-called silicide). Specifically, the gate electrode 130 may be formed of a laminated structure consisting of a metal layer made of TiN or TaN and a polysilicon layer provided on the gate insulating film 140. Such a laminated structure allows the gate electrode 130 to have lower wiring resistance than when it is formed of only a polysilicon layer.

The source or drain region 151 is a second conductivity type region formed in the semiconductor substrate 100. Specifically, the source or drain region 151 is provided in the active region 150 extending in the third direction, sandwiching the gate electrode 130. The source side of the source or drain region 151 is electrically connected to the lower electrode 111, and the drain side of the source or drain region 151 is electrically connected to the first wiring layer 310, which is the bit line BL, via the contact 210.

For example, the source or drain region 151 can be formed by introducing second conductivity type impurities (e.g., n-type impurities such as phosphorus (P) or arsenic (As)) into the semiconductor substrate 100 in the active region 150. Note that an LDD (Lightly Doped Drain) region having a lower concentration of second conductivity type impurities than the source or drain region 151 may be formed in the semiconductor substrate 100 between the source or drain region 151 and the gate electrode 130.

The sidewall insulating film 132 is made of an insulating material and is provided as a sidewall on the side surface of the gate electrode 130. The sidewall insulating film 132 can be formed by uniformly depositing an insulating film in a region including the gate electrode 130 and then vertically anisotropically etching the insulating film. For example, the sidewall insulating film 132 may be formed in a single layer or multiple layers using an insulating oxynitride such as silicon oxide (SiO _x ), silicon nitride (SiN _x ), or silicon oxynitride (SiON).

The sidewall insulating film 132 shields the second-conductivity-type impurities when they are introduced into the semiconductor substrate 100, thereby enabling self-aligned control of the positional relationship between the gate electrode 130 and the source or drain region 151. Furthermore, because the sidewall insulating film 132 can gradually control the introduction of the second-conductivity-type impurities into the semiconductor substrate 100, it is also possible to form the above-mentioned LDD region between the source or drain region 151 and the gate electrode 130 in a self-aligned manner.

The cap layer 131 is provided on the gate electrode 130 and functions as a word line WL that electrically connects the gate electrodes 130 of each memory cell. For example, the cap layer 131 may be formed of a metal or a metal compound. Furthermore, as described above in the description of the gate electrode 130, the cap layer 131 may be formed of a metal, alloy, metal compound, or alloy of a metal (such as Ni) and polysilicon (so-called silicide) provided on polysilicon. That is, the gate electrode 130 and cap layer 131 may be formed of a metal layer made of TiN or TaN provided on the gate insulating film 140, a polysilicon layer (gate electrode 130), and a metal layer made of TiN or TaN (cap layer 131). Such a layered structure allows the semiconductor memory device 10 to further reduce wiring resistance.

The contact region 152 is provided on the surface of the semiconductor substrate 100 in the source or drain region 151, and can reduce the contact resistance between the source or drain region 151 and the lower electrode 111 or the contact 210. Specifically, the contact region 152 may be composed of an alloy of silicon (so-called silicide) and a metal such as Ni.

The planarization film 200 is made of an insulating material, burying the transistor 21 and spreading over the entire surface of the semiconductor substrate 100. For example, the planarization film 200 may be made of an insulating oxynitride such as silicon oxide (SiO _x ), silicon nitride (SiN _x ), or silicon oxynitride (SiON).

Although not shown in FIG. 2 , a liner layer made of an insulating material may be provided over the entire surfaces of the semiconductor substrate 100, the sidewall insulating film 132, and the cap layer 131. The liner layer can provide a high etching selectivity between the liner layer and the planarization film 200 in the process of forming an opening in the planarization film 200 for providing the capacitor 11 or the contact 210. This allows the liner layer to prevent etching from progressing to the semiconductor substrate 100 in the etching process. The liner layer may be made of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). For example, when the planarization film 200 is made of silicon oxide (SiOx), the liner layer may be made of silicon nitride (SiNx).

The liner layer may also be configured as a layer that applies compressive or tensile stress to the semiconductor substrate 100 below the gate insulating film 140. In such a case, the liner layer can control the carrier mobility of the channel formed in the semiconductor substrate 100 through its stress effect.

The opening 110 is provided from above the first wiring layer 310, penetrating the planarization film 200 and the first insulating layer 300 so as to expose the source or drain region 151. By providing the opening 110 from a higher layer, the semiconductor memory device 10 can further increase the area of the cylindrical capacitor 11 provided inside the opening 110. Therefore, the semiconductor memory device 10 can further increase the capacitance of the capacitor 11 provided inside the opening 110.

The lower electrode 111 is made of a conductive material and is provided along the inside of an opening 110 formed in the planarization film 200 and the first insulating layer 300. Specifically, the opening 110 is provided to expose one of the source or drain regions 151, and the lower electrode 111 is provided on one of the source or drain regions 151 exposed by the opening 110. This allows the lower electrode 111 to be electrically connected to the source side of the source or drain region 151. The lower electrode 111 is also recessed from the opening surface of the opening 110 provided in the first insulating layer 300. This prevents the lower electrode 111 from shorting out with the upper electrode 115, etc.

For example, the lower electrode 111 may be composed of a metal such as titanium (Ti) or tungsten (W), or a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN). The lower electrode 111 may also be composed of ruthenium (Ru) or ruthenium oxide (RuO2). The lower electrode 111 can be formed using techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or sputtering using ionized metal plasma (IMP).

The ferroelectric film 113 is made of a ferroelectric material and is provided on the lower electrode 111 along the inside of the opening 110 provided in the planarization film 200 and the first insulating layer 300. The ferroelectric film 113 is formed of a ferroelectric material that is spontaneously polarized and whose remanent polarization direction can be controlled by an external electric field.

For example, the ferroelectric film 113 may be formed of a ferroelectric material with a perevskite structure, such as lead zirconate titanate (Pb( _Zr , _Ti ) _O3 : _PZT ) or strontium _tantalate bismuthate ( _SrBi2Ta2O9 :SBT). The ferroelectric film 113 may also be a ferroelectric film obtained by altering a film made of a high-dielectric material, such as HfOx, ZrOx, or _HfZrOx , through heat treatment or the like, or may be a ferroelectric film obtained by altering a film made of the above-mentioned high-dielectric material by introducing atoms, such as lanthanum (La), silicon (Si), or gadolinium (Gd). Furthermore, the ferroelectric film 113 may be formed of a single layer or multiple layers. For example, the ferroelectric film 113 may be a single-layer film made of a ferroelectric material, such as _HfOx . The ferroelectric film 113 can be formed by using ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), or the like.

The upper electrode 115 is made of a conductive material and is provided on the ferroelectric film 113 so as to fill the openings 110 provided in the planarization film 200 and the first insulating layer 300. For example, the upper electrode 115 may be made of a metal such as titanium (Ti) or tungsten (W), or may be made of a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN). The upper electrode 115 may also be made of ruthenium (Ru) or ruthenium oxide (RuO ₂ ). The upper electrode 115 can be formed by using atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like.

The capacitor 11 is constructed by sandwiching the above-mentioned ferroelectric film 113 between a lower electrode 111 and an upper electrode 115. This allows the semiconductor memory device 10 to store information based on the polarization direction of the ferroelectric film 113 of the capacitor 11.

The contact 210 is made of a conductive material and is provided so as to penetrate the planarization film 200. Specifically, the contact 210 is provided on the other of the source or drain regions 151, and electrically connects the drain side of the source or drain region 151 to the first wiring layer 310, which is the bit line BL.

For example, the contact 210 may be composed of a metal such as titanium (Ti) or tungsten (W), or may be composed of a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN). The contact 210 may be formed as a single layer, or as a multi-layer stack. For example, the contact 210 may be formed as a stack of Ti or TiN and W.

The first wiring layer 310 is made of a conductive material and is provided on the planarization film 200. Specifically, the first wiring layer 310 is provided on the contact 210 as wiring extending in a first direction perpendicular to the second direction in which the gate electrode 130 (word line WL) extends. The first wiring layer 310 functions as a bit line BL by electrically connecting to the drain side of the source or drain region 151 via the contact 210. The first wiring layer 310 may be made of a metal material such as aluminum (Al), or may be configured with a copper (Cu) damascene structure or dual damascene structure.

The first insulating layer 300 buries the first wiring layer 310 and is provided on the planarization film 200, spreading over the entire surface of the semiconductor substrate 100. The first insulating layer 300 may be formed of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON).

The via contact 311 is made of a conductive material and is provided on the first wiring layer 310. Specifically, the via contact 311 penetrates the first insulating layer 300 and electrically connects the lower first wiring layer 310 with the upper wiring layer 312. The via contact 311 may be made of a metal material such as aluminum (Al), or may be constructed using a copper (Cu) damascene structure.

The upper wiring layer 312 is made of a conductive material and is provided on the via contact 311. The upper wiring layer 312 may be made of a metal material such as aluminum (Al), or may have a copper (Cu) damascene structure. The upper wiring layer 312 may be formed simultaneously with or shared with wiring for other circuits provided in the logic region or the like.

The upper electrode 115 of the capacitor 11 is electrically connected to a second wiring layer (not shown). The second wiring layer is made of a conductive material and is provided above the first insulating layer 300 and the upper wiring layer 312. Specifically, the second wiring layer is provided on the upper electrode 115 of the capacitor 11 as a wiring extending in the first direction, similar to the first wiring layer 310. The second wiring layer functions as a source line SL by being electrically connected to the upper electrode 115. The second wiring layer may be made of a metal material such as aluminum (Al), or may be configured with a copper (Cu) damascene structure or a dual damascene structure.

In the semiconductor memory device 10, the above structure provides a ferroelectric capacitor 11 inside the opening 110 that penetrates the planarization film 200 and the first insulating layer 300. This allows the semiconductor memory device 10 to expand the area of the capacitor 11, thereby increasing the capacitance of the capacitor 11. Therefore, the semiconductor memory device 10 can obtain a signal with a sufficient margin for operation.

Furthermore, the semiconductor memory device 10 can more efficiently arrange the transistors 21 and capacitors 11 by defining the extension directions of the active region 150, word lines WL, source lines SL, and bit lines BL. This allows the semiconductor memory device 10 to suppress an increase in the area occupied by the memory cells.

(1.3. Manufacturing method)
3A to 3H, a method for manufacturing the semiconductor memory device 10 according to this embodiment will be described. 3A to 3H are schematic views for explaining a step in the method for manufacturing the semiconductor memory device 10 according to this embodiment.

As with FIG. 2, layers extending over the entire surface of the semiconductor substrate 100 are omitted from FIGS. 3A to 3H. Each of the cross-sectional views in FIGS. 3A to 3H shows a cross section taken along line A-A, line B-B, or line C-C, respectively, shown in the plan view in the upper left.

First, as shown in FIG. 3A, an isolation layer 105 is formed on the semiconductor substrate 100, and an active region 150 is formed in which the transistor 21 will be formed in a later process.

Specifically, a SiO ₂ film is formed on a semiconductor substrate 100 made of Si by dry oxidation or the like, and a Si ₃ N ₄ film is then formed by low-pressure CVD or the like. A patterned resist layer is then formed on the Si 3 N 4 film to protect the area where the active region 150 will be formed, and the SiO ₂ film, Si ₃ N ₄ film, and semiconductor substrate 100 are then etched to a depth of 350 nm to 400 nm. Next, SiO 2 is deposited to a thickness of 650 nm to 700 nm, and the openings formed by the etching are filled to form the element isolation layer 105. For example, high-density plasma CVD, which has good step coverage and can form a dense SiO ₂ film, may be used to deposit the SiO ₂ .

Subsequently, the excess SiO ₂ film is removed by CMP (Chemical Mechanical Polishing) or the like to planarize the surface of the semiconductor substrate 100. The SiO ₂ film may be removed by CMP until the Si ₃ N ₄ film is exposed, for example.

Furthermore, _{the Si3N4} film is removed using hot phosphoric acid or the like. It is also possible to anneal the semiconductor substrate 100 in an _N2 , _O2 , or _H2 / _O2 environment before removing the _Si3N4 film in order to make the _SiO2 film of the _element isolation layer 105 a denser film or to round the corners of the active region 150. Next, the surface of the semiconductor substrate 100 corresponding to the active region 150 is oxidized to a depth of about 10 nm to form an oxide film 100A, and then a first conductivity type impurity (e.g., boron (B)) is ion-implanted to convert the semiconductor substrate 100 in the active region 150 into a first conductivity type well.

Next, as shown in Figure 3B, a gate insulating film 140 is deposited, and then a gate electrode 130 is formed on the gate insulating film 140.

Specifically, first, the oxide film 100A covering the surface of the semiconductor substrate 100 is stripped using a hydrofluoric acid solution or the like. Then, a gate insulating film 140 made of _SiO2 is formed on the semiconductor substrate 100 to a thickness of 1.5 nm to 10 nm by dry oxidation using _O2 at 700°C or RTA (Rapid Thermal Anneal) processing. Note that, in addition to _O2 , a mixed gas of _H2 / _O2 , _N2O , or NO may also be used as the gas used for dry oxidation. Furthermore, when forming the gate insulating film 140, nitrogen doping into the _SiO2 film is also possible by using plasma nitridation.

Next, polysilicon is deposited to a thickness of 50 nm to 150 nm using low-pressure CVD with SiH ₄ gas as the source gas and a deposition temperature of 580°C to 620°C. The deposited polysilicon is then anisotropically etched using a patterned resist as a mask to form the gate electrode 130. For example, an HBr-based gas or a Cl-based gas can be used for the anisotropic etching. For example, for a 40 nm node, the gate electrode 130 may be formed with a gate width of approximately 40 nm to 50 nm.

The gate electrode 130 functions as a word line WL. The gate electrode 130 may be formed simultaneously with or shared with the gate electrodes of other transistors provided in the logic region, etc.

Next, as shown in FIG. 3C, sidewall insulating films 132 are formed on both side surfaces of the gate electrode 130, and source or drain regions 151 are formed in the active region 150 of the semiconductor substrate 100.

Specifically, LDD regions are formed by ion-implanting arsenic (As), a second conductivity type impurity, at a concentration of 5 to 20× ¹⁰ ions/cm ² at 5 keV to 20 keV on both sides of the gate electrode 130. Forming the LDD regions can suppress the short channel effect, thereby suppressing variations in the characteristics of the transistor 21. Phosphorus (P) can also be used as the second conductivity type impurity.

Next, _SiO2 is deposited by plasma CVD to a thickness of 10 nm to 30 nm, and then _Si3N4 is deposited by plasma CVD to a thickness of 30 nm to 50 nm _to form a sidewall insulating film. Thereafter, the sidewall insulating film is anisotropically etched to form sidewall insulating films 132 on both side surfaces of the gate electrode 130.

Thereafter, arsenic (As), a second conductivity type impurity, is ion-implanted at a concentration of 1 to 2×10 ¹⁵ /cm ² at 20 keV to 50 keV to introduce the second conductivity type impurity on both sides of the gate electrode 130. As a result, source or drain regions 151 are formed in the active region 150 on both sides of the gate electrode 130. Furthermore, rapid thermal annealing (RTA) is performed at 1000°C for 5 seconds to activate the ion-implanted impurity. This forms the transistor 21. It is also possible to activate the impurity by spike RTA to promote activation of the introduced impurity and suppress diffusion of the impurity.

Furthermore, Ni is deposited over the entire surface of the semiconductor substrate 100 to a thickness of 6 to 8 nm by sputtering or the like, and then RTA is performed at 300° _C to 450°C for 10 to 60 seconds to convert the Ni on the _Si into silicide (NiSi). Unreacted Ni on _{the SiO2} is removed using _H2SO4 / _H2O2 to form a cap layer 131 and contact region 152 made of low-resistance NiSi on the gate electrode 130 and the source or drain region 151. Alternatively, _Co or NiPt may be deposited instead of Ni to form the cap layer 131 and contact region 152 of CoSi2 or NiPtSi. The RTA temperature when Co or NiPt is deposited may be set appropriately.

Next, as shown in Figure 3D, a planarization film 200 is formed over the entire surface of the semiconductor substrate 100 so as to embed the transistor 21.

Specifically, SiO ₂ is deposited on the semiconductor substrate 100 to a thickness of 100 nm to 500 nm using CVD or the like, and then planarized by CMP to form the planarization film 200 .

Although not shown, a liner layer made of SiN _x may be formed on the entire surface of the semiconductor substrate 100 before the planarization film 200 is formed. For example, the liner layer is formed by depositing SiN _x to a film thickness of 10 nm to 50 nm using plasma CVD. The liner layer may also be formed as a layer that imparts compressive stress or tensile stress to the semiconductor substrate 100. By forming the liner layer, the planarization film 200 can be etched in a later step under conditions that increase the etching selectivity between the planarization film 200 and the liner layer, thereby enabling etching to be performed with greater control.

Next, as shown in FIG. 3E, contacts 210 are formed to electrically connect to the other of the source or drain regions 151 and the gate electrode 130, and then a first wiring layer 310 is formed on the contacts 210.

Specifically, the planarization film 200 is etched to form an opening on the other of the source or drain regions 151. Subsequently, Ti and TiN are deposited in the formed opening by CVD or the like, and then W is deposited, followed by planarization by CMP, thereby forming a contact 210 on the other of the source or drain regions 151. Note that Ti and TiN may also be deposited by sputtering using IMP (Ion Metal Plasma), or the like. Planarization may also be performed by full surface etch-back instead of CMP.

Note that contacts electrically connected to the gate electrode 130 can also be formed using the same process. Furthermore, these contacts 210 may be formed simultaneously with the contacts of other transistors provided in the logic region, etc.

Then, a first wiring layer 310 is formed on the planarization film 200 using Al or the like as the wiring material. The first wiring layer 310 extends in the first direction over the contact 210, thereby functioning as the bit line BL. Note that the first wiring layer 310 may also be formed using a damascene structure using Cu as the wiring material.

Next, as shown in FIG. 3F, a first insulating layer 300 is formed to bury the first wiring layer 310, and then an opening 110 is formed that penetrates the planarization film 200 and the first insulating layer 300 and exposes the source or drain region 151.

Specifically, SiO ₂ is deposited on the planarization film 200 using CVD or the like to a thickness of 100 nm to 500 nm so as to bury the first wiring layer 310, and then planarized by CMP to form the first insulating layer 300. The first insulating layer 300 may be formed of a low-dielectric-constant material (e.g., SiOC containing carbon) having a dielectric constant lower than that of SiO _2. Although not shown, a liner layer made of SiN _x may be formed on the planarization film 200 before forming the first insulating layer 300. For example, the liner layer may be formed by depositing SiN _x to a thickness of 10 nm to 50 nm using plasma CVD.

Next, an opening 110 is formed in the planarization film 200 and first insulating layer 300 on the other of the source or drain regions 151 by anisotropic etching using a lithographically patterned resist as a mask. The opening 110 can be formed with a width of, for example, 60 nm. In this case, if the aspect ratio of the opening 110 is approximately 20 or less, the etching to form the opening 110 and the subsequent filling of the opening 110 by deposition can be carried out without any problems. Anisotropic etching can be carried out using, for example, a fluorocarbon-based gas. Furthermore, the use of the liner layer described above allows for the etching to be stopped with good control.

Next, as shown in Figure 3G, a capacitor 11 is formed inside the opening 110.

Specifically, the bottom electrode 111 is formed by first depositing TiN to a thickness of 5 to 10 nm on the source or drain region 151 along the internal shape of the opening 110 using sputtering by ALD, CVD, or IMP. Resist is then applied to the deposited bottom electrode 111, and etch-back is performed under conditions that result in similar selectivity between the resist and the bottom electrode 111, thereby recessing the bottom electrode 111 from the opening surface of the opening 110. This leaves the bottom electrode 111 on the bottom and side surfaces of the opening 110, while recessing the shoulder of the bottom electrode 111, forming a recess.

Next, hafnium oxide (HfO _x ), a high dielectric material, is deposited on the lower electrode 111 along the internal shape of the opening 110 to a film thickness of 3 nm to 10 nm by CVD or ALD to form a ferroelectric film 113. Note that hafnium oxide (HfO _x ), a high dielectric material, is converted into a ferroelectric material by annealing in a later stage.

It is also possible to use high-dielectric materials such as zirconium oxide (ZrO _x ) or hafnium zirconium oxide (HfZrO _x ) instead of hafnium oxide. Furthermore, these high-dielectric materials can be converted into ferroelectric materials by doping them with lanthanum (La), silicon (Si), gadolinium (Gd), or the like.

Thereafter, TiN is deposited on the ferroelectric film 113 using CVD, ALD, sputtering, or the like to a thickness of 5 nm to 20 nm so as to fill the opening 110, thereby forming the upper electrode 115. Note that TaN or the like can also be used as a material for forming the upper electrode 115. Subsequently, crystallization annealing is performed to convert the HfO _x constituting the ferroelectric film 113 into a ferroelectric material. Note that the crystallization annealing to convert HfO _x into a ferroelectric material may be performed in this process or in another process. The temperature of the crystallization annealing can be arbitrarily changed, for example, within the range of 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring. Subsequently, CMP or the like is performed to remove excess ferroelectric film 113 and upper electrode 115 deposited on the first insulating layer 300. This completes the formation of the capacitor 11.

Then, as shown in Figure 3H, via contacts 311 and upper wiring layer 312 are formed on the first wiring layer 310. Specifically, the via contacts 311 and upper wiring layer 312 can be formed using a damascene structure with Cu or other wiring materials. Note that the via contacts 311 and upper wiring layer 312 may also be formed from Al or other materials.

The above steps allow the semiconductor memory device 10 according to this embodiment to be formed.

(1.4. Operation example)
Next, a description will be given of the write and read operations of the semiconductor memory device 10 according to this embodiment. Figure 4 is a cross-sectional view schematically showing the cross section of the semiconductor memory device 10 according to this embodiment taken along the active region 150.

As shown in FIG. 4, the semiconductor memory device 10 includes a transistor 21 and a capacitor 11 connected to the source side of the source or drain region 151 of the transistor 21. The semiconductor memory device 10 is driven by a word line WL connected to the gate electrode 130 of the transistor 21, a bit line BL connected to the drain side of the source or drain region 151 of the transistor 21 via a contact 210, and a source line SL connected to the capacitor 11.

Table 1 below shows an example of the voltages (unit: V) applied to SWL, SBL, SSL, Well, UWL, UBL, and USL shown in Figure 4 during write and read operations of the semiconductor memory device 10.

In Table 1, Vth is the threshold voltage for turning on the channel of transistor 21, and Vw is the voltage capable of reversing the polarization state of capacitor 11. Furthermore, SWL, SBL, and SSL respectively indicate the word line WL, bit line BL, and source line SL of the selected memory cell, while UWL, UBL, and USL respectively indicate the word line WL, bit line BL, and source line SL of the unselected memory cell. Well indicates the active region 150 of the semiconductor substrate 100.

For example, when writing information "1" to a memory cell, Vw+Vth is applied to the word line WL connected to the selected memory cell of the semiconductor memory device 10, Vw is applied to the bit line BL, 0V is applied to the source line SL, and 0V is applied to the active region 150 of the semiconductor substrate 100. Furthermore, the word line WL, bit line BL, and source line SL connected to unselected memory cells of the semiconductor memory device 10 are each set to 0V.

In this manner, in the selected memory cell, when Vw is applied to the bit line BL, the potential of the other of the source or drain region 151 of the transistor 21 becomes Vw, and therefore the potential of the lower electrode 111 of the capacitor 11 becomes Vw. Meanwhile, the potential of the source line SL is 0V, so the potential of the upper electrode 115 becomes 0V. Therefore, an electric field of Vw is applied to the ferroelectric film 113 of the capacitor 11, which causes the lower electrode 111 side to have a higher potential, thereby controlling the polarization state of the ferroelectric film 113. Through the above operation, for example, data "1" can be written to the memory cell.

At this time, the potential of the source or drain region 151 of the transistor 21 of the selected memory cell becomes Vw, but in the transistors 21 of the unselected memory cells, the word line WL and gate electrode 130 are at 0V. Therefore, in the adjacent unselected memory cells, no potential is applied to the lower electrode 111, and no electric field is applied to the ferroelectric film 113 of the capacitor 11.

When writing information "0" to a memory cell, Vw+Vth is applied to the word line WL connected to the selected memory cell of the semiconductor memory device 10, and Vw is applied to the source line SL. The bit line BL is set to 0V, and the active region 150 of the semiconductor substrate 100 is set to 0V. The word line WL, bit line BL, and source line SL connected to unselected memory cells of the semiconductor memory device 10 are each set to 0V.

In this manner, in the selected memory cell, because the bit line BL is 0V, the potential of the other of the source or drain region 151 of the transistor 21 is 0V, and the potential of the lower electrode 111 of the capacitor 11 is 0V. Meanwhile, because the potential of the source line SL is Vw, the potential of the upper electrode 115 is Vw. Therefore, a potential difference of Vw, which places the upper electrode 115 at a higher potential, is applied to the ferroelectric film 113 of the capacitor 11, controlling the polarization state of the ferroelectric film 113. Through the above operation, data such as "0" can be written to the memory cell.

At this time, the potential of the source line SL of the selected memory cell becomes Vw, but in the transistor 21 of the unselected memory cell, the word line WL and gate electrode 130 are at 0V. Therefore, in the adjacent unselected memory cell, no potential is applied to the lower electrode 111, and no electric field is applied to the ferroelectric film 113 of the capacitor 11.

Information is read from memory cells of the semiconductor memory device 10 by utilizing the change in displacement current that occurs when writing predetermined information (e.g., "1") to a memory cell, based on the information ("0" or "1") stored before writing.

For example, Table 1 shows the voltages applied to SWL, SBL, SSL, Well, UWL, UBL, and USL when writing information "1" to a memory cell and then reading information from the memory cell. In this case, if the information stored in the memory cell is "1," the amount of displacement current is small, and if the information stored in the memory cell is "0," the amount of displacement current is large. This allows the semiconductor memory device 10 to determine whether the information stored in the memory cell is "0" or "1."

However, when information is read from a memory cell using the above read operation, the information stored in the memory cell is overwritten with the specified information written during the read operation. In other words, in semiconductor memory device 10, reading information from a memory cell is a destructive read. Therefore, in semiconductor memory device 10, after a read operation, a rewrite operation is performed to repair the information destroyed by the read operation.

2. Second embodiment
(2.1. Configuration example)
Next, a semiconductor memory device according to a second embodiment of the present disclosure will be described with reference to Fig. 5. Fig. 5 is a schematic diagram showing the planar configuration and cross-sectional configuration of a semiconductor memory device 10A according to this embodiment.

5, in order to clarify the arrangement of each component, the planarization film 200 formed to extend over the entire surface of the semiconductor substrate 100 is omitted. Each cross-sectional view in FIG. 5 shows a cross section taken along line A-A, line B-B, or line C-C shown in the top left plan view.

As shown in FIG. 5, the semiconductor memory device 10A according to the second embodiment differs from the semiconductor memory device 10 according to the first embodiment in that a capacitor 11 is provided inside an opening 110 that includes a first opening 110A and a second opening 110B that have different opening diameters.

Specifically, the first opening 110A is formed in the planarization film 200 with a larger diameter than the second opening 110B. The diameter of the first opening 110A may be, for example, large enough so that it does not contact the first opening 110A of an adjacent memory cell in the first direction and does not overlap with the gate electrode 130 in the second direction. Furthermore, the depth of the first opening 110A may be large enough so that it does not contact the gate electrode 130, sidewall insulating film 132, or cap layer 131.

The second opening 110B has a smaller diameter than the first opening 110A and is formed in the planarization film 200 inside (i.e., at the bottom) of the first opening 110A. The size of the second opening 110B may be, for example, approximately the same as the size of the source or drain region 151. The depth of the second opening 110B may also be such that the source or drain region 151 is exposed from the bottom of the first opening 110A.

Therefore, the opening 110, which includes the first opening 110A and the second opening 110B, is provided with a shape in which the opening diameter widens on the upper side, opposite the lower side where the semiconductor substrate 100 is provided. By providing the capacitor 11 inside the opening 110, which includes the first opening 110A and the second opening 110B, the semiconductor memory device 10A can further increase the area of the capacitor 11 while suppressing short circuits between the capacitor 11 and the gate electrode 130. Therefore, the semiconductor memory device 10A can obtain signals with sufficient margins for operation while improving device reliability.

In the semiconductor memory device 10A according to the second embodiment, the opening 110 may be provided so as to penetrate only the planarization film 200, or, as in the semiconductor memory device 10 according to the first embodiment, may be provided so as to penetrate the planarization film 200 and the first insulating layer 300 from above the first wiring layer 310.

(2.2. Manufacturing method)
6A to 6G, a method for manufacturing the semiconductor memory device 10A according to this embodiment will be described. 6A to 6G are schematic views illustrating a step in the method for manufacturing the semiconductor memory device 10A according to this embodiment.

As with FIG. 5, layers extending over the entire surface of the semiconductor substrate 100 are omitted from FIGS. 6A to 6G. Each of the cross-sectional views in FIGS. 6A to 6G shows a cross section taken along line A-A, line B-B, or line C-C, respectively, shown in the plan view in the upper left.

First, as shown in Figure 6A, the transistor 21, planarization film 200, and contact 210 are formed using steps similar to those shown in Figures 3A to 3E of the first embodiment.

Next, as shown in FIG. 6B, a first opening 110A is formed in the planarization film 200 on the other of the source or drain regions 151 by anisotropic etching using a lithographically patterned resist as a mask. The first opening 110A can be formed to a width of 90 nm and a depth of 100 nm, for example.

Next, as shown in FIG. 6C, spacers 117 are formed on the inner surface of the first opening 110A. Specifically, amorphous silicon (a-Si) is deposited to a thickness of 15 nm on the planarization film 200, including the first opening 110A, and the a-Si is then anisotropically etched to form spacers 117 only on the inner surface of the first opening 110A. The spacers 117 can be formed from a material that will serve as a mask during the etching process to form the second opening 110B in the subsequent step, and can be formed from, for example, silicon nitride (SiNx), silicon oxynitride (SiON), or silicon carbide (SiC). The deposition temperature for the a-Si is selected taking into account its effect on the underlying transistor 21, etc.

Next, as shown in FIG. 6D, a second opening 110B is formed at the bottom of the first opening 110A, and then a lower electrode 111 is formed along the internal shapes of the first opening 110A and the second opening 110B.

Specifically, the second opening 110B can be formed by etching the planarization film 200 using the spacer 117 as a mask. For example, the second opening 110B can be formed with good control by using high SiO ₂ /SiN etching conditions to stop etching at the liner layer and then etching down to the contact region 152 above the source or drain region 151. The second opening 110B can be formed with a width (e.g., 60 nm) smaller than that of the first opening 110A. This increases the distance between the gate electrode 130 and the second opening 110B, thereby preventing short circuits between the gate electrode 130 and the capacitor 11. At this time, the spacer 117 can also be removed. Specifically, by using chemical dry etching (CDE) to increase the etching selectivity between Si and SiO ₂ , only the spacer 117 can be removed with good control.

Then, using ALD or CVD, TiN is deposited to a thickness of 5 to 10 nm on the source or drain region 151, following the internal shape of the first opening 110A and the second opening 110B, thereby forming the bottom electrode 111. Note that TaN or other materials can also be used as the material for forming the bottom electrode 111.

Next, as shown in FIG. 6E, resist is applied onto the deposited lower electrode 111, and then etch-back is performed under conditions that result in similar selectivity between the resist and the lower electrode 111, thereby causing the lower electrode 111 to retreat from the opening surface of the first opening 110A. This leaves the lower electrode 111 on the bottom and side surfaces of the first opening 110A and the second opening 110B, while retreating the shoulder of the lower electrode 111, forming a recess.

Next, as shown in Figure 6F, a ferroelectric film 113 and an upper electrode 115 are deposited on the lower electrode 111 to form the capacitor 11.

Specifically, first, a high-dielectric material, hafnium oxide (HfOx), is deposited on the lower electrode 111 by CVD or ALD to a thickness of 3 to 10 nm along the internal shape of the opening 110, forming the ferroelectric film 113. Note that the high-dielectric material, hafnium oxide (HfOx), is converted into a ferroelectric material by subsequent annealing.

Instead of hafnium oxide, it is also possible to use high-dielectric materials such as zirconium oxide (ZrOx) or hafnium zirconium oxide (HfZrOx). Furthermore, these high-dielectric materials can be converted into ferroelectric materials by doping them with lanthanum (La), silicon (Si), gadolinium (Gd), etc.

Then, TiN is deposited on the ferroelectric film 113 using CVD, ALD, sputtering, or the like to a thickness of 5 to 20 nm so as to fill the first opening 110A and the second opening 110B, thereby forming the upper electrode 115. Note that TaN or other materials can also be used to form the upper electrode 115. Next, crystallization annealing is performed to convert the HfOx that constitutes the ferroelectric film 113 into a ferroelectric material. Note that the crystallization annealing to convert HfOx into a ferroelectric material may be performed in this process or in another process. The crystallization annealing temperature can be changed as desired, as long as it is within the range of 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring. Subsequently, CMP or the like is performed to remove excess ferroelectric film 113 and upper electrode 115 deposited on the planarization film 200. This completes the formation of the capacitor 11.

Next, as shown in Figure 6G, a first wiring layer 310 is formed on the contact 210, and a second wiring layer 320 is formed on the upper electrode 115 of the capacitor 11.

Specifically, by using a damascene structure with Cu as the wiring material, a first wiring layer 310 can be formed on the contact 210. The first wiring layer 310 functions as the bit line BL by extending in a first direction on the contact 210. Similarly, by using a damascene structure with Cu or other wiring materials, a second wiring layer 320 can be formed on the upper electrode 115. The second wiring layer 320 functions as the source line SL by extending in a first direction on the upper electrode 115 of the capacitor 11. Note that the first wiring layer 310 and the second wiring layer 320 may also be formed of Al or other materials.

The above steps allow the semiconductor memory device 10A according to this embodiment to be formed.

3. Third embodiment
(3.1. Configuration example)
Next, a semiconductor memory device according to a third embodiment of the present disclosure will be described with reference to Fig. 7 and Fig. 8. Fig. 7 is a schematic diagram showing a cross-sectional configuration of a semiconductor memory device 10B according to this embodiment. Fig. 8 is a schematic diagram showing a planar layout of the semiconductor memory device 10B according to this embodiment.

As shown in FIG. 7 , the semiconductor memory device 10B according to the third embodiment is an FeRAM that includes a capacitor 11 for storing information and a transistor 21 for controlling the selection and deselection of the capacitor 11, similar to the semiconductor memory device 10 according to the first embodiment and the semiconductor memory device 10A according to the second embodiment.

Specifically, the transistor 21 is composed of a source or drain region 151 provided in the semiconductor substrate 100 and a gate electrode 130 provided on the semiconductor substrate 100. The drain side of the source or drain region 151 is electrically connected to the contact 210, and the source side of the source or drain region 151 is electrically connected to the three-dimensional capacitor 11.

A cap layer 131 made of silicide, an alloy of cobalt (Co) or nickel (Ni) and silicon (Si), is provided on the surface of the gate electrode 130. Similarly, a contact region 152 made of silicide, an alloy of cobalt (Co) or nickel (Ni) and silicon (Si), is provided on the surface of the source or drain region 151.

The contact 210 is formed by embedding a barrier metal layer 210B and a conductive layer 210A inside an opening in a planarization film 200 made of, for example, silicon oxide (SiOx). The conductive layer 210A is made of tungsten (W) or polysilicon (poly-Si), and electrically connects the contact region 152 to the first wiring layer 310. The barrier metal layer 210B is made of, for example, Ti, TiN, or Ru, and covers the surface of the conductive layer 210A to suppress interaction between the conductive layer 210A and the planarization film 200. The contact 210 may be made of any structure and material as long as it can form an ohmic electrical connection with the contact region 152 and the source or drain region 151.

The capacitor 11 is provided inside an opening provided in the planarization film 200 and the interlayer insulating film 201. In the semiconductor memory device 10B according to this embodiment, the capacitor 11 is provided at a different height than the contact 210. For example, the capacitor 11 may be provided so as to be higher than the contact 210 by the height of the interlayer insulating film 201.

The interlayer insulating film 201 is formed on the planarization film 200 using, for example, silicon oxide (SiOx) or silicon nitride (SiNx). The interlayer insulating film 201 is provided to prevent the contacts 210 from being exposed to cleaning solutions or the like and being damaged in the subsequent process of forming the capacitors 11.

Capacitor 11 is constructed by sequentially stacking a lower electrode 111 made of Ti or TiN, a ferroelectric film 113, and an upper electrode 115 made of Ti or TiN. Capacitor 11 is an embedded capacitor in which the lower electrode 111 and the upper electrode 115 are insulated via the ferroelectric film 113. In capacitor 11, the area where the lower electrode 111 and the upper electrode 115 face each other in parallel, and the fringe components from the electrode edges of the lower electrode 111 and the upper electrode 115, form the effective capacitance area.

The ferroelectric film 113 may be composed of a high-dielectric material such as hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium oxide (HfZrOx). The ferroelectric film 113 may also be composed of a ferroelectric material converted by doping the above high-dielectric material with lanthanum (La), silicon (Si), gadolinium (Gd), or the like.

A first insulating layer 300 is provided on the interlayer insulating film 201. The first insulating layer 300 is provided with a first wiring layer 310 electrically connected to the contact 210 and a second wiring layer 320 electrically connected to the upper electrode 115 of the capacitor 11. The lower end of the second wiring layer 320 is arranged to cover the ferroelectric film 113 and upper electrode 115 of the capacitor 11, thereby preventing contact with the lower electrode 111.

As shown in FIG. 8, the semiconductor memory device 10B includes an active region 150 provided on the semiconductor substrate 100, a gate electrode 130 functioning as a word line WL, a contact 210, a capacitor 11, a first wiring layer 310 functioning as a bit line BL, and a second wiring layer 320 functioning as a source line SL.

The first wiring layer 310, which functions as the bit line BL, and the second wiring layer 320, which functions as the source line SL, are provided extending in a first direction within the plane of the semiconductor substrate 100. Furthermore, the gate electrode 130, which functions as the word line WL, is provided extending in a second direction perpendicular to the first direction. The active region 150 is a region in which the transistor 21 is provided, and is provided extending in a third direction obliquely intersecting both the first and second directions. Furthermore, the contact 210 is provided at the intersection of the active region 150 and the first wiring layer 310, and the capacitor 11 is provided at the intersection of the active region 150 and the second wiring layer 320.

(3.2. Manufacturing method)
Next, a method for manufacturing the semiconductor memory device 10B according to this embodiment will be described with reference to Figures 9A to 9I. Figures 9A to 9I are cross-sectional views illustrating a step in the method for manufacturing the semiconductor memory device 10B according to this embodiment.

First, as shown in Figure 9A, a transistor 21 is formed on a semiconductor substrate 100 through known processes (for example, the processes shown in Figures 3A to 3D), and a planarization film 200 is deposited on the semiconductor substrate 100 so as to embed the transistor 21.

Next, as shown in FIG. 9B, an opening is formed in the planarization film 200 in a region corresponding to one of the source or drain regions 151, and a contact 210 is formed inside the formed opening.

9C , an interlayer insulating film 201 is formed on the planarizing film 200. The interlayer insulating film 201 can be formed of, for example, silicon oxide (SiO _x ) or silicon nitride (SiN _x ). The interlayer insulating film 201 is provided to prevent the contacts 210 from being exposed to cleaning solutions or the like and being damaged in a later step of forming the capacitor 11.

Next, as shown in FIG. 9D, an opening 110 for forming a capacitor 11 is formed in the planarization film 200 in the region corresponding to the other of the source or drain regions 151.

Here, it is desirable to clean the bottom of the opening 110 with a cleaning solution containing sulfuric acid or a cleaning solution containing ammonium hydroxide (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ) in order to improve the contact resistance and the variation in contact resistance between the capacitor 11 and the transistor 21. The cleaning solution may damage the contact 210, but in the semiconductor memory device 10B according to this embodiment, the interlayer insulating film 201 is provided on the contact 210, so that damage to the contact 210 by the cleaning solution can be prevented.

Then, as shown in Figure 9E, a conductive material is deposited inside the opening 110 and on the interlayer insulating film 201 to form the lower electrode layer 111A.

Next, as shown in FIG. 9F, resist is applied onto the deposited lower electrode layer 111A, and then etch-back is performed under conditions that result in similar selectivity between the resist and the lower electrode layer 111A, thereby recessing the lower electrode layer 111A from the opening surface of the opening 110. This leaves the lower electrode 111 on the bottom and side surfaces of the opening 110, while recessing the shoulder of the lower electrode 111, forming a recess. As a result, the lower electrode 111 is formed so that its upper end is lower than the opening surface of the opening 110, in order to prevent a short circuit with the second wiring layer 320, which will be formed later.

Next, as shown in Figure 9G, a ferroelectric film layer 113A and an upper electrode layer 115A are deposited on the lower electrode 111.

Next, as shown in Figure 9H, the ferroelectric film layer 113A and the upper electrode layer 115A outside the interior of the opening 110 are removed by dry etching, polishing, or the like, thereby forming the ferroelectric film 113 and the upper electrode 115.

Then, as shown in Figure 9I, a first insulating layer 300 is deposited on the interlayer insulating film 201, and then a first wiring layer 310 and a second wiring layer 320 are formed using a damascene structure or the like using copper (Cu) as the wiring material.

The above steps allow the semiconductor memory device 10B according to this embodiment to be formed.

(3.3. Modifications)
(First Modification)
10 to 11F, a first modification of the semiconductor memory device 10B according to this embodiment will be described. Fig. 10 is a schematic diagram showing a cross-sectional configuration of the semiconductor memory device 10B according to the first modification.

As shown in FIG. 10, the semiconductor memory device 10B according to the first modification differs from the structure shown in FIG. 7 in that the ferroelectric film 113 and upper electrode 115 are patterned and deposited on the interlayer insulating film 201. The upper electrode 115 is patterned into a wiring shape on the interlayer insulating film 201, allowing it to function as the second wiring layer 320. Therefore, the semiconductor memory device 10B according to the first modification does not need to include the second wiring layer 320. According to the semiconductor memory device 10B according to the first modification, by not including the second wiring layer 320, it is possible to prevent a short circuit between the lower electrode 111 and the second wiring layer 320.

Now, a method for manufacturing the semiconductor memory device 10B according to this modification will be described with reference to Figures 11A to 11F. Figures 11A to 11F are cross-sectional views illustrating one step in the method for manufacturing the semiconductor memory device 10B according to this modification.

First, as shown in Figure 11A, a transistor 21 and a contact 210 are formed on a semiconductor substrate 100 using steps similar to those shown in Figures 9A to 9D, and an opening 110 is formed in a planarization film 200 and an interlayer insulating film 201.

Next, as shown in FIG. 11B, a conductive material is deposited inside the opening 110 and on the interlayer insulating film 201 to form the lower electrode layer 111A.

Next, as shown in FIG. 11C, resist is applied onto the deposited lower electrode layer 111A, and then etched back under conditions that result in similar selectivity between the resist and the lower electrode layer 111A, thereby recessing the lower electrode layer 111A from the opening surface of the opening 110. This leaves the lower electrode 111 on the bottom and side surfaces of the opening 110, while recessing the shoulder of the lower electrode 111, forming a recess. In this variation, the lower electrode 111 may be formed so that its upper end is higher than the opening surface of the opening 110.

Next, as shown in Figure 11D, a ferroelectric film layer 113A and an upper electrode layer 115A are deposited on the lower electrode 111.

Next, as shown in Figure 11E, the ferroelectric film layer 113A and upper electrode layer 115A on the interlayer insulating film 201 are patterned into wiring shapes to form the ferroelectric film 113 and upper electrode 115.

Then, as shown in Figure 11F, a first insulating layer 300 is deposited on the interlayer insulating film 201, and a first wiring layer 310 is formed using a damascene structure or the like using copper (Cu) as the wiring material.

The above steps allow the semiconductor memory device 10B according to this modified example to be formed.

(Second Modification)
A second modification of the semiconductor memory device 10B according to this embodiment will now be described with reference to Fig. 12. Fig. 12 is a schematic diagram showing the cross-sectional configuration of the semiconductor memory device 10B according to the second modification.

As shown in FIG. 12, the semiconductor memory device 10B according to the second modification differs from the structure shown in FIG. 7 in that the lower electrode 111, ferroelectric film 113, and upper electrode 115 are deposited on an interlayer insulating film 201. The lower electrode 111, ferroelectric film 113, and upper electrode 115 on the interlayer insulating film 201 are patterned, and a second wiring layer 320 is provided on the upper electrode 115. The semiconductor memory device 10B according to the second modification can be formed by simultaneously etching the lower electrode 111, ferroelectric film 113, and upper electrode 115 deposited on the interlayer insulating film 201.

(Third Modification)
A third modification of the semiconductor memory device 10B according to this embodiment will now be described with reference to Fig. 13. Fig. 13 is a schematic diagram showing a cross-sectional configuration of the semiconductor memory device 10B according to the third modification.

13, the semiconductor memory device 10B according to the third modification differs from the structure shown in Fig. 7 in that no contact region 152 is provided in the source or drain region 151 electrically connected to the capacitor 11. The semiconductor memory device 10B according to the third modification can be formed by selectively silicidating a patterned silicon nitride (SiN _x ) film or the like in the process of forming the transistor 21.

4. Fourth Embodiment
(4.1. Configuration example)
Next, a semiconductor memory device according to a fourth embodiment of the present disclosure will be described with reference to Fig. 14. Fig. 14 is a schematic diagram showing the planar configuration and cross-sectional configuration of a semiconductor memory device 10C according to this embodiment.

In the plan view at the top left of Figure 14, the planarization film 200, which extends over the entire surface of the semiconductor substrate 100, and the first to third insulating layers 300, 400, and 600 are omitted to clarify the arrangement of each component. Each cross-sectional view in Figure 14 shows a cross section taken along line B-B, line C-C, or line D-D, respectively, shown in the plan view at the top left. Note that line B-B and line C-C represent the cross-sectional configuration of memory cell 10CC in semiconductor memory device 10C, and line D-D represents the cross-sectional configuration of the peripheral region of semiconductor memory device 10C. Memory cell 10CC here refers to the region in which capacitor 51, described below, is provided. The peripheral region refers to the region surrounding the memory cell region in which multiple memory cells 10CC are provided. Logic circuits, for example, are provided in the peripheral region of semiconductor memory device 10C.

As shown in FIG. 14, the semiconductor memory device 10C according to the fourth embodiment differs from the semiconductor memory device 10 according to the first embodiment in that it has a capacitor 51 instead of the capacitor 11 (see FIG. 1) of the first embodiment. Hereinafter, components that are substantially the same as those in the semiconductor memory device 10 according to the first embodiment will be designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

The semiconductor memory device 10C is an FeRAM including a capacitor 51 that stores information and a transistor 21 that controls the selection and deselection of the capacitor 51. In addition to the capacitor 51 and the transistor 21, the semiconductor memory device 10C also includes a semiconductor substrate 100, a planarization film 200, a contact 210, a first wiring layer 310, a first insulating layer 300, a second insulating layer 400, and a third insulating layer 600. The semiconductor substrate 100 has a main surface 100S.

The planarization film 200, which serves as an interlayer insulating film, is provided to cover the transistor 21 and the main surface 100S of the semiconductor substrate 100.

Transistor 21 is composed of a source or drain region 151 provided in semiconductor substrate 100 and a gate electrode 130 provided on semiconductor substrate 100. The drain side of source or drain region 151 is electrically connected to contact 210, and the source side of source or drain region 151 is electrically connected to a three-dimensional capacitor 51 via contact 210 and first wiring layer 310.

The contact 210 is made of a conductive material and is provided so as to penetrate the planarization film 200. Specifically, the contact 210 is provided on the other of the source or drain regions 151, and electrically connects the drain side of the source or drain region 151 to the first wiring layer 310, which is the bit line BL.

The first wiring layer 310 is provided on the opposite side of the contact 210 from the transistor 21. The first wiring layer 310 is electrically connected to the contact 210. The first wiring layer 310 is made of a conductive material and is provided on the planarization film 200. Specifically, the first wiring layer 310 is provided on the contact 210 as wiring extending in a first direction perpendicular to the second direction in which the gate electrode 130 (word line WL) extends. The first wiring layer 310 functions as a bit line BL by electrically connecting to the drain side of the source or drain region 151 via the contact 210. In addition, a capacitor 51 is provided on the first wiring layer 310, i.e., on the opposite side of the contact 210 from the first wiring layer 310.

The first insulating layer 300 embeds the capacitor 51 and the first wiring layer 310. The first insulating layer 300 is provided on the planarization film 200, spreading across the entire surface of the semiconductor substrate 100. A via contact 311 and an upper wiring layer 312 are stacked on top of the first wiring layer 310. The via contact 311 and the upper wiring layer 312 are also embedded in the first insulating layer 300. However, the upper wiring layer 312 is exposed on the top surface of the first insulating layer 300.

The via contact 311 is made of a conductive material and is in contact with the first wiring layer 310. The via contact 311 electrically connects the first wiring layer 310 and the upper wiring layer 312. The via contact 311 may be made of a metal material such as aluminum (Al), or may be made of a copper (Cu) damascene structure.

The upper wiring layer 312 is made of a conductive material and is provided on the via contact 311. The upper wiring layer 312 may be made of a metal material such as aluminum (Al), or may be formed in a copper (Cu) damascene structure. The upper wiring layer 312 may be formed simultaneously with or shared with the wiring of other circuits provided in the logic region, etc.

The first wiring layer 310, via contact 311, and upper wiring layer 312 are arranged to penetrate the first insulating layer 300.

The second insulating layer 400 extends along the main surface 100S so as to completely cover the first insulating layer 300. The second insulating layer 400 may be formed of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). A via contact 411 and an upper wiring layer 412 are embedded in the second insulating layer 400. The via contact 411 and the upper wiring layer 412 are stacked in order on the upper wiring layer 312. The upper wiring layer 412 is exposed on the top surface of the second insulating layer 400.

The via contact 411 is made of a conductive material and is in contact with the upper wiring layer 312. The material used to make the via contact 411 can be, for example, the same as the material used to make the via contact 311. The upper wiring layer 412 is made of a conductive material and is provided on top of the via contact 411. The material used to make the upper wiring layer 412 can be, for example, the same as the material used to make the upper wiring layer 312. The upper wiring layer 412 can be formed simultaneously with or shared with the wiring of other circuits provided in the logic region, etc.

The first insulating layer 300 and the second insulating layer 400 have openings 410 at positions corresponding to the first wiring layer 310 in the stacking direction perpendicular to the main surface 100S. The openings 410 are recesses that reach the first wiring layer 310 in the stacking direction. The openings 410 have a structure in which a lower portion 410L located above the first wiring layer 310 communicates with an upper portion 410U located above the lower portion 410L. For example, the area occupied by the lower portion 410L along the main surface 100S is smaller than the area occupied by the upper portion 410U along the main surface 100S. The first insulating layer 300 and the second insulating layer 400 extend to the peripheral region of the semiconductor memory device 10C. The first insulating layer 300 and the second insulating layer 400 also extend to a circuit region including a logic circuit provided in the peripheral region of the semiconductor memory device 10C. The capacitor 51 is embedded in the first insulating layer 300 and the second insulating layer 400, which also extend into the circuit region.

The capacitor 51 is provided to fill the opening 410. The capacitor 51 is located above the contact 210 and the first wiring layer 310. The capacitor 51 includes a lower electrode 511 provided along the inner surface of the opening 410, a ferroelectric film 513 provided on the lower electrode 511 along the opening 410, and an upper electrode 515 provided on the ferroelectric film 513. The lower electrode 511 is electrically connected to the source or drain region 151 (e.g., the source) of the transistor 21 via the first wiring layer 310, etc. The upper electrode 515 is electrically connected to the second wiring layer 612 (described below) as the source line SL. Here, the area of the upper electrode 515 along the main surface 100S is larger than the area of the connection portion between the lower electrode 511 and the first wiring layer 310 along the main surface 100S.

The third insulating layer 600 extends along the main surface 100S so as to completely cover the second insulating layer 400. The third insulating layer 600 may be formed of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). A via contact 611 and a second wiring layer 612 are embedded in the third insulating layer 600. The via contact 611 and the second wiring layer 612 are stacked in order on the upper electrode 515 and the upper wiring layer 412, respectively. The second wiring layer 612 is exposed on the upper surface of the third insulating layer 600.

The via contact 611 is made of a conductive material and is in contact with the upper wiring layer 412. The material constituting the via contact 611 can be, for example, the same as the material constituting the via contact 311. The second wiring layer 612 is made of a conductive material and is provided on top of the via contact 611.

The second wiring layer 612 is electrically connected to the upper electrode 515 of the capacitor 51 through the via contact 611. The second wiring layer 612 is provided on the upper electrode 515 of the capacitor 51 as a wiring extending in the first direction, similar to the first wiring layer 310. The second wiring layer 612 functions as a source line SL by being electrically connected to the upper electrode 515. The second wiring layer 612 may be made of a metal material such as aluminum (Al), or may be made of a copper (Cu) damascene structure or a dual damascene structure.

In the semiconductor memory device 10C having the above structure, the capacitor 51 is provided above the first wiring layer 310, i.e., on the opposite side of the transistor 21 from the first wiring layer 310. This allows the area and thickness of the capacitor 51 to be larger than, for example, when a capacitor is provided in the gap between the first wiring layers 310. In other words, the capacitance of the capacitor 51 can be increased. Therefore, the semiconductor memory device 10C can ensure a signal with a sufficient margin for its operation. In addition, the degree of freedom in designing the planar shape of the capacitor 51 is improved.

(4.2. Manufacturing method)
Next, a method for manufacturing the semiconductor memory device 10C according to this embodiment will be described with reference to Figures 15A to 15I. Figures 15A to 15I are schematic views illustrating one step in the method for manufacturing the semiconductor memory device 10C.

As in FIG. 14, layers extending over the entire surface of the semiconductor substrate 100 are omitted from FIGS. 15A to 15I. Furthermore, each of the cross-sectional views in FIGS. 15A to 15I shows a cross section taken along line A-A, line B-B, line C-C, or line D-D, respectively, shown in the plan view in the upper left.

First, as shown in FIG. 15A, an element isolation layer 105 is formed on a semiconductor substrate 100 in the same manner as in the first embodiment, and an active region 150 in which a transistor 21 will be formed in a subsequent process is formed.

Next, as shown in Figure 15B, a gate insulating film 140 is deposited in the same manner as in the first embodiment, and then a gate electrode 130 is formed on the gate insulating film 140.

Next, as shown in FIG. 15C, in the same manner as in the first embodiment, sidewall insulating films 132 are formed on both side surfaces of the gate electrode 130, and source or drain regions 151 are formed in the active region 150 of the semiconductor substrate 100.

Next, as shown in Figure 15D, a planarization film 200 is formed over the entire surface of the semiconductor substrate 100, burying the transistor 21, in the same manner as in the first embodiment.

Next, as shown in FIG. 15E, contacts 210 are formed to electrically connect to the other of the source or drain regions 151 and the gate electrode 130. After that, a first wiring layer 310 is formed on the contacts 210. The first wiring layer 310 can become bit lines BL by extending in the first direction on the contacts 210. The first wiring layer 310 can also be used as wiring that constitutes logic circuits in the peripheral region. Furthermore, the first wiring layer 310 provided in the memory cell region electrically connects the contacts 210 and the lower electrodes 511 of the capacitors 51 on line B-B.

Next, as shown in Figure 15F, a first insulating layer 300 is formed to cover the planarization film 200 and the first wiring layer 310.

Specifically, the first insulating layer 300 is formed by depositing a SiO ₂ film to a thickness of 100 nm to 500 nm on the planarization film 200 using CVD or the like so as to bury the first wiring layer 310. When forming the first insulating layer 300, the deposited SiO ₂ film may be planarized by, for example, CMP. The first insulating layer 300 may be formed of a low-dielectric-constant material (e.g., SiOC containing carbon) having a dielectric constant lower than that of SiO _2. Note that, before forming the first insulating layer 300, a liner layer made of SiNx may be formed on the planarization film 200. For example, the liner layer may be formed by depositing SiNx to a thickness of 10 nm to 50 nm using plasma CVD.

After forming the first insulating layer 300, the via contact 311 and upper wiring layer 312 are formed on the first wiring layer 310. Specifically, the via contact 311 and upper wiring layer 312 can be formed by using a damascene structure with Cu or other wiring materials. Note that the via contact 311 and upper wiring layer 312 may also be formed from Al or other materials.

Next, as shown in Figure 15G, a second insulating layer 400 is formed to cover the first insulating layer 300.

Specifically, a SiO ₂ film is deposited on the first insulating layer 300 using CVD or the like to a thickness of 100 nm to 500 nm, thereby forming the second insulating layer 400. When forming the second insulating layer 400, the deposited SiO ₂ film may be planarized, for example, by CMP. The second insulating layer 400 may be formed of a low-dielectric-constant material (e.g., SiOC containing carbon) having a dielectric constant lower than that of SiO _2. Note that, before forming the second insulating layer 400, a liner layer made of SiNx may be formed on the first insulating layer 300. For example, the liner layer may be formed by depositing SiNx to a thickness of 10 nm to 50 nm using plasma CVD.

After forming the second insulating layer 400, the via contact 411 and upper wiring layer 412 are formed on the upper wiring layer 312. Specifically, the via contact 411 and upper wiring layer 412 can be formed by using a damascene structure with Cu or other wiring materials. Note that the via contact 411 and upper wiring layer 412 may also be formed from Al or other materials.

Next, as shown in Figure 15H, an opening 410 is formed to expose the first wiring layer 310 in the memory cell region.

Specifically, the opening 410 is formed by selectively digging down the first insulating layer 300 and the second insulating layer 400 using anisotropic etching with a lithographically patterned resist as a mask. First, the lower portion 410L of the opening 410 is formed to a width of, for example, 60 nm, narrower than the upper portion 410U of the opening 410. After forming the lower portion 410L, the upper portion 410U is formed in the same manner as the lower portion 410L. The width of the upper portion 410U is wider than the width of the lower portion 410L, for example, 100 nm to 150 nm. As long as the aspect ratios of the lower portion 410L and the upper portion 410U are both approximately 20 or less, the etching to form the lower portion 410L and the upper portion 410U and the subsequent deposition to fill the opening 410 can be performed without any problems. Anisotropic etching can be performed using, for example, a fluorocarbon-based gas. Furthermore, the use of the liner layer described above allows for well-controlled etching stop.

Next, as shown in Figure 15I, a capacitor 51 is formed inside the opening 410.

Specifically, first, a lower electrode 511 is formed by depositing TiN to a thickness of 5 to 10 nm on the exposed first wiring layer 310 along the internal shape of the opening 410 using ALD, CVD, or IMP sputtering.

Next, a high-dielectric material, hafnium oxide (HfOx), is deposited on the lower electrode 511 by CVD or ALD to a thickness of 3 to 10 nm, following the internal shape of the opening 410, to form a ferroelectric film 513. Note that the high-dielectric material, hafnium oxide (HfOx), is converted into a ferroelectric material by annealing in a later step.

Instead of hafnium oxide, it is also possible to use high-dielectric materials such as zirconium oxide (ZrOx) or hafnium zirconium oxide (HfZrOx). Furthermore, these high-dielectric materials can be converted into ferroelectric materials by doping them with lanthanum (La), silicon (Si), gadolinium (Gd), etc.

Then, TiN is deposited on the ferroelectric film 513 using CVD, ALD, sputtering, or the like to a thickness of 5 to 20 nm so as to fill the opening 410, thereby forming the upper electrode 515. Note that TaN or other materials can also be used to form the upper electrode 515. Next, crystallization annealing is performed to convert the HfOx that constitutes the ferroelectric film 513 into a ferroelectric material. Note that the crystallization annealing to convert HfOx into a ferroelectric material may be performed in this process or in another process. The crystallization annealing temperature can be changed as desired, as long as it is within the range of 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring. Subsequently, CMP or the like is performed to remove excess ferroelectric film 513 and upper electrode 515 deposited on the second insulating layer 400. This completes the formation of the capacitor 51.

Next, as shown in Figure 14, a third insulating layer 600 is formed to cover the second insulating layer 400.

Specifically, a SiO ₂ film is deposited on the second insulating layer 400 using CVD or the like to a thickness of 100 nm to 500 nm to form the third insulating layer 600. When forming the third insulating layer 600, the deposited SiO ₂ film may be planarized by, for example, CMP. The third insulating layer 600 may be formed of a low-dielectric-constant material (e.g., SiOC containing carbon) having a dielectric constant lower than that of SiO _2. Note that, before forming the third insulating layer 600, a liner layer made of SiNx may be formed on the second insulating layer 400. For example, the liner layer may be formed by depositing SiNx to a thickness of 10 nm to 50 nm using plasma CVD.

After forming the third insulating layer 600, via contacts 611 and second wiring layers 612 are formed on the upper electrodes 515 and upper wiring layers 412, respectively. Specifically, the via contacts 611 and second wiring layers 612 can be formed using a damascene structure with Cu or other wiring materials. The via contacts 611 and second wiring layers 612 may also be formed from Al or other materials. The second wiring layers 612 can also serve as source lines SL by extending in the first direction, for example. The second wiring layers 612 can also be used as wiring that constitutes logic circuits in the peripheral region.

The above steps allow the semiconductor memory device 10C according to this embodiment to be formed.

(4.3. Operational example)
16 is a cross-sectional view schematically showing a cross section of the semiconductor memory device 10C according to this embodiment taken along the active region 150. The write and read operations of the semiconductor memory device 10C according to this embodiment will now be described.

As shown in FIG. 16, the semiconductor memory device 10C includes a transistor 21 and a capacitor 51 connected to the source side of the source or drain region 151 of the transistor 21. The semiconductor memory device 10C is driven by a word line WL connected to the gate electrode 130 of the transistor 21, a bit line BL connected to the drain side of the source or drain region 151 of the transistor 21 via a contact 210, and a source line SL connected to the capacitor 51.

The write and read operations of the semiconductor memory device 10C are performed in the same manner as the write and read operations of the semiconductor memory device 10 of the first embodiment described above. Therefore, the voltages listed in Table 1 above are applied to SWL, SBL, SSL, Well, UWL, UBL, and USL, respectively, as shown in FIG. 16.

Note that Vth in Table 1 is the threshold voltage for turning on the channel of transistor 21. Similarly, Vw in Table 1 is the voltage capable of reversing the polarization state of capacitor 51. Also, SWL, SBL, and SSL in Table 1 represent the word line WL, bit line BL, and source line SL of the selected memory cell, respectively. Furthermore, UWL, UBL, and USL in Table 1 represent the word line WL, bit line BL, and source line SL of the unselected memory cell, respectively. Well in Table 1 represents the active region 150 of the semiconductor substrate 100.

When writing information such as "1" to a selected memory cell 10CC of the semiconductor memory device 10C, Vw+Vth is applied to the word line WL connected to the selected memory cell 10CC, Vw is applied to the bit line BL, 0V is applied to the source line SL, and 0V is applied to the active region 150 of the semiconductor substrate 100. Furthermore, the word line WL, bit line BL, and source line SL connected to unselected memory cells 10CC of the semiconductor memory device 10C are each set to 0V.

When writing information "0" to a selected memory cell 10CC of the semiconductor memory device 10C, Vw+Vth is applied to the word line WL connected to the selected memory cell 10CC, and Vw is applied to the source line SL. The bit line BL is set to 0V, and the active region 150 of the semiconductor substrate 100 is set to 0V. The word line WL, bit line BL, and source line SL connected to unselected memory cells 10CC of the semiconductor memory device 10C are each set to 0V.

Reading information from memory cell 10CC of semiconductor memory device 10C is performed, for example, by utilizing the change in displacement current that occurs when writing predetermined information (e.g., "1") to memory cell 10CC, based on the information ("0" or "1") stored before writing. The details are the same as for reading information from memory cells of semiconductor memory device 10.

5. Fifth embodiment
(5.1. Configuration example)
Next, a semiconductor memory device according to a fifth embodiment of the present disclosure will be described with reference to Fig. 17. Fig. 17 is a schematic diagram showing the planar configuration and cross-sectional configuration of a semiconductor memory device 10D according to this embodiment.

In the plan view at the upper left of Figure 17, the planarization film 200 formed over the entire surface of the semiconductor substrate 100 and the first to third insulating layers 300, 400, and 600 are omitted to clarify the arrangement of each component. Each cross-sectional view in Figure 17 shows a cross section taken along line B-B, line C-C, or line D-D, respectively, shown in the plan view at the upper left. Note that line B-B and line C-C represent the cross-sectional configuration of memory cell 10DD in semiconductor memory device 10D, and line D-D represents the cross-sectional configuration of the peripheral region of semiconductor memory device 10D. Memory cell 10DD here refers to the region in which capacitor 71, described below, is provided. The peripheral region refers to the region surrounding the memory cell region in which multiple memory cells 10DD are provided. The peripheral region of semiconductor memory device 10D may include, for example, a logic circuit.

As shown in FIG. 17, the semiconductor memory device 10D according to the fifth embodiment differs from the semiconductor memory device 10C according to the fourth embodiment in that it has a capacitor 71 instead of capacitor 51. Below, components that are substantially the same as those in the semiconductor memory device 10C according to the fourth embodiment will be designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

The semiconductor memory device 10D is an FeRAM that includes a capacitor 71 that stores information and a transistor 21 that controls the selection and deselection of the capacitor 71.

Like capacitor 51, capacitor 71 is provided to fill opening 410. Capacitor 71 is composed of a lower electrode 711 provided along the inner surface of opening 410, a ferroelectric film 713 provided on lower electrode 711 along opening 410, and an upper electrode 715 provided on ferroelectric film 713. The lower electrode 711 is electrically connected to the source or drain region 151 (e.g., the source) of transistor 21 via the first wiring layer 310 or the like. The upper electrode 715 is electrically connected to the second wiring layer 612 serving as source line SL.

In the semiconductor memory device 10C of the third embodiment described above, the upper end of the lower electrode 511 reaches the upper surface of the second insulating layer 400, i.e., the surface opposite the semiconductor substrate 100. In contrast, in the semiconductor memory device 10D of the present embodiment, the upper end of the lower electrode 711 is located below the upper surface of the second insulating layer 400. Also, in the semiconductor memory device 10C of the third embodiment described above, the outer edge of the upper electrode 515 along the main surface 100S is located in a position recessed inward from the inner edge of the opening 410. Therefore, the area of the upper electrode 515 along the main surface 100S is smaller than the area of the opening 410 along the main surface 100S. In contrast, in the semiconductor memory device 10D of the present embodiment, the outer edge of the upper electrode 715 extends in the in-plane direction along the main surface 100S of the semiconductor substrate 100 until it contacts the inner edge of the opening 410. That is, in the in-plane direction along the main surface 100S of the semiconductor substrate 100, the shape and area of the upper electrode 715 are substantially the same as the shape and area of the opening 410. Therefore, the area of the upper electrode 715 along the main surface 100S is substantially equal to the area of the lower electrode 711 along the main surface 100S.

In the semiconductor memory device 10D having the above structure, similar to the semiconductor memory device 10C, the capacitor 71 is provided on the opposite side of the first wiring layer 310 from the transistor 21. This allows the area and thickness of the capacitor 71 to be larger than when, for example, a capacitor is provided in the gap between the first wiring layers 310. In other words, the capacitance of the capacitor 71 can be increased. Therefore, the semiconductor memory device 10D can ensure a signal with a sufficient margin for its operation. In addition, the degree of freedom in designing the planar shape of the capacitor 71 is improved.

Furthermore, in the semiconductor memory device 10D, the area of the upper electrode 715 along the main surface 100S is made substantially equal to the area of the lower electrode 711 along the main surface 100S. Therefore, compared to the semiconductor memory device 10C, for example, during the manufacturing process, when forming the via contact 611 connected to the upper electrode 715, it is easier to align the upper electrode 715 with the via contact 611. This can improve manufacturing yield.

(5.2. Manufacturing method)
18A to 18C, a method for manufacturing the semiconductor memory device 10D according to this embodiment will be described. Figures 18A to 18C are schematic views illustrating one step in the method for manufacturing the semiconductor memory device 10D.

As with FIG. 17, layers extending over the entire surface of semiconductor substrate 100 are omitted from FIGS. 18A to 18C. Each of the cross-sectional views in FIGS. 18A to 18C shows a cross section taken along line B-B, line C-C, or line D-D, respectively, shown in the plan view in the upper left.

First, the opening 410 is formed using the same process as shown in Figures 15A to 15H of the fourth embodiment. Next, as shown in Figure 18A, a bottom electrode film 711Z is formed inside the opening 410. Specifically, the bottom electrode film 711Z is formed by depositing TiN to a thickness of 5 to 10 nm on the exposed first wiring layer 310 along the internal shape of the opening 410 using sputtering by ALD, CVD, or IMP.

Then, as shown in FIG. 18B, the lower electrode 711 is formed. Specifically, a resist is applied onto the deposited lower electrode film 711Z, and etch-back is performed under conditions that result in similar selectivity between the resist and the lower electrode film 711Z. This causes the upper end of the lower electrode film 711Z to be recessed from the upper surface of the second insulating layer 400. This results in a lower electrode 711 that covers the bottom and side surfaces of the opening 410 and whose upper end is recessed from the upper surface of the second insulating layer 400.

Next, as shown in FIG. 18C, hafnium oxide (HfOx), a high-dielectric material, is deposited on the lower electrode 711 by CVD or ALD to a thickness of 3 to 10 nm along the internal shape of the opening 410, forming a ferroelectric film 713. Note that the high-dielectric material hafnium oxide (HfOx) is converted into a ferroelectric material by annealing in a subsequent step.

Instead of hafnium oxide, it is also possible to use high-dielectric materials such as zirconium oxide (ZrOx) or hafnium zirconium oxide (HfZrOx). Furthermore, these high-dielectric materials can be converted into ferroelectric materials by doping them with lanthanum (La), silicon (Si), gadolinium (Gd), etc.

Then, TiN is deposited on the ferroelectric film 713 using CVD, ALD, sputtering, or the like to a thickness of 5 to 20 nm so as to fill the opening 410, thereby forming the upper electrode 715. Note that TaN or other materials can also be used to form the upper electrode 715. Next, crystallization annealing is performed to convert the HfOx that constitutes the ferroelectric film 713 into a ferroelectric material. Note that the crystallization annealing to convert HfOx into a ferroelectric material may be performed in this process or in another process. The crystallization annealing temperature can be changed as desired, as long as it is within the range of 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring. Subsequently, CMP or the like is performed to remove excess ferroelectric film 713 and upper electrode 715 deposited on the second insulating layer 400. This completes the formation of the capacitor 71.

Next, as shown in Figure 17, a third insulating layer 600 is formed to cover the second insulating layer 400.

After forming the third insulating layer 600, the via contact 611 and second wiring layer 612 are formed on the upper electrode 715 and upper wiring layer 412. Specifically, the via contact 611 and second wiring layer 612 can be formed using a damascene structure with Cu or other wiring materials. The via contact 611 and second wiring layer 612 may also be formed from Al or other materials. The second wiring layer 612 can also serve as a source line SL by extending in the first direction, for example. The second wiring layer 612 can also be used as wiring that constitutes the logic circuit in the peripheral region.

The above steps allow the semiconductor memory device 10D according to this embodiment to be formed.

6. Sixth Embodiment
(6.1. Configuration example)
Next, a semiconductor memory device according to a sixth embodiment of the present disclosure will be described with reference to Fig. 19. Fig. 19 is a schematic diagram showing the planar configuration and cross-sectional configuration of a semiconductor memory device 10E according to this embodiment.

In the plan view at the top left of Figure 19, the planarization film 200 formed over the entire surface of the semiconductor substrate 100 and the first to third insulating layers 300, 400, and 600 are omitted to clarify the arrangement of each component. Each cross-sectional view in Figure 19 shows a cross section taken along line B-B, line C-C, or line D-D, respectively, shown in the plan view at the top left. Note that line B-B and line C-C represent the cross-sectional configuration of memory cell 10EE of semiconductor memory device 10E, and line D-D represents the cross-sectional configuration of the peripheral region of semiconductor memory device 10E. Memory cell 10EE here refers to the region in which capacitor 81, described below, is provided. The peripheral region refers to the region surrounding the memory cell region in which multiple memory cells 10EE are provided. Logic circuits, for example, are provided in the peripheral region of semiconductor memory device 10E.

As shown in FIG. 19, the semiconductor memory device 10E according to the sixth embodiment differs from the semiconductor memory device 10D according to the fourth embodiment in that it has a capacitor 81 instead of capacitor 71. Below, components that are substantially the same as those in the semiconductor memory device 10D according to the fourth embodiment will be designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

The semiconductor memory device 10E is an FeRAM that includes a capacitor 81 that stores information and a transistor 21 that controls the selection and deselection of the capacitor 81.

Like capacitor 71, capacitor 81 is provided to fill opening 410. Capacitor 81 is composed of a lower electrode 811 provided along the inner surface of opening 410, a ferroelectric film 813 provided on lower electrode 811 along opening 410, and an upper electrode 815 provided on ferroelectric film 813. The lower electrode 811 is electrically connected to the source or drain region 151 (e.g., the source) of transistor 21 via the first wiring layer 310 or the like. The upper electrode 815 is electrically connected to the second wiring layer 612 serving as source line SL.

In the semiconductor memory device 10D of the fourth embodiment described above, the upper surface of the upper electrode 715 is substantially flush with the upper surface of the second insulating layer 400. In contrast, in the semiconductor memory device 10E of this embodiment, the upper electrode 815 protrudes above the upper surface of the second insulating layer 400, i.e., toward the side opposite the semiconductor substrate 100. This increases the options for forming the capacitor 81. Therefore, by selecting an appropriate forming method, it is possible to improve manufacturing yield.

In the semiconductor memory device 10E having the above structure, the capacitance of capacitor 81 can be made larger than the capacitance of capacitor 71 in the semiconductor memory device 10D. Therefore, the semiconductor memory device 10E can ensure a signal with a sufficient margin for its operation. Note that while the semiconductor memory device 10E in Figure 19 illustrates a case in which the area of the upper electrode 815 along the main surface 100S is substantially equal to the area of the lower electrode 811 along the main surface 100S, the area of the upper electrode 815 along the main surface 100S can also be made larger than the area of the lower electrode 811 along the main surface 100S.

(6.2. Manufacturing method)
Next, a method for manufacturing the semiconductor memory device 10E according to this embodiment will be described with reference to Figures 20A and 20B. Figures 20A and 20B are schematic views illustrating one step in the method for manufacturing the semiconductor memory device 10E.

As with FIG. 19, layers extending over the entire surface of the semiconductor substrate 100 are omitted in FIGS. 20A and 20B. The cross-sectional views in FIGS. 20A and 20B each show a cross section taken along line B-B, line C-C, or line D-D, respectively, shown in the plan view in the upper left.

First, the opening 410 is formed using the same process as shown in Figures 15A to 15H of the fourth embodiment.

Next, as shown in FIG. 20A, a bottom electrode film 811Z is formed to completely cover the inside of the opening 410 and the top surface of the second insulating layer 400. Specifically, the bottom electrode film 811Z is formed by depositing TiN to a thickness of 5 to 10 nm on the exposed first wiring layer 310 along the internal shape of the opening 410 using ALD, CVD, or IMP sputtering. The bottom electrode film 811Z is formed uniformly to also cover the top surface of the second insulating layer 400.

Next, a high-dielectric material, hafnium oxide (HfOx), is deposited on the lower electrode film 811Z by CVD or ALD to a thickness of 3 to 10 nm along the internal shape of the opening 410, forming a ferroelectric film 813Z. Note that the high-dielectric material, hafnium oxide (HfOx), is converted into a ferroelectric material by annealing in a subsequent step. The ferroelectric film 813Z is formed uniformly so as to also cover the lower electrode film 811Z, which covers the upper surface of the second insulating layer 400.

Then, TiN is deposited on the ferroelectric film 813Z using CVD, ALD, sputtering, or the like to a thickness of 5 to 20 nm so as to fill the opening 410, thereby forming the upper electrode film 815Z. Note that TaN or the like can also be used as a material for forming the upper electrode film 815Z. Next, crystallization annealing is performed to convert the HfOx that constitutes the ferroelectric film 813Z into a ferroelectric material. Note that the crystallization annealing to convert HfOx into a ferroelectric material may be performed in this process or in another process. The crystallization annealing temperature can be changed as desired, as long as it is within the range of 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring.

After that, using a resist patterned by lithography as a mask, anisotropic etching is performed on the upper electrode film 815Z, the ferroelectric film 813Z, and the lower electrode film 811Z in that order. This forms a plurality of capacitors 81 each having an upper electrode 815, a ferroelectric film 813, and a lower electrode 811, as shown in FIG. 20B, for example. Either dry etching or wet etching can be used for the anisotropic etching.

7. Seventh embodiment
(7.1. Configuration example)
Next, a semiconductor memory device according to a seventh embodiment of the present disclosure will be described with reference to Fig. 21. Fig. 21 is a schematic diagram showing the planar configuration and cross-sectional configuration of a semiconductor memory device 10F according to this embodiment.

In the plan view at the top left of Figure 21, the planarization film 200 formed over the entire surface of the semiconductor substrate 100 and the first to third insulating layers 300, 400, and 600 are omitted to clarify the arrangement of each component. Each cross-sectional view in Figure 21 shows a cross section taken along line B-B, line C-C, or line D-D, respectively, shown in the plan view at the top left. Note that lines B-B and C-C represent the cross-sectional configuration of memory cell 10FF of semiconductor memory device 10F, and line D-D represents the cross-sectional configuration of the peripheral region of semiconductor memory device 10F. Memory cell 10FF here refers to the region in which capacitor 91, described below, is provided. The peripheral region refers to the region surrounding the memory cell region in which multiple memory cells 10FF are provided. Logic circuits, for example, are provided in the peripheral region of semiconductor memory device 10F.

As shown in FIG. 21, the semiconductor memory device 10F according to the seventh embodiment differs from the semiconductor memory device 10C according to the fourth embodiment in that it has a capacitor 91 instead of capacitor 51. Below, components that are substantially the same as those in the semiconductor memory device 10C according to the fourth embodiment will be designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

The semiconductor memory device 10F is an FeRAM that includes a capacitor 91 that stores information and a transistor 21 that controls the selection and deselection of the capacitor 91.

The capacitor 91 is provided to fill the opening 420. However, unlike the opening 410, the opening 420 is provided to penetrate only the second insulating layer 400. The capacitor 91 includes a lower electrode 911 provided along the inner surface of the opening 420, a ferroelectric film 913 provided on the lower electrode 911 along the opening 420, and an upper electrode 915 provided on the ferroelectric film 913. An upper wiring layer 313 is provided below the lower electrode 911. The upper wiring layer 313 is exposed on the upper surface of the first insulating layer 300 and is electrically connected to the lower surface of the lower electrode 911. The area of the upper wiring layer 313 along the main surface 100S is equal to or greater than the area of the lower electrode 911 along the main surface 100S. A via contact 311 is provided below the upper wiring layer 313. The via contact 311 electrically connects the upper wiring layer 313 to the first wiring layer 310. Therefore, the lower electrode 911 is electrically connected to the source or drain region 151 (e.g., the source) of the transistor 21 via the first wiring layer 310, etc. The upper electrode 915 is electrically connected to the second wiring layer 612 as the source line SL.

In the semiconductor memory device 10F of this embodiment, the lower electrode 911 is electrically connected to the source or drain region 151 (e.g., the source) of the transistor 21 via an upper wiring layer 313 having a larger area than the first wiring layer 310. This facilitates alignment of the lower electrode 911 with the first wiring layer 310, thereby improving manufacturing yield. Furthermore, since the capacitor 91 is provided so as to fill only the opening 420 that penetrates only the second insulating layer 400, the manufacturing process can be simplified compared to forming an opening 410 that includes a lower portion 410L having a relatively small area and an upper portion 410U having a relatively large area. Furthermore, the lower electrode 911 of the capacitor 91 is not directly connected to the first wiring layer 310 serving as a bit line, but is instead in contact with the upper wiring layer 313, which is the layer above the first wiring layer 310. If the lower electrode 911 of the capacitor 91 were to be in direct contact with the first wiring layer 310, which has many layout constraints, forming the capacitor 91 would require, for example, two photolithography steps. However, if the lower electrode 911 is formed so that it contacts the upper wiring layer 313, the capacitor 91 can be formed with a single photolithography step. This is because there are fewer layout constraints on the upper wiring layer 313 than on the first wiring layer 310. This simplifies the manufacturing process.

(7.2. Manufacturing method)
22A to 22D, a method for manufacturing the semiconductor memory device 10F according to this embodiment will be described. Figures 22A to 22D are schematic views illustrating one step in the method for manufacturing the semiconductor memory device 10F.

As with FIG. 21, layers extending over the entire surface of semiconductor substrate 100 are omitted from FIGS. 22A to 22D. Each of the cross-sectional views in FIGS. 22A to 22D shows a cross section taken along line B-B, line C-C, or line D-D, respectively, shown in the plan view in the upper left.

First, a first insulating layer 300 is formed using the same process as shown in Figures 15A to 15F of the fourth embodiment. After the first insulating layer 300 is formed, as shown in Figure 22A, a via contact 311 and an upper wiring layer 312 are sequentially formed on the first wiring layer 310 in the peripheral region. Furthermore, a via contact 311 and an upper wiring layer 313 are sequentially formed on the first wiring layer 310 in the memory cell region. Specifically, the via contact 311 and the upper wiring layers 312 and 313 can be formed using a damascene structure using Cu or the like as the wiring material. Note that the via contact 311 and the upper wiring layers 312 and 313 may also be formed from Al or the like.

Next, as shown in FIG. 22B, a second insulating layer 400 is formed to cover the first insulating layer 300 in the same manner as in the fourth embodiment. After the second insulating layer 400 is formed, a via contact 411 and an upper wiring layer 412 are formed on the upper wiring layer 312 in the same manner as in the fourth embodiment.

Next, as shown in Figure 22C, an opening 420 is formed to expose the upper wiring layer 313 in the memory cell region. Specifically, the opening 420 is formed by selectively digging down the second insulating layer 400 using anisotropic etching with a lithographically patterned resist as a mask. The opening 420 is formed with a width of, for example, 60 nm to 150 nm. If the aspect ratio of the opening 420 is approximately 20 or less, the etching to form the opening 420 and the subsequent filling of the opening 420 by deposition can be carried out without any problems. Anisotropic etching can be performed using, for example, a fluorocarbon-based gas. Furthermore, the use of the liner layer described above allows for the etching to be stopped with good control.

Next, as shown in Figure 22D, a capacitor 91 is formed inside the opening 420.

Specifically, first, a lower electrode 911 is formed by depositing TiN to a thickness of 5 to 10 nm on the exposed upper wiring layer 313 along the internal shape of the opening 420 using ALD, CVD, or IMP sputtering.

Next, hafnium oxide (HfOx), a high-dielectric material, is deposited on the lower electrode 911 by CVD or ALD to a thickness of 3 to 10 nm along the internal shape of the opening 420, forming the ferroelectric film 513. Note that the high-dielectric material hafnium oxide (HfOx) is converted into a ferroelectric material by annealing in a later stage.

Instead of hafnium oxide, it is also possible to use high-dielectric materials such as zirconium oxide (ZrOx) or hafnium zirconium oxide (HfZrOx). Furthermore, these high-dielectric materials can be converted into ferroelectric materials by doping them with lanthanum (La), silicon (Si), gadolinium (Gd), etc.

Then, TiN is deposited on the ferroelectric film 913 using CVD, ALD, sputtering, or the like to a thickness of 5 to 20 nm so as to fill the opening 420, thereby forming the upper electrode 915. Note that TaN or other materials can also be used to form the upper electrode 915. Next, crystallization annealing is performed to convert the HfOx that constitutes the ferroelectric film 913 into a ferroelectric material. Note that the crystallization annealing to convert HfOx into a ferroelectric material may be performed in this process or in another process. The crystallization annealing temperature can be changed as desired, as long as it is within the range of 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring. Subsequently, CMP or the like is performed to remove excess ferroelectric film 913 and upper electrode 915 deposited on the second insulating layer 400. This completes the formation of the capacitor 91.

Next, in the same manner as in the fourth embodiment, the third insulating layer 600 is formed, the via contact 611 is formed, and the second wiring layer 612 is formed.

The above steps allow the semiconductor memory device 10F according to this embodiment to be formed.

The technology disclosed herein has been described above using the first to seventh embodiments and modifications. However, the technology disclosed herein is not limited to the above embodiments, and various modifications are possible.

Furthermore, not all of the configurations and operations described in each embodiment are necessarily essential to the configurations and operations of the present disclosure. For example, among the components in each embodiment, any components that are not recited in the independent claims that represent the superordinate concept of the present disclosure should be understood to be optional components.

Terms used throughout this specification and the appended claims should be interpreted as "open-ended" terms. For example, the terms "include" or "including" should be interpreted as "not limited to the manner described as including." The term "having" should be interpreted as "not limited to the manner described as having."

The terms used in this specification include terms that are used merely for the convenience of explanation and are not intended to limit the configuration or operation. For example, terms such as "right," "left," "upper," and "lower" merely indicate directions on the drawings to which reference is made. Furthermore, the terms "inner" and "outer" merely indicate directions toward and away from the center of the focused element, respectively. The same applies to similar terms and terms of a similar meaning.

The technology according to the present disclosure may also have the following configuration. According to the technology according to the present disclosure having the following configuration, the semiconductor memory device can increase the area of the capacitor without increasing the area of the memory cell, thereby further increasing the capacitance of the capacitor. This allows the semiconductor memory device to obtain a sufficient margin for operation. The effects achieved by the technology according to the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described in the present disclosure.
(1)
a field effect transistor provided on a semiconductor substrate;
an interlayer insulating film provided on the semiconductor substrate;
a contact that penetrates the interlayer insulating film and electrically connects to the drain of the field effect transistor;
a first wiring layer provided on the contact;
a first insulating layer provided on the interlayer insulating film and burying the first wiring layer;
an opening provided in the first insulating layer and the interlayer insulating film from a layer above the first wiring layer;
a ferroelectric capacitor provided inside the opening and electrically connected to the source of the field effect transistor.
(2)
The semiconductor memory device described in (1) above, wherein the ferroelectric capacitor includes a lower electrode provided along the internal shape of the opening, a ferroelectric film provided on the lower electrode, and an upper electrode provided on the ferroelectric film so as to fill the opening.
(3)
the lower electrode is electrically connected to the source of the field effect transistor;
The semiconductor memory device according to (2) above, wherein the upper electrode is electrically connected to a second wiring layer provided on the first insulating layer.
(4)
The semiconductor memory device according to (3) above, wherein the second wiring layer is provided extending in the same direction as the first wiring layer.
(5)
The semiconductor memory device according to (3) or (4) above, wherein the first wiring layer is a bit line, and the second wiring layer is a source line.
(6)
the first wiring layer is provided extending in a first direction within a surface of the semiconductor substrate,
The semiconductor memory device according to any one of (1) to (5) above, wherein the gate electrode of the field effect transistor is provided extending in a second direction perpendicular to the first direction.
(7)
the field effect transistor is provided in an active region of the semiconductor substrate;
The semiconductor memory device according to (6) above, wherein the activation region is provided extending in a third direction obliquely intersecting the first direction and the second direction.
(8)
a field effect transistor provided on a semiconductor substrate;
an interlayer insulating film provided on the semiconductor substrate;
an opening including a first opening formed in the interlayer insulating film and a second opening having a smaller diameter than the first opening and formed inside the first opening;
a ferroelectric capacitor provided inside the opening and electrically connected to the source of the field effect transistor.
(9)
a field effect transistor provided on a semiconductor substrate;
an interlayer insulating film provided on the semiconductor substrate;
a contact that penetrates the interlayer insulating film and electrically connects to the drain of the field effect transistor;
a ferroelectric capacitor provided at least inside an opening provided through the interlayer insulating film at a height different from that of the contact, and electrically connected to a source of the field effect transistor.
(10)
forming a field effect transistor in a semiconductor substrate;
forming an interlayer insulating film on the semiconductor substrate;
forming a contact that penetrates the interlayer insulating film and electrically connects to the drain of the field effect transistor;
forming a first wiring layer on the contact;
forming a first insulating layer on the interlayer insulating film to embed the first wiring layer;
forming an opening in the first insulating layer and the interlayer insulating film from a layer above the first wiring layer;
forming a ferroelectric capacitor inside the opening, the ferroelectric capacitor being electrically connected to the source of the field effect transistor.
(11)
forming a field effect transistor in a semiconductor substrate;
forming an interlayer insulating film on the semiconductor substrate;
forming a first opening in the interlayer insulating film;
forming a second opening inside the first opening, the second opening having a smaller opening diameter than the first opening;
forming a ferroelectric capacitor electrically connected to a source of the field effect transistor inside an opening including the first opening and the second opening.
(12)
a semiconductor substrate having a main surface;
a field effect transistor having a drain and a source provided on the semiconductor substrate;
an interlayer insulating film provided on the semiconductor substrate;
a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field effect transistor;
a first wiring layer provided on the opposite side of the contact from the field effect transistor and electrically connected to the contact;
a first insulating layer provided on the interlayer insulating film and burying the first wiring layer;
a ferroelectric capacitor provided on an opposite side of the field effect transistor from the first wiring layer, the ferroelectric capacitor being electrically connected to the source of the field effect transistor.
(13)
a second insulating layer provided on the opposite side of the semiconductor substrate from the first wiring layer and extending to a circuit region including a logic circuit;
The semiconductor memory device according to (12) above, wherein the ferroelectric capacitor is provided in the first insulating layer and the second insulating layer.
(14)
Further comprising a second wiring layer;
the ferroelectric capacitor has a lower electrode, an upper electrode, and a ferroelectric film sandwiched between the lower electrode and the upper electrode;
the lower electrode is electrically connected to the source;
The semiconductor memory device according to (12) or (13) above, wherein the upper electrode is electrically connected to the second wiring layer.
(15)
The semiconductor memory device according to (14) above, wherein the second wiring layer is provided on the opposite side of the semiconductor substrate as viewed from the first wiring layer.
(16)
The semiconductor memory device according to (14) or (15) above, wherein the first wiring layer and the second wiring layer are both provided extending in a first direction along the main surface.
(17)
the first wiring layer is a bit line,
The semiconductor memory device according to any one of (14) to (16) above, wherein the second wiring layer is a source line.
(18)
the first wiring layer extends in a first direction along the main surface,
The semiconductor memory device according to any one of (12) to (17), wherein the field effect transistor further has a gate electrode extending in a second direction substantially perpendicular to the first direction.
(19)
the semiconductor substrate has an activation region that extends in a third direction obliquely intersecting both the first direction and the second direction and along the main surface;
The semiconductor memory device according to (18) above, wherein the field effect transistor is provided in the activation region.
(20)
The semiconductor memory device according to (14) above, wherein a first area of the upper electrode along the main surface is larger than a second area of a connection portion between the lower electrode and the source along the main surface.
(21)
The semiconductor memory device according to (14) above, wherein a third area of the upper electrode along the main surface is equal to or greater than a fourth area of the lower electrode along the main surface.
(22)
a third wiring layer provided in a layer between the ferroelectric capacitor and the first wiring layer;
The semiconductor memory device according to (12), wherein the ferroelectric capacitor is electrically connected to the first wiring layer via the third wiring layer.

10, 10A, 10B...Semiconductor memory device, 11...Capacitor, 21...Transistor, 100...Semiconductor substrate, 105...Element isolation layer, 110...Opening, 110A...First opening, 110B...Second opening, 111...Lower electrode, 113...Ferroelectric film, 115...Upper electrode, 130...Gate electrode, 131...Cap layer, 132...Sidewall insulating film, 140...Gate insulating film, 150...Active region, 151...Source or drain region, 152...Contact region, 200...Planarization film, 201...Interlayer insulating film, 210...Contact, 210A...Conductive layer, 210B...Barrier metal layer, 300...First insulating layer, 310...First wiring layer, 311...Via contact, 312...Upper wiring layer, 320...Second wiring layer

Claims (10)

a semiconductor substrate having a main surface;
a field effect transistor having a drain and a source provided on the semiconductor substrate;
an interlayer insulating film provided on the semiconductor substrate;
a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field effect transistor;
a first wiring layer provided on the opposite side of the semiconductor substrate from the contact and electrically connected to the contact;
a first insulating layer provided on the interlayer insulating film and burying the first wiring layer;
a ferroelectric capacitor provided on the opposite side of the semiconductor substrate from the first wiring layer, the ferroelectric capacitor having a lower electrode electrically connected to the source of the field effect transistor, an upper electrode, and a ferroelectric film sandwiched between the lower electrode and the upper electrode;
a second wiring layer provided on the opposite side of the semiconductor substrate as viewed from the ferroelectric capacitor, the second wiring layer being electrically connected to the upper electrode;
a second insulating layer provided on the opposite side of the semiconductor substrate from the first wiring layer and extending to a circuit region including a logic circuit ;
Equipped with
a first area of the upper electrode along the main surface is larger than a second area of a connection portion between the lower electrode and the source along the main surface;
the field effect transistor, the first wiring layer, the ferroelectric capacitor, and the second wiring layer are provided in different layers in a stacking direction orthogonal to the main surface,
The ferroelectric capacitor is provided in the first insulating layer and the second insulating layer.
Semiconductor memory device. The semiconductor memory device according to claim 1 , wherein the second wiring layer is provided on the opposite side of the semiconductor substrate from the first wiring layer. The semiconductor memory device according to claim 1 , wherein the first wiring layer and the second wiring layer are both provided extending in a first direction along the main surface. the first wiring layer is a bit line,
2. The semiconductor memory device according to claim 1, wherein the second wiring layer is a source line. the first wiring layer extends in a first direction along the main surface,
2. The semiconductor memory device according to claim 1, wherein the field effect transistor further includes a gate electrode extending in a second direction substantially perpendicular to the first direction. the semiconductor substrate has an activation region that extends in a third direction obliquely intersecting both the first direction and the second direction and along the main surface;
The semiconductor memory device according to claim 5 , wherein the field effect transistor is provided in the active region. 2. The semiconductor memory device according to claim 1, wherein a third area of said upper electrode along said main surface is equal to or greater than a fourth area of said lower electrode along said main surface. 2. The semiconductor memory device according to claim 1, wherein the lower electrode includes a bottom portion extending along the main surface and facing the upper electrode in the stacking direction, and a wall portion erected on the bottom portion so as to surround the periphery of the upper electrode along the main surface via the ferroelectric film. a semiconductor substrate having a main surface;
a field effect transistor having a drain and a source provided on the semiconductor substrate;
an interlayer insulating film provided on the semiconductor substrate;
a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field effect transistor;
a first wiring layer provided on the opposite side of the semiconductor substrate from the contact and electrically connected to the contact;
a first insulating layer provided on the interlayer insulating film and burying the first wiring layer;
a ferroelectric capacitor provided on the opposite side of the semiconductor substrate from the first wiring layer, the ferroelectric capacitor having a lower electrode electrically connected to the source of the field effect transistor, an upper electrode, and a ferroelectric film sandwiched between the lower electrode and the upper electrode;
a second wiring layer provided on the opposite side of the semiconductor substrate as viewed from the ferroelectric capacitor and electrically connected to the upper electrode;
Equipped with
a first area of the upper electrode along the main surface is larger than a second area of a connection portion between the lower electrode and the source along the main surface;
the field effect transistor, the first wiring layer, the ferroelectric capacitor, and the second wiring layer are provided in different layers in a stacking direction orthogonal to the main surface,
The semiconductor memory device , wherein the first wiring layer and the second wiring layer are both provided to extend in a first direction along the main surface . a semiconductor substrate having a main surface;
a field effect transistor having a drain and a source provided on the semiconductor substrate;
an interlayer insulating film provided on the semiconductor substrate;
a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field effect transistor;
a first wiring layer provided on the opposite side of the semiconductor substrate from the contact and electrically connected to the contact;
a first insulating layer provided on the interlayer insulating film and burying the first wiring layer;
a ferroelectric capacitor provided on the opposite side of the semiconductor substrate from the first wiring layer, the ferroelectric capacitor having a lower electrode electrically connected to the source of the field effect transistor, an upper electrode, and a ferroelectric film sandwiched between the lower electrode and the upper electrode;
a second wiring layer provided on the opposite side of the semiconductor substrate as viewed from the ferroelectric capacitor and electrically connected to the upper electrode;
Equipped with
a first area of the upper electrode along the main surface is larger than a second area of a connection portion between the lower electrode and the source along the main surface;
the field effect transistor, the first wiring layer, the ferroelectric capacitor, and the second wiring layer are provided in different layers in a stacking direction orthogonal to the main surface,
The lower electrode includes a bottom portion that extends along the main surface and faces the upper electrode in the stacking direction, and a wall portion that stands on the bottom portion so as to surround the periphery of the upper electrode along the main surface via the ferroelectric film.
Semiconductor memory device.