JP7753325B2 - Light-emitting display device - Google Patents

Description

The present invention relates to a light-emitting display device, and more particularly to a light-emitting display device having a structure that prevents leakage current between adjacent subpixels. More specifically, the present invention addresses visibility problems caused by leakage current between adjacent subpixels that occurs when the spacing between subpixels becomes narrower at high resolutions, and relates to a light-emitting display device that improves color reproduction by blocking leakage current that occurs between adjacent subpixels.

Recent display devices that can display a variety of information and interact with users viewing that information are required to come in a variety of sizes, shapes, and functions.

Such display devices include liquid crystal display devices (LCDs), electrophoretic display devices (FPDs), and light-emitting diode display devices (LEDs).

Emitting-light displays are self-emitting displays that, unlike liquid crystal displays (LCDs), do not require a separate light source, making them lightweight and thin. Furthermore, emissive displays are advantageous in terms of power consumption due to their low voltage operation, and they also offer excellent color configuration, response speed, viewing angle, and contrast ratio (CR), making them the subject of research as next-generation displays.

The following description assumes that the light-emitting display device is an organic light-emitting display device, but the type of light-emitting layer is not limited to this.

Light-emitting displays display information on a screen by emitting light from multiple pixels containing a light-emitting layer with a light-emitting material layer. Depending on the method of driving the pixels, light-emitting displays can be classified as active matrix type light-emitting displays or passive matrix type light-emitting displays.

Active matrix type light-emitting display devices use thin film transistors (or "TFTs") to control the current flowing through light-emitting diodes to display images.

A light-emitting display device has an anode electrode, a light-emitting layer, and a cathode electrode. When voltage is applied to the anode electrode and the cathode electrode, holes move from the anode electrode and electrons move from the cathode electrode to the light-emitting layer. When holes and electrons combine in the light-emitting layer, excitons are formed during the excitation process, and light is generated by the energy from the excitons.

In order to provide high-quality image information, the resolution of light-emitting display devices is gradually increasing. As the resolution increases, the distance between each sub-pixel becomes narrower, but this can lead to problems such as distortion of image information due to current leaking laterally between adjacent pixels.

In order to create high-resolution light-emitting displays, various studies have been conducted to prevent lateral leakage current (LLC), but the results are still insufficient, and there is an urgent need for development to address this issue.

The problem to be solved by the present invention is to provide a light-emitting display device having a bank trench including at least one second spacer between adjacent subpixels to block or reduce horizontal leakage current that increases as the spacing between adjacent subpixels decreases.

Another problem that the present invention aims to solve is to provide a light-emitting display device that prevents electrons formed inside the light-emitting layer during operation from moving to adjacent subpixels by cutting the light-emitting layer disposed between adjacent subpixels to prevent electrons from moving to adjacent subpixels.

Another problem that the present invention aims to solve is to provide a light-emitting display device that has a structure that blocks horizontal leakage current to resolve the poor visibility caused by adjacent subpixels emitting light at low gradations and improve color reproduction.

According to an embodiment of the present invention, a light-emitting display device may include a substrate having first and second subpixels, each of which includes a light-emitting portion and a non-light-emitting portion surrounding the light-emitting portion; first electrodes disposed in the first and second subpixels, respectively; a bank including a bank hole located in the light-emitting portion and a bank trench located in the non-light-emitting portion; second spacers disposed in the bank trenches; a light-emitting layer disposed on the first electrode and the second spacers, including a plurality of stacks and at least one charge generation layer disposed between the plurality of stacks; and a second electrode disposed on the light-emitting layer.

The light emitting display device according to an embodiment of the present invention can block horizontal leakage current that increases as the spacing between adjacent subpixels decreases by disposing a bank trench including at least one second spacer.

In the light-emitting display device according to an embodiment of the present invention, the light-emitting layer is separated between adjacent subpixels by a bank trench including at least one second spacer, thereby preventing electrons formed in the light-emitting layer during operation from moving to adjacent pixels.

The light-emitting display device according to an embodiment of the present invention blocks horizontal leakage current between adjacent subpixels, thereby resolving poor visibility caused by adjacent pixels emitting light at low gradations and improving color reproduction.

The effects of the present invention are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1 is a plan view of a light emitting display device according to an embodiment of the present invention; 10 is a diagram illustrating a bank trench including a subpixel and a second spacer according to an embodiment of the present invention; 1 is a cross-sectional view of a light emitting display device according to an embodiment of the present invention. 2A to 2C are cross-sectional views illustrating a manufacturing process of a light emitting display device according to an embodiment of the present invention. 2A to 2C are cross-sectional views illustrating a manufacturing process of a light emitting display device according to an embodiment of the present invention. 2A to 2C are cross-sectional views illustrating a manufacturing process of a light emitting display device according to an embodiment of the present invention. 2A to 2C are cross-sectional views illustrating a manufacturing process of a light emitting display device according to an embodiment of the present invention. 1 is a diagram illustrating a light emitting layer according to an embodiment of the present invention.

The advantages and features of the present invention, as well as methods for achieving them, will become apparent from the detailed description of the embodiments set forth below in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and may be configured in a variety of different forms. However, these embodiments are provided so that the disclosure of the present invention will be complete and complete, and will fully convey the scope of the invention to those skilled in the art. The present specification is defined only by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating embodiments of the present invention are illustrative only and the present invention is not limited to the illustrated details. The same reference symbols refer to the same elements throughout the specification. Furthermore, in the description of this specification, if it is deemed that a detailed description of related prior art may unnecessarily obscure the gist of the present invention, such a detailed description will be omitted. When words such as "comprise," "have," and "consist" are used in this specification, other parts may be added unless "only" is used. When a component is expressed in the singular, this also includes the plural unless otherwise explicitly stated.

When interpreting elements, the error range is interpreted as being included even if there is no separate explicit mention of the error range.

When describing the positional relationship between two parts, for example, when the positional relationship between two parts is described using terms such as "above," "on top," "below," or "beside," one or more other parts may be located between the two parts, as long as terms such as "immediately" or "directly" are not used.

When describing a temporal relationship, if the temporal sequence is explained using terms such as "after," "following," "next," or "before," it can also include cases where the sequence is not consecutive, as long as "immediately" or "directly" is not used.

Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may also be a second component within the technical spirit of the present invention.

In describing components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are merely used to distinguish the component from other components, and do not limit the nature, order, sequence, or number of the components. When a component is described as being "coupled," "coupled," or "connected" to another component, it should be understood that the component may be directly coupled or connected to the other component, but unless otherwise expressly stated, other components may be "intervening" between components that may be indirectly coupled or connected.

"At least one" should be understood to include all combinations of one or more of the associated components. For example, "at least one of the first, second, and third components" means not only the first, second, or third component, but also all combinations of two or more of the first, second, and third components.

In this specification, "device" may include display devices such as a liquid crystal module (LCM) or an organic light emitting display module (OLED module), which include a display panel and a driver for driving the display panel. It may also include set electronic apparatuses or set devices or set apparatuses, such as complete or final products including notebook computers, televisions, computer monitors, automotive apparatuses or other forms of vehicles, and mobile electronic apparatuses such as smartphones or electronic pads, including LCMs, OLED modules, etc.

Therefore, the term "device" in this specification can include display devices themselves, such as LCMs, OLED modules, etc., as well as set devices, which are application products or end-use consumer devices that include LCMs, OLED modules, etc.

In some embodiments, an LCM/OLED module composed of a display panel, a driver, etc. may be referred to as a "display device," and a completed electronic device including the LCM/OLED module may be referred to as a "set device." For example, a display device may include a liquid crystal display (LCD) or organic light emitting diode (OLED) display panel and a source PCB, which is a controller for driving the display panel. The set device may further include a set PCB, which is a set controller electrically connected to the source PCB and drives the entire set device.

The display panel used in embodiments of the present invention may be any type of display panel, such as a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, or an electroluminescent display panel, and embodiments are not limited thereto. For example, the display panel may be a display panel that can generate sound by vibrating using a vibration device according to embodiments of the present invention. The display panel used in the display device according to embodiments of the present invention is not limited in shape or size.

The features of the various embodiments of the present invention may be partially or fully combined or combined with each other, and various technical linkages and operations are possible. Each embodiment may be implemented independently of the others, or may be implemented together in a related relationship.

The following detailed description of the embodiments of the present invention will be given with reference to the accompanying drawings and examples. The scales of the components shown in the drawings are different from the actual scales for the convenience of explanation and should not be construed as being limited to the scales shown in the drawings.

Various embodiments of the present invention will now be described in detail with reference to the drawings.

Figure 1 is a plan view of a light-emitting display device according to an embodiment of the present invention.

Referring to FIG. 1, the light emitting display device 100 of the present invention may include various additional elements for generating various signals and driving a plurality of subpixels SP_1, SP_2, and SP_3 in the display area AA. For example, one or more driving circuits for controlling a display panel may be included in the light emitting display device 100. The driving circuits for controlling (or driving) the subpixels SP_1, SP_2, and SP_3 may include a gate driver 112, a data signal line, a multiplexer (MUX), an electrostatic discharge (ESD) circuit, a high potential voltage wiring VDD, a low potential voltage wiring VSS, an inverter circuit, etc. The light emitting display device 100 may also include additional elements in addition to the function for driving the subpixels SP_1, SP_2, and SP_3. For example, the light emitting display device 100 may include additional elements that provide a touch sensing function, a user authentication function (e.g., fingerprint recognition), a multi-level pressure sensing function, a tactile feedback function, etc. The aforementioned additional elements may be located in the non-display area NA or an external circuit connected to the connection interface.

The substrate 110 may include a display area (active area, AA) and a non-active area (non-active area, NA). The display area AA of the substrate 110 may be an area where a plurality of pixels P are arranged and an image is displayed. The non-active area NA of the substrate 110 may be an area where an image is not displayed. For example, the non-active area NA may be a bezel area, and is not limited to this term. The non-active area NA may be adjacent to the display area AA and arranged outside the display area AA. Alternatively, the non-active area NA may be arranged to surround all or part of the display area AA. Alternatively, the non-active area NA may be an area where a plurality of sub-pixels SP_1, SP_2, and SP_3 are not arranged, and is not limited thereto.

The pixel P arranged in the display area AA may further include a plurality of subpixels SP_1, SP_2, and SP_3. The subpixels SP_1, SP_2, and SP_3 are individual units that emit light, and the plurality of subpixels SP may include, but are not limited to, a red subpixel SP_R, a green subpixel SP_G, a blue subpixel SP_B, and/or a white subpixel.

Each of the sub-pixels SP_1, SP_2, and SP_3 includes an organic light-emitting diode (OLED) and a driving circuit. For example, each of the sub-pixels SP_1, SP_2, and SP_3 may include a display element for displaying an image and a driving circuit for driving (or controlling) the display element.

One subpixel SP may include multiple transistors, capacitors, and multiple wirings. For example, the subpixel SP may be composed of two transistors and one capacitor (2T1C), but is not limited to this. It may also be composed of a subpixel that applies 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T2, 8T2C, etc.

The non-display area NA is an area where various wirings, driving circuits, etc. for driving the multiple sub-pixels SP_1, SP_2, and SP_3 arranged in the display area AA are arranged. For example, various ICs and driving circuits such as the gate driver 112 and data driver may be arranged in the non-display area NA.

In FIG. 1, the non-display area NA is illustrated as surrounding the rectangular display area AA, but the shape of the display area AA and the shape and arrangement of the non-display area NA adjacent to the display area AA are not limited to the example shown in FIG. 1. The display area AA and the non-display area NA may have shapes suitable for the design of an electronic device incorporating the light emitting display device 100. In the case of a display device for a wearable device, the display area AA may have a circular shape like a typical wristwatch, and the concept of the present embodiment may also be applied to a free-form display device applicable to a vehicle instrument panel, etc. Exemplary shapes of the display area AA may be, but are not limited to, a pentagon, hexagon, octagon, circle, ellipse, etc.

A bending area (BA) may be provided in a portion of the non-display area NA. The bending area BA may be provided between the display area AA and the pad portion 114 located in the non-display area NA. The bending area BA may also be an area where a connecting wiring portion is formed.

The bending area BA may be a bent area of the substrate 110 to position the pad portion 114 and an external module bonded to the pad portion 114 toward the rear side of the substrate 110. For example, if the bending area BA is bent toward the rear side of the substrate 110, the external module bonded to the pad portion 114 of the substrate 110 may move toward the rear side of the substrate 110, making it impossible to see the external module when viewed from above the substrate 110. FIG. 1 shows a plan view of the light emitting display device 100 in which the pad portion 114 is visible before the bending area BA is bent. However, after the bending area BA is bent, the pad portion 114 is positioned at the top of the rear side of the light emitting display device 100, making the pad portion 114 invisible from the front side of the light emitting display device 100. Furthermore, the bending of the bending area BA reduces the size of the non-display area NA visible from the top of the substrate 110, thereby forming a narrow bezel. Although the present invention has been illustrated with the bending area BA being present in the non-display area NA, this is not limiting. For example, the bending area BA can be located in the display area AA, and since the display area AA itself can be bent in various directions, the bending area BA located in the display area AA can also have the effects described in the present invention.

A pad portion 114 is disposed on one side of the non-display area NA. The pad portion 114 is a metal pattern to which an external module, such as a flexible printed circuit board (FPCB) or a chip on film (COF), is bonded. Although the pad portion 114 is illustrated as being disposed on one side of the substrate 110, the shape and arrangement of the pad portion 114 are not limited thereto.

A gate driver 112 that provides gate signals to the thin film transistors may be disposed on the other side of the non-display area NA. The gate driver 112 includes various gate driving circuits, which may be formed directly on the substrate 110. In this case, the gate driver 112 may be a GIP (Gate-In-Panel).

The gate driver 112 may be disposed between a dam (DAM) disposed in the display area and non-display area NA of the substrate 110.

A high-potential voltage wiring VDD, a low-potential voltage wiring VSS, a multiplexer (MUX), an electrostatic discharge (ESD) circuit, and multiple connecting wiring sections may be arranged between the display area AA and the pad section 114 of the non-display area NA.

High-potential voltage wiring VDD, low-potential voltage wiring VSS, a multiplexer (MUX), and an electrostatic discharge (ESD) circuit unit may be arranged between the display area AA and the bending area BA.

The connecting wiring section may be arranged in the non-display area NA. For example, it may be arranged in a bending area BA of the non-display area NA where the substrate bends. The connecting wiring section may be configured to transmit signals (voltages) from an external module bonded to the pad section 114 to the display area AA or a circuit section such as the gate driver 112. For example, various signals such as various signals for driving the gate driver 112, data signals, high potential voltages, and low potential voltages may be transmitted through the connecting wiring section.

A dam (DAM) may be placed in the non-display area NA so as to surround all or part of the display area AA. The dam (DAM) may be placed adjacent to the display area AA but outside the display area AA.

The dam (DAM) may be arranged along the periphery of the display area AA to control the flow of the organic layer, which is the material of the second sealing layer among the sealing layers described below that is arranged on the light-emitting layer. The number of dams (DAM) may be one or more.

The dam (DAM) may be arranged between the display area AA and the high-potential voltage wiring VDD, the low-potential voltage wiring VSS, the multiplexer (MUX), or the electrostatic discharge (ESD) circuit unit.

Crack detection wiring (Panel Crack Detector, PCD) may also be arranged in a portion of the non-display area NA of the substrate 110.

The crack detection wiring (PCD) may be disposed between the end point (or termination) of the substrate 110 and the dam (DAM). Alternatively, the crack detection wiring (PCD) may be disposed below the dam (DAM) and overlap at least partially with the dam (DAM).

Figure 2 is a diagram illustrating a bank trench including a subpixel and a second spacer according to an embodiment of the present invention.

Referring to FIG. 2, the substrate 110 may include a light-emitting portion EA and a non-light-emitting portion NEA surrounding the light-emitting portion. The light-emitting portions EA may be arranged in multiple numbers on the substrate, spaced apart from one another. The non-light-emitting portion NEA may be arranged surrounding the light-emitting portion.

The light-emitting portion EA is the area where light is emitted from the light-emitting layer to the outside, and referring to Figure 3, it may be an area where the bank 320 is not arranged.

The non-light-emitting area NEA is an area where light is not emitted from the light-emitting layer to the outside, and referring to FIG. 3, it may be an area where the bank 320 is arranged.

The plurality of pixels P arranged in the display area AA may include a first subpixel SP_1, a second subpixel SP_2, and a third subpixel SP_3.

Each of the first to third sub-pixels SP_1, SP_2, and SP_3 may include an emission portion EA.

A pixel P may have one subpixel SP arranged therein, each of which emits a different color. For example, each pixel P may include one first subpixel SP_1, one second subpixel SP_2, and one third subpixel SP_3, each of which emits a different color.

Alternatively, one pixel P may be arranged with at least one subpixel SP emitting different colors, as shown in FIG. 2. For example, at least two second subpixels SP_2 may be arranged.

Example shapes of the first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3 may be, but are not limited to, a square, a pentagon, a hexagon, an octagon, a circle, an ellipse, etc.

The first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3 can emit light of different colors, and the first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3 can emit at least one of red, green, and blue.

The third subpixel SP_3 may have a larger area than the other subpixels. Referring to FIG. 2, the third subpixel SP_3 may be larger than the first subpixel SP_1 and larger than the second subpixel SP_2.

By configuring a light-emitting display device with a high resolution, the separation distance between the first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3 becomes smaller.

The light-emitting display device 100 may include a light-emitting layer including a plurality of stacks (light-emitting units). It may further include a charge-generation layer between the plurality of stacks. The charge-generation layer may adjust the charge balance between the plurality of stacks.

The charge generation layer may be composed of multiple layers, including a first charge generation layer and a second charge generation layer. The first charge generation layer may include an N-type charge generation layer and a P-type charge generation layer. The first charge generation layer may be an organic layer doped with an alkali metal such as lithium (Li), sodium (Na), potassium (K), or cesium (Cs), or an alkaline earth metal such as magnesium (Mg), strontium (Sr), barium (Ba), or radium (Ra).

Metals contained in the charge generation layer can cause lateral leakage current (LLC). For example, when a specific subpixel is activated, current leaks laterally between adjacent pixels, causing the adjacent subpixel to emit weak light, distorting image information.

The first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3 may each require a different driving voltage to emit light.

For example, the drive voltage required to emit blue light may be greater than the drive voltage required to emit other red or green light.

When the third subpixel SP_3 is driven, the adjacent subpixels are weakly driven. This occurs because electrons from the third subpixel SP_3 move to the adjacent subpixels through the charge generation layer disposed continuously between the adjacent pixels, driving them weakly. As a result, the adjacent subpixels, which are in a non-driven state, enter a state similar to that of a driven state and emit weak light. This causes a decrease in color purity and a decrease in color reproduction rate. This phenomenon is often visible at low gradations.

Therefore, horizontal leakage current can be blocked by disposing a bank trench BT having a second spacer 340 between subpixels adjacent to the non-emitting portion NEA.

In FIG. 2, the second spacer 340 is disposed to surround the first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3. However, in other embodiments, the second spacer 340 may be disposed to surround only some of the first subpixel SP_1, the second subpixel SP_2, and the third subpixel SP_3. For example, the second spacer 340 may be disposed to surround only the third subpixel SP_3, which emits blue light. Because this subpixel has the highest driving voltage, there may be a greater possibility of leakage current flowing from this subpixel to adjacent subpixels.

The light-emitting layer is disposed on the bank trench BT having the first electrode and the second spacer 340. The bank trench BT having the second spacer 340 separates the light-emitting layer disposed between adjacent subpixels, thereby preventing electrons formed inside the light-emitting layer from migrating to adjacent pixels during operation.

As a result, horizontal leakage current between adjacent subpixels is blocked, eliminating the poor visibility caused by adjacent pixels emitting light at low gradations and improving color reproduction.

Although FIG. 2 illustrates the second spacer 340 and bank trench BT being disposed between adjacent first subpixel SP_1, second subpixel SP_2, and third subpixel SP_3, they do not have to be disposed between adjacent subpixels and are not limited to the illustration.

The first spacer 330 may be disposed at a predetermined distance from the plurality of subpixels SP. For example, the first spacer 330 may be disposed at a predetermined distance from the plurality of subpixels SP and surrounded by the plurality of subpixels SP. For example, as shown in FIG. 2, four subpixels may surround one first spacer, but this is not limited thereto. The first spacer 330 may provide gaps between the subpixels SP_1, SP_2, and SP_3 and may be spaced apart from the subpixels SP_1, SP_2, and SP_3 by the respective gaps. The first spacer 330 may be referred to as an on-bank spacer, and the second spacer 340 may be referred to as an in-bank spacer.

The plurality of subpixels emitting at least one of the same colors may be arranged symmetrically with respect to the first spacer 330. For example, as shown in FIG. 2, the plurality of second subpixels SP_2 may be arranged to face each other with respect to the first spacer 330. The first spacer 330 may be arranged substantially in the middle of the plurality of subpixels emitting at least one of the same colors.

The first spacer 330 buffers the space between the substrate 110 on which the light-emitting layer 350 is formed and the upper substrate, thereby reducing damage to the light-emitting display device 100 due to external impact.

The first spacer 330 can also protect the light-emitting layer 350. For example, a fine metal mask (FMM) can be used when forming the light-emitting layer 350. The fine metal mask may sag during the process due to its weight. In this case, by placing the first spacer 330, the fine metal mask (FMM) and the first spacer 330 come into contact with each other, preventing the fine metal mask from directly contacting the bank 320 and deforming or damaging the bank 320.

The light-emitting display device of the present invention will be described in detail below with reference to Figures 3, 4a, 4b, 4c, and 4d.

Figure 3 is a cross-sectional view of a light-emitting display device according to an embodiment of the present invention.

Figures 4a, 4b, 4c, and 4d are cross-sectional views illustrating the manufacturing process of a light-emitting display device according to an embodiment of the present invention.

Figure 3 is a cross-sectional view illustrating the I-I' region in which a bank trench including the second spacer of Figure 2 is disposed.

As shown in Figures 3 and 4a, the substrate 110 can support various components of the light-emitting display device. The substrate 110 can be made of glass or a flexible plastic material.

For example, the substrate 110 may be made of at least one of polyimide (PI), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polyethersulfone, and polycarbonate, but is not limited to these.

When the substrate 110 is made of polyimide, it may be composed of two polyimides. An inorganic film may then be further disposed between the two polyimides.

The substrate 110 may refer to elements and functional layers formed on the substrate 110, such as a switching thin film transistor, a driving thin film transistor connected to the switching thin film transistor, an organic light-emitting element connected to the driving thin film transistor, a protective layer, etc., but is not limited to these.

The buffer layer 120 may be disposed over the entire surface of the substrate 110.

The buffer layer 120 may be formed of an insulating inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may also be formed of an insulating organic material, but is not limited to these.

The buffer layer 120 may consist of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers of these. When the buffer layer 120 consists of multiple layers, silicon oxide (SiOx) and silicon nitride (SiNx) may be formed alternately.

The buffer layer 120 may be omitted depending on the type and material of the substrate 110, the structure and type of the thin film transistor, etc.

A thin film transistor 200 may be disposed on the buffer layer 120. The thin film transistor 200 may include a semiconductor pattern, a gate electrode, a source electrode, and a drain electrode.

For ease of explanation, only a driving thin film transistor is illustrated among various thin film transistors that may be included in the light emitting display device 100. However, other thin film transistors, such as a switching thin film transistor, may also be included in the light emitting display device 100. Furthermore, for ease of explanation, the thin film transistor has been described as having a top gate structure, but is not limited to this structure and may be configured with other structures, such as a bottom gate structure.

The semiconductor pattern 210 of the thin film transistor 200 may be disposed on the buffer layer 120.

The semiconductor pattern 210 may be made of a polycrystalline semiconductor. For example, the polycrystalline semiconductor may be made of, but is not limited to, low temperature polysilicon (LTPS), which has high mobility. When the semiconductor pattern is made of a polycrystalline semiconductor, energy consumption is low and reliability is high.

The semiconductor pattern 210 may also be made of an oxide semiconductor. For example, it may be made of any one of IGZO (Indium-gallium-zinc-oxide), IZO (Indium-zinc-oxide), IGTO (Indium-gallium-tin-oxide), and IGO (Indium-gallium-oxide), but is not limited to these. When the semiconductor pattern 210 is made of an oxide semiconductor, it has an excellent effect of blocking leakage current, thereby reducing brightness changes of sub-pixels during low-speed driving.

When the semiconductor pattern 210 is made of a polycrystalline semiconductor or an oxide semiconductor, some regions of the semiconductor pattern 210 may have conductive regions.

The semiconductor pattern 210 may be made of amorphous silicon (a-Si) or various organic semiconductor materials such as pentacene, but is not limited to these.

A first insulating layer 130 may be disposed on the semiconductor pattern 210.

The first insulating layer 130 is disposed between the semiconductor pattern 210 and the gate electrode 230 to insulate the semiconductor pattern 210 from the gate electrode 230.

The first insulating layer 130 may be formed of an insulating inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may also be formed of an insulating organic material, but is not limited to these.

The first insulating layer 130 may have holes to electrically connect each of the source electrode 250 and drain electrode 270 to the semiconductor pattern 210.

The gate electrode 230 of the thin film transistor 200 may be disposed on the first insulating layer 130.

The gate electrode 230 may be arranged to overlap the semiconductor pattern 210.

The gate electrode 230 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and transparent conductive oxide (TCO), or an alloy thereof, but is not limited to these.

A second insulating layer 140 may be disposed on the gate electrode 230.

The second insulating layer 140 is disposed between the gate electrode 230 and the source electrode 250 and drain electrode 270, and can insulate the gate electrode 230 from the source electrode 250 and drain electrode 270.

The second insulating layer 140 may be formed of an insulating inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or may also be formed of an insulating organic material, but is not limited to these.

The second insulating layer 140 may have holes to electrically connect each of the source electrode 250 and drain electrode 270 to the semiconductor pattern 210.

A source electrode 250 and a drain electrode 270 may be disposed on the second insulating layer 140.

The source electrode 250 and drain electrode 270 can be electrically connected to the semiconductor pattern 210 through holes in the first insulating layer 130 and the second insulating layer 140.

The source electrode 250 and the drain electrode 270 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and transparent conductive oxide (TCO), or an alloy thereof, but are not limited to these.

For example, the source electrode 250 and the drain electrode 270 may be made of a three-layer structure of conductive metal material such as titanium (Ti)/aluminum (Al)/titanium (Ti), but are not limited to this.

A protective layer 150 may be disposed on the source electrode 250 and drain electrode 270.

The protective layer 150 can protect the thin film transistor 200. The protective layer 150 can be formed of an insulating inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or can also be formed of an insulating organic material, but is not limited to these.

The protective layer 150 may have holes to electrically connect the thin film transistor 200 and the connecting electrode 170.

The protective layer 150 may be omitted depending on the structure and type of the thin film transistor.

A planarization layer 160 may be disposed on the protective layer 150 or the thin-film transistor 200.

The planarization layer 160 protects the thin film transistors arranged underneath the planarization layer 160 and can reduce or flatten steps caused by various patterns.

The planarization layer 160 may be formed of at least one organic insulating material such as, but not limited to, BCB (BenzoCycloButene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

The planarization layer 160 can be arranged in a single layer, but can also be arranged in two or more layers, taking into account the arrangement of the electrodes.

As light emitting display devices 100 evolve to higher resolutions, the number of various signal wirings increases. Since it is difficult to arrange all wirings on one layer while maintaining minimum spacing, additional layers can be created. These additional layers allow more space for wiring arrangement, making it easier to design the layout of electrical wires/electrodes. Furthermore, if a dielectric material is used in the multi-layered planarization layer, the planarization layer 160 may be used to form capacitance between metal layers.

When the planarization layer 160 is arranged in two layers, it may include a first planarization layer 161 and a second planarization layer 162.

For example, a hole may be formed in the first planarization layer 161, and the connecting electrode 170 may be disposed in the hole. A second planarization layer 162 having a hole may be disposed on the first planarization layer 161 and the connecting electrode 170. An anode electrode 310 may be disposed in the hole in the second planarization layer 162. Therefore, the thin film transistor 200 and the first electrode (anode electrode) 310 may be electrically connected through the connecting electrode 170.

One end (or a portion) of the connecting electrode 170 may be connected to the thin film transistor, and the other end (or another portion) of the connecting electrode may be connected to the first electrode 310.

The connecting electrode 170 may be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), and transparent conductive oxide (TCO), or an alloy thereof, but is not limited to these.

The connecting electrode 170 may be omitted depending on the structure and type of the light-emitting display device 100.

A first electrode 310 may be disposed on the planarization layer 160. The first electrode 310 may be disposed on at least a portion of the light-emitting portion EA and the non-light-emitting portion NEA.

When the light emitting display device 100 is a top emission type, the first electrode 310 is a reflective electrode that reflects light and may be disposed using an opaque conductive material. The first electrode 310 may be formed of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof. For example, the first electrode 310 may have a three-layer structure of silver (Ag), lead (Pd), and copper (Cu), but is not limited to this. Alternatively, the first electrode 310 may further include a transparent conductive material layer with a high work function, such as indium tin oxide (ITO).

When the light emitting display device 100 is a bottom emission type, the first electrode 310 may be disposed using a transparent conductive material that transmits light. For example, the first electrode 310 may be formed of at least one of indium tin oxide (ITO) and indium zinc oxide (IZO).

A bank 320 may be disposed on the first electrode 310 and the planarization layer 160.

The bank 320 can separate multiple subpixels SP, reducing light bleeding and preventing color mixing that occurs at various viewing angles.

The bank 320 can define (or separate) the light-emitting portion EA and the non-light-emitting portion NEA, and the bank 320 can be arranged in the non-light-emitting portion NEA.

The bank 320 may have a bank hole BH that exposes the first electrode 310. The bank 320 may have a bank trench BT in the non-emitting portion NEA disposed between adjacent subpixels.

The bank 320 may be made of at least one of, but is not limited to, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), an organic insulating material such as BCB (Benzocyclobutene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, or a photosensitive material containing a black pigment.

The bank 320 may be transparent, black, or colored. The bank 320 may be disposed to cover or overlie the end of the first electrode 310.

The bank trench BT may be formed by removing a portion of the bank 320. If the bank 320 is completely removed in the region where the bank trench BT is to be formed, the bank trench BT may expose the planarization layer 160. Referring to FIG. 3, the bank 320 is shown as being completely removed in the region where the bank trench BT is to be formed, but the bank 320 may be formed by removing only a portion of the bank 320. In this case, the bank 320 disposed in the region where the bank trench BT is to be formed may have a thickness that is 1/2 to 1/3 the height of the bank 320 in other regions.

The bank trench BT may overlap at least a portion of the first touch electrode 540_R, the first touch connecting electrode 520, the second touch electrode, and the second touch connecting electrode 540_C.

The manufacturing process for the bank trench BT will be described in detail below with reference to Figures 4a to 4d.

At least one first spacer 330 may be disposed on the bank 320. The first spacer 330 may be formed of the same material as the bank 320 and may be formed simultaneously with the bank 320 or in a separate process.

The thickness of the first spacer 330 may be greater than the thickness of the bank 320, and the thickness of the first spacer 330 may be 1 um to 2 um.

A second spacer 340 may be disposed on the bank 320 and the planarization layer 160.

The second spacer 340 separates the light-emitting layer 350 or second electrode 360 disposed behind the second spacer 340, thereby preventing electrons formed inside the light-emitting layer 350 from moving to adjacent pixels during operation. Therefore, even if the spacing between adjacent subpixels is reduced, the second spacer 340 can block horizontal leakage current.

The second spacer 340 may be disposed inside the bank trench BT or may partially cover the side surface of the bank trench BT.

The second spacer 340 may have an inverse tapered shape. For example, the second spacer 340 may have a lower surface and an upper surface, and the size of the upper surface of the second spacer may be larger than the size of the lower surface of the second spacer.

The second spacers 340 may be formed of the same material as the banks 320 or the first spacers 330. The manufacturing process for the second spacers 340 will be described in detail with reference to Figures 4a to 4d.

The thickness of the second spacer 340 may be greater than the thickness of the bank 320.

The second height (vertical distance, H2) from the substrate 110 to the top of the second spacer 340 may be smaller than the second height (vertical distance, H1) from the substrate 110 to the top of the first spacer 330. Because the second spacer 340 is disposed in a bank trench BT formed by etching a portion of the bank 320, the height (vertical distance) from the substrate 110 to the top of the second spacer 340 may be smaller than the height (vertical distance) from the substrate 110 to the top of the first spacer 330 disposed on top of the bank 320. The height or vertical distance may be defined along a direction perpendicular to the display surface of the light emitting display device, i.e., a direction perpendicular to the substrate 110. Also, as shown in FIG. 3, the fourth height H4 of the second spacer 340 may be smaller than the third height H3 of the first spacer 330.

If the second height H2 from the substrate 100 to the top of the second spacer 340 is the same or similar to the first height H1 from the substrate 100 to the top of the first spacer 330, a fine metal mask (FMM) is used when forming the light-emitting layer 350. This can result in the second spacer 340 coming into contact with the fine metal mask (FMM), which can cause deformation or damage to the second spacer 340. However, in this embodiment of the present invention, the second spacer 340 is disposed in the bank trench BT, which can prevent the second spacer 340 from coming into contact with the fine metal mask (FMM), which can cause deformation or damage to the second spacer 340.

The second spacer 340 may include at least three spacers. For example, the second spacer 340 may include a first spacer pattern 340a, a second spacer pattern 340b, and a third spacer pattern 340c.

The first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c may be spaced apart. Spacer pattern holes PH may be formed between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c. That is, the first spacer pattern hole PH may be formed between the first spacer pattern 340a and the second spacer pattern 340b, and the second spacer pattern hole PH may be formed between the second spacer pattern 340b and the third spacer pattern 340c. For example, the second spacer 340 may include a first spacer pattern, a second spacer pattern, and a third spacer pattern, along with a first spacer pattern hole PH between the first spacer pattern and the second spacer pattern, and a second spacer pattern hole PH between the second spacer pattern and the third spacer pattern. The second spacer may include at least a first spacer pattern and a second spacer pattern, along with a spacer pattern hole between the first spacer pattern and the second spacer pattern. Increasing the spacer pattern and spacer pattern holes can further reduce leakage current between subpixels. The second spacer, including the spacer pattern, can prevent the light-emitting layer 350 (and the second electrode 360) from being deposited on the sloped side surfaces of the second spacer because the spacer pattern forms protrusions that block the sloped side surfaces from deposition. The spacer pattern allows discontinuities/disconnections/gaps to be formed in the light-emitting layer 350, thereby reducing leakage current between subpixels.

At least one spacer pattern of the second spacer 340 may be spaced apart from the bank 320. For example, the second spacer pattern 340b of the second spacer 340 may be spaced apart from the bank 320.

At least one spacer pattern of the second spacer 340 may cover at least a portion of the bank 320. For example, the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 may be arranged to cover a portion of the bank 320.

In FIG. 3, the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 are illustrated as covering a portion of the bank 320, but in other embodiments, multiple second spacer patterns 340b may be arranged within the bank trench BT without covering a portion of the bank.

In Figure 3, the second spacer 340 is illustrated with three segments, but the number can be changed depending on the design and is not limited to this.

The light-emitting layer 350 may be disposed on the first electrode 310, bank 320, first spacer 330, second spacer 340, and planarization layer 160.

The light-emitting layer 350 is separated by the second spacer 340 and spacer pattern hole PH disposed in the non-emitting portion NEA, thereby preventing electrons formed within the light-emitting layer 350 from moving to adjacent pixels during operation. This prevents horizontal leakage current caused by a reduced spacing between adjacent subpixels. The light-emitting layer 350 does not form a continuous layer, but may include multiple cuts, gaps, or discontinuities separating each portion of the light-emitting layer 350. The cuts, gaps, or discontinuities may be formed by the second spacer 340 within the bank trench BT. In particular, the light-emitting layer 350 includes a discontinuity between a portion formed on the bank 320 and a portion formed on the first spacer pattern 340a, a discontinuity between a portion formed on the first spacer pattern 340a and a portion formed on the second spacer pattern 340b (i.e., a portion formed by the first spacer pattern hole PH), a discontinuity between a portion formed on the second spacer pattern 340b and a portion formed on the third spacer pattern 340c (i.e., a portion formed by the second spacer pattern hole PH), and a discontinuity between a portion formed on the third spacer pattern 340c and a portion formed on the bank 320. Here, the cut may refer to a cut through a layer, i.e., a complete cut penetrating the entire layer, or a cut at the surface of a layer, i.e., a cut partially formed in a layer (i.e., a thickness reduction). For example, the light-emitting layer 350 may have a reduced thickness in a region corresponding to the second spacer 340. The second spacer 340 may include one or more flared side portions where the light-emitting layer 350 is thinned or uneven or discontinuous. This may reduce leakage current transmission through the corresponding light-emitting portion. That is, in the region of the second spacer 340, deposition of the light-emitting layer 350 is reduced, reducing leakage current transmission. In the region of the second spacer 340, the light-emitting layer 350 may not be continuous or uniform.

At least a portion of the light-emitting layer 350 may be disposed on the planarization layer 160. At least a portion of the light-emitting layer 350 may be disposed within the bank trench BT. At least a portion of the light-emitting layer 350 may be disposed between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c of the second spacer 340.

As shown in FIG. 5, the light-emitting layer 350 may include a plurality of stacks (light-emitting units). For example, the light-emitting layer 350 may include a first light-emitting portion 351, a second light-emitting portion 353, and a charge generation layer 352 disposed between the first light-emitting portion 351 and the second light-emitting portion 353. The components of the light-emitting layer 350 will be described in detail below with reference to FIG. 5.

A second electrode (cathode electrode) 360 may be disposed on the light-emitting layer 350.

The second electrode 360 may be cut by the second spacer 340 at the non-emitting portion NEA. The second electrode 360 may not form a continuous layer, but may include a plurality of cuts, gaps, or discontinuities that separate portions of the second electrode 360 and correspond to the cuts, gaps, or discontinuities in the light-emitting layer 350.

At least a portion of the second electrode 360 may be disposed within the bank trench BT. At least a portion of the second electrode 360 may be disposed between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c of the second spacer 340.

For example, each of the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c has an inverse tapered shape, in which the side of each spacer pattern 340a, 340b, and 340c forms an acute angle with the top surface of the second planarization layer 162. As a result, the light-emitting layer 350 and the second electrode 360 are cut between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c, and a residual layer RL including the light-emitting layer 350 and the second electrode 360 may be disposed on the second planarization layer 162 between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c. In other words, the residual layer RL may refer to the light-emitting layer 350 and the second electrode 340 disposed in the spacer pattern hole PH of the second spacer 340. A portion of the light-emitting layer 350 included in the residual layer RL may be separated from a portion of the light-emitting layer 350 disposed on the first spacer pattern 340 a, the second spacer pattern 340 b, and the third spacer pattern 340 c. A portion of the second electrode 360 included in the residual layer RL may be separated from a portion of the second electrode 350 disposed on the first spacer pattern 340 a, the second spacer pattern 340 b, and the third spacer pattern 340 c. A portion of the light-emitting layer 350 disposed on one or more spacer patterns 340 a, 340 b, and 340 c may be separated from a portion of the light-emitting layer 350 disposed on an adjacent bank 320. A portion of the light-emitting layer 350 disposed on one or more spacer patterns 340 a, 340 b, and 340 c may be separated from a portion of the light-emitting layer 350 disposed on an adjacent bank 320. A portion of the second electrode 360 disposed on top of one or more spacer patterns 340a, 340b, 340c may be separated from a portion of the second electrode 360 disposed on top of an adjacent bank 320.

The second electrode 360 supplies electrons to the light-emitting layer 350 and may be made of a conductive material with a low work function.

When the light emitting display device 100 is a top emission type, the second electrode 360 may be disposed using a transparent conductive material that transmits light. For example, the second electrode 360 may be formed of at least one of indium tin oxide (ITO) and indium zinc oxide (IZO), but is not limited thereto.

It can also be arranged using a translucent conductive material that transmits light. For example, it can be formed of at least one of alloys such as LiF/Al, CsF/Al, Mg:Ag, Ca/Ag, Ca:Ag, LiF/Mg:Ag, LiF/Ca/Ag, and LiF/Ca:Ag.

When the light emitting display device 100 is a bottom emission type, the second electrode 360 is a reflective electrode that reflects light and may be disposed using an opaque conductive material. For example, the cathode electrode 360 may be formed of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

Although not shown, a capping layer (CPL) may be disposed on the second electrode 360.

The capping layer is intended to protect the second electrode 360 and increase the light extraction efficiency of the light-emitting layer. The capping layer may be formed as a single layer or multiple layers, but is not limited thereto.

The capping layer may be omitted depending on the structure and type of the light-emitting display device.

An encapsulation layer 400 may be disposed on the second electrode 360 or the capping layer. The encapsulation layer 400 can protect the first electrode 310, the light-emitting layer 350, and the second electrode 360 from external moisture, oxygen, or foreign matter or particles. For example, it can prevent the penetration of external oxygen and moisture to prevent oxidation of the light-emitting material and electrode material.

The encapsulation layer 400 may be made of a transparent material so that light emitted from the light-emitting layer can pass through.

The sealing layer 400 may include a first sealing layer 410, a second sealing layer 420, and a third sealing layer 430 that block the penetration of moisture and oxygen. The first sealing layer 410, the second sealing layer 420, and the third sealing layer 430 may have an alternating laminated structure.

The first encapsulation layer 410 and the third encapsulation layer 430 may be made of at least one inorganic material, such as, but not limited to, silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlyOz). The first encapsulation layer 410 and the third encapsulation layer 430 may be formed using a vacuum deposition method, such as, but not limited to, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

The first sealing layer 410 and the third sealing layer 430 may be formed of at least two or more layers. For example, the first sealing layer 410 may have a three-layer structure of silicon oxide (SiOx)/silicon nitride (SiNx)/silicon oxide (SiOx), but is not limited to this. Alternatively, the first sealing layer 410 may have a four-layer structure of silicon oxide (SiOx)/silicon nitride (SiNx)/silicon oxide (SiOx)/silicon oxide (SiOx), but is not limited to this.

The second encapsulation layer 420 can cover foreign matter or particles that may occur during the manufacturing process. In addition, the second encapsulation layer 420 can planarize the surface of the first encapsulation layer 410. For example, the second encapsulation layer 420 can be a particle cover layer, but is not limited to this term.

The second sealing layer 420 may be an organic material, such as, but not limited to, silicon oxycarbide (SiOCz), epoxy, polyimide, polyethylene, or an acrylate-based polymer.

The second sealing layer 420 may be made of a thermosetting or photocurable material that is cured by heat or light.

A touch sensor layer 500 may be disposed on the sealing layer 400.

The touch sensor layer 500 may include a first touch electrode 540_R, a first touch connecting electrode 520, a second touch electrode, and a second touch connecting electrode 540_C.

A portion of the first touch electrode 540_R, the first touch connecting electrode 520, the second touch electrode, and the second touch connecting electrode 540_C may be arranged to overlap the second spacer 340 and/or the bank trench BT.

The first touch electrode 540_R, the second touch electrode, the first touch connecting electrode 520, and the second touch connecting electrode 520_C may be formed in a mesh pattern in which metal lines having small spacings intersect with each other. The mesh pattern may have a diamond shape, and the shape of the mesh pattern may be, but is not limited to, a square, pentagon, hexagon, circle, ellipse, etc.

The first touch electrode 540_R, the second touch electrode, the first touch connecting electrode 520, and the second touch connecting electrode 540_C may be arranged using an opaque conductive material with low resistance. For example, they may be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), tungsten (W), gold (Au), and transparent conductive oxide (TCO), or an alloy thereof, but are not limited thereto.

For example, the first touch electrode 540_R, the second touch electrode, the first touch connecting electrode 520, and the second touch connecting electrode 540_C may have a three-layer structure of titanium (Ti)/aluminum (Al)/titanium (Ti) made of a conductive metal material, but is not limited to this.

The first touch electrode 540_R, the second touch electrode, the first touch connecting electrode 520, and the second touch connecting electrode 540_C may be made of the same material as the source electrode 250 and the drain electrode 270.

A touch buffer layer 510 may be disposed on the encapsulation layer 400. The touch buffer layer 510 can prevent chemicals (such as a developer or etchant) used in the manufacturing process of the touch sensor layer 500 or external moisture from penetrating into the light-emitting layer 350, which contains organic materials. In addition, the touch buffer layer 510 can prevent the problem of multiple touch sensor metals disposed on top of the touch buffer layer 510 being disconnected due to external impact, and can block interference signals that may be generated when the touch sensor layer 500 is driven.

The touch buffer layer 510 may be made of at least one of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiOx), or organic insulating materials such as BCB (Benzocyclobutene), acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited to these.

A first touch connecting electrode 520 may be disposed on the touch buffer layer 510.

For example, the first touch connecting electrode 520 may be disposed between adjacent first touch electrodes 540_R in the first direction (or X-axis direction). The first touch connecting electrode 520 may electrically connect a plurality of adjacent first touch electrodes 540_R spaced apart in the first direction (or X-axis direction), but is not limited thereto.

The first touch connecting electrode 520 may be arranged to overlap the second touch connecting electrode 540_C that connects adjacent second touch electrodes in the second direction (or Y-axis direction). The first touch connecting electrode 520 and the second touch connecting electrode 540_C may be formed in different layers and thus may be electrically insulated.

A touch insulating layer 530 may be disposed on the touch buffer layer 510 and the first touch connecting electrode 520.

The touch insulating layer 530 may include holes to electrically connect the first touch electrode 540_R and the first touch connecting electrode 520.

The touch insulating layer 530 can electrically insulate the second touch electrode and the second touch connecting electrode 540_C.

The touch insulating layer 530 may consist of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited to these.

A first touch electrode 540_R, a second touch electrode, and a second touch connecting electrode 540_C may be disposed on the touch insulating layer 530.

The first touch electrode 540_R and the second touch electrode may be spaced apart by a certain distance. At least one first touch electrode 540_R adjacent in the first direction (or X-axis direction) may be spaced apart from each other. At least one first touch electrode 540_R adjacent in the first direction (or X-axis direction) may be connected to a first touch connecting electrode 520 disposed between the first touch electrodes 540_R. For example, adjacent first touch electrodes 540_R may be connected to the first touch connecting electrode 520 through a hole in the touch insulating layer 530.

Second touch electrodes adjacent in the second direction (or Y-axis direction) may be connected by a second touch connecting electrode 540_C. The second touch electrode and the second touch connecting electrode 540_C may be formed in the same layer. For example, the second touch connecting electrode 540_C may be disposed between a plurality of second touch electrodes in the same layer as the second touch electrode. The second touch connecting electrode 540_C may be formed extending from the second touch electrode.

The first touch electrode 540_R, the second touch electrode, and the second touch connecting electrode 540_C may be formed in the same process.

A touch planarization layer 550 may be disposed on the first touch electrode 540_R, the second touch electrode, and the second touch connecting electrode 540_C.

The touch drive circuit may receive a touch sensing signal from the first touch electrode 540_R. The touch drive circuit may also transmit a touch drive signal to the second touch electrode. The touch drive circuit may sense a user's touch using mutual capacitance between the plurality of first touch electrodes 540_R and the second touch electrodes. For example, when a touch operation is performed on the light emitting display device 100, a change in capacitance may occur between the first touch electrode 540_R and the second touch electrode. The touch drive circuit may detect the touch coordinates by sensing this change in capacitance.

The manufacturing process of the bank trench BT and the second spacer 340 will be described in detail below. Figures 4a, 4b, 4c, and 4d are cross-sectional views illustrating the manufacturing process of an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 4a, a first electrode 310 is disposed on the light-emitting portion EA of the substrate 110 on which the thin film transistor 200 is disposed.

Referring to FIG. 4b, a bank 320 and a first spacer 330 are disposed on the non-light-emitting portion NEA of the substrate 110 on which the first electrode 310 is disposed.

The bank 320 may include a bank hole BH that exposes the first electrode 310 to the light-emitting portion EA. The bank hole BH may be formed by etching a portion of the bank 320.

At least one first spacer 330 may be arranged on the bank 320.

In FIG. 4b, the bank 320 and the first spacer 330 are illustrated as being formed in the same process using a half-tone mask, but they may also be formed in separate processes.

Referring to FIG. 4c, a bank trench BT is formed between adjacent subpixels. The bank trench BT may be formed by etching a portion of the bank 320. The bank trench BT may expose the planarization layer 160.

In FIG. 4c, the bank 320 is shown as being completely etched in the region where the bank trench BT is to be formed, but it may be only partially etched. For example, the bank 320 may be only partially etched in the region where the bank trench BT is to be formed, rather than being completely etched, so that a portion of the bank 320 is disposed on the planarization layer 160.

Referring to FIG. 4d, a second spacer 340 may be disposed within the bank trench BT.

The second spacer 340 may include a first spacer pattern 340a, a second spacer pattern 340b, and a third spacer pattern 340c. The first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c may be spaced apart from one another. Spacer pattern holes PH may be formed between the first spacer pattern 340a, the second spacer pattern 340b, and the third spacer pattern 340c.

At least one spacer pattern of the second spacer 340 may cover at least a portion of the bank 320. For example, the first spacer pattern 340a and the third spacer pattern 340c of the second spacer 340 may be spaced apart from the bank 320.

Although FIGS. 4a to 4d illustrate the bank hole BH, bank trench BT, first spacer 330, and second spacer 340 being formed, this is not limited thereto, and the bank hole BH and bank trench BT may be formed simultaneously, followed by the formation of the first spacer 330 and second spacer 340.

The light-emitting layer of the present invention will be explained below with reference to Figure 5.

Figure 5 is a diagram illustrating a light-emitting layer according to an embodiment of the present invention.

For ease of explanation, only two stacks (light-emitting units) are shown, but two or more stacks and one or more charge-generating layers contained between the two or more stacks may be included.

The light-emitting layer 350 can include multiple stacks (light-emitting units). For example, the light-emitting layer 350 can include a first stack 351, a second stack 352, and a charge-generating layer 352 disposed between the first stack 351 and the second stack 352.

A first electrode (310, anode), a first stack 351, a charge generation layer 352, a second stack 353, and a second electrode 360 may be sequentially disposed on a substrate 110 having a first subpixel SP_1, a second subpixel SP_2, and a third subpixel SP_3.

The first stack 351 may include a hole injection layer 351-A, a first hole transport layer 351-B, a first light-emitting material layer 351-C, and a first electron transport layer 351-D.

The second stack 353 may include a second hole transport layer 353-A, a second light emitting material layer 353-B, a second electron transport layer 353-C, and an electron injection layer 353-D.

The charge generation layer 352 may further include an n-type charge generation layer (n-CGL) that assists in the injection of electrons into the first stack 351 and a p-type charge generation layer (p-CGL) that assists in the injection of holes into the second stack 352.

Although not shown in the drawings, an electron blocking layer may be disposed between the first hole injection layer 351-A and the first light emitting material layer 351-C, and a hole blocking layer may be disposed between the first light emitting material layer 351-C and the charge generation layer 352. Alternatively, an electron blocking layer may be disposed between the charge generation layer 352 and the second light emitting material layer 353-B, and a hole blocking layer may be disposed between the second light emitting material layer 353-B and the electron injection layer 353-D.

The components of the light-emitting layer 350 can be at least partially separated between adjacent subpixels by a bank trench BT including a second spacer 340 disposed below the light-emitting layer 350. Therefore, electrons formed within the light-emitting layer 350 are prevented from moving to adjacent subpixels, thereby resolving poor visibility caused by adjacent subpixels emitting light, particularly at low gradations, and improving color reproduction.

The first light-emitting material layer 351-C and the second light-emitting material layer 353-B may be arranged in a spaced-apart pattern to correspond to each subpixel. For example, the first light-emitting material layer 353-C and the second light-emitting material layer 353-B may be arranged in at least a portion of the end of the bank hole BH and the bank 320.

The hole injection layer 351-A facilitates the injection of holes and may be made of, but is not limited to, one or more selected from the group consisting of HATCN (1,4,5,8,9,11-hexaazatriphenylene-hexanitrile), CuPc (copper phthalocyanine), PEDOT (poly(3,4)-ethylenedioxythiophene), PANI (polyaniline), and NPD (N,N-dinaphthalyl-N,N'-diphenylbenzidine).

The first hole transport layer 351-B and the second hole transport layer 353-A facilitate the transport of holes and may be made of, but are not limited to, one or more compounds selected from the group consisting of NPD (N,N-dinaphthalyl-N,N'-diphenylbenzidine), TPD (N,N'-bis-(3-mePHylphenyl)-N,N'-bis-(phenyl)-benzidine), s-TAD, and MTDATA (4,4',4"-Tris(N-3-mePHylphenyl-N-phenyl-amino)-triphenylamine).

The first electron transport layer 351-D and the second electron transport layer 353"-C facilitate the transport of electrons and may be made of one or more materials selected from the group consisting of, but not limited to, Alq3 (tris(8-hydroxyquinolino)aluminum), PBD (2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4 oxadiazole), TAZ, spiro-PBD, BAlq, and SAlq.

The electron injection layer 353-D facilitates electron injection and may be made of, but is not limited to, Alq3 (tris(8-hydroxyquinolino)aluminum), PBD (2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4 oxadiazole), TAZ, spiro-PBD, BAlq, or SAlq.

The first light-emitting material layer 351-C and the second light-emitting material layer 353-B may be disposed within the bank holes BH and spaced apart between adjacent subpixels. For example, the first light-emitting material layer 351-C and the second light-emitting material layer 353-B may be deposited on each subpixel using a fine metal mask (FMM).

The first light-emitting material layer 351-C and the second light-emitting material layer 353-B may overlap. The first light-emitting material layer 351-C and the second light-emitting material layer 353-B may emit light of the same color. The first light-emitting material layer 351-C and the second light-emitting material layer 353-B may emit light in the same wavelength band, but are not limited to this.

The first light-emitting material layer 351-C and the second light-emitting material layer 353-B may contain light-emitting materials that emit red, green, and blue light, respectively, and the light-emitting materials may be formed using phosphorescent or fluorescent materials.

For example, in the case of the first red light-emitting material layer 351R and the second red light-emitting material layer 353R arranged in the first subpixel SP_1, the first red light-emitting material layer 351R and the second red light-emitting material layer 353R include a host material including CBP (carbazole biphenyl) or mCP (1,3-bis(carbazol-9-yl), and a host material including PIQIr(acac) (bis(1-phenylisoquinolin) acetylacetonate iridium), PQIr(acac) (bis(1-phenylisoquinolin) acetylacetonate The dopant may be a phosphorescent material containing one or more dopants selected from the group consisting of PQIr (tris(1-phenylquinoline)iridium), PQIr (tris(1-phenylquinoline)iridium), and PtOEP (octaethylporphyrin platinum), or alternatively, may be a fluorescent material containing PBD:Eu(DBM)3(Phen) or Perylene, but is not limited to this.

For example, in the case of the first green light-emitting material layer 351G and the second green light-emitting material layer 353G arranged in the second subpixel SP_2, the first green light-emitting material layer 351G and the second green light-emitting material layer 353G may be made of a phosphorescent material containing a host material including CBP or mCP and a dopant material such as an Ir complex including Ir(ppy)3 (fac tris(2-phenylpyridine) iridium), or alternatively, may be made of a fluorescent material including Alq3 (tris(8-hydroxyquinolino)aluminum), but is not limited to this.

For example, in the case of the first blue light-emitting material layer 351B and the second blue light-emitting material layer 353B disposed in the third subpixel SP_3, the first blue light-emitting material layer 351B and the second blue light-emitting material layer 353B may be made of a phosphorescent material including a host material including CBP or mCP and a dopant material including (4,6-F2ppy)2Irpic. They may also be made of a fluorescent material including any one selected from the group consisting of spiro-DPVBi, spiro-6P, distyrylbenzene (DSB), distyrylarylene (DSA), PFO-based polymers, and PPV-based polymers, but are not limited to these.

The first luminescent material layer 351-C and the second luminescent material layer 353-B may further include an auxiliary luminescent material layer. For example, the auxiliary luminescent material layer may be disposed below or above the first luminescent material layer 351-C and the second luminescent material layer 353-B. The auxiliary luminescent material layer may emit the same color as the first luminescent material layer 351-C and the second luminescent material layer 353-B, respectively, or may emit a different color.

The n-type charge generation layer (n-CGL) can be formed of alkali metals, alkali metal compounds, or organic materials or compounds thereof that act as electron injectors. For example, it can be composed of a mixed layer of n-type materials such as anthracene derivatives doped with lithium (Li) or cesium (Cs), but is not limited to this.

The p-type charge generation layer (p-CGL) can be formed from an organic material that is also used as a hole injection layer material. For example, it can consist of a single layer of a p-type material such as HATCN or F4-TCNQ, but is not limited to this.

The components included in the first stack 351, the second stack 353, and the charge generation layer 352 may be formed in multiples of two or more, or may be omitted, if necessary.

A display device according to an embodiment of the present invention can be described as follows:

According to an embodiment of the present invention, a light-emitting display device may include a substrate having first and second subpixels, each of which includes a light-emitting portion and a non-light-emitting portion surrounding the light-emitting portion; first electrodes disposed in the first and second subpixels, respectively; a bank including a bank hole located in the light-emitting portion and a bank trench located in the non-light-emitting portion; a first spacer disposed on top of the bank; a second spacer disposed in at least one bank trench; a light-emitting layer disposed on the first electrode and the second spacer, including a plurality of stacks and at least one charge generation layer disposed between the plurality of stacks; and a second electrode disposed on the light-emitting layer.

According to an embodiment of the present invention, the second spacer may have an inverse tapered shape.

According to embodiments of the present invention, the height from the substrate to the top of the second spacer may be different from the height from the substrate to the top of the first spacer.

According to an embodiment of the present invention, the height from the substrate to the top of the second spacer may be less than the height from the substrate to the top of the first spacer.

According to embodiments of the present invention, the thickness of the second spacer may be greater than the thickness of the bank.

According to an embodiment of the present invention, the second spacer may include at least a first spacer pattern and a second spacer pattern, and a spacer pattern hole may be disposed between the first spacer pattern and the second spacer pattern.

According to an embodiment of the present invention, the second spacer may include at least a first spacer pattern, a second spacer pattern, and a third spacer pattern, and a first spacer pattern hole may be arranged between the first spacer pattern and the second spacer pattern, and a second spacer pattern hole may be arranged between the second spacer pattern and the third spacer pattern.

According to an embodiment of the present invention, at least one of the first spacer pattern, the second spacer pattern, and the third spacer pattern may cover a portion of the bank.

According to an embodiment of the present invention, the light-emitting display device may further include a thin-film transistor disposed on the substrate, and a planarization layer disposed on the thin-film transistor.

According to embodiments of the present invention, the bank trenches can expose the planarization layer.

According to an embodiment of the present invention, the second spacer may be disposed on top of the planarization layer.

According to embodiments of the present invention, the light-emitting layer may be disposed on top of the planarization layer.

According to an embodiment of the present invention, the light-emitting layer may include a cut portion formed in the non-light-emitting portion by the second spacer.

According to embodiments of the present invention, the at least one charge generating layer may include a first charge generating layer and a second charge generating layer.

According to an embodiment of the present invention, each of the plurality of stacks may include a luminescent material layer.

According to an embodiment of the present invention, the light-emitting display device may further include a sealing layer disposed on the second electrode and a touch sensor layer disposed on the sealing layer.

According to an embodiment of the present invention, the touch sensor layer may include a first touch electrode and a second touch electrode overlapping the second spacer.

According to an embodiment of the present invention, the height of the second spacer may be smaller than the height of the first spacer.

According to an embodiment of the present invention, a light-emitting display device may include a substrate including a display area having a plurality of subpixels and non-emitting portions between the plurality of subpixels, and a non-display area adjacent to the display area, a first electrode disposed in each of the plurality of subpixels, a bank that partitions the plurality of subpixels, a light-emitting layer disposed on the first electrode, a second electrode disposed on the light-emitting layer, and a cutting portion that cuts the light-emitting layer between two adjacent subpixels among the plurality of subpixels.

According to an embodiment of the present invention, the bank may include a plurality of bank holes corresponding to a plurality of subpixels, respectively, and a bank trench corresponding to a non-light-emitting portion.

According to an embodiment of the present invention, the light emitting display device may further include a first spacer disposed on the bank.

According to an embodiment of the present invention, the cut may be formed by a second spacer disposed within the bank trench.

According to an embodiment of the present invention, the second spacer may be made of the same material as the bank.

According to an embodiment of the present invention, the height of the second spacer may be smaller than the height of the first spacer.

Although the present invention has been described in more detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments and can be modified in various ways without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed herein are intended to be illustrative rather than restrictive of the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not restrictive. The scope of protection of the present invention should be interpreted by the scope of the following claims, and all technical spirits within the equivalent range should be interpreted as being included in the scope of the present invention.

110: Substrate 200: Thin film transistor 340: Second spacer BT: Bank trench

Claims (21)

a substrate including first and second subpixels, each of which includes a light-emitting portion and a non-light-emitting portion surrounding the light-emitting portion;
a first electrode disposed in each of the first sub-pixel and the second sub-pixel;
a bank including a bank hole located in the light-emitting portion and a bank trench located in the non-light-emitting portion;
a first spacer disposed on an upper portion of the bank;
a second spacer disposed within the at least one bank trench;
a light emitting layer disposed on the first electrode and the bank trench, the light emitting layer including a plurality of stacks and at least one charge generating layer disposed between the plurality of stacks;
a second electrode disposed on the light-emitting layer ;
Including ,
the second spacer includes a plurality of spacer patterns, and at least one spacer pattern hole is disposed between the plurality of spacer patterns;
Light-emitting display device. The light-emitting display device of claim 1, wherein the second spacer has an inverse tapered shape. The light-emitting display device of claim 1, wherein the height from the substrate to the top of the second spacer is different from the height from the substrate to the top of the first spacer. The light-emitting display device of claim 1, wherein the height from the substrate to the top of the second spacer is smaller than the height from the substrate to the top of the first spacer. The light-emitting display device of claim 1, wherein the thickness of the second spacer is greater than the thickness of the bank. The light-emitting display device of claim 1, wherein the second spacer includes at least a first spacer pattern and a second spacer pattern, and a spacer pattern hole is disposed between the first spacer pattern and the second spacer pattern. 2. The light emitting display device of claim 1, wherein the second spacer includes at least a first spacer pattern, a second spacer pattern, and a third spacer pattern, a first spacer pattern hole is disposed between the first spacer pattern and the second spacer pattern , and a second spacer pattern hole is disposed between the second spacer pattern and the third spacer pattern. The light-emitting display device of claim 7, wherein at least one of the first spacer pattern, the second spacer pattern, and the third spacer pattern covers a portion of the bank. a thin film transistor disposed on the substrate;
The light emitting display device of claim 1 , further comprising a planarization layer disposed on the thin film transistor. The light-emitting display device of claim 9, wherein the bank trench exposes the planarization layer. The light-emitting display device of claim 9, wherein the second spacer is disposed on top of the planarization layer. The light-emitting display device of claim 9, wherein the light-emitting layer is disposed on top of the planarization layer. The light-emitting display device of claim 1, wherein the light-emitting layer includes a cut portion formed in the non-light-emitting portion by the second spacer. The light-emitting display device of claim 1, wherein the at least one charge generation layer includes a first charge generation layer and a second charge generation layer. The light-emitting display device of claim 1, wherein each of the plurality of stacks includes a light-emitting material layer. a sealing layer disposed on the second electrode;
The light emitting display device according to claim 1 , further comprising a touch sensor layer disposed on the encapsulation layer. The light-emitting display device of claim 16, wherein the touch sensor layer includes a first touch electrode and a second touch electrode overlapping the second spacer. The light-emitting display device of claim 1, wherein the height of the second spacer is smaller than the height of the first spacer. a substrate including a display area having a plurality of subpixels and non-light-emitting portions between the plurality of subpixels, and a non-display area adjacent to the display area;
a first electrode disposed in each of the plurality of sub-pixels;
a bank that partitions the plurality of sub-pixels;
a first spacer disposed on an upper portion of the bank;
a light-emitting layer disposed on the first electrode;
a second electrode disposed on the light-emitting layer;
a cutting portion that cuts the light-emitting layer between two adjacent subpixels among the plurality of subpixels,
the bank includes a plurality of bank holes respectively corresponding to the plurality of sub-pixels and a bank trench corresponding to the non-light-emitting portion;
the cut is formed by a second spacer disposed in the bank trench;
the second spacer includes a plurality of spacer patterns, and at least one spacer pattern hole is disposed between the plurality of spacer patterns;
Light-emitting display device. The light emitting display device of claim 19 , wherein the second spacers are made of the same material as the banks. The light emitting display device of claim 19 , wherein the height of the second spacer is smaller than the height of the first spacer.