JP7753992B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device having a polarization super junction (hereinafter simply referred to as PSJ) structure composed of a first nitride semiconductor layer and a second nitride semiconductor layer, and a method for manufacturing the same.

Semiconductor devices with a PSJ structure have been proposed (see, for example, Non-Patent Document 1). Specifically, these semiconductor devices include a semiconductor substrate with a PSJ structure in which a first nitride semiconductor layer, a second nitride semiconductor layer, and another first nitride semiconductor layer are stacked in this order on a substrate. The first nitride semiconductor layer is, for example, a gallium nitride layer (hereinafter simply referred to as a GaN layer), and the second nitride semiconductor layer is, for example, an aluminum gallium nitride layer (hereinafter simply referred to as an AlGaN layer). In the PSJ structure, two-dimensional electron gas (hereinafter simply referred to as 2DEG) is generated on one side of the interface between the GaN layer and the AlGaN layer, and two-dimensional hole gas (hereinafter simply referred to as 2DHG) is generated on the other side.

This semiconductor device is constructed by forming semiconductor elements such as MOSFETs (short for Metal Oxide Semiconductor Field Effect Transistors) on the semiconductor substrate. Furthermore, gate electrodes, source electrodes, drain electrodes, and other elements connected to the semiconductor elements are formed together on one surface of the semiconductor substrate opposite the substrate. Therefore, in this semiconductor device, when a predetermined voltage is applied to the gate electrode, a current flows along the surface of the semiconductor substrate.

Akira Nakajima, Yasunobu Sumida, Mahesh H. Dhyani, Hiroji Kawai and E. M. Sankara Narayanan “High Density Two-Dimensional Hole Gas Induced by Negative Polarization at GaN/AlGaN Heterointerface,” Published 10 December 2010, The Japan Society of Applied Physics

However, in semiconductor devices such as those described above, the gate electrode, source electrode, and drain electrode are all arranged on one side of the semiconductor substrate, which can lead to significant restrictions on the width and thickness of each electrode.

In view of the above, the present invention aims to provide a semiconductor device and a manufacturing method thereof that can reduce the constraints on electrodes connected to semiconductor elements.

In order to achieve the above object, claims 1 and 4 provide a semiconductor device having a semiconductor element formed thereon, the semiconductor substrate (10) having one surface (10a) and another surface (10b) and having the semiconductor element formed thereon, one surface side electrodes (19, 21, 51, 52, 61) arranged on one surface side of the semiconductor substrate and electrically connected to the semiconductor element, and another surface side electrodes (22, 53, 62) arranged on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element, the semiconductor substrate being hexagonal, the first main surface (11a) being an m-plane, one direction in the planar direction of the first main surface being a direction along the c-axis direction, and the second main surface (11b) opposite to the first main surface being an m-plane of the semiconductor substrate. The semiconductor device has a GaN substrate (11) that forms the other surface, a plurality of first column regions (12) that are arranged on the first main surface of the GaN substrate, are composed of a first nitride semiconductor layer, and are extended in one direction in the surface direction of the GaN substrate, and second column regions (13) that are arranged on the first main surface of the GaN substrate, are composed of a second nitride semiconductor layer that has a band gap higher than that of the first nitride semiconductor layer, are arranged between the first column regions, and form a PSJ structure (14) together with the first column regions, the first column regions and the second column regions being arranged alternately along the c-axis direction of the first main surface, allowing a current to flow between one surface and the other surface of the semiconductor substrate.
In addition, in claim 1, the device has a base layer (15) arranged on a polarization super junction structure and having a first conductivity type or a second conductivity type, and the one-side electrode has a base layer electrode (21, 52) connected to the base layer, an emitter layer (41) arranged on the base layer in a state where a part of the base layer is exposed, and an emitter electrode (51) as a one-side electrode connected to the emitter layer.
In the fourth aspect, the first column region and the second column region are formed of doped layers, and charge balance is maintained .

This allows the PSJ structures to be arranged along the surface of the GaN substrate, allowing current to flow in the thickness direction of the semiconductor substrate. Therefore, the electrodes connected to the semiconductor element can be arranged separately on one side and the other side of the semiconductor substrate as one-side electrodes and other-side electrodes. This makes it easier to reduce the constraints on the electrodes connected to the semiconductor element.

Claim 8 relates to a method for manufacturing a semiconductor device according to claim 1, and includes the steps of: preparing a GaN substrate; epitaxially growing a second column region-forming layer (130) that forms a second column region on a first main surface of the GaN substrate; forming a burying trench (131) in a portion of the second column region-forming layer where the first column region is to be located, and designating a portion different from the portion where the burying trench is formed as the second column region; epitaxially growing a first column region-forming layer (120) that forms the first column region so that the burying trench is filled; designating the portion located in the burying trench as the first column region, thereby constructing a PSJ structure having a first column region and a second column region.

This allows the manufacture of a semiconductor device in which PSJ structures are arranged along the surface of the GaN substrate, allowing current to flow in the thickness direction of the semiconductor substrate. This makes it easier to reduce the constraints on the electrodes connected to the semiconductor element.

Claim 11 is a method for manufacturing a semiconductor device related to claim 1, comprising the steps of: preparing a GaN substrate; epitaxially growing a first column region-forming layer (120) that constitutes a first column region on a first main surface of the GaN substrate; forming a burying trench (121) in a portion of the first column region-forming layer where the second column region is to be disposed, and designating a portion different from the portion where the burying trench is formed as the first column region (12); epitaxially growing a second column region-forming layer (130) that constitutes the second column region so that the burying trench is filled, and designating the portion located in the burying trench as the second column region, thereby configuring a PSJ structure having first and second column regions , and thereby configuring a polarization superjunction structure, whereby the first and second column regions are configured as doped layers .

This allows the manufacture of a semiconductor device in which PSJ structures are arranged along the surface of the GaN substrate, allowing current to flow in the thickness direction of the semiconductor substrate. This makes it easier to reduce the constraints on the electrodes connected to the semiconductor element.

Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described below.

1 is a cross-sectional view of a semiconductor device according to a first embodiment. FIG. 2 is a schematic diagram showing the crystal orientation of a GaN substrate. FIG. 1 is an energy band diagram of a PSJ structure. FIG. 2 is a schematic diagram illustrating the semiconductor device according to the first embodiment in an on state. FIG. 2 is a schematic diagram illustrating the semiconductor device according to the first embodiment in an off state. 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. 5B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 5A. 5C is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 5B. 5D is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 5C. 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a modified example of the first embodiment. 6B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 6A. 6C is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 6B. 6D is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 6C. FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 10 is a schematic diagram illustrating a semiconductor device according to a second embodiment in an on state. FIG. 10 is a schematic diagram illustrating a semiconductor device according to a second embodiment in an off state. FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. FIG. 10 is an energy band diagram of a PSJ structure according to a third embodiment. FIG. 2 is an enlarged view of the vicinity of the Fermi level in the energy band diagram of the first embodiment. FIG. 11 is an enlarged view of the vicinity of the Fermi level in the energy band diagram of the third embodiment. FIG. 11 is a schematic diagram illustrating a semiconductor device according to a third embodiment in an on-state. FIG. 11 is a schematic diagram illustrating a semiconductor device according to a third embodiment in an off state. 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a third embodiment. 14B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 14A. 14C is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 14B. 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a modification of the third embodiment. 15B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 15A. 15B is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 15B. FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment. FIG. 10 is a schematic diagram illustrating a semiconductor device according to a fourth embodiment in an on-state. FIG. 10 is a schematic diagram illustrating a semiconductor device according to a fourth embodiment in an off state. FIG. 10 is a cross-sectional view of a semiconductor device according to another embodiment.

Embodiments of the present invention will be described below with reference to the accompanying drawings. Note that in the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

(First embodiment)
A first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is suitable for use, for example, in a vehicle such as an automobile, for driving various electronic devices for the vehicle. In this embodiment, a semiconductor device in which an inversion-type MOSFET with a trench gate structure is formed as the semiconductor element will be described. Furthermore, when indicating a crystal orientation, a bar (-) should normally be placed above the desired number. However, due to limitations on expression based on electronic filing, a bar is placed before the desired number in this specification.

As shown in FIG. 1, the semiconductor device of this embodiment includes a GaN substrate 11 having a first major surface 11a and a second major surface 11b. Specifically, the GaN substrate 11 is an n ⁺ -GaN substrate made n ⁺ -type by ion implantation or an epitaxial layer, and constitutes a drain region in this embodiment. The GaN substrate 11 has a hexagonal crystal structure. In this case, the crystal orientation of the GaN substrate 11 is as shown in FIG. 2. In this embodiment, the first major surface 11a and the second major surface 11b of the GaN substrate 11 are {1-100} m-planes, and one direction in the plane of the first major surface 11a and the second major surface 11b is along the <0001> c-axis direction. In this embodiment, the left-right direction of the paper in FIG. 1 is along the c-axis direction, with the left side of the paper being the Ga-face side and the right side of the paper being the N-face side.

A PSJ structure 14 is disposed on a GaN substrate 11. The PSJ structure 14 includes a first column region 12 formed of an undoped u-GaN layer and a second column region 13 formed of an undoped u-AlGaN layer. In this embodiment, the u-GaN layer corresponds to the first nitride semiconductor layer, and the u-AlGaN layer corresponds to the second nitride semiconductor layer having a higher band gap than the first nitride semiconductor layer. The u-AlGaN layer constituting the second column region 13 is formed so as to satisfy 0≦x<1, where Al _1-x Ga _x N. Furthermore, the term "undoped layer" in this embodiment refers to a layer that is not doped with impurities, or a layer that contains n-type and p-type impurities but has a fixed charge of less than 5×10 ¹⁶ /cm ³ . Furthermore, the phrase "the fixed charge is less than 5×10 ¹⁶ /cm ³ even when n-type impurities and p-type impurities are contained" assumes that the n-type impurities or p-type impurities are unintentionally contained during manufacturing, rather than being actively doped with impurities. Furthermore, the fixed charge here means the concentration of positively charged ionized impurities after emitting electrons in the case of n-type, and the concentration of negatively charged ionized impurities after emitting holes in the case of p-type.

The first column regions 12 and the second column regions 13 are each composed of an epitaxial layer. The first column regions 12 and the second column regions 13 extend in one direction along the surface of the GaN substrate 11 as the longitudinal direction, and are arranged alternately in a direction intersecting the longitudinal direction. In other words, the first column regions 12 and the second column regions 13 are arranged in a stripe pattern. The first column regions 12 and the second column regions 13 are arranged alternately along the c-axis direction.

In the PSJ structure 14 thus constructed on the GaN substrate 11, 2DEG (i.e., negative polarization charges) and 2DHG (i.e., positive polarization charges) are induced at the AlGaN/GaN interface, which is the interface between the first column region 12 and the second column region 13, due to polarization effects and other factors. Specifically, as shown in Figure 3, in the first column region 12, 2DEG is generated on the Ga-face side, and 2DHG is generated on the N-face side. As a result, in the second column region 13, 2DEG is generated on the Ga-face side, and 2DHG is generated on the N-face side. Note that Figure 3 is an energy band diagram of the portion along line III-III in Figure 1.

1, a base layer 15 made of a p-GaN layer doped with p-type impurities is disposed on the PSJ structure 14. The base layer 15 is made of an epitaxial layer, and although not particularly limited, the doping amount of the p-type impurity Mg (i.e., magnesium) is 1×10 ¹⁹ /cm ² and the thickness is about 500 nm.

A source region 16 made of an n-GaN layer doped with n ⁺ type impurities is disposed on the surface of the base layer 15. The source region 16 is formed of an epitaxial layer or an ion-implanted layer formed by ion implantation. In this embodiment, the source region 16 corresponds to an impurity region.

In this embodiment, the semiconductor substrate 10 is configured to include the GaN substrate 11, PSJ structure 14, base layer 15, source region 16, etc., as described above. One surface 10a of the semiconductor substrate 10 in this embodiment is configured as the source region 16, and the other surface 10b is configured as the second main surface 11b of the GaN substrate 11.

A plurality of gate trenches 17 are formed in the semiconductor substrate 10, penetrating the source region 16 and base layer 15 from the one surface 10a side to reach the first column region 12. The multiple gate trenches 17 extend longitudinally in one direction of the surface 10a of the semiconductor substrate 10 (i.e., the depth direction in Figure 1), so that the gate trenches 17 form equally spaced stripes. Specifically, the multiple gate trenches 17 extend longitudinally along the first column region 12.

Each gate trench 17 is filled with a gate insulating film 18 formed to cover the wall surface of the gate trench 17, and a gate electrode 19 made of polysilicon or the like formed on this gate insulating film 18. This forms a trench gate structure.

In addition, contact trenches 20 are formed in the semiconductor substrate 10 between adjacent trench gate structures, so as to penetrate the source region 16 from the one surface 10a side and reach the base layer 15. Note that in this embodiment, the contact trenches 20 are formed so as to reach the base layer 15 located above the second column region 13.

A source electrode 21 is disposed in the contact trench 20. In this embodiment, the source electrode 21 is composed of multiple metals, such as Ni/Al. Specifically, the portion of the source electrode 21 that contacts the portion that constitutes the n-type region (i.e., the source region 16) is composed of a metal that can make ohmic contact with the n-type region. In addition, the portion of the source electrode 21 that contacts the p-type region (i.e., the base layer 15) is composed of a metal that can make ohmic contact with the p-type region. In this embodiment, the source electrode 21 has a first portion 21a that contacts the base layer 15 and contains Ni, and a second portion 21b that contacts the source region 16 and contains Al/Ti. In this embodiment, the gate electrode 19 and the source electrode 21 correspond to one-side electrodes. In this embodiment, the source electrode 21 corresponds to a base layer electrode.

A drain electrode 22 electrically connected to the GaN substrate 11 is formed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the drain electrode 22 corresponds to the other surface electrode.

In the semiconductor device of this embodiment, an n-channel inversion trench gate MOSFET is configured with this structure. In this embodiment, the n ⁺ type and ^n- type correspond to the first conductivity type, and the p type corresponds to the second conductivity type.

Next, the operation and effects of the semiconductor device of this embodiment will be described with reference to Figures 4A and 4B. Note that the GaN substrate 11 and drain electrode 22 are omitted in Figures 4A and 4B.

First, in the PSJ structure 14, as shown in FIG. 4A, 2DEG 31 and 2DHG 32 are generated at the interface between the first column region 12 and the second column region 13. When a voltage equal to or greater than the threshold voltage, for example, 6 V, is applied to the gate electrode 19, an inversion layer is formed on the surface of the base layer 15 that contacts the gate trench 17. This causes electrons to be supplied from the source electrode 21, resulting in an on-state in which current flows to the drain electrode 22 via the 2DEG 31 formed in the first column region 12. In other words, current flows through the semiconductor device along the thickness direction of the semiconductor substrate 10. At this time, because there are no parts of the 2DHG 32 that are easily extracted, the current flowing through the semiconductor device is dominated by electron current.

As shown in Figure 4B, when the gate voltage applied to the gate electrode 19 becomes a voltage less than the threshold voltage, for example, 0 V, no inversion layer is formed in the base layer 15, and no new electrons are supplied from the source electrode 21. Therefore, even if a positive voltage, for example, 300 V, is applied to the drain electrode 22, the semiconductor device enters an off state in which no current flows. At this time, electrons supplied to the first column region 12 are discharged from the drain electrode 22 side. Holes generated in the first column region 12 are discharged from the source electrode 21 side. As a result, the PSJ structure 14 becomes depleted, entering a charge-balanced state in which polarization charges are balanced. The dotted lines in Figure 4B show a schematic diagram of electric field intensity contours.

For this reason, such a semiconductor device ideally achieves a breakdown voltage characteristic of up to 3 MV/cm, which is the breakdown field strength of GaN. In other words, for example, by making the thickness of the PSJ structure 14 1 μm, a breakdown voltage of 300 V can be obtained.

Here, for example, it has been reported that a semiconductor device having a superjunction structure using silicon has a maximum breakdown strength of 0.3 MV/cm. Therefore, compared to such semiconductor devices, the semiconductor device of this embodiment can achieve the same maximum breakdown strength with a column thickness (i.e., column depth) that is 1/10 of that of such semiconductor devices. In other words, the semiconductor device of this embodiment can be made to have a PSJ structure 14 with a thinner column thickness than a semiconductor device having a superjunction structure using silicon, making the manufacturing process easier. Note that the column thickness is, in other words, the length along the stacking direction of the GaN substrate 11 and the PSJ structure 14.

Furthermore, as shown in Figure 4B, the electric field strength is less likely to concentrate in the PSJ structure 14 of this embodiment. This prevents a large electric field strength from being applied to the gate insulating film 18, improving the reliability of the gate insulating film 18.

Next, a method for manufacturing the above semiconductor device will be described with reference to Figures 5A to 5D.

5A, an n ⁺ type GaN substrate 11 is prepared, with its first main surface 11a and second main surface 11b being m-planes. Then, a second column region-forming layer 130 that forms the second column region 13 is disposed by epitaxial growth on the first main surface 11a of the GaN substrate 11. The second column region-forming layer 130 is composed of an undoped u-AlGaN layer.

Next, as shown in FIG. 5B, resist 100 is placed on the second column region forming layer 130, and the resist 100 is patterned so that the region where the first column region 12 is to be formed is exposed. Then, dry etching such as ICP-RIE (Inductively Coupled Plasma-Reactive Ion Etching) is performed using the resist 100 as a mask to form buried trenches 131 for disposing the first column region 12. As a result, the second column region 13 is formed in the portion of the second column region forming layer 130 that is sandwiched between the buried trenches 131. In other words, the second column region 13 is formed in the portion of the second column region forming layer 130 where the buried trenches 131 are not formed.

Next, as shown in FIG. 5C, a first column region-forming layer 120 that constitutes the first column region 12 is disposed by epitaxial growth so that the burying trench 131 is filled. As a result, the first column region 12 is formed in the portion that is located in the burying trench 131, and a PSJ structure 14 having the first column region 12 and second column region 13 is formed. The first column region-forming layer 120 is composed of an undoped u-GaN layer.

Next, as shown in FIG. 5D, the first column region forming layer 120 formed on the second column region forming layer 130 is removed by polishing or CMP (Chemical Mechanical Polishing) or other methods.

After that, although detailed steps will be omitted, the semiconductor device is manufactured by carrying out a predetermined semiconductor manufacturing process to form the base layer 15, source region 16, trench gate structure, source electrode 21, drain electrode 22, etc.

In the present embodiment described above, the PSJ structures 14 are arranged along the surface direction of the GaN substrate 11, allowing current to flow in the thickness direction of the semiconductor substrate 10. Therefore, the electrodes 19, 21, and 22 connected to the semiconductor element can be arranged separately on the one surface 10a and the other surface 10b of the semiconductor substrate 10, making it easier to reduce the constraints on the electrodes 19, 21, and 22.

In this embodiment, a base layer 15 composed of a p-GaN layer is disposed on the PSJ structure 14. Therefore, when manufacturing a semiconductor device, after performing the step in FIG. 5C, the base layer 15 may be formed by depositing a p-GaN layer directly on the u-GaN layer without performing the step in FIG. 5D.

(1) In this embodiment, a MOSFET is formed as the semiconductor element, and the base layer 15 disposed on the PSJ structure 14 is connected to the source electrode 21. Therefore, when the device is off, holes that may be present in the first column region 12 can be extracted from the source electrode 21, and the PSJ structure 14 can be placed in a state where the polarization charge is balanced.

(2) In this embodiment, the first column region 12 and the second column region 13 are arranged along the surface of the GaN substrate 11, and current flows in the thickness direction of the semiconductor substrate 10. This makes it easier to pass a large current compared to when a PSJ structure is formed by stacking GaN and AlGaN layers and using this PSJ structure to form a MOSFET. That is, a semiconductor device having a PSJ structure in which GaN and AlGaN layers are stacked can be considered a semiconductor device in which a MOSFET is formed by arranging a gate electrode on the PSJ structure. However, in this semiconductor device, if too many GaN and AlGaN layers are stacked, the semiconductor device may not be able to switch between the on and off states using the gate voltage applied to the gate electrode. In contrast, in this embodiment, the first column region 12 and the second column region 13 are arranged along the surface of the GaN substrate 11, and current flows in the thickness direction of the semiconductor substrate 10. Therefore, the number of first column regions 12 and second column regions 13 can be changed as needed, making it easier to accommodate large currents.

(3) In this embodiment, the first column region 12 and the second column region 13 are composed of undoped layers. Therefore, compared to the case where the first column region 12 and the second column region 13 are composed of doped layers as in the third embodiment described below, the amount of impurities is smaller, which allows holes to escape more quickly when the device is turned off, thereby increasing the switching speed.

(Modification of the first embodiment)
A modification of the first embodiment will be described. In the first embodiment, the PSJ structure 14 may be formed on the GaN substrate 11 as follows. That is, as shown in FIG. 6A , after preparing the GaN substrate 11, a first column region-forming layer 120 that forms the first column region 12 is disposed on the first main surface 11a of the GaN substrate 11 by epitaxial growth. Next, as shown in FIG. 6B , a resist 100 is disposed on the first column region-forming layer 120, and dry etching is performed to form burying trenches 121 in which the second column region 13 will be disposed. As a result, the first column region 12 is formed in the portion of the first column region-forming layer 120 that is sandwiched between the burying trenches 121. That is, the first column region 12 is formed in the portion of the first column region-forming layer 120 in which the burying trenches 121 are not formed.

Next, as shown in FIG. 6C, a second column region forming layer 130 is deposited by epitaxial growth so as to fill the burying trench 121. As a result, a second column region 13 is formed in the portion located in the burying trench 121, and a PSJ structure 14 having a first column region 12 and a second column region 13 is formed.

Then, as shown in FIG. 6D, the second column region forming layer 130 formed on the first column region forming layer 120 is removed. In this way, the PSJ structure 14 may be disposed on the GaN substrate 11.

Second Embodiment
A second embodiment will be described. This embodiment differs from the first embodiment in that the semiconductor element is changed. As the rest of the configuration is the same as the first embodiment, a description thereof will be omitted here.

7, the semiconductor device of this embodiment is configured by forming an HBT (abbreviation for Heterojunction Bipolar Transistor) as a semiconductor element. Specifically, an emitter layer 41 made of an n-type n-GaN layer is disposed on the base layer 15, on the side opposite the first column region 12 with the base layer 15 in between. Then, a contact layer 42 made of an n ⁺ -type n ⁺ -GaN layer having a higher impurity concentration than the emitter layer 41 is disposed on the emitter layer 41. Note that the base layer 15 of this embodiment is doped with Mg, a p-type impurity, at a concentration of 1× ¹⁰²⁰ / ^cm2 and has a thickness of 100 nm or less.

The semiconductor substrate 10 has one surface 10a formed by the contact layer 42 and the other surface 10b formed by the second major surface 11b of the GaN substrate 11. Therefore, in this embodiment, the semiconductor substrate 10 can also be said to have an exposing trench 43 formed on one surface 10a of the semiconductor substrate 10 so that the base layer 15 is exposed between the emitter layers 41.

An emitter electrode 51 is disposed on the contact layer 42. A base electrode 52 is disposed on the portion of the base layer 15 that is exposed from the emitter layer 41. A collector electrode 53 is disposed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the emitter electrode 51 and the base electrode 52 correspond to one-surface electrodes, and the collector electrode 53 corresponds to the other-surface electrode.

Next, the operation and effects of the semiconductor device of this embodiment will be described with reference to Figures 8A and 8B.

Similar to the first embodiment described above, in the PSJ structure 14, as shown in FIG. 8A, 2DEG 31 and 2DHG 32 are generated at the interface between the first column region 12 and the second column region 13. When, for example, 3 to 4 V is applied to the base electrode 52, electrons are supplied from the emitter electrode 51, and current flows to the collector electrode 53 via the 2DEG 31 formed in the first column region 12. In this case, because there are no parts of the 2DHG 32 that are easily extracted, the current flowing through the semiconductor device is dominated by electron current.

As shown in Figure 8B, when the voltage applied to the base electrode 52 becomes, for example, 0 V, the base potential rises and new electrons are no longer supplied from the emitter electrode 51. Therefore, even if a positive voltage, for example, 300 V, is applied to the collector electrode 53, the semiconductor device enters an off state in which no current flows. At this time, electrons supplied to the first column region 12 are discharged from the collector electrode 53. Holes generated in the first column region 12 are discharged from the base electrode 52. This depletes the PSJ structure 14, bringing it into a charge-balanced state where the polarization charges are balanced. The dotted lines in Figure 8B show a schematic diagram of the electric field intensity contours.

In the present embodiment described above, the PSJ structures 14 are arranged along the surface direction of the GaN substrate 11, and current flows in the thickness direction of the semiconductor substrate 10. Therefore, the same effects as those of the first embodiment can be obtained.

(1) In this embodiment, an HBT is formed as the semiconductor element, and the base layer 15 disposed on the PSJ structure 14 is connected to the base electrode 52. Therefore, when the device is off, holes that may be present in the first column region 12 can be extracted from the base electrode 52, allowing the PSJ structure 14 to be in a state where the polarization charge is balanced.

(Third embodiment)
A third embodiment will now be described. This embodiment differs from the first embodiment in that the configurations of the first column region 12 and the second column region 13 are modified. As the rest of the configuration is the same as the first embodiment, a description thereof will be omitted here.

The basic configuration of the semiconductor device of this embodiment is the same as that of the first embodiment. However, in this embodiment, as shown in FIG. 9, the first column region 12 is composed of an n-GaN layer doped with n-type impurities, and the second column region 13 is composed of a p-AlGaN layer doped with p-type impurities. In other words, the first column region 12 and the second column region 13 are composed of doped layers.

An example of an n-type impurity doped into the first column region 12 is Si (i.e., silicon). An example of a p-type impurity doped into the second column region 13 is Mg. The impurity concentrations of the first column region 12 and the second column region 13 are adjusted according to the width along the arrangement direction (i.e., the C-axis direction) and the activation rate of the doped impurities so that charge balance is maintained. Here, configuring the first column region 12 and the second column region 13 so that charge balance is maintained means configuring the first column region 12 and the second column region 13 as follows. That is, the first column region 12 and the second column region 13 are configured so that the product of the width of the first column region 12, the n-type impurity concentration, and the activation rate of the n-type impurity is equal to the product of the width of the second column region 13, the p-type impurity concentration, and the activation rate of the p-type impurity.

The first column region 12 and the second column region 13 are composed of doped layers that are actively doped with impurities, and have an impurity concentration that results in a fixed charge of 5×10 ¹⁶ /cm ³ or more. In the GaN layer, at room temperature, the activation rate of p-type Mg is approximately 10% at most, and the activation rate of n-type Si is approximately 100%.

In this PSJ structure 14, 2DEG and 2DHG are induced at the AlGaN/GaN interface between the first column region 12 and the second column region 13 due to polarization effects and the like. In this embodiment, the first column region 12 is composed of an n-GaN layer, and the second column region 13 is composed of a p-AlGaN layer. Therefore, as shown in Figure 10, compared to Figure 3 above, the energy band in the first column region 12 changes to be convex downward, and the energy band in the second column region 13 changes to be convex upward. Note that Figure 10 is an energy band diagram of a portion along line X-X in Figure 9.

11 and 12, in the semiconductor device of this embodiment, the region where the conductor bottom energy Ec is lower than the Fermi level (i.e., quantum well width d1) is wider than in the semiconductor device of the first embodiment. As a result, the 2DEG generated on the Ga-face side of the first column region 12 increases. Note that in the semiconductor device of this embodiment, the region where the valence band top energy Ev is higher than the Fermi level (i.e., quantum well width d2) is narrower than in the semiconductor device of the first embodiment. As a result, the 2DHG generated on the N-face side of the first column region 12 decreases.

Next, the operation and effects of the semiconductor device of this embodiment will be described with reference to Figures 13A and 13B. Note that the GaN substrate 11 and drain electrode 22 are omitted in Figures 13A and 13B.

In the semiconductor device of this embodiment, as shown in FIG. 13A, 2DEG 31 and 2DHG 32 are generated at the interface between the first column region 12 and the second column region 13, as in the first embodiment. Furthermore, since the first column region 12 is composed of an n-type layer, fixed positive charges 33 are generated, and since the second column region 13 is composed of a p-type layer, fixed negative charges 34 are generated. Furthermore, as described above, the amount of 2DEG 31 generated on the Ga-face side of the first column region 12 increases. Therefore, the electron current can be increased when the semiconductor device is in the on state, improving current capability.

As shown in Figure 13B, when the gate voltage applied to the gate electrode 19 becomes less than the threshold voltage, an inversion layer is not formed in the base layer 15, and new electrons are no longer supplied from the source electrode 21. The electrons supplied to the first column region 12 are then discharged from the drain electrode 22, and holes generated in the first column region 12 are discharged from the source electrode 21, resulting in an off-state. The PSJ structure 14 then becomes depleted, entering a charge balance state where the polarization charges are balanced and the fixed charges are balanced. The dotted lines in Figure 13B show a schematic diagram of the electric field intensity contours.

Next, the manufacturing method for the above semiconductor device will be described with reference to Figures 14A to 14C.

First, as shown in Fig. 14A, an n ⁺ type GaN substrate 11 is prepared, with the first main surface 11a and the second main surface 11b being m-planes. Then, a second column region-forming layer 130 that forms the second column region 13 is disposed on the first main surface 11a of the GaN substrate 11 by epitaxial growth. At this time, in this embodiment, the second column region-forming layer 130 is disposed while being doped with a p-type impurity such as Mg. In other words, the second column region-forming layer 130, which is a doped layer, is disposed.

Next, as shown in FIG. 14B, resist 100 is placed on the second column region forming layer 130, and dry etching is performed to form burying trenches 131 for disposing the first column regions 12. As a result, second column regions 13 composed of p-AlGaN layers are formed in the portions of the second column region forming layer 130 that are sandwiched between the burying trenches 131.

Next, as shown in FIG. 14C , a first column region forming layer 120 that constitutes the first column region 12 is deposited by epitaxial growth so that the burying trench 131 is filled. In this embodiment, the first column region forming layer 120 is deposited while being doped with n-type impurities such as Si. In other words, the first column region forming layer 120, which is a doped layer, is deposited. As a result, the first column region 12 is formed in the portion that is located in the burying trench 131, and a PSJ structure 14 having the first column region 12 and second column region 13 is formed. The impurity concentrations of the first column region forming layer 120 and the second column region forming layer 130 are adjusted so that charge balance is maintained when the first column region 12 and second column region 13 are formed.

After that, although not specifically shown, the semiconductor device of this embodiment is manufactured by performing the steps shown in Figure 5D and subsequent steps in the same manner as in the first embodiment described above.

In the present embodiment described above, the PSJ structures 14 are arranged along the surface direction of the GaN substrate 11, and current flows in the thickness direction of the semiconductor substrate 10. Therefore, the same effects as those of the first embodiment can be obtained.

(1) In this embodiment, the first column region 12 is composed of an n-GaN layer doped with n-type impurities, and the second column region 13 is composed of a p-AlGaN layer doped with p-type impurities. Charge balance is maintained between the first column region 12 and the second column region 13. Therefore, when the semiconductor device is turned on, the 2DEG can be increased, improving current performance.

(Modification of the third embodiment)
A modification of the third embodiment will be described. In the third embodiment, a PSJ structure 14 may be formed on a GaN substrate 11, as in the modification of the first embodiment. That is, as shown in FIG. 15A , after preparing a GaN substrate 11, a first column region-forming layer 120 that forms the first column region 12 is disposed by epitaxial growth on the first main surface 11a of the GaN substrate 11. At this time, the first column region-forming layer 120 is disposed while being doped with an n-type impurity such as Si. Next, as shown in FIG. 15B , a resist 100 is disposed on the first column region-forming layer 120, and dry etching is performed to form burying trenches 121 for disposing the second column region 13. As a result, the first column region 12 is formed in the portion of the first column region-forming layer 120 that is sandwiched between the burying trenches 121. Next, as shown in FIG. 15C , a second column region-forming layer 130 is disposed by epitaxial growth so as to fill the burying trenches 121. At this time, the second column region forming layer 130 is disposed while being doped with a p-type impurity such as Mg. As a result, the second column region 13 is formed in the portion disposed in the burying trench 121, and a PSJ structure 14 having the first column region 12 and the second column region 13 is formed.

6D as in the modified example of the first embodiment, a base layer 15 made of a p-GaN layer is disposed on the PSJ structure 14. Therefore, when manufacturing a semiconductor device, after the step of FIG. 15C is performed, the second column region-forming layer 130 formed on the first column region-forming layer 120 may not be removed, and a p-GaN layer may be formed as is to form the base layer 15. In other words, the PSJ structure 14 and the base layer 15 may be formed continuously by setting x to 1 in the Al _1-x Ga _x N layer that forms the second column region 13.

(Fourth embodiment)
A fourth embodiment will now be described. This embodiment differs from the second embodiment in that the configurations of the first column region 12 and the second column region 13 are modified. As the rest of the configuration is the same as the second embodiment, a description thereof will be omitted here.

As shown in FIG. 16, the semiconductor device of this embodiment is configured with an HBT similar to that of the second embodiment. However, similar to the third embodiment, the semiconductor device of this embodiment has the first column region 12 configured with an n-GaN layer doped with n-type impurities, and the second column region 13 configured with a p-AlGaN layer doped with p-type impurities. In other words, the first column region 12 and the second column region 13 are configured with doped layers. Note that, similar to the third embodiment, the widths and impurity concentrations of the first column region 12 and the second column region 13 are adjusted to maintain charge balance.

Next, the operation and effects of the semiconductor device of this embodiment will be described with reference to Figures 17A and 17B.

As in the second embodiment, in the PSJ structure 14, as shown in FIG. 17A, 2DEG 31 and 2DHG 32 are generated at the interface between the first column region 12 and the second column region 13. Also, as in the third embodiment, fixed positive charges 33 are generated in the first column region 12, and fixed negative charges 34 are generated in the second column region 13. Furthermore, in the first column region 12, the amount of 2DEG 31 (i.e., negative polarization charges) generated on the Ga-face side increases. This increases the electron current when the semiconductor device is in the on state, improving current capability.

As shown in Figure 17B, when the voltage applied to the base electrode 52 becomes, for example, 0 V, the base potential rises and new electrons are no longer supplied from the emitter electrode 51. Therefore, even if a positive voltage, for example, 300 V, is applied to the collector electrode 53, the semiconductor device enters an off state in which no current flows. At this time, electrons supplied to the first column region 12 are discharged from the collector electrode 53. Holes generated in the first column region 12 are discharged from the base electrode 52. As a result, the PSJ structure 14 becomes depleted, and a charge balance state is achieved in which the polarization charges are balanced and the fixed charges are balanced. The dotted lines in Figure 17B show a schematic diagram of the electric field intensity contours.

In the present embodiment described above, the PSJ structures 14 are arranged along the surface direction of the GaN substrate 11, and current flows in the thickness direction of the semiconductor substrate 10. Therefore, the same effects as those of the first embodiment can be obtained.

(1) In this embodiment, the first column region 12 is composed of an n-GaN layer doped with n-type impurities, and the second column region 13 is composed of a p-AlGaN layer doped with p-type impurities. The widths and impurity concentrations of the first column region 12 and the second column region 13 are adjusted to maintain charge balance. Therefore, when the semiconductor device is turned on, the 2DEG 31 can be increased, improving current performance.

(Other embodiments)
Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

For example, the first and third embodiments described semiconductor devices in which a MOSFET was formed as the semiconductor element, and the second and fourth embodiments described semiconductor devices in which an HBT was formed as the semiconductor element. However, the semiconductor element may be another type of semiconductor element, or may be a diode, as shown in FIG. 18 . Specifically, in this semiconductor device, a PSJ structure 14 is disposed on a GaN substrate 11 to form a semiconductor substrate 10. One surface 10a of the semiconductor substrate 10 is formed on the PSJ structure 14 side, and the other surface 10b is formed by the second major surface 11b of the GaN substrate 11. An anode electrode 61 serving as a one-surface electrode is disposed on the one surface 10a of the semiconductor substrate 10, and a cathode electrode 62 serving as a other-surface electrode is disposed on the other surface 10b. In this case, as in the third and fourth embodiments, the first column region 12 and the second column region 13 may be formed as doped layers.

In the first and third embodiments, an n-channel trench gate MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the semiconductor device may have a p-channel trench gate MOSFET formed therein instead of an n-channel MOSFET. Furthermore, the semiconductor device may have an IGBT formed therein with a similar structure in addition to the MOSFET. In the case of an IGBT, the vertical MOSFET is the same as that described in the first embodiment, except that the n ⁺ type GaN substrate 11 in the first and third embodiments is replaced with a p ⁺ type GaN substrate 11.

Furthermore, in the second and fourth embodiments described above, an npn-type HBT in which the first conductivity type is n-type and the second conductivity type is p-type was used as an example of the semiconductor element. However, the semiconductor device may also be configured with a pnp-type HBT formed as the semiconductor element.

In the third and fourth embodiments, a semiconductor device was described in which the first column region 12 was doped with n-type impurities and the second column region 13 was doped with p-type impurities. However, the first column region 12 may be configured as a layer doped with p-type impurities and the second column region 13 may be configured as a layer doped with n-type impurities. In this case, compared to when the first column region 12 and the second column region 13 are undoped layers, the region where the upper end energy Ev of the valence band is higher than the Fermi level (i.e., the quantum well width d2) increases, resulting in a higher hole concentration. Therefore, such a semiconductor device is preferably applied to a configuration in which hole current is dominant in the on state.

In the third and fourth embodiments, examples were described in which the first column region 12 and the second column region 13 were formed as doped layers by epitaxial growth while doping with impurities. However, the first column region 12 and the second column region 13, which are doped layers, may also be formed as follows. For example, after performing the step of FIG. 5D in the first embodiment, impurity ions may be implanted to form the first column region 12 composed of an n-GaN layer and the second column region 13 composed of a p-AlGaN layer.

(Features of the present invention)
[Claim 1]
A semiconductor device in which a semiconductor element is formed,
a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which the semiconductor element is formed;
One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element;
and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element,
The semiconductor substrate is
a gallium nitride substrate (11) having a hexagonal crystal structure, a first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and a second main surface (11b) opposite to the first main surface constituting the other surface of the semiconductor substrate;
a plurality of first column regions (12) arranged on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) arranged on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which together with the first column regions form a polarization super junction structure (14),
the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface,
A semiconductor device in which a current flows between one surface and the other surface of the semiconductor substrate.
[Claim 2]
a base layer (15) disposed on the polarization superjunction structure and having a first conductivity type or a second conductivity type;
2. The semiconductor device according to claim 1, wherein the one-surface electrode has a base layer electrode (21, 52) connected to the base layer.
[Claim 3]
an impurity region (16) disposed on the base layer and connected to the base layer electrode;
3. The semiconductor device according to claim 2, further comprising: a trench gate structure having a gate insulating film (18) formed on a wall surface of a trench (17) that penetrates the base layer and reaches the polarization super junction structure; and a gate electrode (19) formed on the gate insulating film as the one-side electrode.
[Claim 4]
an emitter layer (41) disposed on the base layer in a state where a part of the base layer is exposed;
3. The semiconductor device according to claim 2, further comprising an emitter electrode (51) as the one-surface electrode connected to the emitter layer.
[Claim 5]
The semiconductor device according to claim 1 , wherein the one-surface electrode is disposed on the polarization super junction structure and is directly connected to the polarization super junction structure.
[Claim 6]
6. The semiconductor device according to claim 1, wherein the first column region and the second column region are formed of an undoped layer.
[Claim 7]
6. The semiconductor device according to claim 1, wherein the first column region and the second column region are formed of doped layers, and a charge balance is maintained.
[Claim 8]
a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which a semiconductor element is formed;
One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element;
and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element,
The semiconductor substrate is
a gallium nitride substrate (11) having a hexagonal crystal structure, a first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and a second main surface (11b) opposite to the first main surface constituting the other surface of the semiconductor substrate;
a plurality of first column regions (12) arranged on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) arranged on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which together with the first column regions form a polarization super junction structure (14),
the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface,
A method for manufacturing a semiconductor device in which a current flows between one surface and another surface of the semiconductor substrate,
providing the gallium nitride substrate;
epitaxially growing a second column region forming layer (130) that forms the second column region on a first main surface of the gallium nitride substrate;
forming a buried trench (131) in a portion of the second column region forming layer where the first column region is to be disposed, and defining a portion different from the portion where the buried trench is formed as the second column region;
epitaxially growing a first column region forming layer (120) that forms the first column region so that the burying trench is filled, and configuring the polarization super junction structure having the first column region and the second column region, with the portion located in the burying trench being the first column region.
[Claim 9]
a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which a semiconductor element is formed;
One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element;
and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element,
The semiconductor substrate is
a gallium nitride substrate (11) having a hexagonal crystal structure, a first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and a second main surface (11b) opposite to the first main surface constituting the other surface of the semiconductor substrate;
a plurality of first column regions (12) arranged on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) arranged on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which together with the first column regions form a polarization super junction structure (14),
the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface,
A method for manufacturing a semiconductor device in which a current flows between one surface and another surface of the semiconductor substrate,
providing the gallium nitride substrate;
epitaxially growing a first column region forming layer (120) that forms the first column region on a first main surface of the gallium nitride substrate;
forming a buried trench (121) in a portion of the first column region forming layer where the second column region is to be disposed, and defining a portion different from the portion where the buried trench is formed as the first column region;
epitaxially growing a second column region forming layer (130) that forms the second column region so that the burying trench is filled, and configuring the polarization super junction structure having the first column region and the second column region, with the portion located in the burying trench being the second column region.
[Claim 10]
10. The method for manufacturing a semiconductor device according to claim 8, wherein the polarization superjunction structure is formed by forming the first column region and the second column region each made of an undoped layer.
[Claim 11]
10. The method for manufacturing a semiconductor device according to claim 8, wherein the first column region and the second column region are formed of doped layers by forming the polarization super junction structure.

REFERENCE SIGNS LIST 10 Semiconductor substrate 11 GaN substrate 11a First main surface 11b Second main surface 10a One surface 10b Other surface 12 First column region 13 Second column region 14 PSJ structure 21 Source electrode (one-surface electrode)
22 Drain electrode (other surface electrode)

Claims (11)

A semiconductor device in which a semiconductor element is formed,
a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which the semiconductor element is formed;
One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element;
and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element,
The semiconductor substrate is
a gallium nitride substrate (11) having a hexagonal crystal structure, a first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and a second main surface (11b) opposite to the first main surface constituting the other surface of the semiconductor substrate;
a plurality of first column regions (12) arranged on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) arranged on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which together with the first column regions form a polarization super junction structure (14),
the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface,
A current flows between one surface and the other surface of the semiconductor substrate ,
a base layer (15) disposed on the polarization superjunction structure and having a first conductivity type or a second conductivity type;
The one-surface electrode has a base layer electrode (21, 52) connected to the base layer,
an emitter layer (41) disposed on the base layer in a state where a part of the base layer is exposed;
an emitter electrode (51) as the one-surface electrode connected to the emitter layer . 2. The semiconductor device according to claim 1 , wherein the first column region and the second column region are formed of undoped layers. 2. The semiconductor device according to claim 1 , wherein the first column region and the second column region are formed of doped layers, and a charge balance is maintained. A semiconductor device in which a semiconductor element is formed,
a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which the semiconductor element is formed;
One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element;
and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element,
The semiconductor substrate is
a gallium nitride substrate (11) having a hexagonal crystal structure, a first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and a second main surface (11b) opposite to the first main surface constituting the other surface of the semiconductor substrate;
a plurality of first column regions (12) arranged on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) arranged on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which together with the first column regions form a polarization super junction structure (14),
the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface,
A current flows between one surface and the other surface of the semiconductor substrate ,
The first column region and the second column region are formed of doped layers, and a charge balance is maintained . a base layer (15) disposed on the polarization superjunction structure and having a first conductivity type or a second conductivity type;
5. The semiconductor device according to claim 4 , wherein the one-surface electrode has a base layer electrode (21, 52) connected to the base layer. an impurity region (16) disposed on the base layer and connected to the base layer electrode;
6. The semiconductor device according to claim 5, further comprising: a trench gate structure having a gate insulating film (18) formed on a wall surface of a trench (17) that penetrates the base layer and reaches the polarization super junction structure; and a gate electrode (19) formed on the gate insulating film as the one -side electrode. The semiconductor device according to claim 4 , wherein the one-surface electrode is disposed on the polarization super junction structure and is directly connected to the polarization super junction structure. a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which a semiconductor element is formed;
One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element;
and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element,
The semiconductor substrate is
a gallium nitride substrate (11) having a hexagonal crystal structure, a first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and a second main surface (11b) opposite to the first main surface constituting the other surface of the semiconductor substrate;
a plurality of first column regions (12) arranged on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) arranged on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which together with the first column regions form a polarization super junction structure (14),
the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface,
A method for manufacturing a semiconductor device in which a current flows between one surface and another surface of the semiconductor substrate,
providing the gallium nitride substrate;
epitaxially growing a second column region forming layer (130) that forms the second column region on a first main surface of the gallium nitride substrate;
forming a buried trench (131) in a portion of the second column region forming layer where the first column region is to be disposed, and defining a portion different from the portion where the buried trench is formed as the second column region;
epitaxially growing a first column region forming layer (120) that forms the first column region so that the burying trench is filled, and configuring the polarization super junction structure having the first column region and the second column region, with the portion located in the burying trench being the first column region. The method for manufacturing a semiconductor device according to claim 8 , wherein the polarization super junction structure is formed by forming the first column region and the second column region each made of an undoped layer. The method for manufacturing a semiconductor device according to claim 8 , wherein the polarization super junction structure comprises forming the first column region and the second column region each made of a doped layer. a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which a semiconductor element is formed;
One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element;
and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element,
The semiconductor substrate is
a gallium nitride substrate (11) having a hexagonal crystal structure, a first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and a second main surface (11b) opposite to the first main surface constituting the other surface of the semiconductor substrate;
a plurality of first column regions (12) arranged on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) arranged on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which together with the first column regions form a polarization super junction structure (14),
the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface,
A method for manufacturing a semiconductor device in which a current flows between one surface and another surface of the semiconductor substrate,
providing the gallium nitride substrate;
epitaxially growing a first column region forming layer (120) that forms the first column region on a first main surface of the gallium nitride substrate;
forming a buried trench (121) in a portion of the first column region forming layer where the second column region is to be disposed, and defining a portion different from the portion where the buried trench is formed as the first column region;
epitaxially growing a second column region forming layer (130) that forms the second column region so that the burying trench is filled, and configuring the polarization superjunction structure having the first column region and the second column region, with the portion located in the burying trench being the second column region;
A method for manufacturing a semiconductor device in which the polarization super junction structure is formed by forming the first column region and the second column region each formed of a doped layer .