JP7758449B2 - SUBSTRATE PROCESSING SYSTEM, CONTROL DEVICE, AND SUBSTRATE TRANSPORTATION AND PROCESSING METHOD - Google Patents

Description

This disclosure relates to a substrate processing system, a control device, and a substrate transport processing method.

Patent Document 1 discloses a substrate processing system in which substrates are sequentially transported to multiple process modules (treatment modules) by a transfer module, and the substrates are subjected to a predetermined substrate treatment. In this type of substrate processing system, a single cycle time is set to equalize the thermal history of the substrates, and substrate treatment by the transfer module and substrate treatment by the process module are performed in cycle time units.

However, if a processing delay occurs in a module, the transport device will not be able to transport the substrates in time, causing disruption to the transport of substrates by the transport module. For this reason, substrate processing systems absorb processing delays by adding a leeway (interval) to the cycle time to allow for processing delays.

Japanese Patent Application Laid-Open No. 2020-9837

This disclosure provides technology that enables stable substrate transport and substrate processing, even when significant processing delays occur.

According to one aspect of the present disclosure, there is provided a substrate processing system including one or more transfer modules that transfer substrates; a plurality of process modules that perform substrate processing on the substrates transferred by the one or more transfer modules; and a control device that sets a common cycle time during which the transfer processing of the one or more transfer modules and the processing of the plurality of process modules are performed in one period, and creates and controls a schedule for the plurality of process modules and a schedule for the one or more transfer modules during one period of the cycle time, wherein the schedule for the plurality of process modules includes an unloading period for unloading the substrates, a load period for loading the substrates, a process period for performing the substrate processing, and a surplus period that is a period for absorbing processing delays, and the control device controls the created schedule for the plurality of process modules. and when it is determined that the delay time cannot be absorbed, changing the set cycle time to a cycle time with another period for the substrate in the module in which the delay occurred and the substrate upstream of the module in which the delay occurred , and executing the schedule of the plurality of process modules and the schedule of the one or more transport modules for the cycle time with another period .

According to one aspect, even if a significant delay occurs in processing, substrate transport and substrate processing can be performed stably.

1 is a plan view schematically illustrating an overall configuration of a substrate processing system according to an embodiment. 2 is a block diagram showing an example of the hardware configuration of a control device of the substrate processing system 1. FIG. FIG. 3A is an explanatory diagram showing the flow of transporting a single wafer and processing the substrate in the substrate processing system, and FIG. 3B is an explanatory diagram illustrating the transport timing of the first transport module in the substrate processing system. 10A and 10B are explanatory views for explaining a method for transferring a plurality of wafers W in the substrate processing system. FIG. 10 is an explanatory diagram showing a cycle time for transporting a wafer. FIG. 2 is an explanatory diagram illustrating an example of a schedule of cycle times of each process module and each transfer module; FIG. 2 is a block diagram showing functional blocks formed in a control device in a wafer transfer method. 10A and 10B are diagrams illustrating an example in which delay time can be absorbed in delay absorption determination. 10A and 10B are diagrams illustrating an example in which a delay cannot be absorbed in a delay absorption determination. 10 is a flowchart showing a substrate transfer and processing method of the substrate processing system. 10A to 10C are explanatory diagrams showing the operation of a period change process in the substrate transport processing method. FIG. 10 is a plan view showing the overall configuration of a substrate processing system according to a modified example.

The following describes embodiments of the present disclosure with reference to the drawings. In each drawing, identical components are designated by the same reference numerals, and duplicate descriptions may be omitted.

Figure 1 is a plan view showing the overall configuration of a substrate processing system 1 according to one embodiment. As shown in Figure 1, the substrate processing system 1 according to one embodiment is configured as a multi-chamber type having multiple process modules PM. The substrate processing system 1 is used in one process of semiconductor manufacturing, and multiple transfer modules TM sequentially transport substrates to each process module PM, where appropriate substrate processing is performed in each process module PM.

Substrates that undergo substrate processing include silicon semiconductor wafers, compound semiconductor wafers, and oxide semiconductor wafers (hereinafter, the substrates will also be referred to as wafers W). Wafers W may have recess patterns such as trenches and vias. Substrate processing performed by process modules PM includes film formation, etching, ashing, cleaning, and the like.

The substrate processing system 1 transfers a wafer W from an atmospheric atmosphere to a vacuum atmosphere, performs substrate processing on the wafer W in each transfer module TM and each process module PM in the vacuum atmosphere, and then transfers the wafer W from the vacuum atmosphere to the atmospheric atmosphere after substrate processing. To this end, the substrate processing system 1 includes a front module FM (e.g., an Equipment Front End Module (EFEM)) that transfers substrates in the atmospheric atmosphere, and a load lock module LLM that switches between the atmospheric atmosphere and the vacuum atmosphere. The substrate processing system 1 also includes a control device 80 that controls the front module FM, load lock module LLM, each process module PM, and each transfer module TM.

The front module FM has multiple load ports 11, a series of loaders 12 adjacent to each load port 11, and an alignment device 13 (orienter) located adjacent to the loader 12. Each load port 11 is set with a FOUP (Front Opening Unified Pod) containing multiple wafers W after the previous manufacturing process, and an empty FOUP containing wafers W that have been processed in the substrate processing system 1.

The loader 12 is formed as a rectangular box with a clean space inside. The front module FM is equipped with an atmospheric transfer device 14 inside this loader 12. The alignment device 13 works in conjunction with the atmospheric transfer device 14 to adjust the circumferential position of the wafer W removed from the FOUP and the attitude of the wafer W supported by the atmospheric transfer device 14.

The atmospheric transfer device 14 removes wafers W from FOUPs set in each load port 11 and transfers them to the alignment device 13 via the clean space within the loader 12. The atmospheric transfer device 14 then transfers the wafers W, which have been aligned in cooperation with the alignment device 13, into the load lock module LLM. The atmospheric transfer device 14 also removes the wafers W from the load lock module LLM and places them in a FOUP via the clean space within the loader 12.

Two load lock modules LLM are provided between the front module FM and the transfer module TM. Each load lock module LLM has a load lock container 21 capable of temporarily accommodating a wafer W. A gate 22 equipped with a valve (not shown) that airtightly closes the load lock container 21 is provided between each load lock module LLM and the front module FM. In addition, a gate 23 equipped with a valve (not shown) that airtightly closes the load lock container 21 is provided between the load lock module LLM and the transfer module TM.

One of the two load lock modules LLM (left side in FIG. 1) receives a wafer W transferred from the front module FM in an atmospheric atmosphere and then depressurizes it to a vacuum atmosphere, allowing the wafer W to be transferred to the transfer module TM. The other of the two load lock modules LLM (right side in FIG. 1) receives a wafer W transferred from the transfer module TM in a vacuum atmosphere and then increases the pressure to an atmospheric atmosphere, allowing the wafer W to be transferred to the front module FM. The substrate processing system 1 may be configured with only one load lock module LLM (load lock vessel 21). In this case, the load lock vessel 21 may be configured with a vertically separated space for loading from the front module FM to the transfer module TM and a space for unloading from the transfer module TM to the front module FM.

The substrate processing system 1 according to this embodiment has multiple (four) transfer modules TM arranged side by side, and multiple (eight) process modules PM installed adjacent to each transfer module TM. Hereinafter, the multiple transfer modules TM will be referred to as the first transfer module TM1, second transfer module TM2, third transfer module TM3, and fourth transfer module TM4, in that order, from the proximal side to the distal side of the two load lock modules LLM. The first transfer module TM1, second transfer module TM2, third transfer module TM3, and fourth transfer module TM4 form a group of transfer modules aligned in a straight line in a direction perpendicular to the longitudinal direction of the loader 12.

On the other hand, multiple process modules PM are installed four on the left side of the transport module group and four on the right side of the transport module group, corresponding to the four transport modules TM. Below, using Figure 1 as an example, the process modules PM installed to the left of each transport module TM will be referred to as the left-row process module group, and the process modules PM installed to the right of each transport module TM will be referred to as the right-row process module group. The left-row process module group and the right-row process module group extend parallel to each transport module group.

The left-row process module group includes, in order from the proximal side to the distal side of the load lock module LLM, the first process module PM1, the third process module PM3, the fifth process module PM5, and the seventh process module PM7. The right-row process module group includes, in order from the proximal side to the distal side of the load lock module LLM, the second process module PM2, the fourth process module PM4, the sixth process module PM6, and the eighth process module PM8.

The first process module PM1 is located to the left of and between the first and second transfer modules TM1 and TM2, and is connected to the first and second transfer modules TM1 and TM2. The second process module PM2 is located to the right of and between the first and second transfer modules TM1 and TM2, and is connected to the first and second transfer modules TM1 and TM2.

The third process module PM3 is located to the left of and between the second and third transfer modules TM2 and TM3, and is connected to the second and third transfer modules TM2 and TM3. The fourth process module PM4 is located to the right of and between the second and third transfer modules TM2 and TM3, and is connected to the second and third transfer modules TM2 and TM3.

The fifth process module PM5 is located to the left of and between the third and fourth transfer modules TM3 and TM4, and is connected to the third and fourth transfer modules TM3 and TM4. The sixth process module PM6 is located to the right of and between the third and fourth transfer modules TM3 and TM4, and is connected to the third and fourth transfer modules TM3 and TM4.

The seventh process module PM7 is located to the left of the fourth transfer module TM4 and is connected to the fourth transfer module. The eighth process module PM8 is located to the right of the fourth transfer module TM4 and is connected to the fourth transfer module TM4.

Each transfer module TM includes a transfer container 31 that can be decompressed to a vacuum atmosphere, and a transfer robot 32 installed within the transfer container 31. The transfer container 31 is formed as a hexagonal box in a plan view. Two load lock modules LLM, a first process module PM1, and a second process module PM2 are connected to predetermined sides of the transfer container 31 of the first transfer module TM1. The first process module PM1 to the fourth process module PM4 are connected to predetermined sides of the transfer container 31 of the second transfer module TM2. The third process module PM3 to the sixth process module PM6 are connected to predetermined sides of the transfer container 31 of the third transfer module TM3. The fifth process module PM5 to the eighth process module PM8 are connected to predetermined sides of the transfer container 31 of the fourth transfer module TM4.

The transfer robot 32 is configured to be able to move freely in the horizontal and vertical directions within the transfer container 31 and rotate by θ in the horizontal direction, and has a bifurcated fork to hold the wafer W horizontally during transfer. The transfer robots 32 provided in each of the first transfer module TM1 to fourth transfer module TM4 can be operated independently of each other under the control of the control device 80. The transfer robot 32 delivers and receives wafers W by moving toward and away from modules adjacent to the transfer container 31 (two load lock modules LLM, first process module PM1 to eighth process module PM8).

On the other hand, each of the multiple process modules PM has a processing vessel 41 that houses a wafer W and performs substrate processing. The processing vessel 41 is formed in a polygonal shape (pentagonal) in plan view. Gates 42 are provided between the transfer vessel 31 and each processing vessel 41, connecting the spaces between them to allow the wafer W to pass through, and a valve (not shown) is installed inside each gate 42 to open and close the processing vessel 41.

Each process module PM also includes a stage (not shown) inside the processing vessel 41 on which a wafer W can be placed. The stage includes multiple lift pins (not shown), and receives and delivers the wafer W from and to the transfer robot 32 based on the elevation and lowering of each lift pin.

The substrate processing performed by each process module PM may be any of the above-mentioned film formation processes, etching processes, ashing processes, cleaning processes, etc. The substrate processing system 1 may be configured so that each of the first process module PM1 to the eighth process module PM8 performs a different substrate processing, or may be configured so that all of the modules perform the same substrate processing.

The above-described substrate processing system 1 can be used, for example, to manufacture a stacked film (MTJ film) used in MRAM (Magnetoresistive Random Access Memory). Manufacturing an MTJ film involves multiple processes, such as pre-cleaning, film formation, oxidation, heating, and cooling, each of which is performed in the first through eighth process modules PM1 through PM8. In this case, one or more of the first through eighth process modules PM1 through PM8 may also serve as standby modules for storing wafers W.

Figure 2 is a block diagram showing an example of the hardware configuration of the control device 80 of the substrate processing system 1. As shown in Figure 2, the control device 80 of the substrate processing system 1 includes a main control unit 81, an input device 82, an output device 83, a display device 84, a storage device 85, an external interface 86, and a bus 87 connecting these devices to each other. The input device 82 is a keyboard, mouse, touch panel, etc. The output device 83 is a printer, etc. The display device 84 is a display (including a touch panel), etc.

The main control unit 81 has a CPU (Central Processing Unit) 811, RAM (Random Access Memory) 812, and ROM (Read Only Memory) 813. The storage device 85 has an information-readable storage medium such as an HDD (Hard Disk Drive), and stores information such as programs required for control and processing recipes for wafers W. The CPU 811 uses the RAM 812 as a working area to execute programs stored in the ROM 813 or storage device 85, causing the substrate processing system 1 to perform various processes on wafers W.

Figure 3(A) is an explanatory diagram showing the flow of transfer and substrate processing of one wafer W in the substrate processing system 1, and Figure 3(B) is an explanatory diagram illustrating the transfer timing of the first transfer module TM1 in the substrate processing system 1. As shown in Figure 3(A), the substrate processing system 1 performs substrate processing in sequence in each process module PM in the left-row process module group, and then performs substrate processing in sequence in each process module PM in the right-row process module group.

Specifically, the wafer W is transferred from the left load lock module LLM to the first transfer module TM1, where it is then transferred to the first process module PM1 by the first transfer module TM1. The wafer W then undergoes a first substrate processing in the first process module PM1. After substrate processing in the first process module PM1, the wafer W is transferred from the first process module PM1 to the third process module PM3 by the second transfer module TM2. The wafer W then undergoes a second substrate processing in the third process module PM3. After substrate processing in the third process module PM3, the wafer W is transferred from the third process module PM3 to the fifth process module PM5 by the third transfer module TM3. The wafer W then undergoes a third substrate processing in the fifth process module PM5. After substrate processing in the fifth process module PM5, the wafer W is transferred from the fifth process module PM5 to the seventh process module PM7 by the fourth transfer module TM4. The wafer W then undergoes a fourth substrate processing in the seventh process module PM7.

After substrate processing in the seventh process module PM7, the wafer W is transferred from the seventh process module PM7 to the eighth process module PM8 by the fourth transfer module TM4. The wafer W then undergoes a fifth round of substrate processing in the eighth process module PM8. After substrate processing in the eighth process module PM8, the wafer W is transferred from the eighth process module PM8 to the sixth process module PM6 by the fourth transfer module TM4. The wafer W then undergoes a sixth round of substrate processing in the sixth process module PM6. After substrate processing in the sixth process module PM6, the wafer W is transferred from the sixth process module PM6 to the fourth process module PM4 by the third transfer module TM3. The wafer W then undergoes a seventh round of substrate processing in the fourth process module PM4. After substrate processing in the fourth process module PM4, the wafer W is transferred from the fourth process module PM4 to the second process module PM2 by the second transfer module TM2. The wafer W then undergoes the eighth substrate processing in the second process module PM2. After substrate processing in the second process module PM2, the wafer W is transferred from the second process module PM2 to the right-side load lock module LLM by the first transfer module TM1.

This allows the substrate processing system 1 to sequentially perform eight substrate processing operations on a wafer W. However, the substrate processing system 1 does not wait until eight substrate processing operations have been completed on one wafer W before processing the next wafer W. After substrate processing is completed in each process module PM and the wafer W is removed, the next wafer W is loaded and substrate processing is performed again. For this reason, the substrate processing system 1 is basically configured to perform wafer W processing synchronously in each process module PM and each transfer module TM.

Next, the procedure for transferring and processing multiple wafers W in the substrate processing system 1 will be described with reference to FIG. 4. FIG. 4 is an explanatory diagram illustrating the method for transferring multiple wafers W in the substrate processing system 1, with (A) being a first operational diagram, (B) being a second operational diagram, and (C) being a third operational diagram. Note that in FIG. 4, the wafers W housed in each process module PM are numbered 1 through 9 in order of the number of times they have undergone substrate processing. That is, wafer W1 has undergone eighth substrate processing in the second process module PM2, and wafer W2 has undergone seventh substrate processing in the fourth process module PM4. The wafers W3 through W8 have undergone successively fewer substrate processing times. Wafer W9 is an unprocessed wafer W waiting in the left-hand load lock module LLM.

In this way, once substrate processing of the wafers W in each process module PM is completed, the substrate processing system 1 transfers each wafer W. At this time, the controller 80 controls the operation of the first transfer module TM1 to the fourth transfer module TM4 to perform a transfer process in which all wafers W proceed to the next module.

Specifically, as shown in FIG. 4A, the controller 80 first synchronously transfers wafers W1 through W4 from the right-hand process module group. Specifically, the first transfer module TM1 unloads wafer W1 from the second process module PM2 and loads wafer W1 into the right-hand load lock module LLM. The second transfer module TM2 unloads wafer W2 from the fourth process module PM4 and loads wafer W2 into the second process module PM2 immediately after unloading wafer W1. The third transfer module TM3 unloads wafer W3 from the sixth process module PM6 and loads wafer W3 into the fourth process module PM4 immediately after unloading wafer W2. The fourth transfer module TM4 unloads wafer W4 from the eighth process module PM8 and loads wafer W4 into the sixth process module PM6 immediately after unloading wafer W3. Each transfer module TM performs unloading and loading operations approximately simultaneously, allowing wafers W to be transferred in a short time without interfering with each other. This leaves the eighth process module PM8 empty.

Next, as shown in FIG. 4(B), the controller 80 controls the fourth transfer module TM4 to unload the wafer W5 from the seventh process module PM7 on the left side and load the wafer W5 into the eighth process module PM8 on the right side. This transfer is an operation to move the wafer W from the left-hand process module group to the right-hand process module group, and is performed solely by the fourth transfer module TM4.

Then, as shown in FIG. 4C, the controller 80 synchronously transfers wafers W6 through W9 from the left-hand process module group and the left-hand load lock module LLM. That is, the fourth transfer module TM4 unloads wafer W6 from the fifth process module PM5 and loads wafer W6 into the seventh process module PM7. The third transfer module TM3 unloads wafer W7 from the third process module PM3 and loads wafer W7 into the fifth process module PM5 immediately after unloading wafer W6. The second transfer module TM2 unloads wafer W8 from the first process module PM1 and loads wafer W8 into the third process module PM3 immediately after unloading wafer W7. The first transfer module TM1 unloads wafer W9 from the load lock module LLM and loads wafer W9 into the first process module PM1 immediately after unloading wafer W8. In this case, each transfer module TM performs unloading and loading operations approximately simultaneously, allowing the wafers W to be transferred in a short time without interfering with each other.

Figure 5 is an explanatory diagram showing the cycle time for transferring wafers W. As described above, the control device 80 of the substrate processing system 1 sets a synchronization cycle time as shown in Figure 5 to synchronously transfer each wafer W in the left process module group and synchronously transfer each wafer W in the right process module group. The "cycle time" is a control period that synchronizes the left-row transfer process that transfers each wafer W in the left process module group and the right-row transfer process that transfers each wafer W in the right process module group. This cycle time has a duration that includes each process in each process module PM and each process in each transfer module TM. For the atmospheric transfer device 14 of the front module FM, the cycle time also serves as information that determines the time interval for loading and unloading wafers W into and from the load lock module LLM.

The cycle time of each transport module TM includes a left column transport period in which left column transport processing is performed and a right column transport period in which right column transport processing is performed when the cycle time is performed once (one revolution). The left column transport period and right column transport period are set at time positions within the cycle time that do not overlap with each other. Furthermore, within the cycle time of each transport module TM, periods other than the left column transport period and right column transport period are transport standby periods in which the transport robot 32 waits for operation. Note that while Figure 5 shows the start point of the cycle time as the start point of the left column transport period, the start point of the cycle time can, of course, be set arbitrarily.

The cycle time scheduling of each transfer module TM performed by the control device 80 will be explained below with reference to FIG. 3(B), using the cycle time of the first transfer module TM1 as an example. The first transfer module TM1 is the transfer module TM used first in the wafer W transfer path (removing the wafer W loaded into the load lock module LLM), and serves as the basis for setting the cycle time.

When a FOUP is set on the load port 11, the controller 80 reads the FOUP (wafer W) information and sets a cycle time based on each past process in the process module PM (unloading, loading, substrate processing, etc.). The controller 80 first registers the start of the left row transfer period for the left row process module group as the start point of the cycle time (zero seconds). The controller 80 then sets the left row transfer period (the time it takes to transport a wafer W from the load lock module LLM to the first process module PM1) from this start point.

Next, the controller 80 determines the start point of the right row transfer period (in other words, the transfer wait period between the left row transfer period and the right row transfer period) in the cycle time of the first transfer module TM1. This transfer wait period can be set, for example, based on the time required for unloading, loading, and substrate processing in each process module PM. Setting the start point of this right row transfer period will be described in detail later. Then, the controller 80 sets the right row transfer period (the time required to transport a wafer W from the second process module PM2 to the load lock module LLM) from this start point.

This allows the control device 80 to schedule the left column transport period and the right column transport period in the cycle time of the first transport module TM1, as shown by the arrows in Figure 3(B). Furthermore, similar to the first transport module TM1, the control device 80 can also schedule the left column transport period and the right column transport period for each of the cycle times of the second to fourth transport modules TM2 to TM4.

In addition to the left-column transfer process and right-column transfer process described above, the fourth transfer module TM4 also performs an inter-column transfer process in which wafers W are transferred from the left-column process module group to the right-column process module group (see FIG. 4B). Therefore, the control device 80 schedules the cycle time of the fourth transfer module TM4 to include an inter-column transfer period in addition to the left-column and right-column transfer periods (see also FIG. 6).

On the other hand, as shown in Figure 5, each process in each process module PM includes an unloading process for unloading the wafer W, a load process for loading the wafer W, and substrate processing of the wafer W when the cycle time is performed once (one revolution). Each process module PM is scheduled during the cycle time with an unloading period, which is the period for the unloading process, a load period, which is the period for the load process, and a process period, which is the period for the substrate processing. The unloading period, load period, and process period are basically arranged in this order and are set at time positions that do not overlap with each other.

Each of the one or more process modules PM has a slack period in addition to the unloading period, loading period, and process period during its cycle time. A "slack period" is the period during which processing delays occurring in a given module are tolerable, and is the total cycle time minus the unloading period, loading period, and process period. Because the unloading and loading periods between process modules PM are approximately the same length, the slack period essentially varies depending on the length of the process period of each process module PM. In other words, a process module PM with a long process period has a short slack period, while a process module PM with a short process period has a long slack period. Therefore, it is recommended to set the slack period based on the process module PM with the longest process period.

By setting the cycle time as described above, each transfer module TM and each process module PM can repeat synchronized processing within one cycle time, even if each module performs different processing within the cycle time. As a result, the substrate processing system 1 can promote the overall efficiency of processing multiple wafers W.

Figure 6 is an explanatory diagram illustrating the cycle time schedule for each process module PM and the cycle time schedule for each transport module TM. As shown in Figure 6, each process module PM has the same length of load-in and load-out periods during the cycle time, but the process periods differ from one another. For example, the first process module PM1, the third process module PM3, and the fifth process module PM5 have the same load-in and load-out periods. However, the process periods are in the following order: fifth process module PM5 > first process module PM1 > third process module PM3.

In particular, in the example of Figure 6, the fifth process module PM5 has the longest process period of all the process modules PM. The control device 80 of the substrate processing system 1 sets the cycle time based on this fifth process module PM5. That is, the substrate processing system 1 can set the cycle time to the sum of the unloading period, loading period, and process period of the fifth process module PM5. For example, if the unloading period, loading period, and process period of the fifth process module PM5 are 10 seconds, 10 seconds, and 120 seconds, respectively, the cycle time of the substrate processing system 1 is set to 140 seconds. Note that the cycle time may be calculated by adding a margin to the sum of the unloading period, loading period, and process period of the process module PM with the longest process period.

Furthermore, the seventh process module PM7 has the same loading period as the first process module PM1, the third process module PM3, and the fifth process module PM5, but its unloading period differs from these process modules PM. This is because the fourth transfer module TM4 performs inter-row transfer processing from the left-row process module group to the right-row process module group. Similarly, the eighth process module PM8 has the same loading period as the second process module PM2 and the sixth process module PM6, but its loading period differs from these process modules PM.

Furthermore, the fourth process module PM4 is configured to immediately unload the wafer W after substrate processing has been performed on the wafer W without waiting for a margin period (hereinafter referred to as non-waiting unloading processing). This non-waiting unloading processing is set appropriately depending on the content of the substrate processing, and is performed, for example, to suppress the thermal effects and oxidation caused by remaining inside the processing vessel 41. Therefore, although the fourth process module PM4 has the same loading period as the second process module PM2 and the sixth process module PM6, its unloading period differs from these process modules PM.

Meanwhile, the control device 80 sets the cycle time schedule for each transport module TM according to the schedules of each process module PM. For example, the control device 80 synchronizes the start of all left column transport processes (left column transport periods) with zero seconds, which is the start of the cycle time. For this left column transport period, the control device 80 sets the right column transport period based on the unloading period, loading period, and process period of each process module PM, and the inter-column transport period of the fourth transport module TM4. For example, if the unloading period of each process module PM is 10 seconds and the loading period of each process module PM is 10 seconds, the implementation period of the left column transport period and the right column transport period will each require 20 seconds. Furthermore, the inter-column transport period of the fourth transport module TM4 will also require 20 seconds.

As shown in Figures 4(A) to 4(C), considering that each wafer W is transferred in the order of right-column transfer processing, inter-column transfer processing, and left-column transfer processing, it is preferable to set the inter-column transfer period before the start of the left-column transfer period, and set the right-column transfer period before the start of this inter-column transfer period. Therefore, as shown in Figure 6, for example, if the cycle time is 140 seconds, the control device 80 sets the start of the inter-column transfer period at 120 seconds and the start of the right-column transfer period at 100 seconds for the cycle time of the fourth transfer module TM4. As a result, the fourth transfer module TM4 is scheduled to perform 20 seconds of left-column transfer processing, 80 seconds of standby, 20 seconds of right-column transfer processing, and 20 seconds of inter-column transfer processing, in that order, during the cycle time.

On the other hand, the first to third transport modules TM1 to TM3 do not perform inter-column transport processing, and therefore enter a transport standby period while the inter-column transport processing is being performed. Therefore, the first transport module TM1 and third transport module TM3 are scheduled to perform a 20-second left-column transport process, an 80-second standby, a 20-second right-column transport process, and a 20-second standby in that order during the cycle time.

Furthermore, as described above, the second transfer module TM2 must perform non-standby unloading processing for the fourth process module PM4. Therefore, the second transfer module TM2 is scheduled to perform the following cycle time in order: 20 seconds of left-row transfer processing, 20 seconds of standby, 10 seconds of unloading during right-row transfer processing, 60 seconds of standby, 10 seconds of loading during right-row transfer processing, and 20 seconds of standby.

Here, the leeway period in the cycle time of each process module PM and the transfer standby period in the cycle time of the transfer module TM can be used as periods to absorb module processing delays in the substrate processing system 1. For example, if the leeway period of the first process module PM1 is 20 seconds, the first process module PM1 can tolerate a 20-second delay in substrate processing. Also, for example, if the transfer standby period between the left column transfer process and the right column transfer process in the first transfer module TM1 is 80 seconds, the first transfer module TM1 can tolerate a delay in the left column transfer process of a period (60 seconds) calculated by subtracting the 20-second left column transfer period from 80 seconds.

However, if processing in a certain module is significantly delayed, the processing delay cannot be tolerated even with the marginal time of each process module PM and the transfer standby time of each transfer module TM. For example, if the atmospheric transfer device 14 is delayed by 70 seconds in transferring a wafer W from the alignment device 13 to the load lock module LLM, the first transfer module TM1, which has an 80-second transfer standby time, will experience a period of overlap between the left-row transfer process and the right-row transfer process. Because the first transfer module TM1 can only transfer wafers from either the left-row process module group or the right-row process module group, this disrupts the transfer process. If the substrate processing system 1 were to shift the overall cycle time of each module to accommodate the processing delay, all wafers W currently being processed in each process module PM would spend significantly longer in their processing vessels 41. This would increase the thermal impact on the delayed wafers W, potentially resulting in inconsistent thermal histories between the delayed wafers W and the undelayed wafers W, potentially resulting in differences in the quality (good or bad) of the substrate processing.

In response to this, when processing in a certain module is significantly delayed, the substrate processing system 1 according to this embodiment performs processing to shift the cycle time of wafers W upstream of the delayed module by one or more periods without changing the cycle time. This allows the substrate processing system 1 to maintain the same cycle time when processing the next wafer W, thereby stabilizing substrate processing in each process module PM.

To perform the above processing, the control device 80 configures the functional units shown in Figure 7 by having the CPU 811 read and execute programs stored in the ROM 813. Figure 7 is a block diagram showing the functional blocks formed within the control device 80 in the wafer W transfer method.

Specifically, the control device 80 includes a transport control unit 91, a wafer detection unit 92, a process processing time memory unit 93, a schedule unit 94, a delay time acquisition unit 95, and a delay determination processing unit 96.

The transfer control unit 91 controls each transfer module TM and atmospheric transfer device 14 according to the cycle time and schedule created by the schedule unit 94. For example, the transfer control unit 91 controls the atmospheric transfer device 14 in accordance with the cycle time to remove a wafer W from a FOUP and transfer the wafer W to the alignment device 13 and load lock module LLM in that order. Furthermore, the transfer control unit 91 serially transfers wafers W in each transfer module TM and each process module PM, which have been depressurized to a predetermined vacuum atmosphere, to sequentially perform substrate processing, as shown in FIG. 3(A). Furthermore, the transfer control unit 91 controls wafers W, for which all substrate processing has been completed, to be returned from the load lock module LLM to the FOUP.

The wafer detection unit 92 detects the position of each wafer W within the substrate processing system 1 and stores the position and the time spent at that position in the process processing time memory unit 93. The control device 80 may display the wafer position detected by the wafer detection unit 92 on the device screen of the display device 84. The control device 80 may also notify the transfer control unit 91 and the schedule unit 94 of the position of the wafer W detected by the wafer detection unit 92.

The actual process processing time memory unit 93 stores the time required for processing in each process module PM and each transfer module TM (hereinafter referred to as actual process processing time) along with information about the wafer W. The actual process processing time is the actual length of time required for the unloading period, loading period, processing period, and margin period of each process module PM, as well as the left column transfer period, right column transfer period, inter-column transfer period, and transfer standby period of each transfer module TM, as shown in FIG. 6. For example, the control device 80 calculates the actual process processing time based on the wafer position detected by the wafer detection unit 92, feedback of the operating status of each process module PM, and feedback of the operating status of each transfer module TM.

The scheduler 94 sets the cycle time using the cycle time function and creates a schedule that links the substrate processing in each process module PM with the transport processing in each transport module TM. The scheduler 94 extracts the load-in period, load-out period, and process period for each process module PM from the process processing performance time memory unit 93, and sets a margin period so that the cycle time for all process modules PM is the same. In the example of the process modules PM shown in Figure 6, as mentioned above, the fifth process module PM5 has the longest process period, so the cycle time is determined based on this fifth process module PM5.

The scheduler 94 also has a transfer interval designation function that sets the left column transfer period, right column transfer period, and inter-column transfer period for each transfer module TM based on the cycle time. As described above, the scheduler 94 sets the transfer process for each transfer module TM by aligning the start of the left column transfer period and the end of the inter-column transfer period with the start point of the cycle time, and further aligning the start of the inter-column transfer period with the end of the right column transfer period. Furthermore, if there is a process module PM that performs non-standby unloading processing (the fourth process module PM4 in FIG. 6), the unloading period is adjusted to match the processing of that process module PM. Furthermore, the scheduler 94 sets the transfer timing of wafers W by the atmospheric transfer device 14 (sending wafers W from a FOUP to a load lock module LLM and returning them from the load lock module LLM to the FOUP) based on the created cycle time. This allows the transfer control unit 91 to control each transfer module TM according to the schedule for each transfer module TM created by the scheduler 94.

The delay time acquisition unit 95 acquires the processing delay time of each module and transmits the delay time to the delay determination processing unit 96. For example, the delay time acquisition unit 95 receives processing progress information (actual time) from multiple control units that respectively control the front module FM, each load lock module LLM, each process module PM, etc. Then, the delay time acquisition unit 95 calculates the delay time by subtracting the time actually required for processing from a preset target processing period.

The delay determination processing unit 96 is located between the scheduling unit 94 and the transport control unit 91, and performs appropriate processing based on the delay time. For example, the delay determination processing unit 96 compares the schedule created by the scheduling unit 94 with the delay time acquired by the delay time acquisition unit 95. If no delay time has occurred, the delay determination processing unit 96 sends the schedule as is to the transport control unit 91. On the other hand, if a delay time has occurred in the module, the delay determination processing unit 96 performs a delay absorption determination based on the length of the delay time to determine whether further delay time can be absorbed.

This delay absorption determination will be explained in detail below with reference to Figures 8 and 9. Figure 8 shows an example in which delay time can be absorbed in delay absorption determination, with (A) being the first explanatory diagram, (B) being the second explanatory diagram, and (C) being the third explanatory diagram. Figure 9 shows an example in which delay time cannot be absorbed in delay absorption determination, with (A) being the first explanatory diagram and (B) being the second explanatory diagram. The following explanation will focus on an example in which delay time occurs in processing in a load lock module LLM (including a front module FM) that switches from air atmosphere to vacuum atmosphere and loads a wafer W.

For example, suppose a 50-second delay occurs in the processing of the load lock module LLM. In this case, as shown in FIG. 8A, the delay determination processing unit 96 first checks whether the left column transfer process and the right column transfer process overlap in the first transfer module TM1, which transfers wafers W from the load lock module LLM to the first process module PM1. Here, because the right column transfer process starts at 100 seconds in the first transfer module TM1, even if the delay time is 50 seconds, the left column transfer process will not overlap with the right column transfer process. Therefore, the schedule for the first transfer module TM1 is corrected so that the start point of the left column transfer period is shifted by 50 seconds.

Next, as shown in FIG. 8B, the delay determination processing unit 96 checks the margin period of the first process module PM1 and calculates the time required to make up for the delay in the first process module PM1, which is the downstream module. If the margin period of the first process module PM1 is 20 seconds, the delay time of 50 seconds can be reduced to 30 seconds.

The delay determination processing unit 96 then checks whether the left column transport process and the right column transport process will overlap during the 30-second delay (delay time - first process module margin) in the second transport module TM2. Here, since the right column transport process starts at 40 seconds in the second transport module TM2, if the delay is 30 seconds, the left column transport process will not overlap with the right column transport process, even if 10 seconds are added to the unloading period of the right column transport process. Therefore, the schedule for the second transport module TM2 is corrected to shift the start point of the left column transport period by 30 seconds.

Next, as shown in FIG. 8(C), the delay determination processing unit 96 checks the margin period of the third process module PM3 and calculates the time required to make up for the 30-second delay. For example, if the margin period of the third process module PM3 is 50 seconds, the entire 30-second delay can be tolerated by this third process module PM3. Therefore, the delay time can be set to 0 seconds in the third transfer module TM3, and the schedule for the third transfer module TM3 set by the schedule unit 94 can be used as is.

As described above, the delay determination processor 96 absorbs the delay time occurring in the upstream module using the margin of one or more downstream process modules PM, while ensuring that the left-row transport period and right-row transport period in each downstream transport module TM do not overlap. This allows the delay determination processor 96 to determine that the delay time can be absorbed. As a result, the substrate processing system 1 corrects each schedule to allow for the delay time, and by sending the schedule to the transport controller 91, the previously set cycle time can be maintained.

In contrast, suppose a 60-second delay occurs in the processing of the load lock module LLM. In this case, because the right-row transfer process of the first transfer module TM1 starts at 100 seconds, the delay determination processing unit 96 determines that the left-row transfer period does not overlap with the right-row transfer period, even if the delay time is 60 seconds, as shown in Figure 9 (A). Therefore, the schedule for the first transfer module TM1 is corrected to shift the start point of the left-row transfer period by 60 seconds.

Next, as shown in FIG. 9B, the delay determination processing unit 96 checks the margin period of the first process module PM1 and calculates the time required to make up for the delay of the first process module PM1. If the margin period of the first process module PM1 is 20 seconds, the delay time of 60 seconds can be reduced to 40 seconds.

The delay determination processor 96 then checks whether the left-row transfer process and the right-row transfer process overlap during the 40-second delay (delay time - first process module margin) in the second transfer module TM2. Here, the second transfer module TM2 starts the right-row transfer process at 40 seconds, so if the delay time is 40 seconds, the left-row transfer period and the right-row transfer period will overlap. Therefore, the delay determination processor 96 determines that the delay cannot be absorbed when the delay time is 60 seconds. If the delay cannot be absorbed, the substrate processing system 1 performs period change control to wait one cycle of the cycle time for the module where the delay occurred and for each process module PM and each transfer module TM upstream of the module. This period change process is described in detail in a later flowchart. This allows the substrate processing system 1 to easily realign the schedules of the module upstream of the delayed module with the schedules of each process module PM and each transfer module TM before the delay occurred. Note that the cycle change control that changes the cycle time to another cycle time is not limited to shifting the cycle time by one cycle, but may shift the cycle time by multiple cycles depending on the delay time.

The substrate processing system 1 according to this embodiment is basically configured as described above, and its operation will be described below with reference to Figure 10. Figure 10 is a flowchart showing the substrate transport and processing method of the substrate processing system 1.

As described above, the control device 80 of the substrate processing system 1 coordinates the transfer of wafers W by each transfer module TM with the substrate processing by each process module PM. At this time, the scheduler 94 sets the cycle time based on the past unloading, loading, and processing periods for each process module PM stored in the process processing performance time memory 93 (step S1).

Furthermore, the scheduling unit 94 determines the schedule for each process module PM and each transfer module TM according to the cycle time (step S2).

Then, the transfer control unit 91 transfers the wafers W based on the schedules for each transfer module TM sent from the scheduling unit 94 (step S3). As a result, as shown in FIGS. 4A and 4B, the substrate processing system 1 synchronously performs a right-row transfer process for transferring each wafer W in the right-row process module group, an inter-row transfer process for transferring a wafer W in the left-row process module group to the right-row process module group, and a left-row transfer process for transferring each wafer W in the right-row process module group. Furthermore, each process module PM performs substrate processing on each wafer W based on commands from the control device 80 (the schedule for each process module PM set by the scheduling unit 94).

When each module is operating, the delay time acquisition unit 95 acquires the actual processing time of the front module FM, the actual processing time of each process module PM, the actual processing time of each transport module TM, etc., and calculates the delay time of each process (step S4).

Furthermore, the delay determination processing unit 96 monitors whether a delay has occurred in each process based on the delay time information for each process transmitted from the delay time acquisition unit 95 (step S5). That is, if the delay time for each process is zero (step S5: YES), the delay determination processing unit 96 determines that there is no delay in each process and proceeds to step S6. On the other hand, if the delay time for any of the processes is other than zero (step S5: NO), the delay determination processing unit 96 determines that the processing of the module is delayed by that amount and proceeds to step S7.

In step S6, the delay determination processing unit 96 sends the schedule for each transfer module TM to the transfer control unit 91, which then performs transfer processing for each transfer module TM according to a schedule that matches the cycle time (see also Figure 6). For example, if no delay time has occurred in each module, each wafer W is transferred according to the schedule for each transfer module TM set by the scheduling unit 94.

On the other hand, if the delay time is other than zero, in step S7 the delay determination processing unit 96 performs a delay absorption determination to confirm whether the delay time can be absorbed (see also Figures 8 and 9). If the delay absorption determination determines that the delay time can be absorbed (step S7: YES), the delay determination processing unit 96 proceeds to step S6 and performs transport while maintaining the cycle time of each transport module TM. At this time, for modules upstream of the module in which the delay time is occurring, the delay determination processing unit 96 corrects the schedule to one that absorbs the delay time calculated in the delay absorption determination and sends it to the transport control unit 91. This allows the transport control unit 91 to perform transport processing in accordance with the corrected schedule.

If the delay absorption determination determines that the delay cannot be absorbed (step S7: NO), the delay determination processing unit 96 proceeds to step S8. Then, in step S8, a period change process is performed to change the period of the cycle time of the wafer W.

Figure 11 is an explanatory diagram showing the operation of the period change process of the substrate transfer processing method, where (A) is the first operation diagram, (B) is the second operation diagram, and (C) is the third operation diagram. Note that Figure 11 shows an example in which a significant delay time occurs in the load lock module LLM that loads the wafer W.

In the cycle change process, as shown in Figure 11(A), the controller 80 does not transfer wafer W9 in load lock module LLM, which cannot absorb the delay time, at the cycle time when the delay time occurs. As a result, wafers W1 through W8 downstream of load lock module LLM are transferred, and the wafers W move to the next modules. As a result, an empty state is created in first process module PM1, where wafer W9 is not transferred.

The control device 80 ends the current cycle in this state and starts the next cycle. During the next cycle, the first process module PM1, which does not have a wafer W, temporarily suspends substrate processing, and each process module PM that has a wafer W performs substrate processing. Note that when substrate processing is temporarily suspended, the process module PM does not need to stop operation of all components. For example, it is preferable for the process module PM to operate the temperature adjustment mechanism to maintain the temperature inside the processing vessel 41 in order to properly process the next substrate.

After substrate processing, the control device 80 transfers each wafer W in accordance with the cycle time, as shown in Figure 11 (B). That is, wafers W1 through W9 are transferred to the next process module PM. At this time, wafer W9 is transferred to the process module PM that was previously temporarily stopped. A state in which there is only one empty process module PM between wafers W1 through W8 and wafer W9 is maintained.

As shown in FIG. 11(C), the control device 80 then sequentially transfers each wafer W using each transfer module TM, and performs substrate processing on each wafer W using each process module PM. This allows the substrate processing system 1 to avoid situations where the cycle time is not met, even though some process modules PM may not contain wafers W. As a result, the transfer robots 32 of each transfer module TM can be operated synchronously.

Returning to FIG. 10, after completing step S8, the control device 80 determines whether or not to terminate substrate processing of the wafer W (step S9). If substrate processing of the wafer W is to continue (step S9: NO), the process returns to step S2, and the same process flow is repeated. On the other hand, if substrate processing of the wafer W is to terminate (step S9: YES), an appropriate termination step is performed, and the current substrate transfer processing method is terminated.

The substrate processing system 1 according to the present disclosure is not limited to the above embodiment and may take various modified forms. For example, if a delay in substrate processing occurs in one of the process modules PM and the cycle time is shifted, the substrate processing system 1 preferably adds information to the management information of the wafer W that indicates that the cycle time has been shifted for the wafer W that is waiting in that process module PM (and any process modules PM upstream of that process module PM). This allows the user to easily consider the cause of the shift in cycle time if a defect occurs in the substrate processing of the wafer W.

Figure 12 is a plan view showing the overall configuration of a substrate processing system 1A according to a modified example. As shown in Figure 12, the transfer module TM of the substrate processing system 1A according to the modified example has a single, continuous transfer container 31, and this transfer container 31 is equipped with multiple (five) transfer robots 32, which differs from the substrate processing system 1 according to the above embodiment. In this way, even when multiple transfer robots 32 are installed in a single transfer container 31 (transfer module TM), the substrate processing system 1A can perform the same substrate transfer processing method as described above to sequentially process wafers W. Furthermore, even with this substrate processing system 1A, if a significant delay occurs, appropriate processing can be performed, such as absorbing the delay or changing the cycle time to another cycle time.

The technical concepts and effects of the present disclosure described in the above embodiments are described below.

A first aspect of the present disclosure is a substrate processing system 1 including one or more transfer modules TM that transfer substrates (wafers W), multiple process modules PM that perform substrate processing on substrates transferred by the one or more transfer modules TM, and a control device 80 that sets a common cycle time for repeating the processing of the one or more transfer modules TM and the processing of the multiple process modules PM, and creates and controls a schedule for the multiple process modules PM and a schedule for the one or more transfer modules TM based on the cycle time. The schedules for the multiple process modules PM include an unloading period for unloading substrates, a load period for loading substrates, a process period for performing substrate processing, and a slack period for absorbing processing delays. The control device 80 controls the following when a delay occurs in processing in a module of the substrate processing system 1: determining whether the delay in module processing can be absorbed by the slack period; and, if it is determined that the delay cannot be absorbed, changing the cycle time for transporting substrates from the delayed module and substrates upstream of the delayed module to a different cycle time.

As described above, if a significant delay occurs in processing, the substrate processing system 1 can stably synchronize substrate transport and substrate processing by changing the set cycle time for transporting substrates (wafers W) to a different cycle time. On the other hand, if the delay can be absorbed by the slack period, processing continues according to the cycle time, making it possible to avoid delays in the substrate processing as a whole. Therefore, the substrate processing system 1 can increase the throughput of substrate transport and substrate processing.

In addition, the control device 80 sets the cycle time based on the past unloading, loading, and processing periods of multiple process modules PM. This enables the substrate processing system 1 to accurately set the cycle time for transporting and processing substrates (wafers W).

The cycle time is the length of time it takes to load a substrate (wafer W) into one or more transfer modules TM, and is set based on the process module with the longest process period among the multiple process modules PM. This allows the substrate processing system 1 to reliably set a cycle time that includes the process periods of all of the multiple process modules PM.

Furthermore, when the delay time can be absorbed, the control device 80 shifts the schedule of one or more transfer modules TM based on the delay time, and absorbs the delay time using the slack time of multiple process modules PM. This allows the substrate processing system 1 to effectively absorb processing delays while maintaining the cycle time when the delay time can be absorbed.

Furthermore, in the process of changing the cycle time, the process module PM upstream of the module where the delay occurred waits until the delay time exceeds the cycle time, and then the substrate (wafer W) is unloaded. This allows the substrate processing system 1 to smoothly transport the substrate after the cycle time has been changed in accordance with the new cycle time.

The multiple process modules PM form a left-row process module group arranged adjacent to the left side of one or more transfer modules TM, and a right-row process module group arranged adjacent to the right side of one or more transfer modules TM. The schedule for the one or more transfer modules TM includes a left-row transfer period for transfer of the left-row process module group, a right-row transfer period for transfer of the right-row process module group, an inter-row transfer period for transfer between the left-row process module group and the right-row process module group, and a transfer wait period for waiting for substrate (wafer W) transfer. The control device 80 sets the schedule for the one or more transfer modules TM so that the left-row transfer period, right-row transfer period, and inter-row transfer period do not overlap. This allows the substrate processing system 1 to appropriately set the timing of substrate transfer in a configuration having a left-row process module group and a right-row process module group.

Furthermore, in the process of determining whether the delay time can be absorbed, a determination is made as to whether the delay time will cause the left column transfer period, right column transfer period, or inter-column transfer period to overlap in the transfer module TM downstream of the module where the delay occurred. If the left column transfer period, right column transfer period, or inter-column transfer period do not overlap, the delay time is absorbed by the slack period of the process module PM adjacent to the downstream transfer module TM. However, if the left column transfer period, right column transfer period, or inter-column transfer period overlap, a process is performed to change the cycle time. This allows the substrate processing system 1 to appropriately change the cycle time in a configuration that performs left column transfer processing, right column transfer processing, and inter-column transfer processing.

Furthermore, in the process of determining whether the delay time can be absorbed, if the delay time in the transport module TM does not cause the left column transport period, right column transport period, or inter-column transport period to overlap, the process of absorbing the delay time using the slack period of the process module PM is repeated in order from the module where the delay occurred toward the downstream side of the multiple transport modules TM until the delay time causes the left column transport period, right column transport period, or inter-column transport period to overlap, or until the delay time has been absorbed. This allows the substrate processing system 1 to accurately determine whether the delay time can be absorbed.

A second aspect of the present disclosure is a control device 80 for a substrate processing system 1 that transports substrates (wafers W) to multiple process modules PM using one or more transfer modules TM for substrate processing. The control device 80 sets a common cycle time for repeating the processing of one or more transfer modules TM and the processing of multiple process modules PM, and creates and controls a schedule for the multiple process modules PM and a schedule for the one or more transfer modules TM based on the cycle time. The schedules for the multiple process modules PM include an unloading period for unloading substrates, a load period for loading substrates, a process period for performing substrate processing, and a slack period for absorbing processing delays. When a delay occurs in processing in a module of the substrate processing system, the control device controls the following steps: determining whether the delay in module processing can be absorbed by the slack period; and, if it is determined that the delay cannot be absorbed, changing the cycle time for transporting substrates from the delayed module and substrates upstream of the delayed module to a different cycle time.

A third aspect of the present disclosure is a substrate transfer and processing method for transferring substrates (wafers W) to multiple process modules PM using one or more transfer modules TM for substrate processing, the method comprising the steps of: setting a common cycle time for repeating the processing of the multiple process modules PM and the processing of one or more transfer modules TM; creating a schedule for the multiple process modules PM based on the cycle time, the schedule including an unloading period for unloading substrates, a load period for loading substrates, a process period for performing substrate processing, and a slack period for absorbing processing delays, and a schedule for the one or more transfer modules TM; controlling the one or more transfer modules TM and the multiple process modules PM based on the schedule; determining, when a delay occurs in processing in a module of the substrate processing system 1, whether the delay in module processing can be absorbed by the slack period; and, if it is determined that the delay cannot be absorbed, changing the cycle time for transporting substrates from the delayed module and substrates upstream of the delayed module to a different cycle time.

Even in the second and third aspects, substrate transport and substrate processing can be carried out stably even if a significant delay occurs in processing.

The substrate processing system 1, control device 80, and substrate transport and processing method according to the presently disclosed embodiments are illustrative in all respects and not restrictive. The embodiments may be modified and improved in various ways without departing from the spirit and scope of the appended claims. The matters described in the above multiple embodiments may be configured in other ways as long as they are not inconsistent, and may be combined as long as they are not inconsistent.

1 Substrate processing system 80 Control device PM Process module TM Transfer module W Wafer

Claims (10)

one or more transfer modules for transferring substrates;
a plurality of process modules for performing substrate processing on the substrates transferred by the one or more transfer modules;
a control device that sets a common cycle time during which transfer processing by the one or more transfer modules and processing by the plurality of process modules are performed in one period, and creates and controls a schedule for the plurality of process modules and a schedule for the one or more transfer modules during one period of the cycle time,
the schedules for the plurality of process modules include an unloading period for unloading the substrates, an loading period for loading the substrates, a process period for performing the substrate processing, and a margin period for absorbing processing delays;
The control device
When repeating the cycle time by controlling the plurality of process modules and the one or more transfer modules based on the created schedules of the plurality of process modules and the one or more transfer modules,
a step of determining, when a delay occurs in processing of a module of the substrate processing system, whether or not the delay time in processing of the module can be absorbed by the leeway period;
when it is determined that the delay time cannot be absorbed, changing the set cycle time to a cycle time of another period for the substrates in the module where the delay occurred and the substrates upstream of the module where the delay occurred, and executing the schedules of the plurality of process modules and the schedules of the one or more transfer modules for the cycle time of the other period .
Substrate processing system. the control device sets the cycle time based on the past unloading periods, the past loading periods, and the past process periods of the plurality of process modules.
The substrate processing system of claim 1 . the cycle time is a time length for loading the substrate into the one or more transfer modules, and is set based on the process module with the longest process period among the plurality of process modules.
The substrate processing system of claim 2 . The control device
If the delay time can be absorbed, shifting the schedule of the one or more transfer modules based on the delay time, and absorbing the delay time by the slack periods of the plurality of process modules.
The substrate processing system according to claim 1 . In the step of changing the cycle time, the substrate is unloaded after waiting until the delay time exceeds the cycle time in a process module upstream of the module in which the delay has occurred.
The substrate processing system according to claim 1 . the plurality of process modules form a left row process module group arranged adjacent to the left side of the one or more transfer modules, and a right row process module group arranged adjacent to the right side of the one or more transfer modules,
the schedule for the one or more transfer modules includes a left column transfer period for transferring the left column process module group, a right column transfer period for transferring the right column process module group, an inter-column transfer period for transferring between the left column process module group and the right column process module group, and a transfer waiting period for waiting for the transfer of the substrate;
the control device sets schedules for the one or more transport modules so that the left column transport period, the right column transport period, and the inter-column transport period do not overlap.
The substrate processing system according to claim 1 . In the step of determining whether the delay time can be absorbed, it is determined whether the left column transport period, the right column transport period, or the inter-column transport period overlaps due to the delay time in a transport module downstream of the module in which the delay occurs;
When the left column transfer period, the right column transfer period, or the inter-column transfer period does not overlap, the delay time is absorbed by the surplus period of the process module adjacent to the downstream transfer module,
performing a step of changing the cycle time when the left column transfer period, the right column transfer period, or the inter-column transfer period overlaps;
The substrate processing system according to claim 6 . In the step of determining whether the delay time can be absorbed, when the left column transfer period, the right column transfer period, or the inter-column transfer period does not overlap in the transfer module due to the delay time, a process of absorbing the delay time by the slack period of the process module is repeated in order from the module where the delay occurred toward the downstream side of the plurality of transfer modules until the left column transfer period, the right column transfer period, or the inter-column transfer period overlap due to the delay time, or until absorption of the delay time is completed.
The substrate processing system of claim 7 . A control device for a substrate processing system that transports substrates to a plurality of process modules by one or more transport modules and performs substrate processing,
the control device sets a common cycle time for performing the transfer processing of the one or more transfer modules and the processing of the plurality of process modules during one period , and creates and controls a schedule for the plurality of process modules and a schedule for the one or more transfer modules during one period of the cycle time;
the schedules for the plurality of process modules include an unloading period for unloading the substrates, an loading period for loading the substrates, a process period for performing the substrate processing, and a margin period for absorbing processing delays;
The control device
When repeating the cycle time by controlling the plurality of process modules and the one or more transfer modules based on the created schedules of the plurality of process modules and the one or more transfer modules,
a step of determining, when a delay occurs in processing of a module of the substrate processing system, whether or not the delay time in processing of the module can be absorbed by the leeway period;
when it is determined that the delay time cannot be absorbed, changing the set cycle time to a cycle time of another period for the substrates in the module where the delay occurred and the substrates upstream of the module where the delay occurred, and executing the schedules of the plurality of process modules and the schedules of the one or more transfer modules for the cycle time of the other period .
Control device. A substrate transport and processing method for transporting substrates to a plurality of process modules by one or more transport modules and performing substrate processing, comprising:
setting a common cycle time for performing the processes in the plurality of process modules and the transfer process in the one or more transfer modules in one period ;
creating a schedule including an unloading period for unloading the substrate, an loading period for loading the substrate, a processing period for performing the substrate processing, and a surplus period for absorbing processing delays in the plurality of process modules during one period of the cycle time, and a schedule for the one or more transfer modules during one period of the cycle time ;
Furthermore, when repeating the cycle time by controlling the plurality of process modules and the one or more transfer modules based on the created schedules of the plurality of process modules and the one or more transfer modules,
a step of determining, when a delay occurs in processing of a module of the substrate processing system, whether or not the delay time in processing of the module can be absorbed by the leeway period;
when it is determined that the delay time cannot be absorbed, changing the set cycle time to a cycle time of another period for the substrates in the module where the delay occurred and the substrates upstream of the module where the delay occurred, and executing a schedule for the plurality of process modules and a schedule for the one or more transfer modules for the cycle time of the other period .
A substrate transport and processing method.