JP7761830B2 - Semiconductor device and power conversion device using the same - Google Patents

Description

The present invention relates to the structure of a semiconductor device, and in particular to technology that is effective when applied to a semiconductor module having multiple semiconductor chips connected in parallel.

Today, power devices such as diodes and IGBTs (Insulated Gate Bipolar Transistors) play an important role in a wide range of fields, including electricity, transportation, communications, and home appliances. As core components used in power supplies and power conversion equipment, power devices have become increasingly diverse in type, with higher voltage resistance, larger capacity, and more powerful and functional.

In particular, in recent years, there has been a demand for even greater capacity and performance in response to the trend toward expanding applications for inverter devices. One method of achieving this is to widely use high-capacity semiconductor modules, in which multiple semiconductor chips such as diodes and IGBTs are placed on a single insulating substrate and connected in parallel to form a single module.

In a semiconductor module having multiple semiconductor chips connected in parallel as described above, depending on the operating conditions, vibrations due to resonance between the semiconductor chips can occur due to the mutual inductance of the multiple bonding wires connecting the metal circuit pattern on the insulating substrate to the semiconductor chips. For example, vibrations are likely to occur during reverse recovery of a diode or when an IGBT is turned off. High-frequency vibrations are also likely to occur when operating at low voltages and low temperatures. These vibrations due to resonance between semiconductor chips have a higher frequency than other vibrations, and can propagate through space, posing a risk of interference with various communication devices, as well as leading to power loss in the semiconductor module itself.

As background art in this technical field, there is, for example, technology such as that disclosed in Patent Document 1. Patent Document 1 discloses a power module in which a plurality of diodes D1 to D4 are arranged in a line so that the lengths of the Al wires L1 to L4 are the same, and Al wires L25 and L26 are added to connect the diodes D1 and D2, and the diodes D3 and D4, respectively, thereby shifting the frequency band of high-frequency vibration to a band that does not pose a practical problem, thereby reducing radiation noise (see FIG. 10 and paragraphs [0024] to [0028] of Patent Document 1).
Furthermore, Patent Document 2 discloses a method for designing a semiconductor power module that does not oscillate when turned off by adjusting the wiring length or the like to set values of inductance L and capacitance C of the resonant circuit that do not establish oscillation conditions (see paragraph [0043] of Patent Document 2, etc.).
Furthermore, Patent Document 3 discloses a semiconductor switch device that suppresses current oscillations during turn-off by inserting a ferrite core, which is a high-frequency loss element, at a position on the wiring path between the gate wiring branch point and the gate pad (see, for example, FIG. 1 and paragraphs [0029] and [0049] of Patent Document 3).

JP 2012-38803 A JP 2013-229383 A Japanese Patent Application Laid-Open No. 2001-185679

However, while Patent Document 1 mentioned above can shift the frequency band of high-frequency vibrations to a band that does not pose a practical problem, its effectiveness in reducing high-frequency vibrations between diodes is thought to be limited.

Furthermore, the above-mentioned Patent Document 2 imposes certain constraints on the module design, such as the need to adjust the wiring length.

Furthermore, in Patent Document 3, a ferrite core, which is a high-frequency loss element, must be provided on the substrate, which is disadvantageous in terms of miniaturization and cost of the semiconductor device.

The object of the present invention is to provide a semiconductor device having multiple semiconductor chips connected in parallel, which can sufficiently suppress high-frequency vibrations caused by resonance between semiconductor chips due to the mutual inductance of multiple bonding wires connecting the semiconductor chips to a metal circuit pattern on an insulating substrate, and a power conversion device using the same.

To solve the above problem, the present invention provides a semiconductor device in which a first semiconductor chip and a second semiconductor chip are connected in parallel, the semiconductor device comprising: a first bonding wire connecting a wiring pattern to the first semiconductor chip; a second bonding wire connecting the wiring pattern to the second semiconductor chip; and a third bonding wire and a fourth bonding wire directly connecting the first semiconductor chip and the second semiconductor chip, wherein the third bonding wire and the fourth bonding wire intersect when the semiconductor device is viewed in a plan view.

The present invention makes it possible to realize a semiconductor device having multiple semiconductor chips connected in parallel, and a power conversion device using the same that can sufficiently suppress high-frequency vibrations caused by resonance between the semiconductor chips due to the mutual inductance of multiple bonding wires connecting the semiconductor chips to a metal circuit pattern on an insulating substrate.

This improves the reliability and reduces loss in semiconductor devices.

Other issues, configurations, and advantages will become clear from the description of the following embodiments.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention; 1 is a plan view of a semiconductor device according to a first embodiment of the present invention; FIG. 2B is a diagram conceptually illustrating the mutual inductance of the bonding wires crossing each other in FIG. 2A. FIG. 2C is a diagram showing a modification of FIGS. 2A and 2B. FIG. 10 is a diagram showing an example of conventional bonding wire connections. 1A and 1B are diagrams illustrating examples of bonding wire connections between semiconductor chips. 1A and 1B are diagrams illustrating examples of bonding wire connections between semiconductor chips. 1A and 1B are diagrams illustrating examples of bonding wire connections between semiconductor chips. 1A and 1B are diagrams illustrating examples of bonding wire connections between semiconductor chips. FIG. 10 is a diagram showing the relationship between the angle AOB of the bonding wire between semiconductor chips and the mutual inductance IBC between the semiconductor chips. FIG. 10 is a plan view of a semiconductor chip according to a second embodiment of the present invention. FIG. 5B is a diagram showing a modification of FIG. 5A. FIG. 10 is a plan view of a semiconductor device according to a second embodiment of the present invention. FIG. 10 is a perspective view showing a state in which a conventional semiconductor device is mounted using bonding wires. FIG. 1 is a diagram conceptually illustrating a problem in a conventional semiconductor device.

Embodiments of the present invention will be described below using the drawings. Note that identical components in each drawing will be assigned the same reference numerals, and detailed descriptions of overlapping parts will be omitted.

The semiconductor device of Example 1 of the present invention will be described with reference to Figures 1 to 4F, 6A, and 6B.

Figure 1 is a cross-sectional view of the semiconductor device of this embodiment. Figures 2A and 2B are plan views of the semiconductor device of this embodiment. Figure 2A shows the bonding wire crossing angles A and B described below, and Figure 2B conceptually illustrates the inductance interaction of the two bonding wires 8a and 8b in Figure 2A. Figure 3 is a diagram illustrating a modification of Figures 2A and 2B. Figures 4A to 4E are diagrams illustrating examples of bonding wire connections. Figure 4F is a diagram illustrating the relationship between the bonding wire angle AOB between semiconductor chips and the mutual inductance IBC between semiconductor chips. Points A to E in Figure 4F correspond to Figures 4A to 4E, respectively. Figures 6A and 6B illustrate the mounting state of a conventional semiconductor device using bonding wires and the issues involved, shown to make the configuration of this invention easier to understand.

First, we will explain the configuration of a conventional semiconductor device and its problems using Figures 6A and 6B.

As shown in Figure 6A, in a conventional semiconductor device, semiconductor chips 4a and 4b are mounted on a metal circuit pattern 6b formed on an insulating substrate (not shown). The semiconductor chips 4a and 4b are joined to the metal circuit pattern 6b with a joining material such as solder. Each pad electrode 15 of the semiconductor chips 4a and 4b is electrically connected to the metal circuit pattern 6a, which is also formed on the insulating substrate, by bonding wires 8a and 8b.

The semiconductor chips 4a and 4b are, for example, bipolar elements such as diodes and IGBTs. The pad electrode 15 is an anode pad in the case of a diode, and an emitter pad in the case of an IGBT.

As shown in Figures 6A and 6B, the bonding wires 8 connecting each pad electrode 15 of the semiconductor chips 4a and 4b to the metal circuit pattern 6a are generally arranged in a straight line connecting the semiconductor chips 4a and 4b and the metal circuit pattern 6a over the shortest distance to minimize electrical resistance, and are connected by wire bonding.

Conventional semiconductor devices are configured as described above, and as shown in Figure 6B, a resonant loop is formed due to the interaction of the inductances of the bonding wires 8a and 8b closest to the adjacent semiconductor chips, generating high-frequency vibrations between the semiconductor chips 4a and 4b.

As mentioned above, this high-frequency vibration between the semiconductor chips 4a and 4b propagates through space, interfering with and adversely affecting various communication devices, and also leads to power loss in the semiconductor device itself.

Next, the configuration and effects of the semiconductor device of this embodiment will be explained using Figures 1 to 4F.

As shown in Figure 1, the semiconductor device of this embodiment is configured as a semiconductor module 1 having multiple semiconductor chips 4 connected in parallel.

As shown in Figure 1, the semiconductor module 1 of this embodiment mainly comprises multiple insulating substrates 3 arranged on a single base plate 2 and multiple semiconductor chips 4 mounted on each of the multiple insulating substrates 3.

A metal pattern 5 is formed on the underside of the insulating substrate 3, and is joined to the base plate 2 by solder 7. A metal circuit pattern 6 is formed on the upper surface of the insulating substrate 3, and the semiconductor chip 4 is joined to the metal circuit pattern 6 by solder 7.

The multiple semiconductor chips 4 are each connected by bonding wires 8 to metal circuit patterns 6 on which no semiconductor chips 4 are mounted, and are further connected to output terminals 13 and auxiliary terminals 14 via the metal circuit patterns 6.

The insulating substrate 3, semiconductor chip 4, and bonding wires 8 are covered in a resin case 9, and the semiconductor module 1 is constructed by filling the case 9 with insulating resin (gel) 10.

A heat sink 11 is connected via solder or grease 12 to the underside of the base plate 2, i.e., the surface opposite the surface on which the insulating substrate 3 is placed. Heat generated during operation of the semiconductor chip 4 is dissipated through heat exchange by the heat sink 11. The base plate 2 is a support member that supports multiple insulating substrates 3, and also functions as a heat spreader (heat sink).

Here, in the semiconductor device of this embodiment, as shown in FIG. 2A, in addition to the conventional bonding wire wiring shown in FIG. 6B, two bonding wires are further provided to connect the semiconductor chips 4a and 4b to each other, and these two bonding wires are arranged so that they cross each other when the semiconductor device is viewed in a plan view.

In other words, the semiconductor device of this embodiment is a semiconductor device in which semiconductor chips 4a and 4b are connected in parallel, and is equipped with bonding wires that connect the metal circuit pattern 6a, which is a wiring pattern on the insulating substrate 3, to the semiconductor chip 4a, bonding wires that connect the metal circuit pattern 6a to the semiconductor chip 4b, and bonding wires 8a and 8b that directly connect the semiconductor chips 4a and 4b, and is configured so that the bonding wires 8a and 8b intersect when the semiconductor device is viewed in a plan view.

Two bonding wires that intersect with each other form an intersection angle A (or B). Intersection angle A is the angle in the arrangement direction of the semiconductor chips 4a and 4b, and intersection angle B is the angle in the direction perpendicular to the arrangement direction of the semiconductor chips 4a and 4b. Therefore, A + B = 180°.

In this embodiment, the two bonding wires are arranged to cross each other so that the crossing angle A is 60° or greater, and more preferably 90° or greater.

By setting the crossing angle of the two intersecting bonding wires to 60° or more, or 90° or more, the interaction of the inductances of the two bonding wires can be used to sufficiently suppress high-frequency vibrations caused by resonance between the semiconductor chips 4a and 4b, as shown in Figure 2B.

As shown in Figure 3, by setting the crossing angle A of the two intersecting bonding wires to approximately 90°, the mutual inductance between bonding wires 8a and 8b can be reduced to almost zero.

The intersection angle A will be explained in more detail using Figures 4A to 4F.

Figure 4A shows wiring using conventional bonding wires, as shown in Figure 6B. As shown in Figure 4B, adding one bonding wire that directly connects semiconductor chips 4a and 4b reduces the mutual inductance between semiconductor chips 4a and 4b, but this may not be sufficient depending on the operating conditions of semiconductor chips 4a and 4b.

Furthermore, as shown in Figure 4C, if two bonding wires that directly connect semiconductor chips 4a and 4b are added without crossing, the mutual inductance between semiconductor chips 4a and 4b can be reduced, but increasing the number of wires from one to two does not halve the mutual inductance between semiconductor chips 4a and 4b.

On the other hand, as shown in Figure 4D, if the crossing angle A of the two intersecting bonding wires is 60° or more, the mutual inductance between the semiconductor chips 4a and 4b can be more effectively suppressed.

Furthermore, as shown in Figure 4E, when the intersection angle A is greater than 120°, the mutual inductance between the semiconductor chips 4a and 4b stabilizes and does not decrease any further.

For the above reasons, it is preferable that the crossing angle A of two intersecting bonding wires be greater than or equal to 60° and less than or equal to 120°, and more preferably greater than or equal to 90° and less than or equal to 120°.

With reference to Figures 5A to 5C, a semiconductor device according to a second embodiment of the present invention will be described.

Figure 5A is a plan view of a semiconductor chip of the semiconductor device of this embodiment. Figure 5B is a diagram showing a modified example of Figure 5A. Figure 5C is a plan view of the semiconductor device of this embodiment.

In this example, we will explain a more specific configuration example of the semiconductor device shown in Figure 2A.

When IGBTs are used for the semiconductor chips 4a and 4b, the semiconductor chip 4 has a configuration as shown in Figure 5A. The semiconductor chip 4 has an emitter pad 16 and a gate pad 17 formed as pad electrodes 15, and terminations 18 are provided around them to maintain voltage resistance.

Furthermore, when diodes are used for the semiconductor chips 4a and 4b, the semiconductor chip 4 will have a configuration as shown in Figure 5B. The semiconductor chip 4 has an anode pad 19 formed as a pad electrode 15, and terminations 18 are provided around it to maintain voltage resistance.

Figure 5C shows an example configuration using an IGBT. As shown in Figure 5C, the semiconductor device of this embodiment includes an insulating substrate (reference numeral 3 in Figure 1) on which semiconductor chips 4a and 4b are mounted. Metal circuit pattern 6a is disposed on insulating substrate 3 so as to extend along the arrangement direction of semiconductor chips 4a and 4b, and bonding wires connecting metal circuit pattern 6a to semiconductor chip 4a and bonding wires connecting metal circuit pattern 6b to semiconductor chip 4b are disposed approximately parallel to each other.

Metal circuit patterns 6a, 6b, 6c, and 6d are the emitter pattern, collector pattern, emitter auxiliary pattern, and gate pattern, respectively.

In this embodiment, by specifying the crossing angle A of the two intersecting bonding wires in the same manner as in embodiment 1, the interaction of the inductances of the two bonding wires can be used to sufficiently suppress high-frequency vibrations due to resonance between the semiconductor chips 4a and 4b.

The present invention is not limited to the above-described embodiments, and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

1...Semiconductor module 2...Base plate (heat spreader)
3...insulating substrate 4, 4a, 4b...semiconductor chip 5...metal pattern 6, 6a, 6b, 6c, 6d...metal circuit pattern 7...solder 8, 8a, 8b...bonding wire 9...case 10...insulating resin (gel)
11... Heat sink 12... Grease 13... Output terminal 14... Auxiliary terminal 15... Pad electrode 16... Emitter pad 17... Gate pad 18... Termination 19... Anode pad A, B... Intersection angle AOB... Angle of bonding wire between semiconductor chips (A)
IBC: Mutual inductance between semiconductor chips

Claims (8)

In a semiconductor device in which a first semiconductor chip and a second semiconductor chip are connected in parallel,
a first bonding wire connecting a wiring pattern and the first semiconductor chip;
a second bonding wire connecting the wiring pattern and the second semiconductor chip;
a third bonding wire and a fourth bonding wire that directly connect the first semiconductor chip and the second semiconductor chip;
The semiconductor device is characterized in that, when the semiconductor device is viewed from above, the third bonding wire and the fourth bonding wire cross each other. 2. The semiconductor device according to claim 1,
10. A semiconductor device comprising: a first semiconductor chip and a second semiconductor chip; a bonding wire and a bonding wire, the bonding wire and the bonding wire intersecting each other at an angle of 60 degrees or more in an arrangement direction of the first semiconductor chip and the second semiconductor chip; 3. The semiconductor device according to claim 2,
The semiconductor device is characterized in that the crossing angle is 90° or more. 3. The semiconductor device according to claim 2,
The semiconductor device is characterized in that the crossing angle is equal to or greater than 60° and equal to or less than 120°. 4. The semiconductor device according to claim 3,
The semiconductor device is characterized in that the crossing angle is equal to or greater than 90° and equal to or less than 120°. 2. The semiconductor device according to claim 1,
1. A semiconductor device, wherein the first semiconductor chip and the second semiconductor chip are bipolar elements. 2. The semiconductor device according to claim 1,
an insulating substrate on which the first semiconductor chip and the second semiconductor chip are mounted;
the wiring pattern is disposed on the insulating substrate so as to extend along an arrangement direction of the first semiconductor chip and the second semiconductor chip;
The semiconductor device is characterized in that the first bonding wire and the second bonding wire are arranged substantially parallel to each other. A power conversion device comprising the semiconductor device according to any one of claims 1 to 7.