JP7764239B2 - Thickness measurement method and flatness measurement method for high-resistivity silicon wafer - Google Patents

Description

The present invention relates to a method for measuring the thickness and flatness of a high-resistivity silicon wafer, and in particular to a method for measuring the thickness and flatness of a high-resistivity silicon wafer using a capacitance-type thickness measuring device and measuring the flatness of the high-resistivity silicon wafer based on the results.

To grow silicon single crystals using the Czochralski (CZ) method, a quartz crucible placed inside a chamber is filled with polysilicon, which is then heated and melted using a heater installed around the quartz crucible to form molten silicon. A seed crystal (seed) attached to a seed chuck is then immersed in the molten silicon, and the seed chuck is pulled up while the seed chuck and quartz crucible are rotated in the same or opposite directions.

Many silicon single crystals produced using this CZ method are used as semiconductor materials. The resistivity of the grown silicon single crystal is adjusted by the dopant (impurity) added to the silicon melt. Dopants are classified as n-type and p-type, with P (phosphorus) being the most commonly used dopant when growing n-type crystals and B (boron) being the most commonly used dopant when growing p-type crystals.

In recent years, there has been an increasing demand for silicon single crystals with a high resistivity of 10,000 Ω cm or more. Silicon wafers obtained from such silicon single crystals are used, for example, in the manufacture of high-frequency devices for communication.
When producing a silicon single crystal with a high resistivity of 10,000 Ωcm or more, it is common to use a method in which high-purity polycrystalline silicon is placed in a high-purity quartz crucible (the inner surface of which is coated with synthetic quartz) and the silicon is grown without adding a dopant, as disclosed in Patent Document 1 (Japanese Patent Laid-Open Publication No. 5-58788), for example.

For example, if the requirement is simply to produce a silicon single crystal with a high resistivity above a specified value, it is sufficient to grow the single crystal without doping using a quartz crucible and silicon raw material with controlled purity.However, if it is necessary to meet a stricter resistivity range requirement, it is desirable to control the resistivity with a small amount of dopant.
When growing a silicon single crystal with dopants, the dopant concentration in the melt increases as the silicon melt decreases, which causes the resistivity of the single crystal to become non-uniform in the pulling direction (single crystal axis direction).

In order to stabilize the resistivity in the axial direction of a single crystal, Patent Document 2 (JP 4-243995 A) discloses a method in which, for example, when pulling a silicon single crystal from a boron-added silicon melt, the dopant dissolved from the inner surface of the crucible is phosphorus, an n-type impurity that provides the opposite conductivity type to boron. In other words, the increase in carriers due to the increase in boron is compensated for by the n-type impurity, mitigating fluctuations in resistivity in the pulling direction.

Patent Document 3 (JP 2013-142054 A) also discloses a method for controlling the concentration of oxygen atoms in the axial direction of a single crystal in advance, so that thermal donors are formed by subjecting a silicon wafer to heat treatment during the device manufacturing process, thereby achieving an N-type conductivity and the desired resistivity.

Japanese Patent Application Publication No. 5-58788 Japanese Unexamined Patent Publication No. 4-243995 JP 2013-142054 A

Incidentally, in the case of high-resistivity silicon wafers obtained from silicon single crystals, it is necessary to measure the thickness and, based on the results, measure the flatness during the inspection process of the manufacturing process.
However, in the case of a silicon wafer with a high resistivity of, for example, 10,000 Ωcm or more, when the thickness dimension is measured in a non-contact manner using a capacitance-type thickness measuring device, the capacitance cannot be measured normally due to the high resistivity of the wafer, and not only is the correct thickness dimension not obtained, but there is also the problem of large variations.

Specifically, in the case of a high-resistivity silicon wafer, when the thickness is measured using the capacitance method, the measured thickness is several micrometers thinner than the actual thickness, and the measured value varies.
In order to solve the above problem, it is conceivable to extract a sample silicon wafer and perform contact-type thickness measurement, but there are circumstances in which it is more preferable to measure the thickness of all silicon wafers using non-contact-type thickness measurement.

In light of the above circumstances, the inventors of the present application conducted extensive research on the premise of measuring the thickness of high-resistivity silicon wafers obtained from silicon single crystals grown by doping with trace amounts of boron and n-type impurities, or boron and donor defects, using a capacitance-type thickness measuring device, and have arrived at the present invention.

The object of the present invention is to provide a method for measuring the thickness of a high-resistivity silicon wafer and a method for measuring the flatness of a high-resistivity silicon wafer, which can accurately measure the thickness of a high-resistivity silicon wafer using a capacitance-type thickness measuring device and measure the flatness of the wafer based on the results.

The present invention provides a method for measuring the thickness of a high-resistivity silicon wafer, which was developed to solve the above-mentioned problems. The method measures the thickness of a high-resistivity silicon wafer doped with boron and n-type impurities, and is characterized by comprising the steps of: making the n-type impurities in the silicon wafer more functional to temporarily form an n-type silicon wafer with lower resistivity; and performing capacitance-based thickness measurement on the silicon wafer with reduced resistivity.

In the step of making the n-type impurities in the silicon wafer more functional and temporarily forming an n-type silicon wafer having a lower resistivity, it is desirable to temporarily set the resistivity of the silicon wafer to 2000 Ωm or less.
In the step of enhancing the functionality of n-type impurities in the silicon wafer and temporarily forming an n-type silicon wafer with lower resistivity, it is preferable to clean the silicon wafer with a cleaning solution containing hydrogen atoms, and inactivate boron in the silicon wafer with the hydrogen atoms diffused into the silicon wafer. The cleaning solution containing hydrogen atoms is preferably any one of SC-1 cleaning, dilute hydrofluoric acid cleaning, and SH cleaning.

Furthermore, in the step of making the n-type impurities in the silicon wafer more functional and temporarily forming an n-type silicon wafer with lower resistivity, the silicon wafer may be wet-etched with an alkaline or acidic chemical solution, and the boron in the silicon wafer may be inactivated by hydrogen atoms diffused into the silicon wafer.

Furthermore, it is desirable to perform a capacitance-based thickness measurement on the silicon wafer within 16 hours after the step of making the n-type impurities in the silicon wafer more functional and temporarily forming an n-type silicon wafer having a lower resistivity.
Furthermore, in the step of making the n-type impurities in the silicon wafer more functional and temporarily forming an n-type silicon wafer having lower resistivity, thermal donors may be formed in the silicon wafer by heat treating the silicon wafer at a temperature of at least 450°C.

According to this method, silicon wafers are cleaned with a cleaning agent containing hydrogen atoms immediately before capacitance-based thickness measurements are performed. This causes hydrogen atoms to diffuse and penetrate into the wafer, deactivating the boron in the silicon wafer. As a result, the silicon wafer temporarily changes into an n-type silicon wafer with lower resistivity than before cleaning, enabling highly accurate thickness and flatness measurements.

Further, a method for measuring the flatness of a high-resistivity silicon wafer according to the present invention, which has been made to solve the above-mentioned problems, is a method for measuring the flatness of a high-resistivity silicon wafer using any of the above-mentioned methods for measuring the thickness of a high-resistivity silicon wafer, and is characterized in that a capacitance sensor is scanned over the entire surface of the silicon wafer to acquire a thickness distribution of the silicon wafer.
According to this method, the flatness of a high-resistivity silicon wafer can be measured with high precision.

The present invention provides a method for measuring the thickness of a high-resistivity silicon wafer and a method for measuring the flatness of a high-resistivity silicon wafer, which can accurately measure the thickness of the high-resistivity silicon wafer using a capacitance-type thickness measuring device and measure the flatness of the wafer based on the results.

FIG. 1 is a block diagram of a capacitance-type flatness measuring device that can be used in the measuring method of the present invention. FIG. 2 is a flow chart showing an example of a silicon wafer manufacturing process to which the method for measuring the flatness of a silicon wafer according to the present invention is applied. FIG. 3 is a graph showing the results of Experiment 1 of the embodiment of the present invention. FIG. 4 is a graph showing the results of Experiments 2 and 3 of the embodiment of the present invention.

Hereinafter, a method for measuring the thickness and flatness of a high-resistivity silicon wafer according to the present invention will be described with reference to the drawings.
1 is a block diagram of a capacitance-type flatness measurement device that can be used in the measurement method of the present invention. This flatness measurement device 1 includes a pair of capacitance sensors 2 and 3 arranged above and below the surface of a silicon wafer W supported by a support member 8, a movement mechanism 4 for moving the capacitance sensors 2 and 3 along the wafer surface in a scanning manner, and a computer 5 that calculates the wafer thickness at the measurement point using measurements obtained from the capacitance sensors 2 and 3 and measures the flatness of the entire wafer. The support member 8 and the capacitance sensors 2 and 3 are connected by conductive wires 6 and 7, respectively.

The capacitance sensor 2 measures the distance d1 between the sensor tip and the upper surface of the silicon wafer W, and the capacitance sensor 3 measures the distance d2 between the sensor tip and the lower surface of the silicon wafer W. That is, the capacitance sensors 2 and 3 measure the change in capacitance formed between the sensor surface and the wafer surface as the distance between the two surfaces.
The computer 5 calculates the wafer thickness t using the equation t = d3 - (d1 + d2) using the distance d3 between the tips of the capacitance sensors 2 and 3. The movement mechanism 4 scans the capacitance sensors 2 and 3 over the entire wafer to obtain the thickness distribution, and the flatness of the silicon wafer is calculated.

The embodiment of the present invention is characterized in that, in a step prior to the thickness measurement and flatness measurement by this flatness measurement device 1, the silicon wafer W is cleaned with a cleaning solution containing hydrogen atoms, thereby temporarily changing the electrical properties of the silicon wafer W.
Furthermore, the method for measuring the flatness of a high-resistivity silicon wafer according to the present invention can be carried out in the process of manufacturing the silicon wafer, and the above-described silicon wafer cleaning process and measurement by the flatness measuring apparatus 1 are used in the wafer manufacturing process.
The following describes a silicon wafer manufacturing process in which the flatness measurement method of the present invention can be implemented. Fig. 2 is a flow chart showing an example of a silicon wafer manufacturing process in which the silicon wafer flatness measurement method of the present invention can be applied.

The object of the present invention for measuring the flatness of a silicon wafer is a high-resistivity silicon wafer having a resistance of, for example, 10,000 Ωcm or more. Such a silicon wafer is manufactured, for example, as follows.
First, a high-resistivity silicon single crystal having a resistance of 10,000 Ωcm or more is manufactured by the Czochralski method (step S1 in FIG. 2).
In the production of silicon single crystals, n-type impurities (n-type dopants) and boron, such as phosphorus and boron or arsenic and boron, are used simultaneously as trace amounts of dopants. The amounts of the n-type impurities and boron dopants may be determined according to the target resistivity of the silicon wafer to be produced and the design of whether the semiconductor is to be an n-type or a p-type.
As a specific method for adding the dopant, for example, first, raw polysilicon (for example, 150 kg) and silicon chips for adding the dopant containing a trace amount of boron are loaded into a synthetic quartz glass crucible to form a silicon melt.

After forming the silicon melt in the crucible, the single crystal is pulled up in a single crystal pulling process, whereby the crystal diameter is gradually enlarged to form a shoulder portion and a straight body portion that will become the product portion.
During the formation of the body portion, the boron dopant concentration in the melt increases as the silicon melt decreases. If left as is, the resistivity of the single crystal will also become non-uniform in the pulling direction. Therefore, while monitoring the resistivity of the single crystal being grown, n-type impurities that impart the opposite conductivity type to boron are added to the melt while the crystal is being pulled. In other words, the increase in carriers due to the increase in boron is compensated for by the n-type impurities, and the fluctuation in resistivity in the pulling direction is mitigated.
The resistivity of the grown silicon single crystal is estimated by measuring the diameter and length of the single crystal during pulling, and calculating the solidification rate, which is expressed as the weight of the single crystal divided by the weight of the initial silicon raw material, from the measured diameter and length of the single crystal.

After the straight body portion that will become the product is formed, the crystal diameter is gradually reduced, gradually reducing the contact area between the bottom end of the crystal and the molten silicon (forming the tail portion), and the bottom end of the crystal is separated from the molten silicon to produce a silicon single crystal.

The silicon single crystal thus produced is cut into a straight body portion, which is then sliced to obtain a plurality of silicon wafers (step S2 in FIG. 2).
The silicon wafer thus obtained is subjected to beveling (beveling) on the outer periphery using a diamond grindstone, and the end face is formed into, for example, an arc-shaped cross section (step S3 in FIG. 2).
Next, the carrier on which the silicon wafer is placed is rotated between the upper and lower rotating lapping machines, and a lapping process is performed in which both sides are polished while abrasive grains are supplied (step S4 in FIG. 2).
After lapping, a jig with multiple silicon wafers placed in an etching solution mixed with acid is rotated around the wafer axis while etching is performed to remove the damaged layer caused by the previous mechanical processing (step S5 in FIG. 2).

Next, the silicon wafer is placed in a diffusion furnace, and a heat treatment is performed to decompose unstable donors caused by oxygen generated during crystal growth, thereby restoring the original resistivity (step S6 in FIG. 2).
Furthermore, the plate with the silicon wafer bonded thereto is pressed against a rotating surface plate with an abrasive cloth attached, and polishing is performed by mechanical and chemical combined action while supplying an abrasive until the wafer surface becomes a mirror finish (step S7 in FIG. 2).

After polishing is complete, the silicon wafer is cleaned with a cleaning solution containing hydrogen atoms (step S8 in FIG. 2). Specifically, cleaning is performed using one or more of the following cleaning solutions in sequence: SC-1 solution (a solution of 5 parts water, 1 part hydrogen peroxide, and 1 part ammonium hydroxide), dilute hydrofluoric acid solution, and SH solution (a solution of sulfuric acid and hydrogen peroxide). After cleaning with each of these cleaning solutions, cleaning with pure water is performed each time. In the case of SC-1 solution, the wafer is immersed for 10 minutes at a solution temperature of 65°C. In the case of dilute hydrofluoric acid solution, the wafer is immersed for 5 minutes at a solution temperature the same as room temperature. In the case of SH solution, the wafer is immersed for 7 minutes at a solution temperature of 110°C.
During this cleaning process, hydrogen atoms contained in the cleaning solution diffuse and penetrate into the boron-doped silicon wafer. The hydrogen atoms that penetrate into the wafer cause the electrical activity of the boron acceptor to be lost, resulting in inactivation. As a result of the boron being inactivated, the silicon wafer temporarily becomes an n-type silicon wafer in which the n-type impurities function more effectively as dopants than before cleaning, and the resistivity decreases compared to before cleaning. Specifically, the resistivity temporarily decreases to 2000 Ω cm or less.

If more than 16 hours pass after the cleaning process in step S8, hydrogen atoms in the wafers will diffuse outward into the ambient air at room temperature, activating the boron in the wafers and potentially causing the resistivity of the silicon wafers to rise above 10,000 Ωcm again. Therefore, within 16 hours after cleaning, the thickness and flatness of each silicon wafer are measured using flatness measurement device 1 (step S9 in Figure 2).

Here, the silicon wafer temporarily changes to an n-type wafer with a resistivity lowered to 2000 Ωcm or less compared to before cleaning, so that the capacitance between the capacitance sensors 2, 3 and the wafer surface can be measured accurately, and thickness and flatness measurements can be performed with high precision and little effect of resistance.
As described above, if 16 hours have passed since the cleaning process of step S8, hydrogen will diffuse outward, reactivating the boron in the silicon wafer and increasing the resistance value. In this case, cleaning of step S8 can be performed again to inactivate the boron in the silicon wafer, temporarily reducing the resistance value to 2000 Ω cm or less, enabling accurate measurement.

As described above, according to an embodiment of the present invention, a silicon wafer is cleaned with a cleaning agent containing hydrogen atoms immediately before undergoing capacitance-based thickness measurement. This causes hydrogen atoms to diffuse and penetrate into the wafer, deactivating the boron in the silicon wafer. As a result, the silicon wafer temporarily changes to an n-type silicon wafer with lower resistivity than before cleaning, enabling highly accurate thickness and flatness measurements.

In the above embodiment, the silicon wafer is cleaned with a cleaning agent containing hydrogen atoms in step S8 of FIG. 2, but the present invention is not limited to this form.
For example, instead of the cleaning step in step S8, a wet etching step using an alkaline or acidic chemical solution may be performed. For example, in the case of acid etching, the wafer is immersed in the solution at a temperature of 40° C. for 4 minutes. In this case, hydrogen atoms diffuse and penetrate into the wafer, and boron in the silicon wafer can be inactivated.

Alternatively, before the thickness measurement and flatness measurement in step S9, the silicon wafer may be heat-treated at a low temperature of about 450° C. to form thermal donors (oxygen donors) in the wafer, temporarily converting the silicon wafer into an n-type silicon wafer to reduce the resistivity, and the thickness measurement and flatness measurement in step S9 may be performed in this state.
In this case, after the measurement process of step S9, the silicon wafer may be subjected to a heat treatment at about 650°C to eliminate the thermal donors in the wafer and return the resistivity of the wafer to 10,000 Ω cm or more. In this case, the measurement is not limited to being performed within 16 hours after cleaning, but multiple heat treatments are required, so it is advisable to perform the flatness measurement by changing the method appropriately depending on the case.

In addition, while the above embodiment has been described as an example of measuring the thickness and flatness of a silicon wafer with a resistivity of 10,000 Ωcm or more, the present invention is not limited to this form. For example, it can also be applied to measuring the thickness and flatness of a silicon wafer with a resistivity of more than 2,000 Ωcm.

Furthermore, in the above-described embodiment, the electrical characteristics of the silicon wafer that is the subject of thickness measurement and flatness measurement according to the present invention, i.e., the electrical characteristics of the silicon wafer before cleaning in step S8, may be p-type or n-type, and the present invention can be applied to either type.

The method for measuring the thickness of a high-resistivity silicon wafer and the method for measuring the flatness of a high-resistivity silicon wafer according to the present invention will be further explained based on examples.

(Experiment 1)
In Experiment 1, a silicon wafer having a resistivity of 10,000 Ωcm was manufactured based on the embodiment of the present invention, and the thickness of the wafer at its center point was measured using the flatness measurement device 1 shown in FIG.

Example 1
In Example 1, in step S8 of FIG. 2, a silicon wafer having a thickness of 732 μm was immersed in a dilute hydrofluoric acid solution at the same temperature as room temperature for 5 minutes for cleaning, and then, 14 hours later, the thickness of the silicon wafer at the center point was measured using the flatness measurement device 1 of FIG. 1.
The resistivity of the silicon wafer was also measured at the time of thickness measurement. The thickness measurement was repeated 10 times for the same silicon wafer.

(Comparative Example 1)
In Comparative Example 1, a 732 μm silicon wafer was subjected to thickness measurement at the center point of the silicon wafer using the flatness measurement device 1 of FIG. 1 before cleaning in step S8 of FIG.
The resistivity of the silicon wafer was also measured at the time of thickness measurement. The thickness measurement was repeated 10 times for the same silicon wafer.

(Comparative Example 2)
In Comparative Example 2, in step S8 of FIG. 2, a silicon wafer having a thickness of 732 μm was immersed in a dilute hydrofluoric acid solution at the same temperature as room temperature for 5 minutes for cleaning, and then, 62 hours later, the thickness of the silicon wafer at the center point was measured using the flatness measurement device 1 of FIG. 1.
The resistivity of the silicon wafer was also measured at the time of thickness measurement. The thickness measurement was repeated 10 times for the same silicon wafer.

The results for Example 1 and Comparative Examples 1 and 2 are shown in Table 1. The graph in Figure 3 shows the thickness measurement results for Example 1 and Comparative Examples 1 and 2 in a box plot. The vertical axis in the graph in Figure 3 represents the measured wafer thickness (μm).

In Example 1, the thickness measurement within 14 hours after cleaning yielded measurement results close to the true value with little variation. The resistance value at this time was 2000 Ωcm, and it was estimated that accurate thickness measurement was possible if the resistance value was 2000 Ωcm or less.
On the other hand, in Comparative Examples 1 and 2, that is, before and after cleaning, when 62 hours had elapsed, the values deviated from the true values and the variations became large.

(Experiment 2)
In Experiment 2, a silicon wafer with a resistivity of 10,000 Ωcm was cleaned with a cleaning solution containing hydrogen atoms, and the wafer resistivity was measured to verify changes over time.
The results of Experiment 2 are shown in the graph of Figure 4. In the graph of Figure 4, the vertical axis represents resistivity (Ωcm) and the horizontal axis represents the time elapsed after cleaning (h). The change in resistivity in Experiment 2 is shown by the solid line.

(Experiment 3)
In Experiment 3, a silicon wafer with a resistivity of 2100 Ωcm was cleaned with a cleaning solution containing hydrogen atoms, and the wafer resistivity was measured to verify changes over time.
The results of Experiment 3 are shown in the graph of Figure 4. In the graph of Figure 4, the vertical axis represents resistivity (Ωcm) and the horizontal axis represents the time elapsed after cleaning (h). The change in resistivity in Experiment 3 is shown by the dashed line.

As shown in the graph of FIG. 4, in the case of a silicon wafer with a resistivity of 10,000 Ωcm, the resistivity was 2,000 Ωcm for up to 30 hours after cleaning, confirming that thickness measurements could be performed with high accuracy.
On the other hand, in the case of a silicon wafer with a resistivity of 2100 Ωcm, it was confirmed that the resistivity became 2000 Ωcm for up to 20 hours after cleaning, enabling thickness measurements to be performed with high accuracy.
Based on the results of Experiments 2 and 3, the time after cleaning that allows accurate thickness measurement was set to 16 hours with a margin.
As a result of the above examples, it was confirmed that the thickness of a silicon wafer can be measured with high accuracy according to the present invention.

REFERENCE SIGNS LIST 1 Flatness measuring device 2 Capacitance sensor 3 Capacitance sensor 4 Moving mechanism 5 Computer 6 Conducting wire 7 Conducting wire 8 Support member W Silicon wafer

Claims (8)

1. A method for measuring the thickness of a high-resistivity silicon wafer doped with boron and n-type impurities, comprising:
Further functionalizing the n-type impurities in the silicon wafer to temporarily form an n-type silicon wafer having a lower resistivity;
performing a capacitance-type thickness measurement on the silicon wafer whose resistivity has decreased;
A method for measuring the thickness of a high-resistivity silicon wafer, comprising: In the step of further functionalizing the n-type impurities in the silicon wafer to temporarily form an n-type silicon wafer having a lower resistivity,
2. The method for measuring the thickness of a high-resistivity silicon wafer according to claim 1, wherein the resistivity of the silicon wafer is temporarily set to 2000 Ωm or less. In the step of further functionalizing the n-type impurities in the silicon wafer to temporarily form an n-type silicon wafer having a lower resistivity,
3. The method for measuring the thickness of a high-resistivity silicon wafer according to claim 1, wherein the silicon wafer is cleaned with a cleaning solution containing hydrogen atoms, and boron in the silicon wafer is inactivated by the hydrogen atoms diffused into the silicon wafer. The method for measuring the thickness of a high-resistivity silicon wafer described in claim 3, characterized in that the cleaning solution containing hydrogen atoms is either SC-1 cleaning, dilute hydrofluoric acid cleaning, or SH cleaning. In the step of further functionalizing the n-type impurities in the silicon wafer to temporarily form an n-type silicon wafer having a lower resistivity,
3. The method for measuring the thickness of a high-resistivity silicon wafer according to claim 1, wherein the silicon wafer is wet-etched with an alkaline chemical solution or an acidic chemical solution, and boron in the silicon wafer is inactivated by hydrogen atoms diffused into the silicon wafer. After the step of increasing the n-type impurity in the silicon wafer to temporarily form an n-type silicon wafer with lower resistivity,
6. The method for measuring the thickness of a high-resistivity silicon wafer according to claim 1, wherein the thickness of the silicon wafer is measured by a capacitance method within 16 hours. In the step of further functionalizing the n-type impurities in the silicon wafer to temporarily form an n-type silicon wafer having a lower resistivity,
3. The method for measuring the thickness of a high-resistivity silicon wafer according to claim 1, wherein the silicon wafer is subjected to a heat treatment at least at 450° C. to form a thermal donor in the silicon wafer. A method for measuring the flatness of a high-resistivity silicon wafer using the method for measuring the thickness of a high-resistivity silicon wafer according to any one of claims 1 to 7,
A method for measuring the flatness of a high-resistivity silicon wafer, comprising scanning a capacitance sensor over the entire surface of the silicon wafer to obtain a thickness distribution of the silicon wafer.