JP7764635B2 - Power-on reset circuit - Google Patents

Description

This disclosure relates to a power-on reset circuit.

When power supply voltage begins to be supplied to a semiconductor device, if the semiconductor device begins to operate at a stage where the power supply voltage is not at a sufficient level, specifically at a stage where the voltage is so low that the transistor cannot be turned on, there is a risk of malfunction.

For this reason, power-on reset circuits have traditionally been used to detect when the power supply voltage is above a certain level and generate a power-on reset (POR) signal. By starting operation after the POR signal is generated, semiconductor devices can prevent malfunctions.

For example, Japanese Patent Application Laid-Open No. 2019-186943 (Patent Document 1) describes a power-on reset circuit with low current consumption. In the power-on reset circuit described in Patent Document 1, a voltage detector 115 detects that the power supply voltage has risen above a threshold voltage level (VPOR_R) when the power supply voltage is started up, and the output signal of the voltage detector 115 is held in a POR latch 120 to generate a POR signal. Then, after the power supply voltage has risen, power consumption can be reduced by turning off the voltage detector 115.

Furthermore, Patent Document 1 describes that, as shown in Figures 2A and 2B, adjustable resistors (R1, R2) are arranged in the voltage divider circuit of the power supply voltage (V_BUS), and that the threshold voltage level (VPOR_R) of the power-on reset circuit is determined by changing the resistance value of the adjustable resistors.

Japanese Patent Application Laid-Open No. 2019-186943

In recent years, the application of energy harvesting, which converts natural energy such as sunlight into electricity, has expanded. However, when using an energy harvesting power supply, it is expected that the voltage change rate and the length of the period over which voltage is supplied will vary each time the power supply voltage is started, depending on changes in the environment (e.g., the luminosity of the solar cell). Therefore, even when the voltage change rate (rise rate) differs each time the power supply voltage is started, the challenge is to generate a POR signal at the appropriate time to accommodate various voltage change rates.

In particular, in applications where a POR signal is expected to be generated appropriately to operate a semiconductor device in response to a relatively short-term power supply, such as wireless sensor networks that operate when power is obtained through energy harvesting, it is necessary to generate a POR signal at the appropriate time without delay when the rate of change of the power supply voltage is large.

However, in the power-on reset circuit described in Patent Document 1, while it is possible to adapt the resistance values of the adjustable resistors (R1, R2) according to the expected slew rate of the power supply voltage, it is not assumed that the slew rate of the power supply voltage will change each time the power supply voltage is started.

Furthermore, in the power-on reset circuit of Patent Document 1, in order to reduce power consumption, a transistor connected in series with the voltage divider circuit and a downstream latch 120 are required to turn off the voltage detector 115, which includes a voltage divider circuit. This raises concerns that the generation of the POR signal may be delayed when the power supply voltage rises at a high rate.

This disclosure has been made to solve these problems, and the purpose of this disclosure is to provide a power-on reset circuit that reduces power consumption and can operate properly even if the voltage change rate at power-on of the power supply voltage changes.

According to one aspect of the present disclosure, a power-on reset circuit includes a power supply wiring that receives a power supply voltage, a reference voltage wiring that transmits a reference voltage, a voltage divider circuit, a voltage rate detection circuit, and a voltage evaluation circuit. The voltage divider circuit is connected between the power supply wiring and the reference voltage and outputs a divided voltage of the power supply voltage on the power supply wiring to a first node. The voltage rate detection circuit detects the voltage change rate of the power supply voltage when the power supply voltage is started up. The voltage evaluation circuit generates an output signal that indicates the comparison result between the voltage at the first node and a predetermined voltage. The voltage divider circuit is configured to variably set the impedance between the power supply wiring and the reference voltage while maintaining a constant division ratio of the divided voltage to the power supply voltage in accordance with the voltage change rate detected by the voltage rate detection circuit. This impedance is set to decrease as the voltage change rate increases.

According to the present disclosure, by appropriately changing the impedance of the voltage divider circuit in accordance with the rate of voltage change at power-on of the power supply voltage, it is possible to provide a power-on reset circuit that can reduce power consumption and operate appropriately even if the rate of voltage change at power-on of the power supply voltage changes.

FIG. 10 is a circuit diagram illustrating a configuration of a power-on reset circuit according to a comparative example. 10 is a conceptual operational waveform diagram of a power-on reset circuit when a power supply voltage is started up; 1 is a block diagram illustrating a configuration of a power-on reset circuit according to a first embodiment; FIG. 4 is a circuit diagram illustrating a configuration example of a voltage divider circuit in FIG. 3 . FIG. 4 is a circuit diagram illustrating a configuration example of a voltage determination circuit in FIG. 3 . FIG. 2 is an equivalent circuit diagram of the power-on reset circuit according to the first embodiment. FIG. 10 is a circuit diagram illustrating a configuration example of a voltage rate detection circuit according to a second embodiment. 8 is a conceptual waveform diagram illustrating the operation of the voltage rate detection circuit shown in FIG. 7. 8 is a diagram illustrating the operation of the voltage rate detection circuit shown in FIG. 7; FIG. 10 is a circuit diagram illustrating a configuration example of a voltage evaluation circuit according to a third embodiment. FIG. 10 is a circuit diagram illustrating a configuration example of a voltage rate detection circuit according to a third embodiment. 4 is a conceptual operational waveform diagram of the power-on reset circuit according to the first embodiment at the time of starting up the power supply voltage; FIG.

Embodiments of the present disclosure will be described in detail below with reference to the drawings. Note that, in the following, identical or equivalent parts in the drawings will be given the same reference numerals, and their descriptions will not be repeated in principle.

Embodiment 1.
Before describing the power-on reset circuit according to the first embodiment, a comparative example will be described.

(Explanation of Comparative Example)
FIG. 1 is a circuit diagram illustrating a configuration of a power-on reset circuit 5# according to a comparative example.

As shown in Figure 1, the power-on reset circuit 5# includes a voltage divider circuit 10# and a voltage judgment circuit 20#.

The voltage divider circuit 10# has resistive elements RH and RL connected in series between a power supply line PL that receives the power supply voltage AVDD and a reference voltage line NL that transmits a reference voltage VSS. Since the reference voltage VSS is typically ground (ground voltage), hereinafter the reference voltage VSS will be referred to as the ground voltage VSS, and the reference voltage line NL will also be referred to as the ground line NL.

The resistor element RH is connected between the power supply line PL and node N1, and the resistor element RL is connected between node N1 and ground line NL. Therefore, a divided voltage Vdiv of the power supply voltage AVDD by the resistor elements RH and RL is generated at node N1.

Hereinafter, in this specification, the electrical resistance value of each resistive element will also be represented by the same symbol. Therefore, the following equation (1) holds between the divided voltage Vdiv and the power supply voltage AVDD. That is, the voltage division ratio of voltage divider circuit 10# is Kv = RL/(RL + RH) (Kv < 1).

Vdiv=Kv・AVDD…(1)
Voltage evaluation circuit 20# has a transistor 21, a current supply circuit 22, and a signal generation circuit 25 formed of an inverter.

Transistor 21 is an N-type field-effect transistor connected between node N2 and ground wiring NL, and has its gate (control electrode) connected to node N1. Current supply circuit 22 has a resistive element RD connected between power supply wiring PL and node N2. Signal generation circuit 25 outputs an output signal VPOR having a logic level corresponding to the voltage Vdet of node N2. The output signal VPOR corresponds to a so-called power-on reset signal (POR signal).

1, where signal generating circuit 25 is composed of an inverter, when voltage Vdet drops to ground voltage VSS as transistor 21 turns on, output signal VPOR is set to a logic high level (hereinafter referred to as "H level"). On the other hand, while transistor 21 is off, node N2 is pulled up to power supply voltage AVDD, and output signal VPOR is set to a logic low level (hereinafter referred to as "L level"). With respect to the threshold voltage Vt1 of transistor 21, when Vdiv≦Vt1, transistor 21 is off, and when Vdiv>Vt1, transistor 21 is on.

Therefore, when a semiconductor device equipped with a power-on reset circuit starts up and the power supply voltage AVDD rises from the ground voltage VSS, the output signal VPOR is at the L level (ground voltage VSS) while Vdiv≦Vt1, and is at the H level (power supply voltage AVDD) while Vdiv>Vt1. As a result, based on the output signal VPOR, it is possible to determine whether the power supply voltage AVDD is higher than the threshold voltage Vpr, which corresponds to (Vt1/Kv). By adjusting the voltage divider ratio Kv so that the threshold voltage Vpr corresponds to the lower limit voltage at which the operation of the semiconductor device can be guaranteed, the output signal VPOR can be used as a POR signal that allows each circuit mounted on the semiconductor device to start operating.

Figure 2 shows a conceptual operating waveform diagram of the power-on reset circuit when the power supply voltage is started up.

Figure 2 shows waveforms 101 to 103 of the power supply voltage AVDD at startup. Waveforms 101 to 103 differ in the voltage change rate (dAVDD/dt) at startup. For example, when the power supply voltage AVDD is supplied from the output of a solar cell, the voltage change rate differs depending on the amount of light received by the solar cell. Therefore, there is a difference between waveforms 101 to 103 in the timing at which the power supply voltage AVDD reaches the rated value Vst.

Similarly, there are differences between waveforms 101 to 103 in the timing at which the power supply voltage AVDD reaches the above-mentioned judgment voltage Vpr. In waveform 101, the power supply voltage AVDD reaches the judgment voltage Vpr at time t1. In waveform 102, the power supply voltage AVDD reaches the judgment voltage Vpr at time t2, which is later than time t1. In waveform 103, the power supply voltage AVDD reaches the judgment voltage Vpr at time t3, which is later than time t2.

In power-on reset circuit 5#, when power supply voltage AVDD reaches determination voltage Vpr, divided voltage Vdiv reaches threshold voltage Vt1 of transistor 21. Ideally, as shown by the solid lines in Figure 2, transistor 21 turns on at each of times t1 to t3, causing output signal VPOR to change from L level (ground voltage VSS) to H level (power supply voltage AVDD).

However, as shown by the dotted line in Figure 1, node N1 has parasitic capacitance Cp, such as the gate capacitance of transistor 21. As a result, the on-timing of transistor 21 is delayed from times t1-t3 to times t1x-t3x due to the charging time of parasitic capacitance Cp. As a result, output signal VPOR actually changes from low to high at times t1x-t3x, which are later than times t1-t3, as shown by the dotted line.

In this case, it can be seen that for each of waveforms 101 to 103, the voltage error ΔVer between the power supply voltage AVDD and the judgment voltage Vpr when the output signal VPOR actually changes to the H level varies depending on the voltage change rate. Specifically, the greater the voltage change rate, the greater the voltage error ΔVer.

As a result, there is concern that a delay will occur in the start of operation of the semiconductor device in response to the output signal VPOR. In particular, in energy harvesting power supply applications, it is expected that the supply of the power supply voltage AVDD will be sporadic and short-lived. In such cases, there is concern that a delay in the start of operation will result in a degradation of the performance of the semiconductor device.

Here, the delay time from times t1-t3 to times t1x-t3x is determined mainly by an RC time constant that corresponds to the product of the R component of voltage-divider circuit 10# and parasitic capacitance Cp. Therefore, if the resistance value (RH+RL) of voltage-divider circuit 10# is reduced, the charging current of parasitic capacitance Cp increases, thereby shortening the delay time due to the RC time constant. In other words, the operating speed of power-on reset circuit 5# can be increased.

However, lowering the resistance value (RH+RL) increases the steady-state current that flows between the power supply line PL and the ground line NL in the voltage divider circuit 10#. The configuration in Figure 1 allows for high-speed generation of the output signal VPOR (POR signal) without using a transistor connected in series with the voltage divider circuit or a downstream latch circuit, as in Patent Document 1. However, the steady-state current flows steadily while the power supply voltage AVDD is being supplied. As a result, in the power-on reset circuit 5#, lowering the resistance value (RH+RL) in the voltage divider circuit 10# increases the operating speed but increases power consumption, whereas increasing the resistance value (RH+RL) decreases power consumption but decreases operating speed.

Furthermore, when transistor 21 is turned on, the speed at which voltage Vdet at node N2 changes to ground voltage VSS is affected by the magnitude of the current supplied by current supply circuit 22. In the example of FIG. 2, the lower the resistance value RD, the larger the supply current, allowing voltage Vdet to change to ground voltage VSS more quickly. As a result, the timing at which output signal VPOR changes to H level can be advanced, shortening the delay time from time t1 to t3 to time t1x to t3x. In other words, the operating speed of power-on reset circuit 5# can be increased.

On the other hand, transistor 21 remains on while output signal VPOR is at H level. Therefore, due to resistor element RD and transistor 21 (on), a steady current is generated between power supply line PL and ground line NL in voltage evaluation circuit 20# as well. As a result, in power-on reset circuit 5# of FIG. 1, lowering resistance value RD in voltage evaluation circuit 20# also increases operating speed but power consumption, while increasing resistance value RD decreases power consumption but operating speed.

(Power-on reset circuit according to the first embodiment)
FIG. 3 is a block diagram illustrating the configuration of the power-on reset circuit 5 according to this embodiment.

As shown in FIG. 3, the power-on reset circuit 5 includes a voltage divider circuit 10, a voltage evaluation circuit 20, and a voltage rate detection circuit 30, which are connected between the power supply wiring PL and the ground wiring NL. The voltage divider circuit 10 outputs a divided voltage Vdiv of the power supply voltage AVDD on the power supply wiring PL to a node N1. The voltage evaluation circuit 20 generates an output signal VPOR indicating the result of comparing the voltage at node N1 with a predetermined threshold voltage (e.g., the threshold voltage Vt1 of transistor 21). In other words, node N1 corresponds to the "first node."

The voltage rate detection circuit 30 detects the voltage change rate (i.e., dAVdd/dt) of the power supply wiring PL when the power supply voltage AVDD is started, for example, using a capacitor-based differentiation circuit. In the example of Figure 3, the voltage rate detection circuit 30 determines the voltage change rate VRT [V/s] in a predetermined N-stage (N: an integer of 2 or greater) and sets one of the selection signals SEL(0) to SEL(N-1) to the H level depending on the determination result.

Hereinafter, in this specification, when distinguishing between signals, circuit elements, etc. corresponding to each of the above N stages, the N signals, circuit elements, etc. will be represented by numbers in parentheses. On the other hand, when representing these N signals, circuit elements, etc. collectively, the numbers in parentheses will not be represented.

When the voltage change rate VRT is at the highest level of N stages, selection signal SEL(N-1) is set to H level, and the remaining SEL(0) to SEL(N-2) are set to L level. Conversely, when the voltage change rate VRT is at the lowest level of N stages, selection signal SEL(0) is set to H level, and the remaining SEL(1) to SEL(N-1) are set to L level. In this way, the smaller the voltage change rate VRT, the more likely it is that one of the lower-order bits (smaller i) of selection signal SEL(i) for integers i = 0 to (N-1) is set to H level. In other words, the larger the voltage change rate VRT, the more likely it is that one of the higher-order bits (larger i) of selection signal SEL(i) is set to H level. A preferred configuration example of the voltage rate detection circuit 30 will be described in detail in embodiment 2.

FIG. 4 shows a circuit diagram illustrating an example of the configuration of the voltage divider circuit 10 in FIG.
4, the voltage dividing circuit 10 includes N voltage dividing resistors connected in parallel between a power supply line PL and a ground line NL, and a selection circuit 15.

The N voltage-dividing resistors each include resistive elements RH(0) to RH(N-1) connected between the power supply line PL and node N1, and resistive elements RL(0) to RL(N-1) connected between node N1 and ground line NL. Figure 4 shows resistive elements RH(0) and RL(0) that constitute the voltage-dividing resistors on the lowest bit side, RH(N-1) and RL(N-1) that constitute the voltage-dividing resistors on the highest bit side, and RH(M) and RL(M) that constitute the voltage-dividing resistors on the middle bit side (0<M<(N-1)).

Among the N voltage dividing resistors, the voltage dividing ratio Kv, i.e., the ratio of the resistance values of resistor elements RH(0) to RH(N-1) to resistor elements RL(0) to RL(N-1), is equal. That is, RH(0):RL(0) = ... = RH(M):RL(M) = ... = RH(N-1):RL(N-1).

However, the sum of the resistance values of each of the resistor elements RH(0) to RH(N-1) and each of the resistor elements RL(0) to RL(N-1), i.e., the impedance between the power supply wiring PL and the ground wiring NL, varies among the N voltage-dividing resistors. Specifically, RH(0) + RL(0) >> RH(M) + RL(M) >> RH(N-1) + RL(N-1).

The selection circuit 15 has switch elements SWH(0) to SWH(N-1) and switch elements SWL(0) to SWL(N-1). Switch elements SWH(0) to SWH(N-1) are connected in series with resistor elements RH(0) to RH(N-1), respectively, between the power supply wiring PL and node N1. Similarly, switch elements SWL(0) to SWL(N-1) are connected in series with resistor elements RL(0) to RL(N-1), respectively, between the ground wiring NL and node N1.

Switch elements SWH(0) to SWH(N-1) and switch elements SWL(0) to SWL(N-1) are turned on and off in response to selection signals SEL(0) to SEL(N-1). Specifically, each of switch elements SWH(0) to SWH(N-1) and SWL(0) to SWL(N-1) is turned on when the corresponding selection signal SEL is at H level, and turned off when the corresponding selection signal SEL is at L level.

For example, when the selection signal SEL(0) is at H level, the switch elements SWH(0) and SWL(0) are turned on. At this time, the other selection signals SEL(1) to SEL(N-1) are at L level, so the other switch elements SWH(1) to SWH(N-1) and SWL(1) to SWL(N-1) are turned off.

As described above, the voltage rate detection circuit 30 sets one of the N selection signals SEL to H level and the remaining (N-1) selection signals SEL to L level in accordance with the voltage change rate of the power supply voltage AVDD. This turns on the switch elements SWH and SWL to which the selection signal SEL set to H level has been input.

As a result, in the voltage divider circuit 10, one of the N voltage divider resistors is selected according to the voltage rate detected by the voltage rate detection circuit 30 and connected between the power supply wiring PL and the ground wiring NL. Meanwhile, in the other (N-1) voltage divider resistors, the corresponding switch elements SWH and SWL are turned off, so no current flows between the power supply wiring PL and the ground wiring NL. Furthermore, until the voltage rate is detected by the voltage rate detection circuit 30, all switch elements SWH(0) to SWH(N-1) and SWL(0) to SWL(N-1) are in the off state.

In the example of Figure 4, the voltage rate detection circuit 30 sets the selection signal SEL (M) to an H level, turning on the switch elements SWH (M) and SWL (M), and the voltage dividing resistors formed by the resistance elements RH (M) and RL (M) are selectively connected between the power supply wiring PL and the ground wiring NL.

In Figure 4, each of the resistor elements RH(0) to RH(N-1) corresponds to an example of a "second resistor element," and each of the resistor elements RL(0) to RL(N-1) corresponds to an example of a "third resistor element." Also, as described above, node N1 corresponds to an example of a "first node."

FIG. 5 shows a circuit diagram illustrating an example of the configuration of the voltage determination circuit 20 in FIG.
5, voltage evaluation circuit 20 differs from voltage evaluation circuit 20# shown in FIG. 1 in that it has a current control circuit 27 instead of current supply circuit 22. Current control circuit 27 has resistance elements RD(0) to RD(N-1) and switch elements SWD(0) to SWD(N-1) connected in parallel between power supply line PL and node N2. Switch elements SWD(0) to SWD(N-1) are connected in series with resistance elements RD(0) to RD(N-1), respectively, between power supply line PL and node N2.

Switch elements SWD(0) to SWD(N-1) are turned on and off in response to selection signals SEL(0) to SEL(N-1). Specifically, each of switch elements SWD(0) to SWD(N-1) is turned on when the corresponding selection signal SEL is at H level, and turned off when it is at L level. Furthermore, switch elements SWD(0) to SWD(N-1) are all in the off state until the voltage rate is detected by voltage rate detection circuit 30.

In the example of Figure 5, the voltage rate detection circuit 30 sets the selection signal SEL (M) to an H level, turning on the switch element SWD (M) and selectively connecting the resistor element RD (M) between the power supply wiring PL and node N2.

The resistance values of the resistor elements RD(0) to RD(N-1) are different. Specifically, the resistance values are set so that the lower-order bits have larger resistance values, i.e., RD(0) > RD(1) > ... RD(M) ... > RD(N-1). The rest of the configuration of the voltage evaluation circuit 20 is the same as that of the voltage evaluation circuit 20# shown in Figure 1.

In the voltage determination circuit 20, when the switch element SWD is turned on by inputting a selection signal SEL set to H level, one of N resistor elements RD(0) to RD(N-1) with different resistance values is selected according to the voltage rate detected by the voltage rate detection circuit 30 and connected between the power supply wiring PL and node N2.

Therefore, the higher the voltage change rate detected by the voltage rate detection circuit 30, the lower the resistance value of the resistor element RD connected between the power supply line PL and node N2 when the selection signal SEL on the upper bit side is set to the H level. In other words, the supply current Idet from the current control circuit 27 to node N2 increases. This increases the rate of change of the voltage at node N2 when transistor 21 is turned on.

On the other hand, the smaller the voltage change rate detected by the voltage rate detection circuit 30, the higher the resistance value of the resistor element RD connected between the power supply line PL and node N2, as the lower-order bit selection signal SEL is set to the H level. This reduces the steady-state current generated between the power supply line PL and the ground line NL while transistor 21 is on.

In this way, in the voltage evaluation circuit 20, the current control circuit 27 can variably control the supply current Idet so that the supply current Idet increases as the voltage change rate increases. In FIG. 5, the resistance elements RD(0) to RD(N-1) correspond to an example of "plurality of first resistance elements," and the node N2 corresponds to an example of "second node." Furthermore, the switch elements SWD(0) to SWD(N-1) correspond to an example of "plurality of switch elements," and the transistor 21 corresponds to an example of "first transistor."

FIG. 6 is an equivalent circuit diagram of the power-on reset circuit 5 according to the first embodiment.
6, the selection signal SEL(M) is set to the H level in accordance with the voltage change rate detected by the voltage rate detection circuit 30. As a result, in the voltage divider circuit 10, the voltage dividing resistor formed by the resistance elements RH(M) and RL(M) is connected between the power supply wiring PL and the ground wiring NL.

As a result, in the voltage divider circuit 10, according to the voltage change rate detected by the voltage rate detection circuit 30, the voltage division ratio Kv is constant, while the voltage division resistors (RH and RL) are selected so that the impedance (resistance value) between the power supply wiring PL and the ground wiring NL becomes lower as the voltage change rate increases, and conversely, becomes higher as the voltage change rate decreases.

Therefore, according to the power-on reset circuit 5 of the first embodiment, when the voltage change rate is high, the impedance between the power supply wiring PL and the ground wiring NL can be reduced by the voltage divider circuit 10. This reduces the delay time until the transistor 21 turns on when the power supply voltage AVDD reaches the determination voltage Vpr (Vdiv>Vt1), thereby increasing the operating speed. On the other hand, when the voltage change rate is low , the impedance between the power supply wiring PL and the ground wiring NL by the voltage divider circuit 10 is increased, thereby suppressing the current steadily generated between the power supply wiring PL and the ground wiring NL and achieving low power consumption.

Furthermore, in the voltage evaluation circuit 20, a resistive element RD(M) is connected between the power supply line PL and node N2, and a supply current Idet according to the resistance value RD(M) is applied to node N2. Therefore, in the voltage evaluation circuit 20, the resistive element RD is selected according to the voltage change rate detected by the voltage rate detection circuit 30 so that the supply current Idet increases as the voltage change rate increases, and conversely, the supply current Idet decreases as the voltage change rate decreases.

As a result, in the power-on reset circuit 5 according to embodiment 1, when the voltage change rate is high, the supply current Idet from the current control circuit 27 is increased, thereby shortening the time required for the output signal VPOR to change from L level to H level when the transistor 21 is turned on, thereby further increasing the operating speed. On the other hand, when the voltage change rate is high, the supply current Idet from the current control circuit 27 is decreased, thereby suppressing the current steadily generated between the power supply wiring PL and the ground wiring NL while the transistor 21 is on, thereby achieving low power consumption.

Figure 12 shows a conceptual operating waveform diagram of the power-on reset circuit of embodiment 1 at the time of power-on of the power supply voltage, which is compared with Figure 2. In Figure 12, the waveforms 101 to 103 at the time of power-on of the power supply voltage AVDD are the same as those in Figure 2.

Even in the power-on reset circuit 5 of embodiment 1, due to the time required for voltage rate detection by the voltage rate detection circuit 30 and the charging time of node N1 (parasitic capacitance Cp), the timing at which the output signal VPOR changes from L level to H level for each of waveforms 101 to 103 is between times t1y and t3y, which is later than times t1 and t3.

In Figure 12, the time delay (e.g., time t1 to t1y) when the voltage change rate is large is shortened compared to the comparative example in Figure 2 by mainly changing the impedance of the voltage divider circuit 10 and further changing the supply current Idet by the current control circuit 27 according to the voltage change rate.

Furthermore, when the voltage change rate is small, the time delay becomes large (for example, from time t3 to t3y), but as a result, it can be understood from a comparison with Figure 2 that the voltage error ΔVer between the power supply voltage AVDD and the judgment voltage Vpr when the output signal VPOR actually changes to the H level can be equalized even if the voltage change rate is different.

As such, the power-on reset circuit according to embodiment 1 can generate a POR signal at the appropriate timing without increasing power consumption, even if the voltage change rate of the power supply voltage changes during startup. Furthermore, because it does not include a transistor connected in series with a voltage-dividing resistor or a downstream latch circuit, as in Patent Document 1, it can generate a POR signal at high speed. Furthermore, as shown in FIG. 12, even if the voltage change rate changes, the level of the power supply voltage AVDD when the output signal VPOR actually changes to the H level remains the same, thereby stabilizing startup operation of a semiconductor device incorporating the power-on reset circuit.

Embodiment 2.
In the second embodiment, a preferred configuration example of a voltage rate detection circuit will be described.

FIG. 7 is a circuit diagram illustrating an example of the configuration of a voltage rate detection circuit according to the second embodiment.
Referring to FIG. 7, the voltage rate detection circuit 30 includes N rate detection units RDUT(0) to RDUT(N−1) and a control logic 35.

The rate detection units RDUT(0) to RDUT(N-1) output rate detection signals SRDET(0) to SRDET(N-1), respectively, based on the voltage change rate of the power supply voltage AVDD. The control logic 35 generates the selection signals SEL(0) to SEL(N-1) in Figure 1 in accordance with the rate detection signals SRDET(0) to SRDET(N-1).

Note that Figure 7 shows rate detection units RDUT(0), RDUT(M), and RDUT(N-1) as examples, but each has the same circuit configuration, with only some of the circuit constants differing, as described below. Below, the configuration of the Mth rate detection unit RDUT(M) will be described as a representative example.

The rate detection unit RDUT(M) includes a detection capacitor CDET(M), a charging capacitor CREF(M), transistors MND1(M), MND2(M), a current supply circuit 36(M), and an inverter INVD(M).

The detection capacitor CDET(M) is connected between the power supply line PL and node N3(M), and the transistor MND1(M) is connected between node N3(M) and the ground line NL. The transistor MND2(M) is connected between node N4(M) and the ground line NL. The gates of the transistors MND1(M) and MND2(M) are connected to the node N3(M), and the charging capacitor CREF(M) is connected between node N3(M) and the ground line NL. In other words, the transistor MND1(M) is diode-connected.

The charging capacitor CREF(M) includes at least the gate capacitance (parasitic capacitance) of transistor MND2(M), and may also be configured by additionally connecting a parallel plate capacitor, a MOS (Metal Oxide Semiconductor) capacitor, etc. In the following description, the capacitance values of each capacitor will be denoted by the same symbol.

The current supply circuit 36(M) is connected between the power supply wiring PL and node N4(M) and supplies current to node N4(M). In the example of FIG. 7, the current supply circuit 36(M) has a resistive element RDET(M) connected between the power supply wiring PL and node N4(M). That is, the supply current Ird(M) by the current supply circuit 36(M) is adjusted by the resistance value of the resistive element RDET(M); the lower the RDET(M), the larger the supply current Ird(M).

Inverter INVD(M) outputs a rate detection signal SRDET(M) whose logic level corresponds to the voltage of node N4(M). The voltage of node N4(M) is the power supply voltage AVDD while transistor MND2(M) is off, and changes to ground voltage VSS at a speed corresponding to the supply current Ird(M) when transistor MND2(M) is on. Therefore, while the rate detection signal SRDET(M) is at L level (ground voltage VSS) when transistor MND2(M) is off, it changes from L level to H level when transistor MND2(M) is on.

Next, we will explain the operation of the rate detection unit RDUT(M) in response to the input of the power supply voltage AVDD.

When a change occurs in the voltage Vc applied to a capacitor with a capacitance value C, a current Ic = C dVc/dt is generated in the capacitor. Therefore, for a voltage change rate VRT [V/s] (VRT = dAVDD/dt), which is the time rate of change of the power supply voltage AVDD applied to the detection capacitor CDET(M), a detection current Ic(M) is generated in the detection capacitor CDET(M) according to the following equation (2). As can be seen from equation (2), the larger the detection capacitor CDET(M) is, the larger the detection current Ic(M) is, and the larger the voltage change rate VRT is.

Ic(M)=CDET(M)・VRT…(2)
When the power supply voltage AVDD is turned on, the charging capacitor CREF(M) at the node N3(M) is charged by the detection current Ic(M) that is generated in response to changes in the power supply voltage AVDD. When the voltage at the node N3(M) becomes higher than the threshold voltage Vt2 of the transistor MND2(M) as a result of charging, the transistor MND2(M) turns on, and the rate detection signal SRDET(M) changes from the L level to the H level. This generates the rate detection signal SRDET(M).

The capacitance ratio Kc of the detection capacitors CDET(0) to CDET(N-1) relative to the charging capacitors CREF(0) to CREF(N-1) differs among the rate detection units RDUT(0) to RDUT(N-1). In Figure 7, CDET(0)/CREF(0) > ... > CDET(M)/CREF(M) > ... > CDET(N-1)/CREF(N-1), and the rate detection unit RDUT with the lower bit is designed to have a larger capacitance ratio Kc. All element constants other than the capacitance ratio Kc are set in common among the rate detection units RDUT(0) to RDUT(N-1). In other words, the threshold voltage Vt2 is also common among the transistors MND2(0) to MND2(N-1).

Below, we will explain an example in which, to achieve the above capacitance ratio Kc, the capacitance values of the charging capacitors CREF(0) to CREF(N-1) are common among the rate detection units RDUT(0) to RDUT(N-1), while the capacitance values of the detection capacitors CDET(0) to CDET(N-1) are designed to gradually increase in order for the rate detection unit RDUT to be on the lower-order bit side. That is, CDET(0) > ... > CDET(M) > ... > CDET(N-1). For example, the capacitance values of the detection capacitors CDET(0) to CDET(N-1) can be set gradually so that the capacitance value decreases by a factor of 2 in increments of 1/2.

In the configuration example of Figure 7, transistor MND2 of each rate detection unit RDUT corresponds to an embodiment of a "second transistor," node N3 corresponds to an embodiment of a "third node," and node N4 corresponds to an embodiment of a "fourth node." Furthermore, transistor MND2, current supply circuit 36, and inverter INVD can constitute an embodiment of a "rate determination circuit" for generating the rate detection signal SRDET.

Figure 8 is a conceptual waveform diagram explaining the operation of the voltage rate detection circuit. The vertical axis of Figure 8 shows the voltage VN3 at node N3.

Referring to Figure 8, when the power supply voltage AVDD is turned on at time t0, the detection currents Ic(0) to Ic(N-1) generated in each of the rate detection units RDUT(0) to RDUT(N-1) are proportional to the capacitance values of the detection capacitors CDET(0) to CDET(N-1).

In the example of Figure 8, in a certain rate detection unit RDUT, at time ta, when T0 has elapsed since time t0, the voltage VN3 at node N3 reaches the threshold voltage Vt2 of transistors MND2(0) to MND2(N-1). In this case, in a rate detection unit RDUT in which the capacitance value of the detection capacitor CDET is k times (k: real number) that of the rate detection unit RDUT, voltage VN3 reaches the threshold voltage Vt2 at time tb, when (T0/k) has elapsed since time t0, earlier than time ta. Conversely, in a rate detection unit RDUT in which the capacitance value of the detection capacitor CDET is (1/k) times that of the rate detection unit RDUT, voltage VN3 reaches the threshold voltage Vt2 at time tc, when (k·T0) has elapsed since time t0, later than time ta.

Therefore, when the minimum and maximum rate values of the detection range of the voltage change rate of the power supply voltage AVDD are predetermined, the capacitance value (or capacitance ratio Kc) of the detection capacitor CDET is set so that when the power supply voltage AVDD of the minimum rate value is applied to the rate detection unit RDUT (0) in which the capacitance value (i.e., capacitance ratio Kc) of the detection capacitor CDET is maximum, the voltage of node N3 rises to the threshold voltage Vt2 within a predetermined reference time.

Conversely, in the rate detection unit RDUT (N-1) in which the capacitance value (i.e., capacitance ratio Kc) of the detection capacitor CDET is the smallest, the capacitance value (or capacitance ratio Kc) of the detection capacitor CDET is set so that when the power supply voltage AVDD of the above-mentioned maximum rate value is applied, the voltage of node N3 rises to the threshold voltage Vt2 within the same reference time.

Furthermore, for the intermediate rate detection units RDUT(1) to RDUT(N-2), the capacitance value (or capacitance ratio Kc) of the detection capacitor CDET is set in stages so that the value becomes smaller toward the more significant bits within the range between the rate detection units RDUT(0) and RDUT(N-1). As a result, the rate detection signals SRDET(0) to SRDET(N-1) from the rate detection units RDUT(0) to RDUT(N-1) are generated as shown in Figure 9.

FIG. 9 shows a diagram illustrating the operation of the voltage rate detection circuit shown in FIG.
9 , when a power supply voltage AVDD having a minimum rate value R1 is input to the rate detection units RDUT(0) to RDUT(N-1), at the point in time when the reference time has elapsed since the activation of the power supply voltage AVDD was detected based on the voltage of the power supply wiring PL, the transistor MND2(0) is turned on only in the rate detection unit RDUT(0) whose detection capacitor CDET has the largest capacitance value (i.e., capacitance ratio Kc). Meanwhile, in the other rate detection units RDUT(1) to RDUT(N-1), the transistors MND2(1) to MND2(N-1) remain off. As a result, at the time when the reference time has elapsed, the rate detection signal SRDET(0) is at an H level, while the rate detection signals SRDET(1) to SRDET(N-1) are at an L level. That is, the rate detection signal SRDET is generated only in the rate detection unit RDUT(0).

When a power supply voltage AVDD with a voltage change rate VRT at a rate value RM between the minimum rate value R1 and the maximum rate value RN is input to the rate detection units RDUT(0) to RDUT(N-1), transistors MND2(0) to MN2D(M) turn on in the rate detection units RDUT(0) to RDUT(M) after the reference time has elapsed. Meanwhile, in the rate detection units RDUT(M+1) to RDUT(N-1), which are located on the higher-order bit side and have a smaller capacitance value (i.e., capacitance ratio Kc) of the detection capacitor CDET than the rate detection unit RDUT(M), transistors MND2(M+1) to MND2(N-1) remain off. As a result, when the reference time has elapsed, the rate detection signals SRDET(0) to SRDET(M) are at H level, while the rate detection signals SRDET(M+1) to SRDET(N-1) are at L level. That is, the rate detection signal SRDET is generated in the (M+1) rate detection units RDUT(0) to RDUT(M).

In this way, the greater the voltage change rate of the power supply voltage AVDD is than the minimum rate value R1, the more the number of rate detection units RDUT that generate the rate detection signal SRDET by turning on transistor MND2 increases from the lower bit side when the above-mentioned reference time has elapsed.

When a power supply voltage AVDD having a maximum rate value RN is input to the rate detection units RDUT(0) to RDUT(N-1), after the reference time has elapsed, the transistor MND2(N-1) also turns on in the rate detection unit RDUT(N-1) whose detection capacitor CDET has the smallest capacitance value (i.e., capacitance ratio Kc). Therefore, after the reference time has elapsed, all of the rate detection signals SRDET(0) to SRDET(N-1) become H level. The rate detection signal SRDET is generated in the N rate detection units RDUT(0) to RDUT(N-1).

The control logic 35 sets only one of the selection signals SEL(0) to SEL(N-1) to the H level and sets the other (N-1) to the L level in accordance with the rate detection signals SRDET(0) to SRDET(N-1) generated as described above.

Specifically, the control logic 35 can be configured to set only one bit of the selection signal SEL to the H level in correspondence with the most significant bit of the rate detection signals SRDET(0) to SRDET(N-1) that is set to the H level. Furthermore, when all of the rate detection signals SRDET(0) to SRDET(N-1) are at the L level, the selection signal SEL(0) is set to the H level.

By inputting the selection signals SEL(0) to SEL(N-1) generated in this manner to the voltage divider circuit 10 and voltage judgment circuit 20 described in embodiment 1, the power-on reset circuit 5 can operate according to the equivalent circuit diagram shown in Figure 6.

The voltage rate detection circuit 30 described in embodiment 2 has a simple configuration and can quickly detect the voltage change rate in multiple stages (N stages) when the power supply voltage AVDD is started up.

It is also possible to set the supply currents Ird(0) to Ird(N-1) of the current supply circuits 36(0) to 36(N-1) to different values among the rate detection units RDUT(0) to RDUT(N-1) shown in Figure 7. Specifically, since the rate detection units RDUT on the higher bit side are arranged to detect relatively large voltage change rates, it is preferable to set Ird(0) < ... < Ird(M) < ... < Ird(N-1) so that the supply current Ird increases toward the higher bit side.

In the example of Fig. 7, the resistance values of the resistor elements RD ET are set as follows: RD ET (0)>...>RD ET (M)>...>RD ET (N-1), thereby enabling the setting of the supply currents Ird(0) to Ird(N-1). In Fig. 7, each of the resistor elements RD ET (0) to RD ET (N-1) corresponds to an example of a "fourth resistor element."

7 and 5, regarding the threshold voltage Vt1 of transistor 21 of voltage evaluation circuit 20 and the threshold voltage Vt2 of transistor MND2 of each rate detection unit RDUT, it is preferable to set the threshold voltage Vt1 (transistor 21) higher than the threshold voltage Vt2 (transistor MND2) (Vt1 > Vt2). That is, it is preferable that the voltage of node N1 when transistor 21 turns on be higher than the voltage of node N3 when transistor MND2 turns on. This prevents the power-on reset circuit 5 from erroneously generating a POR signal (i.e., the output signal VPOR erroneously changes from low to high), thereby ensuring reliable operation.

Embodiment 3.
In the third embodiment, a modified example of the configuration of the voltage evaluation circuit and the voltage rate detection circuit exemplified in the first and second embodiments will be described.

FIG. 10 is a circuit diagram illustrating an example of the configuration of a voltage evaluation circuit according to the third embodiment.
10, a voltage evaluation circuit 20X according to the third embodiment differs from voltage evaluation circuit 20 shown in FIG. 5 in that current control circuit 27 is replaced with a current control circuit 27X.

Current control circuit 27X differs from current control circuit 27 in that it has current source circuits CSD(0) to CSD(N-1) configured to include transistors instead of resistor elements RD(0) to RD(N-1). The rest of the configuration of current control circuit 27X is the same as that of current control circuit 27. That is, current control circuit 27X has current source circuits CSD(0) to CSD(N-1) connected in parallel between power supply wiring PL and node N2, and switch elements SWD(0) to SWD(N-1). Switch elements SWD(0) to SWD(N-1) are then connected in series with each of current source circuits CSD(0) to CSD(N-1) between power supply wiring PL and node N2.

The output currents Id(0) to Id(N-1) of the current source circuits CSD(0) to CSD(N-1) are different. Specifically, they are set so that the output current is larger on the higher-order bit side, such that Id(0) < Id(1) < ... Id(M) ... < Id(N-1). The switch elements SWD(0) to SWD(N-1) are turned on and off in accordance with the selection signals SEL(0) to SEL(N-1) in the same manner as described in embodiment 1. Therefore, the greater the voltage change rate detected by the voltage rate detection circuit 30, the greater the output current of the current source circuit CSD that is connected by the switch element SWD between the power supply wiring PL and node N2.

As a result, similar to embodiment 1, the greater the voltage change rate detected by the voltage rate detection circuit 30, the greater the supply current Idet from the current control circuit 27X to node N2. This increases the rate of change of the voltage at node N2 when transistor 21 is turned on.

Therefore, even when the voltage evaluation circuit 20X shown in Figure 10 is used, a power-on reset circuit 5 similar to that described in embodiment 1 can be realized. In Figure 10, each of the current source circuits CSD(0) to CSD(N-1) corresponds to an example of a "first current source circuit."

FIG. 11 is a circuit diagram illustrating a configuration example of a voltage rate detection circuit according to the third embodiment.
11, the voltage rate detection circuit 30X according to the third embodiment differs from the voltage rate detection circuit 30 shown in FIG. 7 in that the rate detection units RDUT(0) to RDUT(N-1) have current supply circuits 36X(0) to 36X(N-1) instead of the current supply circuits 36(0) to 36(N-1).

Current supply circuits 36X(0) to 36X(N-1) differ in that they have current source circuits CSDT(0) to CSDT(N-1) configured to include transistors (not shown) instead of resistor elements RD(0) to RD(N-1). The rest of the configuration of voltage rate detection circuit 30X is the same as that of voltage rate detection circuit 30.

As explained at the end of the second embodiment, it is preferable that the supply currents Ird(0) to Ird(N-1) of the current supply circuits 36(0) to 36(N-1) be Ird(0) < ... < Ird(M) < ... < to Ird(N-1) so that the supply current Ird increases toward the rate detection unit RDUT on the more significant bit side. In the configuration of FIG. 11, the output currents of the current source circuits CSDT(0) to CSDT(N-1) are designed so that the output currents of the rate detection units RDUT on the more significant bit side are larger, thereby enabling such settings of the supply currents Ird(0) to Ird(N-1). In FIG. 11, each of the current source circuits CSDT(0) to CSDT(N-1) corresponds to an example of a "second current source circuit." In the configuration example of FIG. 11, the transistor MND2, the current supply circuit 36X, and the inverter INVD constitute one embodiment of a "rate determination circuit" for generating the rate detection signal SRDET.

The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present disclosure is indicated by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

5, 5# Power-on reset circuit, 10, 10# Voltage divider circuit, 15 Selection circuit, 20, 20X, 20# Voltage judgment circuit, 21, MND1(0) to MND1(N-1), MND2(0) to MND2(N-1) Transistors, 22, 36, 36X Current supply circuit, 25 Signal generation circuit, 27, 27X Current control circuit, 30, 30X Voltage rate detection circuit, 35 Control logic, AVDD Power supply voltage, CDET(0) to CDET(N-1) Detection capacitor, CREF(0) to CREF(N-1) Charging capacitor, CSD(0) to CSD(N-1), CSDT(0) to CSDT(N-1) Current source circuit, INVD(0) to INVD(N-1) Inverter, Ic(0) to Ic(N-1) Detection current, Id(0) to ID(N-1) Output current (current source circuit), Idet(0) to Idet(N-1), Ird(0) to Ird(N-1) Supply current, N1 to N4 Node, NL Reference voltage wiring (ground wiring), PL Power supply wiring, RD(0) to RD(N-1), RDET(0) to RDET(N-1), RH(0) to RH(N-1), RL(0) to RL(N-1) Resistive element, RDUT(0) to RDUT(N-1) Rate detection unit, SEL(0) to SEL(N-1) Selection signal, SRDET(0) to SRDET(N-1) Rate detection signal, SWD(0) to SWD(N-1), SWH(0) to SWH(N-1), SWL(0) to SWL(N-1) switch elements, VPOR output signal, VRT voltage change rate, VSS reference voltage (ground voltage), Vdiv divided voltage, Vt1, Vt2 threshold voltage, Vpr determination voltage.

Claims (11)

a power supply wiring for receiving a power supply voltage;
a reference voltage wiring for transmitting a reference voltage;
a voltage divider circuit connected between the power supply wiring and the reference voltage, which divides the power supply voltage and outputs a divided voltage to a first node;
a voltage rate detection circuit for detecting a voltage change rate of the power supply voltage at the time of starting the power supply voltage;
a voltage determination circuit that generates an output signal indicating a comparison result between the voltage of the first node and a predetermined voltage;
the voltage divider circuit is configured to variably set an impedance between the power supply wiring and the reference voltage while maintaining a constant voltage division ratio of the divided voltage to the power supply voltage in accordance with the voltage change rate detected by the voltage rate detection circuit;
The power-on reset circuit is configured such that the impedance decreases as the voltage change rate increases. The voltage determination circuit
a current control circuit connected between the power supply wiring and a second node, the current control circuit variably controlling a supply current from the power supply wiring to the second node in accordance with the voltage change rate detected by the voltage rate detection circuit;
a first transistor connected between the second node and the reference voltage wiring and turned on and off in response to a voltage of the first node;
the output signal is generated to have a logic level corresponding to the voltage of the second node which changes with the on/off of the first transistor;
2. The power-on reset circuit according to claim 1, wherein said current control circuit controls said supply current so that said supply current increases as said voltage change rate increases. The current control circuit
a plurality of first resistor elements connected in parallel between the power supply wiring and the second node;
a plurality of switch elements connected in series with the plurality of first resistor elements, respectively, between the power supply wiring and the second node;
3. The power-on reset circuit according to claim 2, wherein the on/off of the plurality of switch elements is controlled in accordance with the voltage change rate detected by the voltage rate detection circuit so that the greater the voltage change rate, the smaller the electrical resistance value between the power supply wiring and the second node. the current control circuit includes a plurality of first current source circuits each including a transistor, which are connected in parallel between the power supply wiring and the second node;
a plurality of switch elements connected in series with the plurality of first current source circuits between the power supply wiring and the second node;
3. The power-on reset circuit according to claim 2, wherein the on/off of the plurality of switch elements is controlled in accordance with the voltage change rate detected by the voltage rate detection circuit, so that the supply current from the plurality of first current source circuits increases as the voltage change rate increases. The voltage divider circuit
A plurality of voltage dividing resistors;
a selection circuit for selectively connecting the plurality of voltage dividing resistors between the power supply wiring and the reference voltage wiring in accordance with the voltage change rate detected by the voltage rate detection circuit;
Each of the plurality of voltage dividing resistors is
a second resistor element connected between the power supply wiring and the first node;
a third resistor element connected between the reference voltage wiring and the first node,
a ratio of the electrical resistance values of the second resistance element and the third resistance element is common among the plurality of voltage dividing resistors, while a sum of the electrical resistance values of the second resistance element and the third resistance element differs among the plurality of voltage dividing resistors;
5. The power-on reset circuit according to claim 1, wherein the selection circuit is controlled so that the electrical resistance value between the power supply wiring and the reference voltage wiring decreases as the voltage change rate increases. The voltage rate detection circuit includes N rate detection units;
N is an integer of 2 or more,
Each of the N rate detection units
a detection capacitor connected between the power supply wiring and a third node;
a rate determination circuit that generates a rate detection signal in response to the voltage at the third node increasing above a predetermined voltage;
The ratio of the capacitance value of the detection capacitor to the capacitance value of the third node is different among the N rate detection units,
the voltage rate detection circuit detects the voltage change rate in N stages based on the number of rate detection units that generate the rate detection signal among the N rate detection units at a time point when a predetermined reference time has elapsed since the start of the power supply voltage;
2. The power-on reset circuit according to claim 1 , wherein the detected rate of change in voltage increases as the number of the voltages increases. The rate determination circuit
a current supply circuit connected between the power supply wiring and a fourth node, the current supply circuit supplying a current from the power supply wiring to the fourth node;
a second transistor connected between the fourth node and the reference voltage wiring and turned on and off in response to the voltage of the third node;
the rate detection signal is generated when the voltage of the fourth node changes as the second transistor is turned on;
the current supplied by the current supply circuit differs among the N rate detection units;
7. The power-on reset circuit according to claim 6, wherein the supply current is set to be larger for a rate detection unit having a smaller capacitance value of the detection capacitor. The voltage determination circuit
a current control circuit connected between the power supply wiring and a second node, the current control circuit controlling a supply current from the power supply wiring to the second node;
a first transistor connected between the second node and the reference voltage wiring and turned on and off in response to a voltage of the first node;
the output signal is generated to have a logic level corresponding to the voltage of the second node which changes with the on/off of the first transistor;
The voltage rate detection circuit includes N rate detection units;
N is an integer of 2 or more,
Each of the N rate detection units
a detection capacitor connected between the power supply wiring and a third node;
a current supply circuit connected between the power supply wiring and a fourth node, the current supply circuit supplying a current from the power supply wiring to the fourth node;
a second transistor connected between the fourth node and the reference voltage wiring and turned on and off in response to the voltage of the third node;
generating a rate detection signal when the voltage of the fourth node changes as the second transistor is turned on;
The ratio of the capacitance value of the detection capacitor to the capacitance value of the third node is different among the N rate detection units,
the voltage rate detection circuit detects the voltage change rate in N stages based on the number of rate detection units that generate the rate detection signal among the N rate detection units at a time point when a predetermined reference time has elapsed since the start of the power supply voltage;
2. The power-on reset circuit according to claim 1, wherein the voltage at said first node when said first transistor is turned on is higher than the voltage at said third node when said second transistor is turned on. The current supply circuit includes:
a fourth resistor element connected between the power supply wiring and the fourth node, the fourth resistor element having a different electrical resistance value among the N rate detection units;
9. The power-on reset circuit according to claim 7, wherein the electric resistance value is set smaller for a rate detection unit having a smaller capacitance value of the detection capacitor. The current supply circuit includes:
a second current source circuit connected between the power supply wiring and the fourth node, the second current source circuit having different output currents among the N rate detection units;
9. The power-on reset circuit according to claim 7, wherein the rate detection unit has a smaller capacitance value of the detection capacitor, and the output current of the second current source circuit is larger. 9. The power-on reset circuit according to claim 7, wherein the capacitance value of the third node is common among the N rate detection units, but the capacitance values of the detection capacitors are different from one another.