JP7765201B2 - gaming machines - Google Patents

Description

The present invention relates to a gaming machine that performs a lottery process based on gaming actions and produces image effects corresponding to the lottery results, and in particular to a gaming machine that can stably produce impressive bonus effects and image effects.

Pinball gaming machines, such as pachinko machines, are comprised of a symbol start opening on the gaming board, a symbol display section that displays a series of symbol changes based on multiple displayed symbols, and a jackpot opening with an opening/closing plate. When a detection switch installed in the symbol start opening detects the passage of a gaming ball, a winning state is reached. After the gaming ball is paid out as a prize ball, the displayed symbols on the symbol display section change for a predetermined period of time. If the symbols then stop in a predetermined pattern, such as 7-7-7, a jackpot state is reached, and the jackpot opening is repeatedly opened, creating a gaming state advantageous to the player.

Whether or not this type of game state occurs is determined by a jackpot lottery, which is held when a game ball enters the symbol start slot, and the symbol change action described above is based on the results of this lottery. For example, if the lottery results in a winning state, a presentation action known as a reach action is executed for around 20 seconds, after which special symbols are aligned. On the other hand, a similar reach action may also be executed in a losing state, in which case the player will closely watch the progress of the presentation action while strongly hoping for a jackpot state. Then, if the specified symbols are aligned on the stop line at the end of the symbol change action, the player is guaranteed a jackpot state.

The pattern change operation is usually performed on the liquid crystal display unit (Patent Documents 1 to 4), and the H x V dot pixels that make up the liquid crystal display unit are driven in synchronization with the operating clock CK (= dot clock DCK) to update the display. In order to smoothly execute the display update operation (frame update), certain conditions, such as those shown in Figure 42 (g), are required for the pulse widths of the horizontal synchronization signal HS and vertical synchronization signal VS, and the timing between each synchronization signal HS, Vs and the transmission timing of the image signal.

Under the driving conditions shown, the pulse width PWh of the horizontal synchronization signal HS is 96 clock cycles CK, and the front porch FPh and back port BPh required before and after the horizontal synchronization signal PWh are specified as 16 and 48 clock cycles CK, respectively. Meanwhile, the pulse width PWv of the vertical synchronization signal VS is 2 lines, and the front porch FPv and back port BPv required before and after the vertical synchronization signal VS are specified as 19 and 33 lines, respectively.

The external control device that controls the LCD display unit repeatedly supplies the LCD display unit with a horizontal synchronization signal HS that satisfies the above horizontal conditions (PWh, FPh, BPh) and a horizontal synchronization signal HS that satisfies the above vertical conditions (PWvh, FPvh, BPvh), as well as an image signal corresponding to the number of pixels on the display screen.

In addition to the pattern changing action using the LCD display, a preview effect may also be performed in which a movable object called a "gimmick" moves appropriately to uncertainly predict the lottery result. Even after a jackpot state has been reached, a bonus effect may also be performed to effectively excite the player.

The props are usually driven and controlled by a stepping motor, but bipolar drive motors are often used because of the ease of motor control (Patent Documents 5 and 6). Vibration effects in which props such as sword sheaths vibrate up and down are also known (Patent Document 7).

Japanese Patent Application Laid-Open No. 2017-093633 Japanese Patent Application Laid-Open No. 2017-093632 JP 2016-159030 A Japanese Patent Application Laid-Open No. 2016-159029 JP 2016-007258 A Japanese Patent Application Laid-Open No. 2018-153304 Japanese Patent Application Laid-Open No. 2018-192168

However, in this type of gaming machine, there is a strong demand for more complex and varied effects, especially for image effects using liquid crystal displays. There is also a demand for more varied bonus effects.
Here, to achieve the vibration effect of vibrating the device, a cam member is inserted to convert the rotational motion of the DC motor into linear motion (Patent Document 7), but there is also the problem that the DC motor may overheat depending on the player's operation. In other words, while DC motors generally increase their motor current in response to an increase in torque, if a player grips the vibration device too tightly, the motor current increases in response to the increase in torque, and in the worst case scenario, there is a risk that the motor coil windings may burn out.

The present invention was made in consideration of the above-mentioned issues, and aims to provide a gaming machine with further improved performance, including special effects.

In order to achieve the above-mentioned object, the present invention provides an amusement machine equipped with a driver that drives a DC motor (excluding a stepping motor) to rotate based on a motor control signal received from the outside, and a device that moves in response to the rotation of the DC motor, wherein the driver is configured to continuously execute constant current control for the coil current of the DC motor, repeating an increase control toward an upper limit value specified by the motor control signal and a decrease control toward a decrease value (>0) lower than the upper limit value , when in a driving operation state in which the DC motor should be rotated continuously in the same direction, without interruption .

The present invention described above allows for a wide variety of bonus effects and more sophisticated performance without any problems. In other words, the drive current of the DC motor is controlled at a constant current, so even if a player strongly restrains the vibrator, the drive current will not increase to increase torque, eliminating the risk of overheating and the risk of the coil windings burning out.

1 is a perspective view showing a pachinko machine according to an embodiment of the present invention. FIG. 2 is a front view showing the gaming area of the gaming machine of FIG. 1 . FIG. 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1 . 1 is a diagram illustrating specifications of a display device. FIG. 2 is a block diagram illustrating the internal configuration of the display device. 1 is a diagram illustrating the circuit configuration and operation of a power supply control circuit. 2 is a block diagram showing in some detail the circuit configuration of the performance control unit of the gaming machine of FIG. 1. 10 is a diagram illustrating a composite chip that constitutes a performance control unit. FIG. 5 is a block diagram showing the internal configuration of the CPU circuit shown in FIG. 4 . This illustrates the memory map of the built-in CPU (performance control CPU) of the CPU circuit. 1A to 1E are diagrams for explaining various transfer operation modes (a) to (b) and transfer operation procedures (c) to (e) for a DMAC. 1 is a diagram illustrating an index space, an index table, a virtual drawing space, and a drawing area. FIG. 2 is a block diagram illustrating the internal configuration of a data transfer circuit together with related circuit configurations. FIG. 2 is a block diagram showing the internal configuration of a display circuit together with related circuit configurations. 10 is a diagram illustrating a data valid signal ENAB output from a VDP circuit; 10 is a flowchart illustrating a power reset operation after a CPU reset. 17 is a flowchart illustrating a memory section initialization process that is part of FIG. 16. 17 is a flowchart illustrating a main introduction process and an interrupt process, which are part of FIG. 16 . 10 is a flowchart illustrating a CGROM initialization process that is part of the main installation process. 10 is a flowchart illustrating the operation of another embodiment using interrupt processing. 19 is a flowchart illustrating the main introduction process following FIG. 18 and the process up to the steady-state process. 22 is a flowchart illustrating the steady-state processing following FIG. 21 . 1 is a diagram illustrating the configuration of a display list. 10 is a flowchart showing a DL issuing process for issuing a display list DL. 25 is a flowchart illustrating an operation when a DMAC is involved in the operation of FIG. 24. 26 is a flowchart illustrating an operation subsequent to the processing of FIG. 25. 10 is a flowchart illustrating a routine process when a preloader is used. 28 is a flowchart illustrating a part of FIG. 27. 28 is a flowchart illustrating another part of FIG. 27. 10 is a time chart showing the operation of each part of the VDP in an embodiment in which a preloader is not used. 10 is a time chart showing the operation of each part of the VDP in an embodiment using a preloader. FIG. 10 is a block diagram showing the overall circuit configuration of another embodiment. FIG. 33 is a block diagram showing a portion of FIG. 32 in some detail. 10 is a time chart illustrating the operation of another embodiment. 10 is a diagram illustrating yet another embodiment. 10 is a diagram illustrating an embodiment in which a set value is repeatedly set. 1 is a diagram illustrating a circuit configuration of an embodiment using a built-in audio circuit. 10 is a flowchart illustrating an initial setting operation of the audio circuit. 10 is a diagram illustrating another embodiment of a power reset operation after a CPU reset. 10 is a time chart showing an example of a memory read operation and a memory write operation. 10 is a diagram illustrating another embodiment. 1 is a diagram illustrating a method of driving a general display device. 1 is a diagram illustrating a display list. 10 is a diagram illustrating a zoom preview. 10 is a diagram illustrating a process of a CPU for realizing a rotation operation. 1 is a diagram showing the basis of a calculation formula. 4 is a time chart showing the deformation operations of the backlight unit and the liquid crystal display unit when the power is turned on. 10 is a time chart showing another transformation operation of the backlight unit and the liquid crystal display unit when the power is turned on. FIG. 2 is a block diagram illustrating a circuit configuration for realizing a special effect. This diagram illustrates the internal configuration of the serial port and the connection relationship with the motor driver and sensor board. 4 is a diagram illustrating the internal configuration of a sensor substrate. 1 is a diagram illustrating a motor driver. 10 is a diagram illustrating the operation of a bridge driving circuit. 4 is a time chart illustrating a constant current control operation. 1 is a detailed diagram of a portion of a motor driver. 10 illustrates the relationship between the drive data received by the motor driver and the A-phase and B-phase drive currents. FIG. 2 is a block diagram showing the internal configuration of a motor driver. 10 illustrates the relationship between the stepping clock and the drive current that is controlled to be a constant current. FIG. 2 is a block diagram showing the internal configuration of a motor controller. 1 is a diagram illustrating various driving methods. This shows the details of the timer interrupt process, and is a more detailed version of the contents of FIG. 22(b). 4 is a time chart illustrating the operation of the motor controller. 10 is a time chart illustrating the operation of a serial port. This is a diagram illustrating a spiral shaft and an example of a role-playing device effect. This is a diagram explaining the effect of a special device using a DC motor. 1 is a diagram illustrating a driving procedure of a DC motor. 1 is a diagram illustrating a control method and control performance of a DC motor. _{1 is a diagram illustrating an embodiment in which a DC motor is continuously rotated in one direction.}

The present invention will be described in detail below based on examples. Figure 1 is a perspective view showing a pachinko machine GM of this embodiment. This pachinko machine GM is composed of a rectangular wooden outer frame 1 that is detachably attached to an island structure, and an inner frame 3 that is pivotally attached so that it can be opened and closed via hinges 2 fixed to the outer frame 1. A game board 5 is detachably attached to this inner frame 3 from the front side, not the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side so that they can be opened and closed. In this specification, the glass door 6 and the front panel 7 are collectively referred to as the front door member. The inner frame 3 with the front door member (glass door 6 and front panel 7) pivotally attached thereto may also be referred to as the game frame.

Illuminated lamps such as LED lamps are arranged in a roughly C-shape around the periphery of the glass door 6. Meanwhile, a total of three speakers are located on the upper left and right sides and below the glass door 6. The two upper speakers output audio for the left and right channels R and L, respectively, while the lower speaker is configured to output low-pitched sounds.

An upper tray 8 that stores game balls to be fired is attached to the front panel 7, and a lower tray 9 that stores game balls that have spilled over or been removed from the upper tray 8, and a firing handle 10 are provided at the bottom of the inner frame 3. The firing handle 10 is linked to the firing motor, and the game balls are fired by a striking hammer that operates according to the rotation angle of the firing handle 10.

A chance button 11 is provided on the outer periphery of the upper tray 8. This chance button 11 is located in a position where it can be operated with the player's left hand, allowing the player to operate the chance button 11 without removing their right hand from the launch handle 10. This chance button 11 is normally inactive, but when the game state enters the button chance state, the built-in lamp lights up and the button becomes operable. The button chance state is a game state that is set as needed.

In addition, a rotary switch-type volume switch VLSW is located below the chance button 11. By operating the volume switch VLSW, the player can adjust the speaker volume in eight stages, from silent (=0) to the highest level (=7). The speaker volume is initially set by a setting switch (not shown) that can only be operated by an attendant, and the initial volume setting will be maintained unless the player operates the volume switch VLSW. In addition, the abnormality alert sound that alerts the player of the occurrence of an abnormal situation is emitted at the maximum volume, regardless of the volume initially set by the attendant or the volume set by the player.

To the right of the upper tray 8 is an operation panel 12 for operating the card-type ball lending machine, which includes a degree display that displays the remaining balance on the card as a three-digit number, a ball lending switch that commands the lending of a specified amount of game balls, and a return switch that commands the return of the card when the game is over.

As shown in Figure 2, a guide rail 13 consisting of an outer and inner metal rail is provided in a ring shape on the surface of the gaming board 5, with a central opening HO located approximately in the center. A movable effect body (not shown) is stored in a concealed state below the central opening HO, and during a movable preview effect, the movable effect body rises and becomes exposed, realizing a preview effect with a predetermined degree of reliability. Here, a preview effect is an effect that uncertainly notifies the player that a favorable jackpot state is about to occur, and the reliability of the preview effect refers to the probability that a jackpot state will occur.

The central opening HO houses the main display device DS1, which consists of a large (e.g., 1280 horizontal x 1024 vertical pixels) liquid crystal color display. To the right of the main display device DS1 is a movable sub-display device DS2, which consists of a small (e.g., 480 horizontal x 800 vertical pixels) liquid crystal color display. The main display device DS1 is comprised of a main liquid crystal display unit MONI and an LED backlight unit BL, and displays a moving specific symbol associated with a jackpot state, as well as animated background images and various characters. This display device DS1 has special symbol display units Da-Dc in the center and a normal symbol display unit 19 in the upper right corner. The special symbol display units Da-Dc may display reach effects that anticipate a jackpot state, and appropriate preview effects are displayed in and around the special symbol display units Da-Dc.

The sub-display device DS2 normally displays image information in a static state with its display screen tilted at an angle that is easy for the player to see. However, during a specified preview performance, the tilt angle is changed to an angle that is easy for the player to see, and the specified preview image is displayed while moving to the left as shown in the illustration.

In other words, the sub-display device DS2 in this embodiment is not just a display device, but also functions as a movable display device that executes preview effects. Here, the preview effects by the sub-display device DS2 are set to have a high degree of reliability, and players will pay close attention to the movement of the sub-display device DS2 with great anticipation. The sub-display device DS2 also consists of a sub-LCD unit MONI and an LED backlight unit BL.

In the game area where the game balls fall and move, there are a first symbol start opening 15a, a second symbol start opening 15b, a first big prize opening 16a, a second big prize opening 16b, a regular prize opening 17, and a gate 18. Each of these winning openings 15-18 has a detection switch inside, which allows it to detect the passage of the game ball.

Above the first symbol start opening 15a, there is a presentation stage 14 configured so that a gaming ball entering through the inlet IN can move in a seesaw or roulette pattern and then enter the first symbol start opening 15. When a gaming ball enters the first symbol start opening 15, the special symbol display sections Da to Dc begin to change position.

The second symbol start opening 15b is configured to be opened and closed by an electric tulip equipped with a pair of left and right opening and closing claws, and when the stopped symbol after the normal symbol display section 19 changes displays a winning symbol, the opening and closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

The normal symbol display unit 19 displays normal symbols. When a gaming ball is detected passing through the gate 18, the normal symbol changes for a predetermined period of time and then stops, displaying a stop symbol determined by a random number value selected at the time the gaming ball passes through the gate 18.

The first large prize opening 16a is configured with a sliding plate that moves back and forth, while the second large prize opening 16b is configured with an opening/closing plate whose lower end is supported by a shaft and opens forward. There are no particular restrictions on the operation of the first large prize opening 16a or the second large prize opening 16b, but in this embodiment, the first large prize opening 16a corresponds to the first symbol starting opening 15a, and the second large prize opening 16b corresponds to the first symbol starting opening 15b.

In other words, when a gaming ball enters the first symbol start opening 15a, the special symbol display sections Da-Dc begin to move. Then, when the specified jackpot symbol is aligned in the special symbol display sections Da-Dc, the special game representing the first jackpot begins, and the sliding plate of the first big prize opening 16a opens forward, facilitating the entry of the gaming ball.

On the other hand, when a predetermined jackpot pattern is aligned in the special pattern display areas Da-Dc as a result of the variable operation initiated by the entry of a gaming ball into the second pattern start opening 15b, a special game representing a second jackpot is initiated, and the opening and closing plate of the second large winning opening 16b is opened, facilitating the entry of the gaming ball. The gaming value of the special game (jackpot state) varies depending on the aligned jackpot pattern, etc., but the gaming value awarded is determined in advance based on the results of a lottery that corresponds to the timing of the gaming ball's entry.

In a typical jackpot state, after the opening and closing plate of the jackpot opening 16 is opened, it closes after a predetermined time has passed or when a predetermined number of game balls (e.g., 10) have entered the jackpot. This operation may continue for up to 15 times, for example, and is controlled to be advantageous to the player. Furthermore, if the stopped pattern after the change in the special pattern display sections Da to Dc is a specific special pattern, the player is granted the bonus of entering a high probability state (probability change state) after the special play ends.

Figure 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes the above-mentioned operations. Also, Figure 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNI located on the payout control board 25, and Figure 3(c) is a diagram explaining the specifications of the main display device DS1 used in this embodiment.

First, the specifications of the main display device DS1 used in this embodiment will be explained based on Figure 3(c). As previously explained, this display device DS1 is a liquid crystal color display with 1280 horizontal and 1024 vertical pixels. It is configured so that adjacent odd-numbered pixels (ODD) and even-numbered pixels (EVEN) are received by the receiver RV (RVa+RVb) via separate LVDS (Low Voltage Differential Signaling) transmission paths. Therefore, in this embodiment, in accordance with this dual link specification, the ODD signal is transmitted via the first transmission path LVDS1, and the EVEN signal is transmitted via the second transmission path LVDS2 (lower right of Figure 3(a)).

Furthermore, in this display device DS1, the operating clock CK (see Figure 42) that regulates the internal operation of the display device DS1 is specified to have a frequency in the range of 40 MHz to 70 MHz (typical value = 54 MHz). This operating clock CK corresponds to the LVDS clock CLK described below, but for the sake of convenience, the following description will assume that the frequency of the operating clock CK is a typical value of 54 MHz. Furthermore, a configuration will be described in which the update time FR (Frame Rate) required to update one frame of image is matched to approximately 1/60 seconds for a 54 MHz operating clock CK.

This display device DS1 is configured to simultaneously process two adjacent pixels on the left and right of the display screen using a single operating clock CK, based on the ODD signal received from the first transmission path LVDS1 and the EVEN signal received from the second transmission path LVDS2. As a result, the pixel data for 1280 pixels on one horizontal line is updated in an operating time of 640/54 MHz = 11.85 μS, and this operation is repeated for 1024 lines, updating one frame of 1280 x 1024 pixel image display. The image is updated line by line in a non-interlaced manner, from the first line → second line ... → 1024th line.

However, as shown in Figure 3(c), the specifications for display device DS1 stipulate that a typical waiting time (blank period) of 204 clocks be provided in the horizontal direction, and a typical waiting time (blank period) of 42 rows be provided in the vertical direction. Therefore, the actual screen update period FR, taking these blank periods into account, is calculated based on the typical values above as (204 + 640) x (42 + 1024) / 54 MHz ≈ 16.66 mS, resulting in a frame rate FR of approximately 1/60 Hz.

Note that the horizontal waiting time WTh and the vertical waiting time WTv each have a defined tolerance range for their typical values, and in practice, values other than the typical values listed above can be selected. However, to set the frame rate FR = 1/60 seconds, the horizontal and vertical waiting times WTh/WTv must be set accurately so that (WTh + 640) x (WTv + 1024)/54 MHz = 1/60 seconds.

On the other hand, this display device DS1 does not particularly need to receive the horizontal synchronization signal HS or the vertical synchronization signal VS, but does require the transmission of an H-level data enable signal ENAB when transmitting ODD and EVEN signals. In other words, when significant signals (ODD/EVEN signals) are being transmitted over the transmission paths LVDS1 and LVDS2, the data enable signal ENAB must be at an active level (H).

In this embodiment, based on the specifications of the main display device DS1 described above, the performance control board 23 and the main display device DS1 are LVDS-connected via a dual-link transmission path with an LVDS clock CLK frequency of 54 MHz (= 1/2 the dot clock DCK) (Figures 5 and 14(a)). Furthermore, the VDP circuit 52 of this embodiment provides a horizontal blanking period WTh and a vertical blanking period WTv that meet the specifications of the main display device DS1, and is configured so that the data enable signal ENAB is at an active level (H level) when image data (ODD/EVEN signals) are output.

That is, as shown in Figure 4(b), the data valid signal ENAB is configured to be high only during the horizontal display period THd of the horizontal synchronization period TH. Therefore, the data valid signal ENAB is always low during the vertical synchronization period TV other than the vertical display period TVd. Note that the horizontal blanking period WTh and the vertical blanking period WTv use values that differ from their respective typical values (WTh = 204 / WTv = 42), but specific design values will be described later with reference to Figure 15.

In either case, the data valid signal ENAB is repeatedly transmitted as a discrete DE signal via the differential signal lines RA2/RB2 in each operating cycle of the LVDS clock CLK. The data valid signal ENAB shown in Figures 4(b) and 4(c) is a demodulated DE signal, which is discrete data transmitted via LVDS, and is a continuous DE signal on the time axis. Note that the vertical synchronization signal VS and horizontal synchronization signal HS are also repeatedly transmitted on the differential signal lines RA2/RB following the DE signal (data valid signal ENAB), but the main display device DS1 used in this example does not utilize these synchronization signals VS and HS.

However, the display device DS1 does not prohibit the transmission of the horizontal synchronization signal HS or the vertical synchronization signal VS. However, the internal operations defined by these synchronization signals are not executed. In other words, the horizontal line feed timing of the display line is determined to be optimal for the internal circuitry of the display device DS1, regardless of the received horizontal synchronization signal HS, based on the falling edge of the data enable signal ENAB and the number of operating clocks CK (corresponding to the LVDS clock CLK) after the rising edge of the data enable signal ENAB (640 = 1280/2 in this embodiment) (downward arrow in Figure 4(b)).

The same applies to the timing of the vertical line feed after displaying one frame of image; this is determined to be optimal for the internal circuitry of the display device DS1 based on factors such as the number of consecutive data enable signals ENAB with a specified pulse width (1024 in this embodiment) (downward arrow in Figure 4(c)), and is not affected by the received vertical synchronization signal VS. In this way, in this embodiment, there is no need to transmit the horizontal synchronization signal HS or vertical synchronization signal VS to the display device DS1, so there is no need to optimally set the pulse widths PWh/PWv of the synchronization signals HS and VS, the front ports FPh/FPv, and the back ports BPh/BPv, significantly reducing the control burden on the performance control unit 23 and VDP circuit 52.

In addition, the internal operation of the display device DS1 is such that horizontal and vertical line feed operations are performed at optimal timing based on its own internal configuration, eliminating the risk of unnatural display behavior. Incidentally, in the case of a display device that operates based on an externally received horizontal synchronization signal HS or vertical synchronization signal VS, if the pulse width of the synchronization signals HS and VS, or the front porch period and back porch period before and after the synchronization signals HS and VS, are inappropriate, there is a risk that normal display behavior may be impaired.

In Figure 4(a), the first differential signal LVDS1, which uses differential signal lines RA0-RA3 and RACCLK, transmits odd-numbered pixels (ODD signal on side A), and the second differential signal LVDS2, which uses differential signal lines RB0-RB3 and RBCLK, transmits even-numbered pixels (EVEN signal on side B). In this way, in this embodiment, by transmitting two types of ODD signals and EVEN signals over a dual link transmission path, the frequency of the dot clock DCK can be reduced by half, resulting in better noise resistance and allowing for longer transmission distances.

Meanwhile, the main display device DS1 has a built-in conversion receiver RV for the ODD signal and EVEN signal transmitted over the dual link transmission path, and restores the RGB signal from the two LVDS signals (ODD signal and EVEN signal) to display one frame of image (1280 x 1024 dots). As explained above, each RGB signal is made up of 8 bits, so the main display device DS1 displays a full-color image with a gradation of ²⁸ x ²⁸ x ²⁸ .

Figure 5 is a block diagram of the display device DS1, which is composed of a main LCD display unit MONI and an LED backlight unit BL, particularly illustrating the internal configuration of the LCD display unit MONI along with the relevant parts of the VDP circuit 52. As shown, the ODD signal is transmitted to the LVDS-parallel conversion unit RVa via the first LVDS line (side A), and the EVEN signal is transmitted to the LVDS-parallel conversion unit RVb via the second LVDS line (side B). Of the 8-bit RGB data transmitted over differential lines RA0/RB0, image data R0-R5 and G0 are extracted, and image data G1-G5 and B0-B1 are extracted from differential lines RA1/RB1.

In addition, image data B2-B5, the DE signal, the VS signal, and the HS signal are output from differential lines RA2/RB2, and image data G6-G7, R6-R7, and B6-B7 are output from differential lines RA3/RB3. Here, the DE signal is nothing more than the data valid signal ENAB. As mentioned above, the output VS and HS signals are not used.

The LVDS clock CLK on the differential lines RACK/RBCK is then supplied to a PLL circuit, which generates an operating clock CK with the same frequency as the LVDS clock CLK, 54 MHz. This operating clock CK regulates the internal operation of the LCD controller LCD_CTL, which processes image data corresponding to two adjacent RGB pixels (8 bits x 3 x 2) on the left and right of the LCD panel, all at once, in synchronization with a single operating clock CK.

Therefore, processing of a pixel with 1280 (=640 x 2) dots in the horizontal direction will be completed in 11.85 μS (=640/54 MHz), which is the processing time for 640 operation clocks CK. Note that one pixel is made up of three basic RGB pixels, and the image data for each of the three basic RGB pixels is one byte long and has a gradation of ²⁸ x ²⁸ x ²⁸ , so the image data for all pixels (1280 dots) on one line is 3 x 1280 bytes long overall.

As shown in Figure 5, the LCD controller LCD_CNT appropriately controls the source driver SDV, which drives each of 1,280 source signal lines with a drive signal of ²⁸ (=256) gradations, and the gate driver GDV, which controls the ON/OFF of 1,024 gate signal lines. Specifically, the LCD controller LCD_CNT realizes image update operations at a frame rate FR = 1/60 Hz by appropriately operating each component based on the DE signal extracted from the LVDS transmission path and the operating clock CK. As confirmed earlier, the DE signal corresponds to the data valid signal ENAB output by the VDP circuit 52.

In this embodiment, the source driver SDV is configured with 10 driver elements, each with 384 output terminals. As explained above, all pixels (1280 dots) on one line of the liquid crystal panel LCD are made up of 3 x 1280 basic pixels of the three colors RGB, so 10 driver elements are required to drive them. Image data DAT is supplied sequentially from the liquid crystal controller LCD_CNT to these 10 driver elements, which are transferred appropriately based on the start signal SP and transfer clock DCLK. Then, in synchronization with the latch signal LT, analog-converted drive signals are supplied to the 3840 source signal lines. As explained above, it takes 11.85 μS (= 640/54 MHz) to update all pixels (1280 dots) on one line of the liquid crystal panel LCD.

Meanwhile, the LCD controller LCD_CNT updates the gate signal lines to be driven by supplying a gate start signal GS and a gate clock signal GCLK to the gate driver GDV. Here, the gate driver GDV is composed of four driver elements, each with 256 output terminals.

The update timing of the gate signal lines is determined based on the falling edge of the DE signal and the operating clock CK. The horizontal line feed period of the gate signal lines is counted using the operating clock CK, and is calculated as 640 + 204 clocks in typical value calculations (see Figure 3(c)). Based on the number of DE signals (1024), the gate signal lines to be driven are reset to their initial state, a gate start signal GS is output at the optimal timing, and output of the gate clock signal GCLK is resumed. The vertical line feed period of the gate signal lines is counted using the operating clock CK, and is calculated as 42 + 1024 clocks in typical value calculations (see Figure 3(c)). However, as explained above, in this embodiment, the display device DS1 is operated using a design that differs from the typical value (see Figure 15).

The above display operation requires that a power supply voltage of 5V is supplied to the main LCD display unit MONI when the LED backlight unit BL is lit. Therefore, in this embodiment, a power supply control circuit SPY is provided to ensure that the LCD display unit MONI and the backlight unit BL operate in a coordinated manner. The power supply control circuit SPY receives three types of DC voltage (3.3V, 5V, 12V) from the performance interface board 22, and also receives various power supply control signals (STBY, PWM, PS1, PS2) from the performance control CPU 63 of the composite chip 50 (see Figure 7(a)).

The power supply control circuit SPY supplies a DC voltage of 5V as the power supply voltage for the main LCD display unit MONI at the optimal timing (see Figures 6(c) and 6(g)). The power supply control circuit SPY also controls the supply of a DC voltage of 12V as the power supply voltage for the backlight unit BL, and controls the BL_EN terminal and PWM terminal of the LED backlight unit BL to appropriate H/L levels to achieve optimal lighting operation.

Figure 6(a) is a circuit diagram showing the circuit configuration of the power supply control circuit SPY and its relationship to the backlight unit BL and liquid crystal display unit MONI. As shown in the figure, this power supply control circuit SPY is mainly composed of a first switch circuit having transistor Tr1 and MOS transistor Q1, a second switch circuit having transistor Tr2 and MOS transistor Q2, a third switch circuit having transistor Tr3 and MOS transistor Q3, a fourth switch circuit having transistor Tr4 and MOS transistor Q4, and a buffer circuit SBUF that receives various control signals.

The buffer circuit SBUF is a high-speed Schmitt buffer (e.g., TC74VHC9125) powered by the 3.3V DC voltage supplied from the performance interface board 22, and operates with a non-inverted input/output relationship. In other words, the performance control CPU 63 of the composite chip 50 outputs power supply control signals (STBY, PWM, PS1, PS2) with a theoretical H/L width of 3.3V based on the 3.3V power supply voltage. The buffer circuit SBUF then outputs control signals (STBY, PWM, PS1, PS2) of the same logic (see Figure 7(a)).

As shown in Figure 6(a), the four input terminals (STBY, PWM, PS1, PS2) of the buffer circuit SBUF are all connected to ground via pull-down resistors Rpd. When the control signals are in a HiZ (high impedance) state, such as when the connector is disconnected or when the power is turned on, all control signals are configured to be at L level.

Next, in the first to fourth switch circuits, transistors Tr1 to Tr4 are all NPN-type bipolar transistors that are driven to perform switching operations. That is, when the corresponding control signal PS1/STBY/PWM/PS2 is H level, each transistor Tr1/Tr2/Tr3/Tr4 operates ON based on the voltage division ratio of the bias resistor, while when the control signal PS1/STBY/PWM/PS2 is L level, no current flows through the bias resistor and the transistor operates OFF.

When transistors Tr1 and Tr4 are OFF, the collector outputs of each transistor Tr1 and Tr4 are both higher than 3.3V (12V/5V). Furthermore, when MOS transistor Q1 is ON and transistors Tr2 and Tr3 are OFF, the collector outputs of each transistor Tr2 and Tr3 are approximately 12V. In this sense, each transistor Tr1 to Tr4, together with the bias resistor, constitutes a level shift circuit that increases the logic H level of the power supply control signals (STBY, PWM, PS1, PS2).

The bias resistors for transistors Tr1 to Tr4 are R11+R12, R21+R22, R31+R32, and R41+R42, respectively, and a voltage determined by the voltage division ratio of each bias resistor is supplied to the base terminals of transistors Tr1 to Tr4.

In this embodiment, the level shift circuits (Tr1 to Tr4) described above are provided, which allows the backlight's luminance to be increased while significantly reducing the power consumption of the performance control unit 23. In other words, the power supply voltage (12V) of the backlight unit BL can be set to the highest possible level, while the logical H level of the power supply control signals (STBY, PWM, PS1, PS2) can be set to an arbitrary low level (3.3V).

On the other hand, MOS transistors Q1 to Q4 are all Pch type, and perform switching operations according to the ON/OFF states of transistors Tr1 to Tr4. When in ON mode, the source terminal S and drain terminal D are almost conductive.

Specifically, MOS transistor Q1 receives a 12V DC voltage at its source terminal S supplied by the performance interface board 22. When transistor Tr1 turns ON based on an H-level control signal PS1, MOS transistor Q1 also turns ON based on the voltage across bias resistor Rb1, which transitions to a conductive state in response, and outputs a 12V DC voltage to its drain terminal D.

This 12V DC voltage is supplied to the backlight unit BL via an RC filter circuit and Zener diode. The RC filter circuit consists of a 3.3kΩ resistor and a 47μF conductive polymer capacitor (a hybrid capacitor that uses an electrolyte that combines a conductive polymer and electrolyte instead of the electrolyte found in aluminum electrolytic capacitors).

This hybrid capacitor has a rated voltage of 25V and is a cylindrical SMD (Surface Mount Device) with a diameter of 6.3mm and a height of 5.8mm. When powered by 5V, the capacitance is maintained at less than -10% of the nominal value (47μF). The nominal equivalent series resistance (ESR) is 50mΩ.

In a typical circuit configuration, a 47 μF electrolytic capacitor is connected in parallel with a ceramic capacitor (0.1 μF) such as an MLCC (Multilayer Ceramic Capacitor), but in this embodiment, a single hybrid capacitor achieves the desired smoothing and decoupling operations, eliminating the need to use space for other circuit elements.

Incidentally, no other smoothing capacitors or decoupling capacitors are placed within a radius of at least 20 mm from the conductive polymer capacitor. Furthermore, in this embodiment, the decoupling capacitor is surface-mounted, rather than through-hole mounted as with ordinary electrolytic capacitors, which has the advantage of reducing the amount of space required for placement.

The top surface of the surface-mounted cylinder is marked with the numerical value "47" indicating capacitance and the rank symbol "E" indicating a rated voltage of 25V, and the direction of the negative polarity is identified with a black symbol, making it easy to visually check the components on the board.

In addition, this embodiment uses, in particular, an element for MOS transistor Q1, whose ON resistance between source S and drain D is 25 mΩ or more and 35 mΩ or less. Therefore, even if a drive current (drain current ID) of 2.5 A flows steadily, for example, the voltage drop in MOS transistor Q1 is 0.1 V or less, and power loss is suppressed to approximately 0.22 W (= 2.5 * 2.5 * 35/1000). Note that the ON resistance was measured during pulse drive at VGS = -10 V and ID = -4.5 A.

In addition, transistors Q2 and Q3 each receive the voltage at drain terminal D of transistor Q1 at their source terminal S. Therefore, when MOS transistor Q1 is ON and transistors Tr2/Tr3 are turned ON based on the H-level control signal STBY/PWM, MOS transistors Q2 and Q3 are also turned ON based on the voltage across bias resistors Rb2/Rb3, which transition to a conducting state in response. As a result, a DC voltage of 12V is output to drain terminal D of MOS transistors Q2 and Q3 via transistor Q1, which is turned ON.

This 12V DC voltage is output from the drain terminal D of MOS transistor Q2 as the control signal STBY, and from the drain terminal D of MOS transistor Q3 as the control signal PWM. The control signal STBY is supplied to the BL_EN terminal (backlight enable) of the backlight unit BL while being pulled down by the pull-down resistor Rpd, and the control signal PWM is supplied to the PWM terminal (pulse width modulation) of the backlight unit BL while being pulled down by the pull-down resistor Rpd.

In this embodiment, by setting the pull-down resistors Rpd to approximately 33 kΩ, the current flowing through the pull-down resistors Rpd due to a DC voltage of 12 V (STBY/PWM) is suppressed to approximately 0.36 mA. This eliminates the need to select expensive elements for the MOS transistors Q2 and Q3, and in this embodiment, elements with an ON resistance between the source S and drain D of 2.5 Ω or more and 3.8 Ω or less are used. Note that the ON resistance is the result of measurements taken during pulse driving at VGS = -4.5 V and ID = -100 mA.

Next, we will explain the backlight unit BL. The backlight unit BL is composed of N x M light-emitting diodes (LEDs) aligned vertically and horizontally, and a driver DVL that outputs negative logic drive pulses to synchronously light up the N x M light-emitting diodes. This driver DVL is composed of a BL_EN terminal that determines whether internal operation is enabled, a PWM terminal that determines the duty ratio of the negative logic drive pulse using positive logic in the range of 10% to 100%, and output terminals LED1 to LEDn that output drive pulses.

As explained earlier, the BL_EN terminal receives the control signal STBY from the power supply control circuit SPY, and the PWM terminal receives the control signal PWM. When the control signal STBY is at H level (12V), the internal circuitry of the driver DVL operates, enabling drive pulses to be output from the output terminals LED1 to LEDn. These drive pulses are negative logic pulses that are the logical inversion of the control signal PWM.

As such, the drive pulse in this embodiment is a negative logic pulse that is the logical inversion of the control signal PWM supplied to the PWM terminal. Therefore, the closer the duty ratio of the control signal PWM is to 100%, the longer the L level period of the output terminals LED1 to LEDn, and the higher the average current flowing through the light-emitting diodes, resulting in brighter backlight light. On the other hand, the closer the duty ratio is to 10%, the lower the average current flowing through the light-emitting diodes, resulting in dimmer backlight light.

Therefore, by appropriately changing the duty ratio of the control signal (control pulse) PWM, the light intensity of the backlight can be changed. For example, the backlight can be dimmed in demo mode when no player is present. However, in this embodiment, to avoid the complexity of such light emission control, the duty ratio of the control signal is maintained at 100%, and the control signal PWM does not change to a pulsed form, but remains steadily at a high level (12V) when in operation. As a result, the output terminals LED1 to LEDn of the driver DVL remain steadily at a low level when the backlight unit BL is in operation.

By the way, the BL_EN terminal and the PWM terminal are both connected to ground via pull-down resistor Rpd. Therefore, when MOS transistor Q2 is OFF and the control signal STBY is in the HiZ state, driver DVL is in the inactive state, output terminals LED1 to LEDn are in the HiZ state, and all light-emitting diodes are turned off.

Furthermore, when MOS transistor Q3 is OFF and the control signal PWM is in the HiZ state, even if the control signal STBY is H level, the duty ratio is maintained at 0%, so that the output terminals LED1 to LEDn remain H level (12V) and all light-emitting diodes are turned off. Therefore, when the power is turned on and no significant image data is being transferred, or when the power supply control circuit SPY is operating abnormally, the backlight is turned off, thereby preventing unnatural image display. The same idea is behind the connection of pull-down resistors Rpd between the four input terminals of buffer circuit SBUF and ground.

Next, we will explain the relationship between the fourth switch circuit, which includes transistor Tr4 and MOS transistor Q4, and the main LCD display unit MONI. As explained above, transistor Tr4 of the fourth switch circuit is turned ON/OFF based on the H/L level of the control signal PS2.

Meanwhile, MOS transistor Q4 receives a 5V DC voltage at its source terminal S supplied by the performance interface board 22. When transistor Tr1 turns ON, the MOS transistor Q4 also turns ON based on the voltage across bias resistor Rb4, which transitions to a conductive state in response, and outputs a 5V DC voltage to its drain terminal D.

This 5V DC voltage is supplied to the liquid crystal display unit MONI shown in Figure 5 via an RC filter circuit and Zener diode, and is used as the power supply voltage for the liquid crystal display unit MONI. In this embodiment, a device with an ON resistance between source S and drain D of 48 mΩ or more and 65 mΩ or less is used as MOS transistor Q4. Therefore, even if a drive current (drain current ID) of 1.5 A is steadily flowing, for example, the voltage drop across MOS transistor Q1 is 0.1 V or less, and power loss is suppressed to approximately 0.15 W (= 1.5 * 1.5 * 65/1000). Note that the ON resistance was measured during pulse drive at VGS = -4.5 and ID = -2.5 A.

Next, the circuit operation of the power supply control circuit SPY will be explained based on Figures 6(b) to 6(j). After power is applied to the composite chip 50, the system reset signal SYS remains at the L level for an assertion period, and then the composite chip 50 begins control operation (timing T1 in Figure 6(d)). Then, 1000 ms after timing T1, the performance control CPU 63 of the composite chip 50 transitions the control signals PS1 and PS2 to the H level (timing T2).

Then, based on the H-level control signal PS1, MOS transistor Q1 turns ON, and the supply of 12V DC to the backlight unit BL begins. Based on the H-level control signal PS2, MOS transistor Q4 turns ON, and the supply of 5V DC to the liquid crystal display unit MONI begins. However, at this timing T2, the control signals STBY and PWM both remain at L level, so the backlight unit BL does not emit light. Therefore, no matter how the liquid crystal display unit MONI operates, there is no risk of an unnatural image being displayed.

Next, approximately 5 ms after timing T2, the performance control CPU 63 begins initialization of the display clock and display circuit 74. This control will be described in detail later, but these operations are one of the initialization operations performed before the VDP circuit 52 begins operating, and at this stage, no significant image signal is output to the display device DS1.

Then, the performance control CPU 63 initializes the display register appropriately, and then starts operation of the display circuit 74 and LVDS circuit 80 (timing T4). Therefore, from timing T4 onwards, the LVDS signal as a significant image signal is repeatedly output to the display device DS1 every 1/60 seconds (see Figure 6(f)).

However, at time T4, the control signal PWM remains at L level, so the backlight does not emit light. That is, at time T3, the performance control CPU 63 transitions the control signal STBY to H level, controlling the driver DVL to an operable state, but at time T4, the control signal PWM is still L and the duty ratio of the drive pulse is 0%, so the backlight unit BL remains off.

Meanwhile, after starting operation of the display circuit 74 and LVDS circuit 80 (SS4 in FIG. 21), the performance control CPU 63 transitions the control signal PWM to the H level (SS6 in FIG. 21) at time T5, more than 300 mS later, to transition the backlight unit BL to an emitting state with a duty ratio of 100%. If the operation at time T5 is performed, for example, by timer interrupt processing, the liquid crystal display unit MONI is already repeatedly receiving the LVDS signal as a significant image signal every 1/60 seconds at time T5, and an image based on that image signal will be displayed. In other words, since steady-state processing (ST4 to ST14 in FIG. 22) begins immediately after processing step SS6 in FIG. 21, the initial screen based on the display list DL is displayed at time T5.

However, as shown in Figure 21, when the presentation control CPU 63 executes the 300 ms standby process (step SS5 in Figure 21), the display list DL has not yet been issued at timing T5, so the display content will be the screen based on the VRAM (frame buffer FBa) after power-on. Therefore, taking this into consideration, it is preferable to clear the VRAM (especially the frame buffers FBa and FBb) to zero after power-on. However, even if the VRAM is not cleared to zero, there is no problem, as the random image is only displayed for a moment at most when the amusement hall opens for business. In other words, immediately after processing step SS6 in Figure 21, regular processing (ST4 to ST14 in Figure 22) begins, and the initial screen based on the display list DL is displayed.

In this embodiment, the program is designed so that the program execution time from timing T2 to timing T4 is within 20 ms. This is because it is recommended that the display device DS1 used in this embodiment start transmitting an image signal (LVDS signal) within a predetermined time τ (e.g., 20 ms) after power is applied to the liquid crystal display unit MONI.

In this embodiment, the use of control signal PS2 to delay the timing of power supply to the liquid crystal display unit MONI by approximately one second is also based on the above requirement. If power supply to the liquid crystal display unit MONI were to begin simultaneously with power-on, it would be extremely impossible to start transmitting the LVDS signal within the specified time τ (e.g., 20 mS) thereafter due to the assertion period and program execution time (processing time for SP1 to SP10) (see timing T4).

The main display device DS1 has been explained in detail above, but the operation of the sub-display device DS2 is essentially the same, and by performing the operation shown in Figure 6(b), the sub-LCD unit MONI and backlight unit BL operate in a coordinated manner to prevent inappropriate display.

The sub-display device DS2 operates in the same manner as shown in Figure 42, based on the horizontal synchronization signal HS and vertical synchronization signal VS received from the VDP circuit 52. However, it is also preferable for the sub-control device DS2 to be configured to operate based on the data enable signal ENAB, rather than based on the horizontal synchronization signal HS or vertical synchronization signal VS. The data enable signal ENAB is transmitted to the sub-display device DS2 as a continuous signal ENAB, rather than in the form of a discrete DE signal (see the lower right of Figure 14(a)).

Next, returning to Figure 3(a), the overall circuit configuration of the pachinko machine GM will be explained. As shown in Figure 3(a), this pachinko machine GM is mainly composed of a power supply board 20 that receives 24V AC and outputs various DC voltages (35V, 12V, 5V) along with the 24V AC; a main control board 21 that is responsible for central and overall game control operations; a presentation interface board 22 equipped with circuit elements SND for audio presentation; a presentation control board 23 that executes lamp presentations, audio presentations, and image presentations in a unified manner based on control commands CMD received from the main control board 21; a liquid crystal interface board 24 located between the presentation control board 23 and the display devices DS1 and DS2; a payout control board 25 that controls the payout motor M to pay out game balls based on control commands CMD' received from the main control board 21; and a launch control board 26 that launches game balls in response to player operations.

The performance interface board 22, performance control board 23, and LCD interface board 24 are directly connected via male and female connectors, without using wiring cables. This means that even if the circuit configuration of each electronic circuit is complex and advanced, the storage space required for the entire board can be minimized, and noise resistance can be improved by shortening the connection lines.

As shown in the figure, the control command CMD' output by the main control board 21 is transmitted to the dispensing control board 25. Meanwhile, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, the control commands CMD and CMD' are both 16 bits long, but are sent in parallel in two batches of 8 bits each.

The main control board 21 and the payout control board 25 are equipped with computer circuits including a one-chip microcomputer. Furthermore, the performance control board 23 is equipped with a composite chip 50 incorporating computer circuits such as a VDP circuit (Video Display Processor) 52 and an internal CPU circuit 51. Therefore, in this specification, these control boards 21, 25, and 23, the circuits mounted on the performance interface board 22 and LCD interface board 24, and the operations realized by these circuits are sometimes collectively referred to functionally as the main control unit 21, the performance control unit 23, and the payout control unit 25. Furthermore, the performance control unit 23 and the payout control unit 25 are sub-control units relative to the main control unit 21.

This pachinko machine GM is broadly divided into a frame side member GM1, surrounded by a dashed line in Figure 3(a), and a board side member GM2, which is fixed to the back of the game board 5. The frame side member GM1 includes an inner frame 3 to which a glass door 6 and a front panel 7 are pivotally attached, and an outer wooden frame 1 on the outside of that, and is installed in a fixed position in the game hall for an extended period of time, regardless of changes in the model. On the other hand, the board side member GM2 is replaced in response to a model change, and a new board side member GM2 is attached to the frame side member GM1 in place of the original board side member. Note that everything except the frame side member 1 is the board side member GM2.

As shown in the dashed-line frame in Figure 3(a), the frame-side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor/lamp drive board 37, and these circuit boards are each fixed in appropriate locations on the inner frame 3. Meanwhile, the main control board 21 and the performance control board 23 are fixed to the back of the gaming board 5, along with display devices DS1 and DS2 and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by centralized connectors C1 to C3, which are centrally located in one location.

The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC 24V voltage distributed from the gaming hall, and distributes each DC voltage to the performance interface board 22 via the centralized connection connector C2. The three types of DC voltages (35V, 12V, 5V) are also distributed to the payout control board 25 along with the AC 24V voltage. The DC voltages (35V, 12V, 5V) distributed to the payout control board 25 are then distributed to the main control board 21 via the centralized connection connector C1, along with the backup power supply BAK.

The 35V DC power supply is used to drive the ball feed solenoid and launch solenoid used to launch the game balls, and to drive the electromagnetic solenoids that open and close the electric tulip (variable prize-winning device) and the large prize opening 16. The 12V DC power supply is used to drive the LED lamps and motors controlled by each control board, and as the power supply voltage for the digital amplifier. The 5V DC power supply is used to power the single-chip microcomputers on the payout control board 25 and main control board 21, and the logic elements mounted on each control board. The 5V DC power supply is stepped down by the DC/DC converter on the performance interface board 22, and the stepped-down voltages at various levels are then used as the power supply voltage for various computer circuits (such as the composite chip 50 and audio processor 27).

The backup power supply BAK is a 5V DC power supply used to retain data in the built-in RAM of the one-chip microcomputers of the main control unit 21 and payout control unit 25 after power is cut off, and is realized, for example, by an electric double-layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double-layer capacitor placed on the backup power supply board 33 is configured to be charged by the 5V DC voltage received from the payout control board 25 during game operation.

On the other hand, after the power is cut off, the backup power supply BAK retains the data in the built-in RAM of the one-chip microcomputers of the main control unit 21 and payout control unit 25, allowing the main control unit 21 and payout control unit 25 to resume gaming operations that were in place before the power was cut off after the power is turned on. The backup power supply board 33 is equipped with an electric double-layer capacitor that can retain the memory contents of the built-in RAM of each one-chip microcomputer for at least several days.

In this embodiment, unlike conventional equipment configurations, the power supply abnormality signal ABN, which indicates an abnormal drop in the AC 24V voltage, is generated in the power supply monitor unit MNT of the dispensing control board 25, rather than in the power supply board 20. As shown in FIG. 3(b), the power supply monitor unit MNT is configured to include a full-wave rectifier circuit that rectifies the AC 24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light, a phototransistor TR that is powered by the DC 5V received from the power supply board 20 and turns ON when the photodiode D emits light, and an output unit that outputs an H-level detection signal ABN (power supply abnormality signal) when the phototransistor TR turns ON. The photodiode D and phototransistor TR together form a photocoupler PH.

In the above configuration, after power is turned on, the photocoupler PH quickly switches to the ON state, causing the power supply abnormality signal ABN to go to the normal level (H). However, if the AC power subsequently drops abnormally for some reason (normally due to a power outage), the photocoupler PH switches to the OFF state, causing the power supply abnormality signal ABN to go to the abnormal level (L). This power supply abnormality signal ABN is transmitted to the one-chip microcomputer on the payout control board 25 and also to the one-chip microcomputer on the main control board 21 via the centralized connection connector C1. Therefore, each one-chip microcomputer that receives the abnormal-level power supply abnormality signal ABN executes backup processing to store the necessary information in its own internal RAM. As explained above, the information in the internal RAM is maintained by the backup power supply BAK, allowing game operation to resume as it was before the power was shut off after power is turned on.

As shown in Figure 3(a), the performance interface board 22 is equipped with an audio circuit SND such as an audio processor 27, and the performance control board 23 is equipped with a composite chip 50 that incorporates computer circuits such as a VDP circuit 52 and an internal CPU circuit 51. Hereinafter, the internal CPU circuit may be abbreviated as the CPU circuit.

The performance interface board 22 is equipped with reset circuits RST3 and RST4 that detect a rise in power supply voltage when power is turned on and generate various reset signals RT3 and RT4. First, the reset circuit RST3 generates the reset signal RT3 based on the 12V and 5V DC voltages distributed from the power supply board 20. The reset signal RT3 then resets the power supply to only the audio memory 28 and is transmitted directly to the performance control board 23.

As shown in Figure 7(a), the reset signal RT3 transmitted to the performance control board 23 is ANDed with the output of the WDT (Watch Dog Timer) circuit 58 in the AND gate G1, and the result is the system reset signal SYS, which resets the power supply to the CPU circuit 51 and VDP circuit 52 (see Figures 7(a) and 7(d)).

After power is turned on, the reset signal RT3 generated by the reset circuit RST3 remains at L level for a predetermined time as a power reset signal before rising to H level. However, if either the 12V DC voltage or the 5V DC voltage drops thereafter (usually when the power is turned off), the system reset signal SYS also drops to L level in response to the drop in the level of the reset signal RT3, and the CPU circuit 51 and VDP circuit 52 of the performance control board 23 enter a stopped state.

This system reset signal SYS also changes based on the output of the WDT circuit 58 (which is normally at H level). Therefore, when the reset signal RT3 is at H level and the output of the WDT circuit 58 drops to L level due to a program runaway or other cause, the system reset signal SYS also changes to L level, causing an abnormal reset of the CPU circuit 51 and VDP circuit 52 (see Figure 7(d)).

Meanwhile, the reset circuit RST4 generates a reset signal RT4 based on 3.3V generated by dropping the 5V distributed from the power supply board 20. This reset signal RT4 serves as a power reset signal when the power is turned on, resetting the power supply to the audio processor 27.

As shown in the figure, the reset circuit RST4 is also supplied with the system reset signal SYS returned from the performance control board 23, so when the CPU circuit 51 or VDP circuit 52 is abnormally reset, the audio processor 27 is also abnormally reset in synchronization with the abnormal reset of these circuits. As a result, the audio performance, along with the image and lamp performance, returns to its initial state, eliminating the risk of unnatural audio performance continuing.

Next, the payout control board 25, which is the frame side member GM1, and the main control unit 21, which is the board side member GM2, are each equipped with reset circuits RST1 and RST2, which generate a power reset signal when the power is turned on, resetting the power to each computer circuit.

In this way, in this embodiment, reset circuits RST1 to RST4 are placed in the main control unit 21, payout control unit 25, and performance interface board 22, respectively, and the system reset signal SYS is not transmitted between circuit boards. In other words, since there is no wiring cable to transmit the system reset signal SYS, the risk of the computer circuit being abnormally reset due to noise superimposed on the wiring cable is eliminated.

However, the reset circuits RST1 and RST2 provided in the main control unit 21 and dispensing control unit 25 each have a built-in watchdog timer, and if they do not receive a regular clear pulse from the CPU of each control unit 21, 25, the respective CPUs will be forcibly reset.

The main control unit 21 is also equipped with an initialization switch SW that can be operated by an attendant, and is configured to output a RAM clear signal CLR when the power is turned on, indicating whether the initialization switch SW has been turned ON. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the dispensing control unit 25, and determines whether or not to initialize the entire internal RAM area of the one-chip microcomputer of each control unit 21, 25.

In addition, as explained above, the one-chip microcomputers in the main control unit 21 and dispensing control unit 25 receive a power supply abnormality signal ABN from the power supply monitor MNT located in the dispensing control unit 25, and initiate the necessary shutdown processing prior to a power outage or closing of business.

As shown in Figure 3(a), the main control unit 21 receives from the payout control unit 25 a prize ball count signal indicating the payout operation of game balls, a status signal CON related to any abnormalities in the payout operation, and an operation start signal BGN. The status signal CON includes, for example, an out-of-supply signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after power is turned on.

The main control unit 21 also receives switch signals from the detection switches built into each winning slot 16-18 on the gaming board, while driving solenoids such as electric tulips. The solenoids and detection switches are configured to operate on the power supply voltage VB (12V) distributed from the main control unit 21. Furthermore, each switch signal indicating the winning status of the symbol start slot 15 is converted into a TTL-level or CMOS-level switch signal by an interface IC that operates on the power supply voltage VB (12V) and power supply voltage Vcc (5V), and then transmitted to the main control unit 21.

As explained above, the effect interface board 22 receives various levels of DC voltage (5V, 12V, 35V) from the power supply board 20 via the centralized connector C2 (see Figures 3(a) and 7(a)). The 12V DC voltage is the power supply voltage for the digital amplifier 29 and is also used as the drive voltage for LED lamps and the like. The 35V DC voltage is distributed to appropriate locations on the play frame and is used as the drive voltage for solenoids that move movable objects back and forth.

Meanwhile, the 5V DC voltage is supplied as a power supply voltage to circuit elements throughout the performance interface board 22, and is also supplied to two DC/DC converters DC1 and DC2 to generate 3.3V and 1.0V (see Figure 7(a)). The generated 3.3V and 1.0V DC voltages are supplied to the audio processor 27 as power supply voltages for I/O (input/output) and the chip core, respectively. The 3.3V DC voltage also serves as the base voltage for the power reset signal RT4 generated by the reset circuit RST4.

The 5V DC voltage distributed to the performance interface board 22 is distributed to the performance control board 23 together with the 3.3V generated by the DC/DC converter DC1. The 3.3V DC voltage distributed to the performance control board 23 is then supplied as power supply voltage to the composite chip 50, PROM 53, and CGROM 55.

As shown in Figure 7(a), the performance control board 23 is equipped with two DC/DC converters, DC3 and DC4, which generate 1.5V and 1.05V based on the DC voltage of 5V supplied to each. Here, the DC voltage of 1.05V is the power supply voltage for the chip core of the composite chip 50, and the DC voltage of 1.5V is the power supply voltage for I/O (input/output) with the DRAM 54. Therefore, the DC voltage of 1.5V is also supplied to the DRAM 54 as a power supply voltage.

As shown in Figure 3(a), the performance interface board 22 receives a control command CMD and a strobe signal STB from the main control unit 21 and transfers them to the performance control board 23. More specifically, as shown in Figure 7(a), the control command CMD and strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the performance control board 23 via the input buffer 40. Here, the strobe signal STB is the received interrupt signal IRQ_CMD, and the performance control CPU 63 obtains the control command CMD based on the interrupt processing program (interrupt handler) that is activated in response to the received interrupt signal IRQ_CMD.

As shown in Figure 7(a), the input buffer 44 of the performance interface board 22 receives switch signals from the chance button 11 and volume switch VLSW from the frame relay boards 35 and 36, and transmits each switch signal to the CPU circuit 51 of the performance control board 23. Specifically, it transmits to the CPU circuit 51 a 3-bit encoder output indicating the contact position (0-7) of the volume switch VLSW, and a 1-bit signal indicating the ON/OFF state of the chance button 11.

The performance interface board 22 is also connected to the lamp drive board 30 and motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay boards 35 and 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. For convenience, in Figure 7(a), the input buffer 43a and output buffer 43b are collectively referred to as the input/output buffer 43. The input buffer 43a receives outputs SN0 to SNn from an origin sensor that detects the current position of the movable performance element (the rotational position of the performance motors M1 to Mn), and transmits these to the CPU circuit 51 of the performance control board 23.

The lamp drive board 30, motor lamp drive board 31, and lamp drive board 37 are each equipped with the same type of driver IC, and the performance interface board 22 transfers the serial signals received from the performance control board 23 to each driver IC. Specifically, the serial signals are the lamp (motor) drive signal SDATA and the clock signal CK. The drive signal SDATA is transmitted to each driver IC using a clock synchronization method, and lamp performances using numerous LED lamps and electric lamps, as well as special feature performances using performance motors M1 to Mn, are executed.

In this embodiment, the lamp effects are performed by three lamp groups CH0 to CH2, and the lamp drive board 37 receives the lamp drive signal SDATA0 from CH0 in synchronization with the clock signal CK0 via the frame relay boards 35 and 36. The series of lamp drive signals SDATA0 transmitted as serial signals are output from the driver IC to the lamp group CH0 when the operation control signal ENABLE0 changes to active level, thereby updating the lighting status of all the lamps at once.

The above also applies to the lamp drive board 30. The driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 for lamp group CH1 in synchronization with the clock signal CK1, and simultaneously updates the lighting status of lamp group CH1 when the operation control signal ENABLE1 changes to the active level.

Meanwhile, the driver IC mounted on the motor lamp drive board 31 receives a lamp drive signal transmitted in clock synchronization to drive the lamp group CH2, and receives a motor drive signal transmitted in clock synchronization to drive the performance motor group M1-Mn, which is made up of multiple stepping motors. The lamp drive signal and motor drive signal are a series of serial signals SDATA2 that are transmitted serially in synchronization with the clock signal CK1, and the driver IC that receives these signals updates the drive status of the lamp group CH2 and the motor groups M1-Mn when the operation control signal ENABLE2 changes to the active level.

Next, we will explain the audio circuit SND. As shown in Figure 7(a), the performance interface board 22 is equipped with an audio processor (audio synthesis circuit) 27 that reproduces audio signals based on instructions received from the CPU circuit 51 (performance control CPU 63) of the performance control board 23, an audio memory 28 that stores compressed audio data, which is the original data for the reproduced audio signals, and a digital amplifier 29 that receives the audio signals output from the audio processor 27.

The audio processor 27 is configured with a built-in WDT circuit that automatically resets the internal circuit settings to default values (initial values) in the event of an abnormal operation of the internal circuit, and an audio control register SRG. The audio processor 27 then accesses the audio memory 28 based on the operating parameters (setting values via audio commands) received by the audio control register SRG from the performance control CPU 63, and reproduces and outputs the required audio signals.

7A, the audio processor 27 and audio memory 28 are connected by a 26-bit audio address bus and a 16-bit audio data bus, so that the audio memory 28 can store 1 Gbit (= ² × 16) of data.

The audio control registers SRG are divided into register banks 1 to 6, each identified by a register number between 00H and FFH. Therefore, a specific setting operation is achieved by the performance control CPU 63 identifying the register bank and then writing a 1-byte operating parameter to the audio control register SRG with the specified register number (1 byte long).

In this embodiment, the register numbers (00H to FFH) of the sound control register SRG correspond to the address space CS3 of the performance control CPU 63. For example, when setting the operating parameter YYH in the sound control register SRG with register number XXH, the performance control CPU 63 writes XXH to address zero in address space CS3, and then writes YYH to address 1. In other words, the performance control CPU 63 writes XXH and YYH to its data bus in that order. Note that in this specification, the subscript H and the prefixes 0X/0x indicate that the values are expressed in hexadecimal.

In addition, in this specification, address space CS0 to CS7 refers to external memory (excluding built-in memory) for the CPU circuit 51, where the memory type (including whether it is volatile or not) and data bus width (8/16/32 bits) can be specified. This address space CS0 to CS7 is selected by different chip select signals CS0 to CS7, and is configured to be configurable so that the READ/WRITE control signals that function during READ/WRITE access can be optimized according to the memory type. This configuration operation is performed by the bus state controller 66.

Figure 7(e) illustrates the setting operation of the sound register SRG by the performance control CPU 63, showing the contents of the 2-bit address bus A1-A0 and the 1-byte data bus D7-D0. In this embodiment, the chip select signal CS3 is set at power-on so that it automatically becomes active when address space CS3 is accessed; this will be discussed later in connection with Figures 9 and 16.

In any case, in this embodiment, the compressed audio data stored in the audio memory 28 is compressed phrase data identified by a 13-bit phrase number NUM (000H to 1FFFH), and up to 8,192 types (=2 ¹³ ) of a series of background music (BGM), a group of effect sounds (warning sounds), etc. are stored, each corresponding to a phrase number NUM. The phrase number NUM is identified by the setting value (operation parameter) of the audio command transmitted from the effect control CPU 63 to the audio control register SRG of the audio processor 27.

As described above, the audio memory 28 having the above configuration is powered on and reset by the reset signal RT3, and the audio processor 27 is powered on and reset by the reset signal RT4. As shown in Figure 7(c), after power is turned on, the reset signal RT4 rises to a high level after a predetermined assertion period ASRT (low level period). In this embodiment, the internal circuitry of the audio processor 27 then automatically functions and initialization sequence processing is executed. Note that this initialization sequence processing is an internal operation executed in a predetermined procedure, and while the initialization sequence processing is in operation, the performance control CPU 63 cannot access the audio register SRG.

When the internal initialization sequence processing is completed, the interrupt signal IRQ_SND to the CPU circuit 51 changes to L level, and the CPU circuit 51 (performance control CPU 63) executes the interrupt processing program based on the interrupt signal IRQ_SND. The interrupt signal IRQ_SND is then returned to H level based on a specified command; details of this will be discussed further below with reference to Figure 18(c).

As shown in Figure 7(a), the data bus and address bus of the CPU circuit 51 of the performance control unit 23 also extend to the clock circuit (real time clock) 38 and performance data memory 39 mounted on the LCD interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51, and when the clock circuit 38 is selected by the chip select signal CS4, the CPU circuit 51 is configured to be able to access the internal registers (which have 4-bit address values) at will.

The effect data memory 39 is a high-speed accessible memory element, SRAM (Static Random Access Memory), connected to 16 bits of the CPU circuit 51's address bus and the lower 16 bits of the data bus. When the chip is selected by the chip select signal CS4, the game performance information and other data stored in the SRAM (effect data memory) 39 can be accessed by the CPU circuit 51 as appropriate via R/W. In the address space CS4 selected by the chip select signal CS4, addresses 0 to 15 are numbered by the clock circuit 38 and are therefore not used by the SRAM 39.

The clock circuit 38 and effect data memory 39 are powered by a secondary battery (not shown), which is charged appropriately during game operation by the power supply voltage from the power supply board 20. Therefore, even after power is cut off, the clock circuit 38 continues to measure time, and the game performance information stored in the effect data memory 39 is permanently stored (non-volatile). The clock circuit (RTC) 38 is configured to output an interrupt signal IRQ_RTC to the CPU circuit 51 (RTC interrupt). This RTC interrupt includes an alarm interrupt that can specify the date, day of the week, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed. In this embodiment, the alarm interrupt is used to update the daily game performance information at the end of business each day.

As shown on the right side of Figure 7(a), the performance control board 23 is equipped with a composite chip 50 incorporating a CPU circuit 51 and a VDP circuit 52, a control memory (PROM) 53 that stores the control program for the CPU circuit 51, a DRAM (Dynamic Random Access Memory) 54 that can access large amounts of data at high speed, and a CGROM 55 that stores the large amounts of CG data required for performance control.

As will be described later with reference to Figure 10, in this embodiment, the control memory (PROM) 53 is located in address space CS0, which is selected by chip select signal CS0. Furthermore, the DRAM (Dynamic Random Access Memory) 54, which is configured using DDR (Double-Data-Rate 3), is located in address space CS5, which is selected by chip select signal CS5.

Figure 8(a) is a circuit block diagram illustrating the composite chip 50 that constitutes the performance control unit 23, including related circuit elements. As shown, the composite chip 50 of this embodiment incorporates a CPU circuit 51 that issues a display list DL at predetermined time intervals, and a VDP circuit 52 that generates image data based on the issued display list DL and drives the display devices DS1 and DS2. The CPU circuit 51 and VDP circuit 52 are connected via a CPUIF circuit 56 that relays data sent and received between them.

The VDP circuit 52 has a built-in audio circuit SND that performs the same functions as the audio processor 27, but in the first embodiment described below, the audio circuit SND is not used. However, if the audio circuit SND built into the VDP circuit 52 is used, as in the last embodiment described below, the audio memory 28 and audio processor 27 will not be required.

First, the CPU circuit 51 receives the oscillation output (e.g., 100/3 MHz) of oscillator OSC1 at the HCLKI terminal and multiplies the frequency (e.g., by 8) to generate a CPU operating clock of approximately 266.7 MHz (see Figure 14(b)). Here, oscillator OSC1 is configured to output spread spectrum waves, thereby providing EMI (Electromagnetic Interference) protection to prevent radio interference/electromagnetic jamming.

In this embodiment, the CPU operating clock can also be generated based on the output of oscillator OSC2 (described below) rather than oscillator OSC1, making oscillator OSC1 unnecessary. However, in a configuration using a single oscillator, the frequency multiplication ratio of the PLL circuit is a fixed value (e.g., 5), the same as that of the system clock (described below), so the frequency of the CPU operating clock will be 200 MHz (= 40 MHz x 5), the same as the system clock of the VDP circuit 52.

While this configuration has the advantage of sharing the operating cycles of the built-in CPU circuit 51 and VDP circuit 52, it contradicts the desire to make CPU operation as fast as possible. In other words, VDP operation cannot be made faster than a certain point, so it cannot reliably meet the demand for faster CPU operation. Therefore, in this embodiment, two oscillators are provided to optimize the operating cycles of the VDP circuit 52 and CPU circuit 51. Furthermore, providing a separate oscillator OSC1 can also improve the EMI countermeasures mentioned above.

With the above in mind, the VDP circuit 52 receives the oscillation output (40 MHz) of oscillator OSC2, which is separate from oscillator OSC1, at its PLLREF terminal, and multiplies the frequency in a PLL (Phase Locked Loop) circuit to produce the system clock for the VDP circuit 52. The frequency multiplication ratio of the PLL circuit is fixedly determined by the value set in a specific setting terminal. In this embodiment, the setting value in the setting terminal (3-bit PLLMD terminal) is a fixed value of 5, so the system clock for the VDP circuit 52 is 200 MHz (= 40 MHz x 5) (see Figure 14(b)).

In this embodiment, the dot clocks DCK _A to DCK _C that regulate the operation of the display circuits 74A to 74C and the DDR clock of the external DRAM 54 are also generated based on the oscillation output (40 MHz) of the oscillator OSC2. In other words, the output (40 MHz) of the oscillator OSC2 functions as a reference clock for the entire VDP circuit 52.

14 and 15, the display circuits 74A to 74C typically drive display devices with different specifications, and therefore the dot clocks DCK _A to DCK _C that define the operation of each of the display circuits 74A to 74C must correspond to the specifications of the display device to be driven. Based on this need, in this embodiment, the display circuits 74A to 74C are configured to receive one of the output clocks (DCLKAI to DCLKCI) of the dedicated oscillator circuits DCLKA to DCLKC and use that as the dot clock DCK _A to DCK _C.

When this configuration is utilized, there is no need to design the multiplication ratio and division ratio, which will be described later, or to set the VDP register RGij, and it is possible to easily optimize the frequencies of the dot clocks DCK _A to DCK _C. In other words, it is possible to provide a dedicated oscillator circuit DCLKA with an oscillation frequency F _DOT1 corresponding to the dot clock frequency F _DOT1 of the main display device DS1, and also to provide a dedicated oscillator circuit DCLKB with an oscillation frequency F _DOT2 corresponding to the dot clock frequency F _DOT2 of the sub-display device DS2.

However, when such a configuration is adopted, dedicated oscillator circuits are required corresponding to the number of display devices, making the equipment configuration complicated. Therefore, in this embodiment, in order to simplify the equipment configuration, the dot clocks DCK _A and DCK _B of the display circuits 74A and 74B are generated based on the oscillation output (40 MHz) of the oscillator OSC2. Specifically, as shown in Figure 14(b), for the display circuit 74A that drives the main display device DS1, the oscillation output (40 MHz) of the oscillator OSC2 is subjected to a predetermined multiplication process (x108) and division process (1/40) to generate the dot clock DCK _A with a frequency of 108 MHz.

Similarly, for the display circuit 74B that drives the sub-display device DS2, the oscillation output (40 MHz) of the oscillator OSC2 is subjected to a predetermined multiplication process (×108) and division process (1/160) to generate a dot clock DCK _B with a frequency F _dot = 27 MHz. Designing these multiplication and division ratios is quite complicated, and it would be easier to provide a dedicated oscillator circuit, but in this embodiment, emphasis is placed on simplifying the equipment configuration, so a dedicated oscillator circuit is not provided.

In any case, the dot clocks DCK _A to DCK _C are set individually for each of the display circuits 74A to 74C, but in this specification these dot clocks DCK _A to DCK _C may be collectively referred to as the "display clock DCK." In the following explanation, the dot clocks DCK _A and DCK _B may be abbreviated to the "dot clock DCK" for convenience.

In this embodiment, since a low-speed LVDS output configuration is not adopted, the LVDS clock CLK of the LVDS signal output via the display circuit 74A is also generated through the same process as the dot clock DCK _A and has a frequency of 108 MHz. However, since a dual link transmission path is adopted in this embodiment, the actual frequency of the LVDS clock CLK is 54 MHz, as explained in relation to Figure 4. If a single link transmission path is adopted, the frequency of the LVDS clock CLK is 108 MHz.

As described above, in this embodiment, the oscillation output (40 MHz) of oscillator OSC2 is used as the reference clock for the system clock, dot clock DCK, and DDR clock. Taking this importance into consideration, oscillator OSC2 is configured to operate at the same power supply voltage of 3.3 V as VDP circuit 52, and to oscillate and output the reference clock when output enable terminal OE is at H level (= 3.3 V). If the power supply voltage of 3.3 V were to fall below a predetermined level, normal performance operation would be impossible, and so a non-maskable interrupt (NMI) would be generated.

The composite chip 50 is also provided with an HBTSL terminal, and based on the logic level of the HBTSL terminal, it determines whether the boot program (initial setting program) executed after power-on (CPU reset) is stored in CGROM 55 (HBTSL = H) or in some other memory (HBTSL = L). As shown in the figure, in this embodiment, HBTSL is set to the L level, and address zero of the address space CS0 of the performance control CPU 63 is assigned to somewhere other than CGROM; specifically, address space CS0 is assigned to the control memory 53.

On the other hand, when the HBTSL terminal is set to the H level (see dashed line), address zero of the address space CS0 of the performance control CPU 63 is assigned to the CGROM 55. In this case, the memory type and bus width (64/32/16 bits) of the CGROM 55 are determined based on the input values to the 2-bit HBTBWD terminal and the 4-bit HBTRMSL terminal, respectively. These points will be discussed further below with reference to Figure 39.

Next, we will explain the CPUIF circuit 56, which relays data sent and received between the CPU circuit 51 and the VDP circuit 52. As shown in Figure 8(a), the CPUIF circuit 56 is connected to a control memory (PROM) 53 that stores control programs and necessary control data in a non-volatile manner, and a work memory (RAM) 57 with a storage capacity of approximately 2 MB, each of which is configured to be accessible from the CPU circuit 51. As explained above, the control memory (PROM) 53 is located in address space CS0 selected by chip select signal CS0, and the work memory (RAM) 57 is located in address space CS6 selected by chip select signal CS6.

This work memory (RAM) 57 has a DL buffer BUF for temporarily storing a display list DL containing a series of instruction commands that specify each frame of the display devices DS1 and DS2. In this embodiment, the series of instruction commands includes texture load commands such as the TXLOAD command for reading and decoding (expanding) image material (texture) from CGROM 55, texture setting commands such as the SETINDEX command, which have the function of specifying in advance the VRAM area (index space) to decode (expand), primitive drawing commands such as the SPRITE command for placing the decoded image material in a predetermined position in the virtual drawing space, environment setting commands such as the SETDAVR command and SETDAVF command for specifying the drawing area to actually draw on the display device from the images drawn in the virtual drawing space by the drawing commands, and index table control commands (WRIDXTBL) related to the index table IDXTBL that manages the index space.

Figure 12(c) shows the relationship between the virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), the drawing area that can be set arbitrarily within the virtual drawing space, and the actual drawing area in frame buffers FBa and FBb that temporarily store image data to be output to display devices DS1 and DS2.

Next, the CPU circuit 51 is a circuit with performance equivalent to a general-purpose one-chip microcomputer, and is composed of a performance control CPU 63 that comprehensively controls image performance based on the control program in the control memory 53, a watchdog timer (WDT) that forcibly resets the CPU if the program goes out of control, an internal RAM 59 with a storage capacity of approximately 16 kbytes that is used as the CPU's working area, a DMAC (Direct Memory Access Controller) 60 that enables data transfer without going through the CPU 63, a serial input/output port (SIO) 61 with multiple input ports Si and output ports So, a parallel input/output port (PIO) 62 with multiple input ports Pi and output ports Po, and an operation control register REG in which setting values are set to control the operation of each of the above components. However, in this embodiment, which is equipped with an external WDT circuit 58, the watchdog timer (WDT) built into the CPU circuit 51 is not utilized.

For convenience, the term "input/output port" is used in this specification, but in the performance control unit 23, the input/output port includes an input port and an output port that operate independently. This also applies to the input/output circuit 64p and the input/output circuit 64s described below.

The parallel input/output port 62 is connected to an external device (performance interface board 22) via the input/output circuit 64p, and the performance control CPU 63 receives the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB via the input circuit 64p. The 3-bit encoder output and the 1-bit switch signal are supplied to the parallel input/output port (PIO) 62 via the input/output circuit 64p.

Similarly, the received control command CMD is supplied to the parallel input/output port (PIO) 62 via the input/output circuit 64p. The strobe signal STB is also supplied to the interrupt terminal of the performance control CPU 63 via the input/output circuit 64p, thereby activating the reception interrupt process. Therefore, the performance control CPU 63, which has grasped the control command CMD based on the reception interrupt process, will perform a performance lottery and other operations to uniformly control the audio performance, lamp performance, motor performance, and image performance corresponding to this control command CMD.

Although not limited to this, in this embodiment, the SMC circuit (Serial Management Controller) 78 of the VDP circuit 52 is used for lamp and motor effects. The SMC circuit 78 is a composite controller incorporating an LED controller and a motor controller, and is configured to output serial signals in a clock-synchronized manner. The motor controller is also configured to output latch pulses at any timing based on the set value in a specific control register 70, and is also configured to input serial signals in a clock-synchronized manner.

In this embodiment, the motor drive signal and LED drive signal are output from the SMC circuit 78 in synchronization with the clock signal, while a latch pulse is output as the operation control signal ENABLE at an appropriate timing. Furthermore, the origin sensor signals SN0 to SNn from the performance motor groups M1 to Mn are configured to be input serially in clock synchronization.

As explained with reference to Figure 7(a), the clock signals CK0-CK2, drive signals SDATA0-SDATA2, and operation control signals ENABLE0-ENABLE2 are transmitted to the appropriate drive boards 30, 31, and 37 via output buffers 41-43. Furthermore, the origin sensor signals SN0-SNn are serially input from the motor lamp drive board 31 to the SMC circuit 78 via the input/output buffer 43.

However, in this embodiment, it is not necessary to use the SMC circuit 78. In other words, the CPU circuit 51 has a built-in general-purpose serial input/output port SIO61, which can also be used to execute lamp and motor effects.

Specifically, as shown by the dashed lines in Figure 8(a), in the configuration shown by the dashed lines, clock signals CK0-CK2 and drive signals SDATA0-SDATA2 are output via input/output circuit 64s internally connected to serial input/output port SIO61, and operation control signals ENABLE0-ENABLE2 are output via input/output circuit 64p. For convenience, these are referred to as input/output ports and input/output circuits, but it is the output ports and output circuits that actually function.

The serial output port SO is configured to incorporate a 16-stage FIFO register (see Figure 50 (a)). The DMAC circuit 60 is configured to start up upon receiving an operation start instruction (see Figure 22 (b) ST18) from the performance control CPU 63, read the necessary drive data in order from the lamp/motor drive table (see Figure 22 (b)), and transfer it via DMA to the FIFO register of the serial output port SO. The drive data accumulated in the FIFO register is output serially from the serial output port SO in a clock-synchronized manner. The DMAC circuit has multiple DMA channels (e.g., seven), and is configured to DMA transfer lamp drive data via the third DMA channel, which has the lowest priority, and DMA transfer motor drive data via the first DMA channel, which has the highest priority.

The operation control register REG built into the CPU circuit 51 is an 8-bit, 16-bit, or 32-bit register with a register number (address value) starting from 0xFF400000, and is configured to be accessible for write/read as appropriate from the performance control CPU 63 (see Figure 10). Therefore, due to the influence of noise, etc., there is a possibility that an unreasonable value may be set in the operation control register REG.

However, the combined chip 50 can be reset due to an abnormality, for example, by intentionally executing an infinite loop process and activating the external WDT circuit 58. In this case, the value of the operation control register REG is returned to the same default value (initial value) as after power-on, and the value of the VDP register RGij in the VDP circuit 52 is also returned to the default value (initial value), thereby resolving the abnormal state.

Figure 7(b) shows the circuit configuration related to this reset operation and is a diagram explaining the reset mechanism characteristic of this embodiment. Note that in this specification, the VDP register represented as RGij does not refer to the operation control register REG built into the CPU circuit 51, but rather to one of the control register group 70 (see Figure 10) that controls the internal operation of the VDP circuit 52. Also, the system control circuit 520 shown in Figure 7(b) refers to the internal control circuit of the VDP circuit 52 that functions based on the set value of the VDP register RGij (one of the control register group 70 in Figure 10) (see Figure 7(a)). Note that the VDP register RGij is located in address space CS7 selected by the chip select signal CS7 in the address map of the performance control CPU 63.

With the above in mind, the reset mechanism will be explained. As shown in Figure 7(b), the combined chip 50 is configured so that the internal circuitry can be reset via three OR gates G2 to G4, which receive the logically inverted system reset signal SYS bar. However, in this embodiment, as shown by the dashed line, the built-in WDT is not enabled, so the input and output terminals of OR gate G2 are directly connected.

In any case, a pattern check circuit CHK is provided between the CPU circuit 51 and the VDP circuit 52, and the pattern check circuit CHK is configured to output a reset signal RST upon receiving a predetermined keyword string (a reset code string) from the parallel input/output port (PIO) 62.

The internal circuitry of the combined chip 50 is divided into three parts: (1) the CPU circuit 51, (2) the display circuit 74 of the VDP circuit 52, and (3) the VDP circuit 52 other than the display circuit. Each part is configured to receive reset signals from the first to third reset paths via OR gates G2 to G4.

First, OR gate G2, whose input and output terminals are directly connected, is associated with the first reset path and is configured to reset the entire CPU circuit 51 based on the system reset signal SYS bar. Furthermore, OR gate G3 is associated with the second reset path and is configured to receive the system reset signal SYS bar and the reset signal RST from the pattern check circuit CHK, and to reset the entire VDP circuit 52 based on OR logic.

This second reset path is used not only for power reset operations when the power is turned on, but also when the performance control CPU 63 detects a specific abnormality and abnormally resets the entire VDP circuit 52 to return it to its initial state. Specifically, if a serious abnormality is determined to have occurred based on a specific status register RGij that indicates the internal operation of the VDP circuit 52, the pattern check circuit CHK generates a reset signal RST, causing the entire VDP circuit 52 to be abnormally reset. The display circuit 74 is also abnormally reset via the second reset path → third reset path via OR gate G4.

Meanwhile, the internal circuits built into the VDP circuit 52 are configured so that they can be individually reset when necessary via the fourth reset path. Internal circuits that can be individually reset include the index table IDXTBL, data transfer circuit 72, preloader 73, display circuit 74, drawing circuit 76, SMC circuit 78, and audio circuit SND shown in Figure 8(a), as well as the ICM circuit shown in Figure 13.

The method for achieving individual reset operations is as shown at the bottom of Figure 7(b). For example, the display circuit 74 is reset via the fourth reset path 4A → third reset path by writing the first reset value to a specific VDP register RGij (system command register).

Furthermore, each internal circuit (72, 73, 74, 76, SND, ...) of the VDP circuit 52 is individually reset by (1) writing a setting value identifying the target circuit to the first VDP register RGij (reset RQ register), and then (2) writing a second reset value to a specific VDP register RGij (system command register) (fourth reset path 4B). Although not used in this embodiment, the audio circuit SND can also be reset by writing a reset value to a specific VDP register (circuit setting command register) in addition to being reset via the fourth reset path 4B (fourth reset path 4C).

With the above configuration, this embodiment not only automatically returns the entire VDP circuit 52 to its initial state when power is turned on or a program crashes, but also allows individual components to be returned to their initial state as needed to recover from abnormal situations. For example, when the drawing circuit 76 freezes due to a period of no READ/WRITE access to the internal VRAM 71, the drawing circuit 76 is individually initialized via the fourth reset path 4B (see ST16a in Figure 22(d)). The same is true for the preloader 73 and data transfer circuit 72; when a specific abnormality occurs, the preloader 73 is initialized via the fourth reset path 4B (see ST27 in Figure 29), and the data transfer circuit 72 is initialized via the fourth reset path 4B (see ST27 in Figures 24 and 29).

Furthermore, if an underrun error occurs continuously in which the display data is not generated in time for the display timing every 1/60 seconds, the display circuit 74 is individually initialized via the fourth reset path 4A or the fourth reset path 4B (see ST10c in Figure 22). These individual reset operations will be described further below in relation to the program processing described in Figure 22 and subsequent figures.

The above describes the reset mechanism characteristic of this embodiment. When any of reset paths 1 to 4 functions and the internal circuit of the composite chip 50 is reset, the setting value of the VDP register RGij corresponding to that internal circuit returns to the same default value as after power-on.

Next, we will return to the internal configuration of the CPU circuit 51 and continue explaining its distinctive circuit configuration. Figure 9 is a block diagram showing the internal configuration of the CPU circuit 51 in some detail. In addition to the internal RAM 59, DMAC circuit 60, SIO 61, PIO 62, and WDT described above, the CPU circuit 51 is also configured to include many other distinctive circuits.

First, the CPU circuit 51 has a separate CPU fetch bus for instructions and a separate CPU memory access bus for data, realizing a Harvard architecture. As a result, there is no contention between the fetch operation by the CPU core (performance control CPU) 63 to read instructions from memory and the memory access operation, and high-speed processing is achieved by allowing the fetch operations to be performed continuously.

The CPU core 63 is also configured with multiple (e.g., 15) register banks RB0-RB14, and is configured so that its use can be selected. When register bank RBi is enabled for use, the register values (each 32 bits long) of the CPU's internal registers (e.g., 19 registers) are automatically saved to an empty register bank RBi at the start of interrupt processing.

Furthermore, when a specified restore command is executed at the end of interrupt processing, for example, 19 pieces of saved data are automatically restored to the corresponding internal registers. This eliminates the need to execute 19 PUSH commands at the start of interrupt processing and 19 POP commands at the end of interrupt processing, as is the case with conventional configurations, thereby achieving high-speed processing.

In addition, the CPU circuit 51 of this embodiment is equipped with an instruction cache memory 67, an operand cache memory 89, and a cache controller 69, thereby achieving Harvard cache operation. When accessing the same address, cached data is utilized, further speeding up program processing. Furthermore, the bus bridge 65, a controller for peripheral bus (1), a controller for peripheral bus (2), and a controller for peripheral bus (3) are provided, which appropriately connects the internal bus with peripheral bus (1), peripheral bus (2), and peripheral bus (3).

Next, in the circuit configuration of Figure 9, the bus state controller 66 operates based on appropriate settings in the operation control register REG to optimize memory READ and WRITE operations with various memory devices connected to the CPU circuit 51. Memory READ and WRITE operations are executed, for example, according to the operation timing illustrated in Figure 40, but the operation timing of the address data output from the address bus (28 bits), the READ data read to the READ data bus (32 bits), the WRITE data written to the WRITE data bus (32 bits), and control signals such as chip select signals CS0 to CS7 is appropriately specified in accordance with the characteristics of each memory device based on the settings in the operation control register REG.

Separate read and write data buses enable the high-speed operation achieved by the Harvard architecture described above. Note that in this specification, the address bus (28 bits), read data bus (32 bits), and write data bus (32 bits) are sometimes collectively referred to as the external bus to distinguish them from the internal bus shown in Figure 9 and peripheral buses (1) through (3).

Figure 10 illustrates the address spaces CS0 to CS7 selected by the chip select signals CS0 to CS7, and illustrates the address map for the performance control CPU 63, which is accessed via the bus state controller 66. First, each address space CS0 to CS7 is defined to have a maximum size of 64 MB (= 0x4000000H = 67108864).

As explained above, address spaces CS0 to CS7 represent external memory for the CPU circuit 51, which can specify the memory type (including whether it is volatile) and the data bus width (8/16/32 bits). In this embodiment, as shown in Figures 9(b) and 10, the control memory (PROM) 53 is located in address space CS0, the audio control register SRG of the audio processor 27 is located in address space CS3, the internal registers of the clock circuit 38 and the SRAM 39 are located in address space CS4, the external DRAM (DDR) 54 is located in address space CS5, the work memory 57 is located in address space CS6, and the VDP register RGij is located in address space CS7. Explanation of address spaces CS1 and CS2 will be omitted.

As can be seen from Figure 10, address space CS0 to CS7 is reserved not only for address values 0x00000000 to 0x1FFFFFFF (cache-enabled space), but also for address values 0x20000000 to 0x3FFFFFFF (cache-disabled space). This allows for optional selection of cache function utilization by disabling the cache based on the internal operation of the CPU circuit 51 when address bit A29 = 1, and enabling the cache when address bit A29 = 0.

For this reason, in this embodiment, of the 32-bit address information (bits A31 to A0), even if bit A29 is 1 or 0, as long as the values of the remaining 31 bits (bits A31 to A30 and bits A28 to A0) are the same, they will point to the same address in the same memory. For example, whether address 0x18000000 is accessed for READ or address 0x38000000, the same data will be read from address zero of work memory 57. Note that when address 0x18000000 is accessed for READ, the read data is saved in the cache; Figure 9(b) illustrates the access operation with the cache enabled/disabled.

However, it is also possible to disable cache operation for the instruction cache and/or operand cache based on the setting value of a specified operation control register REG. However, in this embodiment, after power-on, cache operation is enabled for the instruction cache and operand cache, and then cache operation is disabled as necessary by accessing the cache-disabled space.

Continuing with the explanation of the memory map in Figure 10, addresses 0x40000000 and above are internal memory space where the bus state controller 66 does not function, and addresses 0xF0000000 to 0xFF3FFFFF are allocated to the cache address array space. Addresses 0xFF400000 to 0xFFF7FFFF and 0xFFFC0000 to 0xFFFFFFFF are allocated to built-in peripheral modules, specifically the operation control register REG of the CPU circuit. The address range of the built-in RAM 59 is 0xFFF80000 to 0xFFFBFFFF.

Continuing with the explanation of the internal configuration of the CPU circuit 51, the compare match timer CMT and multifunction timer unit MTU are circuits that count external signals supplied to the CPU circuit 51 or count a count clock that is a multiplied or divided internal clock, and generate an interrupt signal or the like when the count result reaches a predetermined value. Although not limited to this, in this embodiment, the multifunction timer unit MTU is used to generate a 1 ms interrupt signal and a 20 μS interrupt signal. The multifunction timer unit MTU is also used to implement a clock timer TM that measures the elapsed time after the CPU is reset.

Next, the interrupt controller INTC is a circuit that receives internal interrupts from the VDP circuit 52, DMAC circuit 60, multifunction timer unit MTU, etc., as well as external interrupts such as IRQ_CMD, IRQ_SND, and IRQ_RCT, and activates interrupt processing (interrupt handlers) based on predefined priorities. Here, IRQ_CMD is a command reception interrupt signal that should receive the control command CMD, IRQ_SND is an end interrupt signal indicating that the audio processor 27 has completed the initialization sequence, and IRQ_RCT is an alarm interrupt signal.

In this embodiment, the command receive interrupt IRQ_CMD has the highest interrupt priority, followed by the 20 μS interrupt → 1 ms interrupt → interrupts from the VDP circuit (IRQ0, IRQ1, IRQ2, IRQ3) → DMAC interrupt → IRQ_SND → IRQ_RCT (see Figure 18 (d)). Note that all of these are maskable interrupts, and the non-maskable interrupt NMI is output to the performance control CPU 63 when the reference clock is not being output from the oscillator OSC2, as explained above.

In any interrupt processing, the register values (each 32 bits long) of the CPU's multiple internal registers are automatically saved to one of the free register banks RBi. Then, when a specified restore command is executed at the end of the interrupt processing, the saved data is automatically restored to the corresponding internal register.

Next, we will explain the DMAC circuit 60. The DMAC circuit 60 of this embodiment is a circuit that repeats data transfers from a transfer source (Source) to a transfer destination (Destination) in a specified DMA transfer mode for a specified number of times for each specified data transfer unit, based on the setting value of a specified operation control register REG. Multiple channels DMAC0 to DMACn with the same internal configuration are provided, and can operate in parallel. However, priorities are set (Channel 0 > ... > Channel n), and during parallel operation in channel arbitration operation mode, the operation of the DMACi with the highest priority is prioritized through channel arbitration at a specified timing.

As an example of how the DMAC circuit 60 is utilized, in an embodiment where the serial output port SO is functional (see the dashed line in Figure 10(a)), the operation control register REG of the CPU circuit 51 is specified with the starting address of the lamp/motor drive table (starting value of the source address), the address of the input register of the serial output port SO (fixed value of the destination address), the data transfer unit (8 bits), and the number of transfers. When a specific operation control register REG receives an instruction to start operation, the DMAC circuit 60 updates the source address while DMA transferring the drive data to the specific destination address. Once all DMA transfers have been completed, a DMAC interrupt (operation end interrupt) is generated.

This point is almost the same in the case of the embodiment (Figures 25 and 29(c)) in which the display list DL is issued by the DMAC circuit 60. That is, the performance control CPU 63 sets the starting address of the transfer source (DL buffer BUF), the address of the transfer destination (transfer port TR_PORT), the DMA transfer mode, the data transfer unit, the number of transfers, and other conditions in a predetermined operation control register REG of the CPU circuit 51. These points will be discussed further below in relation to Figure 25.

Generally, DMA transfer modes include cycle steal transfer mode, in which DMA operations do not occupy the memory bus, such as by releasing bus control during a unit DMA transfer operation (R operation/W operation); burst transfer (pipeline transfer) mode, in which bus control is not released until a specified number of transfers are completed, such as by performing multiple R or W operations in succession; and demand transfer mode, in which DMA operations continue as long as a DMA transfer request (demand) from another device is active. However, the DMAC circuit 60 of this embodiment functions in cycle steal transfer mode, which provides a memory release period of at least one cycle between read access activation (R operation) and write access activation (W operation) during DMA transfer, thereby preventing any interference with the operation of the performance control CPU 63.

Figure 11 is a diagram explaining cycle steal transfer operation (a1) and pipeline transfer (a2). As shown in Figure 11 (a1), the DMAC circuit 60 functioning in cycle steal transfer mode operates with at least one cycle between the read access activation (R) and write access activation (W) of one data transfer, and this empty cycle allows the performance control CPU 63 to use the bus. As is clear from the comparison between Figure 11 (a1) and Figure 11 (a2), in pipeline transfer the bus is not released to the CPU until one cycle (one operand transfer) is completed, whereas in cycle steal transfer mode the bus is released to the CPU after each read access, so CPU operation is not significantly delayed.

For example, in an embodiment in which the DMAC circuit 60 is used when issuing a display list DL to the VDP circuit 52, the data transfer unit (1 operand) for one cycle is set to 32 x 2 bits, and the source address of the internal RAM 59 in which the display list DL is stored is incremented appropriately (+8 for each operand transfer), and a DMA transfer operation is performed on the transfer port register TR_PORT (see Figure 13) of the data transfer circuit 72, which is specified by a fixed address.

As will be described later, in this embodiment, the required number of NOP (no operation) commands are added to the display list DL to adjust the overall data size to a fixed value (for example, 4 x 64 = 256 bytes, or an integer multiple thereof), and the issuance of the display list DL is completed by repeating 32-bit x 2 single operand transfers 32 times (or an integer multiple thereof). Note that even if the drawing circuit 76 executes a NOP command, it is in a no operation state, and in fact, no change occurs.

Furthermore, when classifying operating modes based on DMA transfer conditions, they can generally be considered as single operand transfer (see Figure 11 (b1)), consecutive operand transfer (see Figure 11 (b2)), and non-stop transfer (see Figure 11 (b3)).

Here, single operand transfer refers to an operating mode in which, as shown in Figure 11 (b1), one operand is repeatedly transferred each time a DMA transfer request is issued, and a DMA interrupt request is generated when the byte count, which counts the number of transferred bytes, reaches zero. Next, continuous operand transfer refers to an operating mode in which, as shown in Figure 11 (b2), DMA transfer is repeated with one DMA request until the byte count reaches zero.

In these continuous operand transfers (b2) and single operand transfers (b1), channel arbitration is performed each time one operand transfer is completed, and the current channel continues to transfer if there is no DMA request from a channel with a higher priority (channel arbitration operation mode). Therefore, in this embodiment, the single operand transfer method is used for issuing the display list DL to the VDP circuit and for DMA transfers of lamp drive data and motor drive data. Then, during parallel operation, the DMACi of the optimal channel is used to arbitrate channels with the priority of motor data > display list DL > lamp data, for example.

On the other hand, non-stop transfer is an operating mode in which channel arbitration is not performed, and as shown in Figure 11 (b3), DMA transfer is continuously repeated in response to a single DMA request until the byte count reaches zero. In this embodiment, programs and data are DMA transferred using non-stop transfer during the memory section initialization process (SP8 in Figure 16) when the power is turned on.

Now that we've explained the CPU circuit 51, we'll move on to the VDP circuit 52. Connected to the VDP circuit 52 are a CGROM 55 that stores compressed data that constitutes the still and moving images that make up the image presentation, an external DRAM (Dynamic Random Access Memory) 54 with a storage capacity of approximately 4 Gbit, the main display device DS1, and the sub-display device DS2. The DRAM 54 is preferably configured as DDR3 (Double-Data-Rate 3 SDRAM).

As shown in Figure 14(b), DRAM 54 receives a DDR clock generated based on the oscillation output (40 MHz) of oscillator OSC2. Furthermore, the DRAM 54 of this embodiment has a built-in refresh counter, and the self-refresh function is enabled during initial setup (SP4 in Figure 16), eliminating the need for refresh control operations by the performance control CPU 63.

In this embodiment, although not particularly limited, the CGROM 55 is configured as a flash SSD (solid state drive) made up of NAND flash memory with a storage capacity of approximately 62 Gbit, and is configured to obtain the required compressed data via serial transmission. This eliminates the problem of skew (differences in transmission speed for each bit of data) that inevitably occurs in parallel transmission, enabling extremely high-speed transmission operations. In this embodiment, although not particularly limited, the CGROM 55 is accessed at high speed using an HSS (High Speed Serial) method that complies with Serial ATA.

Whether or not it uses the Serial ATA-compliant HSS method, NAND-type flash memory is more mechanically stable than a hard disk and allows for high-speed access. However, because it is sequential access memory, it has problems with random access compared to DRAM or SRAM (Static Random Access Memory). Therefore, in this embodiment, a preload operation is performed in which a group of compressed data (CG data) is read into DRAM 54 prior to the drawing operation, thereby achieving smooth random access of CG data during the drawing operation. Incidentally, access speeds slow in the following order: built-in VRAM > external DRAM > CG ROM.

The VDP circuit 52, in detail, comprises a control register group 70 in which various operating parameters that define the operation of the VDP (Video Display Processor) can be set by the performance control CPU 63; an internal VRAM (video RAM) 71 of approximately 48 MB that is used when generating image data to be displayed on the display devices DS1 and DS2; a data transfer circuit 72 that transmits and receives data between various parts within the chip and with the outside of the chip; and a source and destination bus for the internal VRAM 71. a preloader 73 capable of executing a preload operation for accessing the CGROM 55 for reading prior to a drawing operation; a graphics decoder (GDEC) 75 for decoding (decoding and expanding/expanding) compressed data read from the CGROM 55; a drawing circuit 76 for generating one frame of image data for each of the display devices DS1 and DS2 by appropriately combining the decoded (expanded) still image data and moving image data; a geometry engine 77 for generating a three-dimensional image by appropriate coordinate conversion as part of the operation of the drawing circuit 76; The device is configured with three display circuits (A/B/C) 74A-74C capable of executing appropriate image processing in parallel, an output selection unit 79 that appropriately selects and outputs the output of the three display circuits 74 (A/B/C), an LVDS unit 80 that converts the image data output by the output selection unit 79 into an LVDS signal, an SMC circuit 78 that can send and receive serial data, a CPU IF unit 81 that relays data transmission and reception with the CPU IF circuit 56, a CG bus IF unit 82 that relays data reception from the CGROM 55, a DRAM IF unit 83 that relays data transmission and reception with the external DRAM 54, and a VRAM IF unit 84 that relays data transmission and reception with the built-in VRAM 71 (see Figure 8(a)). An audio circuit SND is also built in.

Figure 8(b) illustrates the relationship between the CPUIF unit 81, CG bus IF unit 82, DRAMIF unit 83, and VRAMIF unit 84 and the control register group 70, CGROM 55, DRAM 54, and built-in VRAM 71. As shown, CG data acquired from CGROM 55 is transferred, for example, as preload data to the preload area of the external DRAM 54 via the data transfer circuit 72 and DRAMIF unit 83.

However, the above-described preload operation is not a required operation, and the data transfer destination is not limited to the external DRAM 54, but can also be the built-in VRAM 71. Therefore, for example, in an embodiment in which the preload operation is not performed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and VRAM IF unit 84 (Figure 8(b)).

In this embodiment, the built-in VRAM 71 requires a decompression area for compressed data read from the CGROM 55, a frame buffer area for storing image data specifying the ARGB information (32 bits = 8 x 4) for each of the W x H display pixels of the display device, and a Z buffer area for storing depth information for each display pixel. In the ARGB information, A represents 8-bit alpha plane data, and RGB represents 8-bit data for the three primary colors.

The above-mentioned areas of the built-in VRAM 71 are indirectly accessed by the performance control CPU 63 based on the various instruction commands (such as the textures and sprites mentioned above) written in the display list DL, but it would be cumbersome to specify the destination address and source address of the built-in VRAM 71 for each READ/WRITE access. Therefore, in this embodiment, during the initial processing after a CPU reset, one-dimensional or two-dimensional logical address spaces (hereinafter referred to as index spaces) required for drawing operations are secured, and an index number is assigned to each index space, making it possible to access them based on the index number.

Specifically, after the CPU is reset, the internal VRAM 71 is roughly divided into three types of memory areas, and the required number of index spaces are reserved in each memory area. Then, by constructing an index table IDXTBL (see Figure 12(a)) that associates and stores index spaces with index numbers, subsequent operations based on the index numbers are realized.

This index space may need to be (1) added after initial processing, or (2) released. Therefore, a flag area FG is provided in the index table IDXTBL to determine whether the timing for the addition/release process is possible and whether the process has actually been completed when the performance control CPU 63 is operating. The built-in VRAM 71 is broadly divided into three types of memory areas: two AAC areas (a1, a2), a page area (b), and an optional area (c), as described below. The index table IDXTBL is divided into three sections corresponding to these three types of memory areas (a1, a2), (b), and (c) (Figure 12(a)). As shown in the figure, in this embodiment, a first AAC area (a1) and a second AAC area (a2) are secured as the AAC area (a), but this is not particularly limited, and either one may be used. In the following description, the first and second AAC regions (a1, a2) may be collectively referred to as AAC region (a).

In this embodiment, the built-in VRAM 71 is configured to be divisible into (a) an AAC area, which has a memory cache function and to which the index space and its index number are automatically assigned by internal processing; (b) a page area, in which the index space can be secured within a range of integer multiples of a two-dimensional unit space of, for example, 4096 bits x 128 lines; and (c) an arbitrary area, in which the start address (space start address) STx and horizontal size Hx can be set arbitrarily (see Figure 12(b)). However, to facilitate the internal operation of the VDP circuit 52, the space start address STx of the index space, which is arbitrarily set in the arbitrary area (c), must have the lowest 11 bits set to 0 and be in units of a specified number of bits (2048 bits = 256 bytes).

After the CPU is reset, the maximum address space required for each area and the area start address (lower 11 bits = 0) are specified, and the AAC area (a1), second AAC area (a2), and page area (b) are secured, with the remaining memory area becoming the optional area (c). To facilitate the internal operation of the VDP circuit 52, the maximum address space for the AAC area is specified in units of 2048 bits, and the maximum address space for the page area is an integer multiple of the unit space of 4096 bits x 128 lines mentioned above.

Next, the required number of index spaces are set in each of the areas (a1, a2), (b), and (c) thus secured. When using the optional area (c), in order to facilitate the internal operation of the VDP circuit 52, the horizontal size Hx of the index space that handles two-dimensional data can be set arbitrarily as a multiple of 256 bits, while its vertical size is a fixed value (for example, 2048 lines).

In any case, the first and second AAC areas (a1, a2) are automatically assigned index spaces and index numbers by the VDP circuit 52. Therefore, if the decoding destination is specified as AAC area (a) using the SETINDEX command, a texture setting command, for example, then the TXLOAD (texture load) command that reads CG data from CGROM 55 only needs to specify the source address of CGROM 55 and the horizontal and vertical size after expansion (decoding). Therefore, in this embodiment, the decoding destination for still images (textures) such as characters that appear temporarily during previews, and for I-stream video, is AAC area (a).

All of these AAC areas (a) are equipped with a memory cache function. For example, if the same texture from CGROM 55 is read into AAC area (a) multiple times, the decoded data cached in AAC area (a) can be used from the second time onwards, reducing unnecessary read accesses and decoding processes. However, since old data is automatically destroyed when AAC area (a) is used up, in this embodiment, when using AAC area (a), the first AAC area (a1) is used as a general rule, and only specific textures that are used repeatedly are stored in the second AAC area (a2).

Examples of textures that are used repeatedly include characters that appear repeatedly during a specific preview performance, or background images when the background screen is constructed with still images. In such cases, the SETINDEX texture setting command is used to set the decoding destination to the second AAC area (a2), and after the TXLOAD command is used to decode the texture of the characters, background images, etc. into the second AAC area (a2), the second AAC area (a2) is not used, thereby protecting the decoded results.

Then, after specifying the second AAC area (a2) as the decoding destination using the SETINDEX command, execute the same TXLOAD command to re-acquire the acquired texture. This results in a cache hit for the acquired texture, eliminating the need for a READ access to CGROM 55 and the time required for the decoding process. As will be described later, this cache hit function is also exhibited with preload data pre-fetched into the preload area, but the significance is that the preload data that hits the cache in the preload area is compressed data before decoding, whereas the cache hit in the AAC area is expanded data after decoding.

The term "texture" generally refers to the feel or texture of an object's surface, but in this specification it is used to include not only sprite image data that makes up a still image, image data that makes up a single frame of video, and image data pasted onto drawing primitives such as triangles and rectangles, but also image data after decode. When copying image data within the internal VRAM 71 (hereafter referred to as moving for convenience), the source image data is set as the texture using the SETINDEX texture setting command, and then the SPRITE command is executed.

When the SPRITE command is executed, the source Source image data is technically drawn in the virtual drawing space shown in Figure 12(c). However, if the correspondence between the drawing area in the virtual drawing space that is actually drawn on the display device and the index space that serves as the frame buffer is set in advance using environment setting commands (SETDAVR, SETDAVF) or texture setting commands (SETINDEX), then, for example, when the SPRITE command is used to draw in the virtual drawing space, the source Source image data will be drawn in a specified index space (frame buffer) (see Figure 12(c)).

In any case, in this embodiment, the built-in VRAM 71 is broadly divided into an AAC area (a1, a2), a page area (b), and an arbitrary area (c), and an appropriate number of index spaces can be allocated to each area. Each index space is identified by an independent index number for each area (a), (b), and (c). The index number is, for example, 1 byte long, and the performance control CPU 63 can freely assign index numbers in the range of 0 to 255 to the page area (b) and arbitrary area (c) (excluding the AAC area (a) which is automatically assigned by the internal circuitry).

In this embodiment, as shown in Figure 12(a), a pair of frame buffers FBa are reserved in the arbitrary area (c) for the display device DS1, and index numbers 255 and 254 are assigned to both of the double buffer structures. In other words, index space 255 and index space 254 are reserved as frame buffer FBa for the main display device DS1, and are used by switching between them in a toggle manner. Although not limited to this, these index spaces 255 and 254 have a horizontal size of 1280, corresponding to the number of horizontal pixels of the display device DS1. Note that each pixel is specified by 32 bits of ARGB information, so the horizontal size of 1280 means 32 x 1280 = 40960 bits (a multiple of 256 bits).

Furthermore, another pair of frame buffers FBb are reserved in the arbitrary area (c) for display device DS2, and index numbers 252 and 251 are assigned to both sides of the double buffer structure. In other words, index space 252 and index space 251 are reserved as frame buffer FBb for sub-display device DS2. These index spaces 252 and 251 have a horizontal size of 480, corresponding to the number of horizontal pixels of display device DS2. In this case, too, each pixel is specified by 32-bit ARGB information, so a horizontal size of 480 means 32 x 480 = 15,360 bits (a multiple of 256 bits).

The reason frame buffers FBa and FBb are reserved in the arbitrary area (c) is that the arbitrary area (c) can be set to any horizontal size as a multiple of 32 bytes (= 256 bits = 8 pixels), and as mentioned above, if it matches the number of horizontal pixels of display devices DS1 and DS2, no wasted space will be generated in the reserved area. On the other hand, the page area (b) can only be set to horizontal and vertical sizes that are integer multiples of the unit space of 128 pixels x 128 lines.

However, the two-dimensional index space secured in the arbitrary area (c) has a fixed vertical size (e.g., 2048 lines). Therefore, in the frame buffer FBa, only the area with a horizontal size of 1280 x vertical size of 1024 is the valid data area for the main display device DS1. The same is true for the sub-display device DS2, where in the frame buffer FBb, only the area with a horizontal size of 480 x vertical size of 800 is the valid data area for the sub-display device DS2 (see Figures 12(c) and 22(e)).

This point will be discussed further below, but in any case, frame buffers FBa and FBb alternate in double buffers (255/254, 252/251) as the drawing area for the drawing circuit 76, and alternate in double buffers (255/254, 252/251) as the display area for the display circuits 74A and 74B. Note that in this embodiment, a missing number (253) occurs because a Z-buffer for storing depth information for display pixels is not used. However, if a Z-buffer were used, the index spaces 253 and 250 of index numbers 253 and 250 in arbitrary area (c) would become the Z-buffers for display devices DS1 and DS2.

In addition, in this embodiment, when additional index space (memory area) is allocated in the arbitrary area (c) where frame buffers FBa and FBb are allocated, index numbers starting from 0 are assigned. Although not limited in any way, in this embodiment, index space (0) is allocated in the arbitrary area (c) as a working area for preview effects in which effect images made up of characters and other still images are made to appear in a part of the display screen in an appropriate rotated position as needed.

However, the use of a work area is not essential, and index space as a work area may be secured in the page area (b) instead of the arbitrary area (c). If the page area (b) is used, an index space with dimensions that are multiples of a square unit space of horizontal size ¹²⁸ (= 4096 bits) × vertical size 128 can be secured, making it suitable for handling small-sized effect images.

In this embodiment, the background images are also composed of moving images, and the image effects are realized almost entirely with moving images. In particular, during the variable effects, a large number of moving images (usually 10 or more) are simultaneously drawn. All of these moving images are stored in CGROM 55 in a compressed state as a series of moving image frames, and are classified as I-stream moving images consisting of only I-frames, and IP-stream moving images consisting of I-frames and P-frames. Here, an I-frame (Intra-coded frame) refers to a frame in which the input image is compressed as is, independently of other screens. On the other hand, a P-frame (Predictive-coded frame) refers to a frame that undergoes forward predictive coding, and requires an I-frame or P-frame located in the past in time.

Therefore, in this embodiment, IP stream video is expanded in the page area (b) rather than the AAC area (a), where there is a concern that old data may be destroyed. That is, a number of index spaces ( _IDX0 to _IDXN ) are secured in the page area (b), which can secure index spaces of dimensions that are multiples of 128 horizontal size and 128 vertical size, and a series of video frames are always decoded using the same index space IDXi corresponding to each video MVi. That is, video MV1 is expanded in index space IDX1, video MV2 is expanded in index space IDX2, and so on, with each video MVi being expanded in its own index space IDXi.

To explain video MVi more specifically, the SETINDEX command specifies in advance that "the decoding destination of IP stream video MVi is index space (i) of index number i in page area (b)," and then the TXLOAD command is executed to obtain one video frame of IP stream video MVi.

Then, one video frame (any of a series of video frames) on CGROM 55 specified by the TXLOAD command is first retrieved into AAC area (a), and then the GDEC (graphics decoder) 75, which starts automatically, decodes and expands the retrieved video frame into index space (i) in page area (b).

In this embodiment, however, I-stream video is treated the same as still images, and the SETINDEX command specifies that the I-stream video MVj's decoding destination is the first AAC area (a1), and the TXLOAD command is executed. As a result, video frames are acquired in the first AAC area (a1), and then the automatically activated GDEC 75 expands the decoded data to the first ACC area (a1). As explained above, the index space for the AAC area (a) is generated automatically, so there is no need to specify an index number. The expansion volume required for the index space, i.e., the horizontal and vertical sizes of the decoded texture (video frame), are specified by the TXLOAD command, regardless of whether the expansion destination is the AAC area (a) or the page area (b).

Incidentally, IP stream video MVi and I stream video MVj generally consist of N video frames (I frames and P frames). Therefore, the TXLOAD command specifies, for example, the source address of the CGROM 55 where the kth (1≦k≦N) video frame is stored, as well as the horizontal and vertical sizes after expansion. Although not limiting, in an embodiment in which still images are hardly used, most of the 48 MB address space (approximately 30 MB) of the built-in VRAM 71 is allocated to the page area (b). Furthermore, in an embodiment in which still images are hardly used, only the first AAC area (a1) is reserved as the AAC area, and the second AAC area (a2) is not reserved, and the cache hit function of the AAC area described above is not utilized.

It is also possible to provide a dedicated GDEC (graphics decoder) circuit to speed up the decoding process of compressed video data. If a dedicated GDEC circuit is built into the VDP circuit 52, then when decoding compressed video data consisting of N compressed video frames, it is sufficient to instruct the GDEC circuit on the starting address of the video compressed data, eliminating the need to specify the starting address for each of the N compressed video frames.

However, if multiple dedicated GDEC circuits like this were built in for each compression algorithm, the internal configuration of the VDP circuit 52 would become even more complex. Therefore, in this embodiment, a software GDEC is used, and decoding of data such as IP stream video, I stream video, still images, and other alpha values is achieved through software processing corresponding to each compression algorithm. Note that the difference in processing time between hardware processing and software processing is not a significant issue; the processing time that is an issue is mainly the access (READ) time from the CGROM 55.

Continuing with the explanation, returning to Figure 8(a), the data transfer circuit 72 is a circuit that performs data transfer operations in a DMA (Direct Memory Access) manner between a resource (storage medium) within the VDP circuit and an external storage medium, with these serving as the transfer source port and transfer destination port. Figure 13 is a block diagram showing the internal configuration of this data transfer circuit 72, along with the related circuit configuration.

As shown in Figure 13, the data transfer circuit 72 is configured to send and receive data to and from the CGROM 55, DRAM 54, and built-in VRAM 71 via the integrated connection bus ICM, which has a router function. The CGROM 55 and DRAM 54 are accessed via the CG bus IF unit 82 and the DMAMIF unit 83.

Meanwhile, the CPU circuit 51 issues a display list DL to the drawing circuit 76 and preloader 73 via the transfer port register TR_PORT built into the data transfer circuit 72. The CPU circuit 51 and data transfer circuit 72 are connected bidirectionally, but when issuing a display list DL, the transfer port register TR_PORT functions as a data write port that accepts one unit of data that makes up the display list DL. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits, corresponding to the FIFO structure of the CPU bus control unit 72d.

As shown in the figure, the performance control CPU 63 can perform WRITE access to the transfer port register TR_PORT via the CPUIF unit 81, but when the DMAC circuit 60 is used, the DMAC circuit 60 will perform WRITE access to the transfer port register TR_PORT directly. The series of instruction commands written to the transfer port register TR_PORT (i.e., the series of instruction commands that make up the display list DL) are automatically stored in 32-bit units in the CPU bus control unit 72d, which has a built-in FIFO buffer with a FIFO structure (32 bits x 130 stages).

The data transfer circuit 72 also performs data transmission and reception operations over the transmission paths of three channels ChA to ChC, and includes a ChA control circuit 72a (N=130 stages) with a FIFO buffer structure (64 bits x N stages), a ChB control circuit 72b (N=1026 stages), and a ChC control circuit 72c (N=130 stages).

The instruction command sequence (display list DL) stored in the CPU bus control unit 72d is then transferred to either the drawing circuit 76 or the preloader 73 based on the setting value of the data transfer register RGij (one of the various control registers 70) by the performance control CPU 63. As shown by the arrows, the display list DL is transferred from the CPU bus control unit 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b, and then to the preloader 73 via the FIFO buffer of the ChC control circuit 72c.

In this embodiment, the ChB control circuit 72b and the ChC control circuit 72c are specialized for the transfer of the display list DL, and the data stored in the FIFO buffer of the CPU bus control unit 72d is transferred as part of the display list DL to the drawing circuit 76 or the display list analyzer of the preloader 73 via the FIFO buffer of the ChB control circuit 72b or the ChC control circuit 72c, respectively.

The drawing circuit 76 then begins drawing operations based on the transferred display list DL. Meanwhile, the preloader 73 performs the necessary preload operations based on the transferred display list DL. The preload operation pre-reads CG data from CGROM 55 into a preload area allocated in DRAM 54, and the display list DL with the texture source address changed for the TXLOAD command, etc. (hereinafter referred to as the rewrite list DL') is saved in the DL buffer area BUF' allocated in DRAM 54.

Meanwhile, the ChA control circuit 72a and the connection bus access arbitration circuit 72e function to transfer data between storage media such as the CGROM 55, DRAM 54, and built-in VRAM 71. Furthermore, the IDXTBL access arbitration circuit 72f functions when accessing the built-in VRAM 71, which requires address information from the index table IDXTBL. Specifically, the ChA control circuit 72a functions, for example, when (a) compressed data from the CGROM 55 is transferred to the built-in VRAM 71, (b) compressed data from the CGROM 55 is preloaded (read ahead) and transferred to the external DRAM 54, and (c) data read ahead from the preload area is transferred to the built-in VRAM 71.

Here, the ChA control circuit 72a is configured to be able to operate in parallel with the ChB control circuit 72b and the ChC control circuit 72c, and the operations (a) to (c) described above can be executed in parallel with the issuance operation of the display list DL (ST8 in FIG. 22, PT11 in FIG. 27) and the transfer operation of the rewrite list DL' (PT10 in FIG. 27). The ChB control circuit 72b and the ChC control circuit 72c can also be executed simultaneously. For example, the processing of step PT10 in FIG. 27, in which the ChB control circuit 72b functions, and the processing of step PT11, in which the ChC control circuit 72c functions, can be executed in parallel. However, because there is only one transfer port register TR_PORT, when one of them (72b/72c) is using the transfer port register TR_PORT, the other (72c/72b) cannot access the transfer port register TR_PORT.

When the ChA control circuit 72a is operating, the connection bus access arbitration circuit 72e arbitrates data transmission with each storage element (CGROM 55, DRAM 54) via the integrated connection bus ICM. Meanwhile, the IDXTBL access arbitration circuit 72f arbitrates data communication with the built-in VRAM 71 by controlling the ChA control circuit 72a based on the index table IDXTBL. In an embodiment in which the preloader 73 is functioning, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b (see Figure 28(b)).

As described above, the data transfer circuit 72 of this embodiment realizes high-speed data transfer between a data transfer source arbitrarily selected from various storage resources (Resources) and a data transfer destination arbitrarily selected from various storage resources (Resources). As can be seen from Figure 13, the storage resources on which the data transfer circuit 72 functions include not only the built-in VRAM 71, but also external devices via the CPU IF unit 56, CG bus IF unit 82, and DRAM IF unit 83.

Furthermore, the amount of data transferred between the external device in which the ChA control circuit 72a functions, such as the amount of data to be acquired at one time from the CGROM 55 (memory sequential READ), is enormous compared to the display list DL in which the ChB control circuit 72b and ChC control circuit 72c function, and the data transfer amounts differ greatly.

It is possible to configure these various types of data transfers so that the unit data volume and total transfer data volume can be precisely set, but this would complicate the control operations within the VDP and hinder smooth transfer operations. Therefore, in this embodiment, a minimum data volume Dmin for data transfer is uniquely defined, and the total transfer data volume is limited to an integer multiple of the minimum data volume DTmin, thereby achieving fast and smooth data transfer operations. Although not particularly limited, in the data transfer circuit 72 of this embodiment, the minimum data volume Dmin (unit data volume) is set to 256 bytes, and the total transfer data volume is limited to an integer multiple of this.

Therefore, the display list DL instruction command sequence stored in the FIFO buffer of the CPU bus control unit 72d in 32-bit increments is transferred to the ChB control circuit 72b and ChC control circuit 72c when the total amount reaches the minimum data amount Dmin, and is then stored in the respective FIFO buffers.

The display list DL is made up of a series of instruction commands. In this embodiment, the display list DL is made up of only instruction commands whose command length is an integer multiple of 32 bits (N > 0), corresponding to the write unit (32 bits) of the transfer port register TR_PORT. Therefore, the drawing circuit 76 and preloader 73, which receive the instruction commands of the display list DL via the data transfer circuit 72, can quickly and smoothly start the command analysis process (DL analyze). Note that the command length of an integer multiple of 32 bits does not necessarily mean that all of the bits are significant, but also includes insignificant bits (don't care bits), meaning that it is an integer multiple of 32 bits.

Next, the preloader 73 will be described. As outlined above, the preloader 73 is a circuit that interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72c) and transfers the CG data in CGROM 55 referenced by the TXLOAD command to the preload area of DRAM 54 in advance. Furthermore, the preloader 73 stores a rewrite list DL' in the DL buffer BUF' of DRAM 54, in which the reference destination of the CG data for this TXLOAD command is rewritten to the address after transfer. The DL buffer BUF' and preload area are reserved in advance during the initial processing after the CPU is reset (SS3 in Figure 21).

The rewrite list DL' is then transferred to the display list analyzer (DL Analyzer) of the drawing circuit 76 via the connection bus access arbitration circuit 72e and ChB control circuit 72b of the data transfer circuit 72 when the drawing operation of the drawing circuit 76 begins. The drawing circuit 76 then executes the drawing operation based on the rewrite list DL'. Therefore, based on a TXLOAD command or the like, CG data that should normally be obtained from the CGROM 55 is instead obtained from the preload area of the DRAM 54 as preload data that has been preloaded into the preload area. In this case, the preload data can be used repeatedly unless it is overwritten and erased, and preload data that hits the cache in the preload area is repeatedly reused.

In this embodiment, the preload area is set in the external DRAM 54, which has sufficient storage capacity, so the cache hit function described above functions effectively. Furthermore, because the external DRAM 54 has a large storage capacity, multiple preloading, for example, is also possible, in which multiple frames of CG data are preloaded at once. In other words, multiple preloading is achieved by appropriately setting the operating period of the preloader 73, which is a series of preloading operations including the CG data prefetching operation, within the range of an integer multiple of the operating cycle δ of the VDP circuit 52 during intermittent operation.

However, for the sake of convenience, the following explanation will be based on an embodiment without multiple preloading, and the preloader 73 in this embodiment will complete the preloading operation for one frame during one operation cycle (δ). As will be described later with reference to FIG. 22, in this embodiment, the operation cycle δ during intermittent operation of the VDP circuit 52 is 1/30 seconds, which is twice the period of the vertical synchronization signal of the display device DS1.

Next, the drawing circuit 76 sequentially analyzes the instruction command sequences of the display list DL and rewrite list DL' transferred via the data transfer circuit 72, and works in conjunction with the graphics decoder 75 and geometry engine 77 to draw one frame's worth of image for each display device DS1, DS2 in the frame buffer formed in the VRAM 71.

As described above, in an embodiment in which the preloader 73 is activated, the CG data in the rewrite list DL' is referenced not to the CGROM 55 but to the preload area set in the DRAM 54. This allows for rapid sequential access to CG data that occurs while the drawing circuit 76 is drawing, making it possible to draw high-resolution moving images with rapid movement without any problems. In other words, according to this embodiment, complex and sophisticated image presentations can be achieved while utilizing an inexpensive SATA module as the CGROM 55.

Regarding whether the preloader 73 is enabled or disabled, even if data corruption occurs during the transfer of the display list DL or rewrite list DL', the drawing circuit 76 will not be able to detect this. Furthermore, noise or other factors may cause the drawing circuit 76 to freeze, resulting in an abnormal halt to READ/WRITE access to the internal VRAM 71. Therefore, in this embodiment, if the drawing circuit 76 detects an irrational instruction command (a bit sequence that cannot be analyzed) or if there is no READ/WRITE access to the internal VRAM 71 for a certain period of time, a drawing abnormality interrupt is generated (drawing abnormality interrupt is enabled). This point will be discussed later with reference to Figure 22(d).

Next, as explained with reference to Figure 12, the frame buffer FB allocated in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a readout area, with the two areas being used alternately. Furthermore, in this embodiment, since two display devices DS1 and DS2 are connected, two frame buffers FBa/FBb are allocated, as shown in Figure 12. Therefore, the drawing circuit 76 draws one frame's worth of image data in the drawing area (write area) of the frame buffer FBa for display device DS1, and also draws one frame's worth of image data in the drawing area (write area) of the frame buffer FBa for display device DS2. Note that while image data is being written to the drawing area, the display circuit 74 reads out the image data from the other readout area (display area) and outputs it to each display device DS1 or DS2.

The display circuit 74 reads image data from frame buffers FBa and FBb, performs final image processing, and outputs the result (see Figure 14(a)). Final image processing includes, for example, scaling by a scaler to enlarge or reduce the image, subtle color correction, and dithering to minimize quantization error across the entire image. The digital RGB signal (24 bits in total) that has undergone this image processing is then typically output along with a horizontal synchronization signal HS, a vertical synchronization signal VS, and so on.

As shown in Figure 14(a), this embodiment is provided with three display circuits A/B/C that perform the above operations in parallel, and each display circuit 74A-74C reads image data from its corresponding frame buffer FBa/FBb/FBc and performs the above final image processing. However, since this embodiment has two display devices, frame buffer FBc is not reserved and display circuit 74C does not function.

Checking the specifications of the main display device DS1, we see that the main display device DS1 must receive adjacent odd-numbered pixels (ODD) and even-numbered pixels (EVEN) in the horizontal direction via separate LVDS (Low Voltage Differential Signaling) transmission paths at the receiver RV (RVa + RVb). Furthermore, the frequency of the main display device DS1's operating clock CK must be approximately 40-70 MHz (typically 54 MHz), and the horizontal and vertical wait times WTh/WTv must be set so that (WTh + 640) x (WTv + 1024)/54 MHz ≒ 1/60 seconds. Furthermore, when outputting image data (ODD/EVEN signals) to the main display device DS1, an active-level data enable signal ENAB must be output.

Therefore, the display circuit 74A must output signals that meet all of the above specifications. Figures 15(a) to 15(e) illustrate the various signals output from the display circuit 74A. First, the frequency of the dot clock (LVDS clock) DCK must be determined. In this embodiment, the main display device DS1 operates on an operating clock CK with a typical value of 54 MHz, so the designed dot clock DCK (in the VDP circuit 52) is set to 108 MHz (= 54 x 2) accordingly.

This is because, on a display panel LCD (see Figure 15(f)) with 1280 horizontal dots and 1024 vertical lines, two adjacent pixels on the left and right are processed at once in synchronization with a 54 MHz operating clock CK, which is essentially equivalent to operating with a 108 MHz dot clock DCK.

The various operating parameters that define the operation of the display circuit 74A are determined based on a dot clock DCK with a frequency of 108 MHz. First, the horizontal and vertical waiting times WTh/WTv must be set so that (WTh + 640) x (WTv + 1024)/54 MHz ≒ 1/60 seconds. However, the operating parameters WTh and WTv for the display circuit 74A must satisfy (WTh + 1280) x (WTv + 1024)/108 MHz ≒ 1/60 seconds.

Furthermore, the tolerance range of the display device DS1 specifications for the horizontal and vertical wait times WTh/WTv must also be taken into consideration. Therefore, in this embodiment, the horizontal wait time WTh is counted using a 108 MHz dot clock DCK, and is set to 382 clocks, and the vertical wait time WTv is set to 59 lines. Therefore, the time required to update one frame of image is (382 + 1280) x (59 + 1024) / 108 MHz = 16.666 mS, and the frame rate FR (Frame Rate) is 1/60 seconds.

This relationship defines the update period FR [seconds] of the display device DS1, and is expressed as FR = THc × TVl/ _Fdot , where _Fdot is the frequency of the dot clock DCK, THc is the number of horizontal synchronization cycles, and TVl is the number of vertical synchronization lines, as described below. If the update period FR is too long, there is a risk of abnormalities such as flickering, whereas if the update period FR is too short, the display device will not be able to perform normal update processing. Therefore, the update period FR should be defined in the range 0.95/60 < FR [seconds] < 1.05/60.

Corresponding to this setting, the data valid signal ENAB is at the L level during the wait time WTh (=382/108 MHz) corresponding to 382 clocks during the image update operation for each line, and then becomes active (H) during the active interval (=1280/108 MHz) corresponding to 1280 clocks (FIG. 15(c)). As shown in FIGS. 15(d) and 15(e), during the active interval of the data valid signal ENAB, image data is output so that the image update operation for one line of 1280 dots of pixels is completed within a predetermined time (11.85 μS = 1280/108 MHz). That is, 1280 pieces of pixel data are output in synchronization with 1280 dot clocks DCK. Since the display device DS1 displays a full-color image with a gradation of ²⁸ × ²⁸ × ²⁸ , the pixel data for one pixel is 3 × 8 bits long.

In this embodiment, the main display device DS1 outputs a vertical synchronization signal VS and a horizontal synchronization signal HS, even though they are not required. The vertical synchronization signal VS is output within the vertical wait time WTv, and the horizontal synchronization signal HS is output within the horizontal wait time WTh. For ease of understanding, Figures 15(a) and 15(b) show the respective operating cycles. Also, Figure 15(f) shows a rectangular frame defined by TH x TV (= 1083 x 1662 clocks) with circles at the top left and bottom right vertices, indicating "Start of display operation" and "End of display operation." These circles represent "V blank start," which defines the operating cycle of the display circuit 74A, which starts every 1/60 seconds. Since the 1083 x 1662 clock that defines the display operation coincides with 1/60 seconds, the elapsed time from the "start of display operation" to the "end of display operation" (the operating cycle of the display circuit 74A) is 1/60 seconds. Note that "V blank start" will be discussed later with reference to Figure 22.

Returning to Figure 14, the output selection unit 79 of this embodiment divides the output signal of the display circuit 74A into dual links by dividing the 108 MHz dot clock DCK by two, and transmits them to the LVDS units 80a and 80b, respectively (see Figures 14(a) and 5). Each LVDS unit 80a, 80b then converts the image data (a total of 24-bit digital RGB signals) into first and second LVDS signals, adds a pair that transmits a clock signal (54 MHz = 108/2), and outputs a total of five pairs of differential signals LVDS1, LVDS2 via two paths to the main display device DS1 (see Figure 14(a) and 4).

As explained earlier, in the main display device DS1, the ODD signal for one pixel and the EVEN signal for the adjacent pixel are processed at the same time, so the frequency of the actual operating clock CK matches the 108 MHz dot clock DCK output by the display circuit 74A.

The above describes the display circuit 74A, which generates images to be transmitted to the main display device DS1. The display circuit 74B generates image data to be transmitted to the sub-display device DS2. The digital RGB signal output by the display circuit 74B is supplied to the digital RGB section 80c via the output selection section 79, and is transmitted to the sub-display device DS2 along with the vertical synchronization signal VS and horizontal synchronization signal HS.

In addition to the synchronization signals VS and HS, the data valid signal ENAB is also transmitted via the digital RGB section 80c, but of course these signals are transmitted as continuous signals rather than as discrete values as in the case of an LVDS transmission line (see Figure 14(a)).

In this embodiment, each display circuit 74A-74B is provided with an underrun counter URCNTa-URCNTc that counts underrun abnormalities, which occur when display data is not generated in time for the display timing (see Figure 15). The counter values of these underrun counters URCNTa-URCNTc are configured to be automatically incremented for each VBLANK when an underrun abnormality occurs.

Next, the SMC circuit 78 (Serial Management Controller) is a composite controller incorporating an LED controller and a motor controller. It outputs LED drive signals and motor drive signals in synchronization with a clock signal to an LED/motor driver (a driver IC incorporating a shift register) mounted on an external board, while also being able to output latch pulses at appropriate timing.

Regarding the internal circuitry and operation of the VDP circuit 52 described above, the operations to be performed by the internal circuitry are defined by operational parameters (setting values) set in the control register group 70 by the performance control CPU 63, and the execution state of the VDP circuit 52 can be determined by reading the operational status values of the control register group 70. The control register group 70 refers to the numerous VDP registers RGij mapped to an address space of approximately 1 MB (0-FFFFFH) on the memory map of the performance control CPU 63, and the performance control CPU 63 writes (sets) operational parameters and reads operational status values via the CPUIF unit 81 (see Figure 8(b)).

The control register group 70 (VDP register RGij) includes a "system control register" in which initial settings related to system operations such as interrupt operations are written, and an AAC area (a) and a page area (b) in the built-in VRAM. The registers include an "index table register" for determining the index table IDXTBL and for constructing or modifying it, a "data transfer register" for writing settings related to the data transfer process by the data transfer circuit 72 between the performance control CPU 63 and the internal circuitry of the VDP circuit 52, a "GDEC register" for specifying the execution status of the graphics decoder 75, a "drawing register" for writing instruction commands and settings related to the drawing circuit 76, a "preloader register" for writing settings related to the operation of the preloader 73, a "display register" for writing settings related to the operation of the display circuit 74, an "LED control register" for writing settings related to the LED controller (SMC circuit 78), a "motor control register" for writing settings related to the motor controller (SMC circuit 78), and an "audio control register SRG" for writing settings related to the audio circuit SND. However, in this embodiment, the audio circuit SND is not used.

In any case, in the following explanation, one or more registers RGij included in the control register group 70 will be referred to either by the individual names mentioned above or collectively as VDP registers RGij. In either case, the performance control CPU 63 controls the internal operation of the VDP circuit 52 by writing appropriate setting values to specific VDP registers RGij. Specifically, the performance control CPU 63 realizes specific image effects based on the display list DL, which is updated at appropriate time intervals, and the setting values in the specific VDP registers RGij. In this embodiment, the performance control CPU 63 is responsible for lamp effects and motor effects as well, so the VDP registers RGij also include LED control registers and motor control registers.

Next, we will explain the unified control operation of image effects, audio effects, motor effects, and lamp effects, which is realized by the composite chip 50 incorporating the above-mentioned CPU circuit 51 and VDP circuit 52.

In this embodiment, the operation of the composite chip 50 is initiated by a power-on reset operation (see Figure 16(a)) caused by power-on or abnormal reset, and is configured to transition through initial setup processing (SP1-SP9) by the initial setup program (boot program) Pinit, and then to main control processing (SP10) by the performance control program Main and the interrupt processing program (vector handler) Vopt. The introductory part of the main control processing is described in Figure 18(a), and the main part of the main control processing is described in Figure 22(a). Note that the processing of step SP27 in Figure 18 does not include the processing of steps SS1-SS3 in Figure 21(a).

Based on the above, the power-on reset operation will be explained with reference to Figure 16(a). When the system reset signal SYS remains at the L level for a predetermined period (assertion period), such as when power is turned on, all operation control registers REG and all VDP registers RGij are automatically set to predetermined default values.

Then, when the system reset signal SYS subsequently changes to H level (negate level) (see timing T1 in Figure 6(d)), in this embodiment, the clock timer TM (Figure 9(a)) starts operating to measure the elapsed time after the CPU reset (SP1). Also, 32-bit data from the first address of address space CS0 is set in the program counter PC of the performance control CPU 63, and the following 32-bit data is set in the stack pointer SP (SP1). In Figures 10 and 17(c), the top area of memory that stores the initial values of the program counter PC and stack pointer SP is called the vector table VECT.

As shown in Figure 16(b), this vector table VECT stores vector numbers that specify priority and interrupt causes, etc., in association with address information. The smaller the vector number, the higher the priority. For example, vector number 11 is a non-maskable interrupt (NMI), and the address information stored therein is the start address of the interrupt processing program executed upon an NMI interrupt. Furthermore, vector number 64 is an internal interrupt from the VDP (VDP_IRQ0), and the address information stored therein is the start address of the interrupt processing program executed upon a VDP_IRQ0 interrupt.

The interrupt priorities are as shown in Figure 18 (d), so the columns for vector numbers smaller than vector number 64 store the start addresses of the interrupt processing programs for the control command receive interrupt IRQ_CMD, the 20μS timer interrupt, and the 1mS timer interrupt. On the other hand, the columns for vector numbers larger than vector number 64 store the start addresses of interrupt processing programs (IRQ_SND, IRQ_RTC, etc.) with a lower priority than VDP_IRQ 1.

In addition, the vector table VECT specifies the values for vector number 0 and vector number 1 to be automatically set in the CPU's program counter and stack pointer upon power-on reset. As shown in Figure 16(b), in this embodiment, the internal operation upon power-on reset (reset assertion period) is to set 4-byte data "****" in the program counter PC and 4-byte data "++++" in the stack pointer SP. Note that "****" is the starting address value of the initialization program Pinit (SP1 to SP9 in Figure 16) stored non-volatilely in address space CS0, and "++++" is the address value of the beginning or end of the stack area allocated in internal RAM 59, which functions in a LIFO (Last-In First-Out) manner.

In this embodiment, the register bank RBi is used effectively, so stack space is not consumed during interrupt processing, and so significant memory capacity is not required. In other words, in this embodiment, the stack space is used exclusively for function processing and subroutine processing.

As a result of the above operations, the performance control CPU 63 will then execute the initial setting program Pinit, which is written after the address value "****". However, the memory READ operation for address space CS0 is executed based on the default value (initial value) of the operation control register REG, which defines the operation of the bus state controller 66 (Figure 9). The initial value of this operation control register REG is a value that is automatically set during the reset assertion period (the period shown in Figure 7(d) when the system reset signal SYS maintains an L level), and is set to the slowest READ access operation (default access operation) so that address space CS0 can be accessed without any problems, regardless of the memory device it is configured with.

To change this default access behavior to the optimal access behavior, an optimal value is first set in a specific operation control register REG, which defines the operation of the bus state controller 66 (Figure 9) for address space CS0 (SP1). That is, to optimize the memory READ operation when accessing PROM 53, which stores the initial setting program Pinit (SP1-SP9), performance control program MainB (SP10 and following), constant data, etc., to suit the memory device, the bus width and whether or not page access is enabled are set, and the operation timing of the chip select signal CS0, READ control signal, WRITE control signal, and other signals are optimally set (see Figure 40).

As a result of the above settings, processing from step SP2 onwards will be executed by optimally reading the program stored in address space CS0 from memory. Next, the performance control CPU 63 sets an optimal value in a specified operation control register REG that defines the operation of the bus state controller 66 (Figure 9) for VDP register RGij, in order to optimize the READ/WRITE access operation when accessing VDP register RGij (SP2).

As explained above, in this embodiment, the VDP register RGij is located in the address space CS7 of the performance control CPU 63, so a predetermined value is written to a predetermined operation control register REG to optimally set the operation timing of the chip select signal CS7 and other control signals.

Next, the register value of a specific VDP register RGij is read, and it is determined whether this value is a predetermined value (device code) (SP3). This is a confirmation that the system clock of the VDP circuit 52 has stabilized. In other words, the VDP circuit 52 operates based on the oscillation output of oscillator OSC2 supplied to the PLLREF terminal, and this is a determination of whether the VDP circuit 52 can normally accept commands from the CPU circuit 51 (i.e., settings to the VDP register RGij, etc.).

Then, once it is confirmed that the system clock has stabilized through the device code read process (SP3), normal operation of the VDP circuit 52 can be expected, and the setting process for the specified VDP register RGij is executed (SP4-SP6). In the process of step SP4, first, the endian setting (big/little) and data bus width when accessing the VDP register RGij from the performance control CPU 63 are set (SP40), and the interrupt significance level (H/L) for the internal interrupts (VDP_IRQ0, VDP_IRQ1, VDP_IRQ2, VDP_IRQ3) from the VDP circuit to the CPU circuit is set (SP41).

In this embodiment, the most significant bit of the setting value is set to big endian, which stores it in the most significant bit of the VDP register RGij, and the data 32 bus width is set to 32 bits. However, if these setting values are the same as the default values, these setting processes can be omitted (the same applies to the following processes).

Furthermore, in the processing of step SP4, the frequency of the display clock is set based on the value set in a predetermined system control register RGij (SP42-SP44). Specifically, for display circuits 74A and 74B, the generation of dot clocks DCKA and DCKB based on the 40 MHz reference clock (output of oscillator OSC2) is set in the predetermined system control register RGij (SP42), and the multiplication ratio and division ratio for this reference clock are specified appropriately for each display circuit (SP43). Furthermore, the start of operation of display circuit 74B is set in the predetermined system control register RGij to synchronize with the start of operation of display circuit 74A (SP44). Furthermore, the LVDS sampling clock is set to the same as the dot clock DCKA of display circuit A (SP43).

In this process, the dot clock DCK is set separately for display circuit 74A and display circuit 74B, and the frequency of the dot clock DCKA for the main display device DS1 applied to display circuit 74A is set to 108 MHz, as explained above. On the other hand, the frequency of the dot clock DCKB for the sub-display device DS2 applied to display circuit 74B is set to 27 MHz, corresponding to 480 horizontal x 800 vertical pixels.

Furthermore, in the processing of step SP4, the LVDS unit 80 is set to be used as a dual link (a pair of LVDS transmission paths) (SP45), and based on the setting value of a predetermined system control register RGij, the operating state of the LVDS unit 80 is switched from a masked state (Default state) that outputs zero to an unmasked state that follows the output of the display circuit 74 (SP45). Note that if the LVDS unit 80 is to be used as a single link (a single LVDS transmission path), the processing of step SP45 will set it accordingly.

As shown in FIG. 6(f), as a result of the processing of step SP45, the operation of the LVDS unit 80 switches from the default state to the non-masked state. After that, after timing T4 when the display circuit 74 starts operating (see SS4 in FIG. 21), the ODD signal and EVEN signal are supplied to the LVDS units 80a and 80b via the output selection unit 79, and the LVDS signal (LVDS1/LVDS2) is transmitted to the display device DS1 via the dual link (see FIG. 14(a)). Note that the LVDS sampling clock is set to 108 MHz, the same as the dot clock DCKA of display circuit A. However, since this embodiment uses a dual link configuration, the LVDS sampling clock in each dual link is 54 MHz (see FIG. 4).

Furthermore, in the processing of step SP4, a setting is made to operate the DDR (DRAM 54) based on the clock signal (reference clock) to the PLLREF terminal (see FIG. 8(a)) (SP46). As explained with reference to FIG. 8(a), the reference clock from oscillator OSC2 is supplied to the PLLREF terminal. Furthermore, by setting appropriate values in a register built into the DDR (DRAM 54), the self-refresh function of the DRAM 54 is enabled, and other settings are made to ensure normal operation of the DRAM 54 (SP47). Through the above processing, the DRAM 54 is placed in a state where it can operate normally, and the subsequent data transfer operation from PROM 53 to DRAM 54 (SP8) and the execution of the control program transferred to the DRAM 54 (SP10) are realized without any problems.

Next, address spaces CS1 to CS6 are defined to realize the memory map shown in Figure 10 (SP5). As explained above, address space CS3 is assigned to the internal registers of the audio processor 27, address space CS4 is assigned to the internal registers of the RTC 38 and the address space of the SRAM 39, address space CS5 is assigned to the external DRAM (DDR) 54, and address space CS6 is assigned to the work memory 57 of the built-in CPU.

Note that since it is fixedly specified that VDP register RGij is assigned to address space CS7, there is no need to define address space CS7. Furthermore, it is fixedly specified in advance that address space CS0 is from address 0x000000000 onwards in the memory map of the CPU circuit 51. Based on this specification, whether address space CS0 is secured in CGROM 55 or assigned to another memory device is specified by the H/L level of the HBTSL terminal.

As explained earlier, in this embodiment, the HBTSL terminal is set to L, indicating that address space CS0 is defined in addition to CGROM 55. Furthermore, since the specific bus width and optimal access operation for control memory 53, which is other than CGROM 55, have already been set in step SP1, processing in step SP5 is not required for address space CS0 either.

Next, for the address spaces CS1 to CS6 defined in step SP5, predetermined values are written to a predetermined operation control register REG regarding the bus width and whether or not page access is to be performed when accessing each address space CSi (SP6). Furthermore, predetermined values are written to a predetermined operation control register REG to optimally set the chip select signal CSi and other signals (SP6). These processes are similar to those in steps SP1 and SP2, and the chip select signal CSi, READ control signal, WRITE control signal, and other operation timings are optimally set by writing to the operation control registers that define the operation of the bus state controller 66 (Figure 9).

Next, a clear signal is output to the WDT circuit 58, which has already started operating, to avoid an abnormal reset (SP7). This takes into account that the WDT circuit 58 automatically starts operating after power is turned on, and similar processing is executed repeatedly thereafter. Note that the processing of step SP9 is stored in control memory 53 as subroutine SP7, but until the end of step SP9, subroutine SP7 in control memory 53 is called, and after the end of step SP9, another subroutine SP7' transferred to external DRAM 54 is called and executed.

Next, of the programs and data stored in address space CS0, the vector handler Vopt (interrupt processing program), error recovery processing program Piram, performance control program MainB, variable D with initial value, and constant data C shown in Figures 16(b) and 17(c) are transferred to external DRAM 54 or internal RAM 59 (SP8). Note that variable D with initial value refers to initial value data stored in a specified variable area. This memory section initialization process (SP8) transfers programs and data to speed up performance control processing and avoids access to ROM, which has slower access speeds.

Next, settings are made to use register bank RBi (SP9). As a result, register banks RB0 to RB14 will function during interrupt processing, speeding up interrupt processing and reducing stack space consumption.

The above processing is realized by executing the "initialization program Pinit" stored in the control memory 53, which is address space CS0 (see Figure 17(c)). Once execution of this initialization program Pinit is complete, the main control processing is then executed by the performance control program Main (SP10). Here, execution of the main control processing refers to the execution of the "performance control program Main" transferred from the control memory 53 to the external DRAM 54 by the transfer processing of step SP8 (see Figure 16(b)).

The processing of the "Performance Control Program Main" is divided into the main installation processing shown in Figure 18(a) and the upper part of Figure 21, and the main main processing shown in the lower part of Figure 21 and Figure 22(a). Specific details will be explained based on Figure 18(a) and Figures 21-22, but before that, the memory section initialization processing (SP8) will be explained. As shown in Figure 17(a), the memory section initialization processing (SP8) first initializes the DMACs of multiple channels to a stopped state. Note that this processing is merely a formality, just to be safe.

Once the above processing is complete, the DMACi for the specified channel is started, and the vector handler Vopt (interrupt processing program) stored in the control memory 53 is DMA transferred to the internal RAM 59 using the non-stop transfer method (see Figure 11 (b3)). In this embodiment, the interrupt processing program Vopt is transferred to the internal RAM 59, making it possible to appropriately handle the abnormality even when an abnormality occurs in the external DRAM 54.

The subsequent processing is also the same, and is executed using the non-stop transfer method using the DMACi of the specified channel, and the error recovery processing program Piram is DMA transferred to the internal RAM 59 (SP62). In this embodiment, the error recovery processing program Piram is transferred to the internal RAM 59, so the peripheral circuits can be reliably reset during the error recovery processing. For example, if the error recovery processing program Piram were transferred to an external DRAM 54 other than the internal RAM 59, the external DRAM 54 could not be reset during the error recovery processing.

Next, the performance control program Main is DMA transferred to the external DRAM 54 (SP63), and constant data C is DMA transferred to the external DRAM 54 (SP64). The constant data includes the lottery data used in the performance lottery, as well as lamp drive data and motor drive data in the various drive data tables shown in Figure 22 (b). In addition, variable D, which has an initial value, is DMA transferred to the external DRAM 54 (SP65), and all of this is performed using a non-stop transfer method using the DMACi of the specified channel.

Finally, clear data is written to the beginning of variable area B in the external DRAM (SP66). If this beginning address is assumed to be ADb, then in the subsequent DMA transfer process, the source address is initially set to ADb and the destination address is initially set to ADb+1. Then, the address values ADb and ADb+1 are incremented while this clear data is diffused, thereby clearing variable area B (SP67).

The processing of steps SP61 to SP66 and step SP67 described above all performs similar operations, as shown in Figure 17(b). That is, first, for the DMACi of a specified channel, the following DMA transfer conditions are set: (1) cycle steal transfer mode, (2) nonstop transfer method, and (3) the source and destination address values are incremented (SP68).

Next, the initial values for the source address and destination address are set (SP69), the transfer size is set, and interrupts are disabled (SP70), and then the DMA transfer operation is started (SP71). Note that the settings in steps SP68 to SP71 are all achieved by setting a specified operation control register REG.

In the initialization process for this memory section, DMA transfer completion interrupts are prohibited (SP70). Therefore, after starting the DMA transfer operation, the status flag of the specified operation control register REG is repeatedly read and accessed to wait for the DMA transfer to complete (SP72). However, taking into account the processing time until the operation completes, a clear signal is repeatedly output to the WDT circuit 58 (SP73). Then, when the DMA transfer completes, the DMACi is stopped based on the setting operation in the specified operation control register REG.

Next, the operation details of the main control processing (main introduction processing + main main processing) will be explained based on Figures 18(a) to 22. With regard to the main control processing (main introduction processing + main main processing), the main introduction processing (SP20 to SP27) is shown at the top of Figure 18(a) and Figure 21, and the initial setting processing (SS1 to SS6), which is part of the main main processing, is shown at the bottom of Figure 21. The details of the regular processing (ST4 to ST14), which is the remainder of the main main processing, are shown in Figure 22.

As shown in Figure 18(a), the main installation process first identifies the bus width and ROM device type for the CGROM 55 (SP20). Specifically, as shown in Figure 19(a), a specific VDP register RGij (e.g., the CG bus status register) that identifies the operating status of the CG bus that controls the interface with the CGROM 55 is accessed for READ (SP80), and a determination is made as to whether operational settings for the CG bus are possible (SP81).

Here, if the value of the CG bus Status register is 1, it means that the internal circuitry of the CG bus is undergoing a reset operation, and that the setting value for the VDP register RGij cannot be accepted. Therefore, after confirming that the value of the CG bus Status register has changed from 1 to 0 (SP81), the system sets operational parameters such as (1) the enable/disable status of each device section SPAi, (2) the type of ROM device, and (3) the data bus width in the specified VDP register RGij for each device section (SPA0-SPAn) that can be defined corresponding to the memory devices that make up the CGROM (SP82).

As shown in Figure 18(a), in this embodiment, the CGROM 55 can be divided into multiple areas (device sections), and for example, the memory device and data bus width can be selected for each device section (SPA0 to SPAn). Memory devices can be broadly classified into, for example, (1) the SATA module (AHSI/F) used in this embodiment, (2) memory elements using a parallel I/F (Interface), and (3) memory elements using a sequential I/F format, and for each broadly classified memory device, it is possible to specifically select the memory device, and the data bus width, etc. can be specified as desired.

Next, to optimize memory READ operations with the memory device selected for each device section (SPA0 to SPAn), specific operating parameters are set in the specific VDP register RGij (SP83). The operating parameters include setting values that define the operation timing of the chip select signal and other control signals (such as the READ control signal). Furthermore, if a memory device using a sequential I/F format is selected, the address latch output timing and the number of read clocks are also specified to achieve the operation shown in Figure 19(b).

Therefore, it is possible to configure CGROM 55 by combining different types of memory devices. However, in this embodiment, CGROM 55 is configured using only SATA modules, with only the device section (SPA0) enabled and the other device sections (SPA1 to SPAn) disabled.

In any case, once the setting processes of steps SP82 to SP83 are complete, a specified value is written to a specified VDP register RGij in order to put those setting processes into effect (SP84). This takes into account the fact that it takes a certain amount of time for the CG bus's internal circuitry to be able to operate in response to the setting processes of steps SP82 to SP83; while the internal circuitry is operating, the value of the CG bus Status register (see SP80) mentioned above is 0.

Therefore, the CG bus Status register is subsequently repeatedly accessed for read (SP85), and processing ends upon confirmation that the value of the Status register has returned from 1 to 0 (SP86). Note that processing in step SP66 may end if the value of the Status register does not return from 1 to 0, regardless of the predetermined number of determinations. However, in this case, the game processing begins in a state in which the CGROM cannot be accessed normally, and the WDT circuit 58 will then be activated at some point, causing the composite chip 50 to enter an abnormal reset state. In this case, the power-on reset operation will be executed again.

On the other hand, after the processing of step SP20 in Figure 18 is executed normally, the internal circuits of the CPU circuit 51, such as the interrupt controller INTC, DMAC circuit 60, and multifunction timer unit MTU, are individually initialized by software processing (SP21).

Next, the multifunction timer unit MTU starts a specified timer measurement operation (SP22), and then writes an enable setting value to a specified operation control register REG for internal interrupts and internal interrupts, setting the interrupt enable state (SP23).

As a result, various interrupts shown in Figure 18(d) may occur thereafter. Normally, at this timing, the sound processor 27 has completed its initialization sequence, and the end interrupt signal IRQ_SND should have dropped to L level, as shown in Figure 7(c). Therefore, the interrupt processing shown in Figure 18(c) is initiated, and the performance control CPU 63 initializes the error flag ERR to 1 and performs READ access to address space CS3 (SP30), obtains the value of a specified sound register SRG in the sound processor 27, and determines whether the initialization sequence has completed normally (SP31).

If the initialization sequence does not end normally, the performance control CPU 63 writes a reset command to a specified audio register SRG of the audio processor 27 (SP32) and sets the error flag ERR, which is initially set to 1, to 2 (SP33). This error flag ERR determines whether or not to execute the audio processor initialization process (SP26), and the error flag ERR = 1 is the execution condition for step SP26.

Meanwhile, in response to receiving the reset command, the audio processor 27 restarts the initialization sequence with the end interrupt signal IRQ_SND at H level, and when the initialization sequence is complete, it drops the end interrupt signal IRQ_SND to L level. As a result, the processing of Figure 18 (c) is executed again.

The above describes exceptional cases where the initialization sequence does not end normally, but normally, following step SP31, step SP32 is executed, and the performance control CPU 63 writes a predetermined value to a predetermined sound register SRG, thereby returning the end interrupt signal IRQ_SND from L level to H level (SP34).

Finally, by writing a specified value to a specified audio register SRG, READ/WRITE access to all audio registers SRG is permitted (SP35). As a result of this processing, the necessary setting processing can be performed in the subsequent audio processor initialization processing (SP26).

The above describes an example of a maskable interrupt corresponding to the interrupt permission setting in step SP23, but a non-maskable interrupt based on the oscillation of oscillator OSC2 stopping can be activated at any time. As explained earlier, the operating clock (CPU system clock) for circuits other than the built-in CPU (performance control CPU 63) is generated by frequency multiplying the output clock of oscillator OSC2 using a PLL (Phase Locked Loop), and if the oscillation of oscillator OSC2 stops, normal operation of the VDP circuit 52 will be impossible thereafter.

Meanwhile, the operating clock of the performance control CPU 63 is generated by multiplying the output clock of oscillator OSC1 using a PLL, allowing program processing to continue. Furthermore, the interrupt processing program is stored in the internal RAM 59. Therefore, the performance control CPU 63 issues an abnormality alert using audio and a lamp (SP28), and continues to output a clear signal to the WDT circuit 58 (SP29). The abnormality alert may be, for example, an audio alert stating, "An abnormality has occurred. Please contact an attendant immediately." The reason for continuing to output a clear signal to the WDT circuit 58 is to avoid an abnormal reset operation. In other words, in the event of a serious abnormality that causes oscillator OSC1 to stop operating, it is unlikely that the device will be able to return to normal even if the abnormal reset process is repeated.

As mentioned above, Figures 18(b) and 18(c) have been explained, so let's return to Figure 18(a) to continue the explanation. In step SP24, necessary areas are set to write-protected to protect the program area of the external DRAM 54. Next, the clock circuit 38, which is battery-powered when the power is cut off, is checked for normal operation when the power is cut off, and the alarm interrupt is reset just to be sure (SP25).

Then, on condition that the error flag ERR = 1, the necessary setting values are written to the built-in register (audio register SRG) of the audio processor 27 and initialization processing is performed (SP26). Note that if the error flag ERR = 0, the process waits for a predetermined time until the error flag ERR = 1, but if the time limit is exceeded, the process transitions to an infinite loop process to activate the WDT circuit 58.

Next, the power supply control circuit SPY is controlled to prepare for the startup of the display device DS1, and the necessary setting values are written to the VDP register RGij to initialize the display clock DCK and display circuit 74 (SP27). The processing of step SP27 is shown in detail as the processing of steps SP50 to SP57 in Figure 21.

The above describes an embodiment in which the end interrupt signal IRQ_SND is received from the audio processor, but it is also preferable to omit the interrupt processing in Figure 18(c). Figure 20 shows a modified embodiment in which the end interrupt signal IRQ_SND is replaced by a 1 ms timer interrupt signal generated by the multifunction timer unit MTU.

Figure 20 illustrates part of the 1 ms timer interrupt process, realizing four stages of operation based on the value (0/1/2/3) of the operation management flag FLG, which is initially set to zero. The IRQ_SND output terminal of the audio processor 27 is open, and the IRQ_SND input terminal of the CPU circuit 51 is fixed to the H level.

In the 1 ms timer interrupt process, first, if it is determined in step SP42 that the operation management flag FLG = 0, it is confirmed that the initialization sequence of the audio processor 27 has ended normally (SP43). If it has ended normally, a predetermined value is written to a predetermined audio register SRG to clear the interrupt signal (IRQ_SND) (SP46), and the operation management flag FLG is set to 1 (SP47). Note that the processes of steps SP43 and SP46 are the same as the processes of steps SP31 and SP34 in Figure 18(c).

On the other hand, if the initialization sequence has not ended normally, a reset command is written to a specified audio register SRG, causing the audio processor 27 to start the initialization sequence (SP44) and resetting the operation management flag FLG to zero (SP45). Note that the processing in step SP44 corresponds to the processing in step SP32 in Figure 18(c).

Normally, the operation management flag FLG = 1 after processing in step SP47, so at the next 1 ms timer interrupt, a specified value is written to a specified audio register to allow access to all audio registers (SP48), and the operation management flag FLG = 2 is set (SP49). The processing in step SP48 corresponds to the processing in step SP35 in Figure 18(c).

Next, in the case of a 1 ms timer interrupt with the operation management flag FLG = 2, as in step SP26 of Figure 18(a), the necessary setting values are written to the built-in register (audio register SRG) of the audio processor 27, initialization processing is performed (SP50), and the operation management flag FLG = 3 is set.

Operation management flag FLG = 3 indicates normal audio control status, and audio control proceeds by setting the necessary operation parameters in the necessary audio registers SRG (SP52).

The above describes a method for checking whether the initialization sequence of the audio processor 27 has completed successfully using an interrupt process triggered by an interrupt signal (IRQ_SND) (SP31 in Figure 18(c)) and a method for checking using a 1 ms timer interrupt process (SP43 in Figure 20), but the present invention is not limited to these methods. For example, it is also preferable to determine whether the initialization sequence of the audio processor 27 has completed successfully as part of the process of step SP26 in Figure 18.

The above explains the overview of the main installation process (SP20 to SP26 in Figure 18). Below, we will explain the details of step SP27 (startup preparation process + initialization process) and the operation of the main main body processing process (SS1 to SS6 and ST4 to ST14) based on Figures 21 and 22.

As shown in Figure 21, in processing step SP27, the performance control CPU 63 first checks the clock timer TM and confirms that one second has passed since the performance control CPU 63 started operating (timing T1 in Figure 6(d)) while outputting a clear signal to the WDT circuit 58 (SP50). This is to maintain the display device DS1 in a non-operating state until the VDP circuit 52 begins actual operation. Furthermore, because a clear signal is output to the WDT circuit 58, activation of the WDT circuit 58 is reliably prevented, and there is no risk of the initialization process up to this point being wasted, such as an abnormal reset of the composite chip 50 (this significance applies to the standby process below).

Next, the performance control CPU 63 transitions the control signals PS1 and PS2 sent to the power supply control circuit SPY from L level to H level (SP51). This process corresponds to the operation at timing T2 shown in Figures 6(g) and 6(h), and the control signals PS1 and PS2 are subsequently maintained at H level.

When the control signal PS1 goes high, the MOS transistor Q1 turns on and the 12V power supply voltage is supplied to the backlight unit BL. However, at timing T2, the BL_EN terminal and PWM terminal of the backlight unit BL driver DVL are both low, so the backlight unit BL does not emit light.

Furthermore, when the control signal PS2 goes high, the MOS transistor Q4 turns on, and the power supply voltage 5 is supplied to the liquid crystal display unit MONI. However, at this time T2, the backlight unit BL is turned off, so there is no risk of an unnatural image being displayed.

Once processing of step SP51 is completed, the performance control CPU 63 then determines the refresh mode based on the setting value of a specified VDP register RGij, sets the refresh period of the built-in VRAM 71, and sets the initial values of the row address (refresh address), and performs initialization processing of the built-in VRAM 71 (SP52).

The VRAM 71 in this embodiment is composed of DRAM (Dynamic Random Access Memory), and the charge stored in the memory cells is gradually lost due to leakage current within the device. Therefore, in this embodiment, for example, a distributed refresh method is used, in which each row is refreshed at a time. All rows in the device are refreshed at the refresh cycle specified in the processing of step SP52, thereby preventing the loss of charge in the memory cells. Therefore, even if there are memory cells in the VRAM 71 that are not accessed for a long period of time, there is no risk of the data being lost. Note that the refresh mode is not limited to the distributed refresh method, and a concentrated refresh method can also be used.

Next, the necessary setting values are written to the VDP register RGij, the display clock DCK is initialized, and the display circuit 74 is initialized (SP54). Note that this process is nothing more than an operation to perform a hardware reset on the relevant internal circuitry.

Next, the control signal STBY sent to the power supply control circuit SPY is transitioned from L level to H level (SP56). This process corresponds to the operation at timing T3 shown in Figure 6(i), and the control signal STBY remains at H level thereafter. At timing T3, the driver DVL of the backlight unit BL has already been supplied with a power supply voltage of 12V (timing T2), so the driver DVL is in an operable state. However, because the control control signal PWM is still maintained at L level, the backlight unit BL does not emit light.

Next, the execution of the processing of step SP4 in FIG. 16 and the execution of the processing of step SP54 in FIG. 21 are confirmed by reading the specified VDP register (status register STS) RGij (SP57). Specifically, first, the status register STS (1) is used to confirm that the display clock set in the processing of step SP4 in FIG. 16 has stabilized.

Next, the status register STS (2) is used to confirm that initialization of the display circuit has been completed successfully in response to the processing of step SP54. Next, the status register STS (3) is used to confirm that initialization of each section LVDS1/LVDS2 of the LVDS circuit 80, which is set to dual link in the processing of step SP45, has been completed successfully. Once it is confirmed that all initialization has been completed successfully, the main installation processing ends (SP57).

Next, the subsequent processing will be described for an example in which the preloader does not function. As shown in Figures 21 to 22(a), the main main body processing is divided into VDP initial setting processing (SS1 to SS6) that is executed after the CPU is reset, and then regular processing (ST4 to ST14) that is repeatedly executed every 1/30 seconds.

Since steady-state processing (ST4 to ST14) begins when the interrupt counter VCNT reaches VCNT≧2 (ST4), the operating period δ of steady-state processing is 1/30 seconds. This operating period δ is nothing more than the actual operating period δ of the VDP circuit 52, which operates intermittently under the control of the performance control CPU 63. The reason for setting the judgment condition as VCNT≧2 is to take into account the possibility that steady-state processing (ST4 to ST14) may take an abnormally long time, causing the timing of VCNT=2 to be missed, but it is also designed to prevent a situation in which VCNT=3 occurs.

Based on the above, the VDP initial setting process will now be explained. As shown in Figure 21, in this embodiment, during the VDP initial setting process, the built-in VRAM 71 with a storage capacity of 48 MB is divided into an ACC area (a) with appropriate storage capacity, a page area (b), and a user-defined area (c) (SS1). Specifically, for the ACC area (a1, a2) and the page area (b), the start addresses and total required data sizes for each area are set in a specified index table register RGij (SS1). The reserved ACC area (a1, a2) and the remaining area not included in the page area (b) then become the user-defined area (c).

Here, the starting addresses of the first and second ACC areas (a1, a2) and the page area (b) must each have the lowest 11 bits set to 0, but can be selected arbitrarily in 2048-bit units (selection in increments of 256 addresses, with 1 address = 1 byte). The total data size can also be selected arbitrarily within the range of an integer multiple of the unit size. While not particularly limited, the unit size of the ACC area (a) is 2048 bits, and the unit size of the page area (b) is 512 kbits.

In this way, in this embodiment, certain conditions are imposed on the area settings of the ACC area (a1, a2) and the page area (b). This is to eliminate as much wasted area as possible from the built-in VRAM 71, which has limited memory capacity, while also facilitating the internal operation of the VDP circuit 52. In other words, while increasing the memory capacity of the built-in VRAM 71 indiscriminately could raise concerns about rising manufacturing costs and increasing the chip area, allowing free area settings that completely eliminate wasted area would complicate internal processing and make it impossible to shorten the processing time for VRAM access. The same reason is also why certain restrictions are imposed on allocating index space, as explained below.

Continuing with the above, following the processing of step SS1, the necessary index space IDXi is reserved for page area (b) and arbitrary area (c) (SS2). Specifically, the necessary information is set in a specified index table register RGij to reserve index space IDXi for each area (b) and (c).

For example, when an index space IDXi is set in page area (b), multiple information (horizontal and vertical multiple information for the unit space) of an arbitrary horizontal size Hx and an arbitrary vertical size Wx corresponding to an arbitrary index number i is set in a predetermined index table register RGij (SS2).

As explained earlier, the index space IDXi of page area (b) has a unit space of 128 horizontal lines x 128 vertical lines, and since one pixel is specified by 32 bits of information, an index space IDXi with a data size (bit length) of 32 x 128 x Hx x 128 x Wx is secured based on the horizontal size Hx and vertical size Wx settings. The starting address (space starting address) of index space IDXi of page area (b) is automatically assigned internally.

Furthermore, when an index space IDXi is set in the arbitrary area (c), an arbitrary start address (space start address) STx and multiple information of an arbitrary horizontal size Hx are set in a predetermined index table register RGij corresponding to an arbitrary index number i (SS2). Here, "arbitrary" means that predetermined conditions are assumed, and the horizontal size Hx is arbitrarily determined in 256-bit units, the lowest 11 bits of the start address STx are 0, and it is arbitrarily determined in 2048-bit units. As explained earlier, the vertical size of the arbitrary area is fixed to 2048 lines, so based on the setting of the horizontal size Hx, an index space of data size (bit length) = 2048 x Hx is secured after the start address STx.

Specifically, as the frame buffer FBa of the main display device DS1, a pair of index spaces with a horizontal size of 1280 x 2048 vertical lines are set in one or more predetermined index table registers RGij, each with a specified index number. As the frame buffer FBb of the sub-display device DS2, a pair of index spaces with a horizontal size of 480 x 2048 vertical lines are set in one or more predetermined index table registers RGij, each with a specified index number. Note that if the number of horizontal pixels of the display device does not match an integer multiple of 256 bits/32 bits, the horizontal size of each index space is set to a value that is larger than the number of horizontal pixels of the display device and is an integer multiple of 256/32 = 8, minimizing the generation of wasted memory space.

As described above, the required number of index spaces IDXi are generated by setting the required size and address information for the page area (b) and the arbitrary area (c) in the specified index table register RGij (SS2). Then, in response to this setting process (SS2), an index table IDXTBL specifying the address and size information for each index space IDXi is automatically constructed. As shown in FIG. 12(a), the index table IDXTBL stores the starting address of each index space IDXi along with other required information, and is referenced during data transfer within the VDP circuit 52 and when retrieving data from an external storage resource (see FIG. 13). Since the index space IDXi for the AAC area (a) is automatically generated and deleted when needed, the setting process of step SS2 is unnecessary.

As shown in Figures 12(a) and 12(b), a pair of frame buffers FBa and FBb are secured in the arbitrary area (c), and each is assigned an index number. In an embodiment that does not use a Z-buffer, a pair of index spaces 255 and 254, assigned index numbers 255 and 254, are secured as frame buffer FBa. Furthermore, a pair of index spaces 252 and 251, assigned index numbers 252 and 251, are secured as frame buffer FBb. In this embodiment, a working area (index space 0) with index number 0 is also secured in the arbitrary area (c).

In this embodiment, the page area (a) is allocated the necessary number of index spaces IDXi to serve as the decoding area for the IP stream video, and each is assigned an index number i. However, initially, only the index space _IDX0 for the background video (IP stream video) is allocated. Then, depending on the needs of the image presentation (variation presentation or preview presentation), the index space IDXj in the page area (a) is increased based on the setting process for the index table register RGij and the instruction command of the display list DL, and then, when it is no longer needed, the index space IDXj is released. That is, Figure 12(a) shows the index table IDXTBL during normal operation.

The index space of the ACC area (a) is automatically generated when necessary based on the instruction commands written in the display list DL, and the starting address of the automatically generated index space IDXj and other necessary information are automatically set in the index table IDXTBL. In this embodiment, this AAC area (a) is used as a decoding area for still images and other textures.

The above operation of reserving index space is achieved primarily by setting the index table register RGij included in the control register group 70. However, following the processing of steps SS1 and SS2, the necessary setting operation (SS3) is performed on the other VDP register RGij, enabling steady-state (intermittent) operation of the VDP circuit 52 shown in Figures 30 and 31.

In this embodiment, the required setting process (SS3) includes at least steps SS30 to SS39. Note that steps SS30 to SS37 do not limit the order of processing, and can be performed in any order regardless of the order described below.

In this embodiment, the number of display lines and horizontal pixels are first set for each display device DS1, SD2 by writing specified operating parameters (number of lines and number of pixels) to a specified display register RGij that defines the operation of the display circuit 74 (SS30). In this embodiment, the number of horizontal pixels for the main display device DS1 is 1280 dots and the number of display lines is 1024 rows. The number of horizontal pixels for the sub-display device DS2 is 480 dots and the number of display lines is 80 rows. As a result of the setting process in step SS34, the vertical and horizontal dimensions of the valid data area (dashed line area in Figure 22(e)) to which the display circuits 74A, 74B should access for READ are specified in each frame buffer FBa, FBb.

Next, predetermined operating parameters (THc, WTh) are written to a predetermined display register RGij that defines the operation of the display circuit 74, thereby setting the number of cycles THc in the horizontal period TH and the horizontal waiting time WTh for each display device DS1, SD2 (SS31). Furthermore, predetermined operating parameters (TVl, WTv) are written to a predetermined display register RGij, thereby setting the number of lines TVl in the vertical period TV and the vertical waiting time WTv for each display device DS1, SD2 (SS32).

As explained with reference to Figure 15, for the main display device DS1, the number of cycles in the horizontal period TH is set to THc = 1662, and the number of lines in the vertical period TV is set to TVl = 1083. The horizontal wait time WTh is set to 382, and the vertical wait time WTv is set to 59 lines. On the other hand, for the sub-display device DS2, the number of cycles in the horizontal period TH is set to THc = 519, the number of lines in the vertical period TV is set to TVl = 867, and the horizontal wait time WTh is set to 39, and the vertical wait time WTv is set to 67 lines. Note that THc - WTh = 519 - 39 = 480, and TVl - WTv = 867 - 67 = 800, which matches the pixel count of the sub-display device (480 horizontal x 800 vertical).

16 determines the frequency F _dot (=108 MHz) of the dot clock DCK, and steps SS30 to SS32 define the number of cycles THc (=1662) in the horizontal period TH and the number of lines TVl (=1083) in the vertical period TV for the main display device DS1, resulting in the display period of one frame being determined as THc x TVl/F _dot . Specifically, the display period of one frame is determined to be 1083 x 1662/108 MHz = 16.667 mS, and the frame rate FR is determined to be 1/60 second.

For the sub-display device DS2, for example, based on the frequency F _dot of the dot clock DCK = 27 MHz, the number of cycles of the horizontal period THc = 519, and the number of lines of the vertical period TVl = 867, the frequency is determined to be 519 x 867/27 MHz = 16.66 mS.

Next, in this embodiment, for the sub-display device DS2, the pulse width of the horizontal periodic signal HS and the number of cycles from the V blank start timing of the pulse rising edge are set in a specific display register RGij (SS33). Also, for the sub-display device DS2, the pulse width of the vertical periodic signal VS and the number of cycles from the V blank start timing of the pulse rising edge are set (SS34).

As explained above, the main display device DS1 does not require a horizontal synchronization signal HS or a vertical synchronization signal VS, so the above processing (SS33 to SS34) for the main display device DS1 is not necessary. However, if the setting processing of steps SS33 to SS34 is omitted, the default values set at power reset will function, so in reality, the display device 74A will also output a horizontal synchronization signal HS and a vertical synchronization signal VS.

According to the default values, for example, a horizontal synchronization signal HS with a pulse width of 40 clocks is output, which becomes active 16 clocks after the V blank start timing, and a vertical synchronization signal VS with a pulse width of 3 lines is output, which becomes active in synchronization with the V blank start timing.

This operation means that a horizontal synchronization signal HS with a horizontal front porch HPv = 16, pulse width PWh = 40, and horizontal back porch BPv = 326 is output to the main display device DS1 during the horizontal wait time WTh = 382 clocks, and a vertical synchronization signal VS with a vertical front porch HPv = 0, pulse width PWv = 3, and vertical back porch BPv = 56 is output during the vertical wait time WTv = 59 lines. However, as mentioned above, these synchronization signals are ignored by the main display device.

In order to prevent synchronization signals HS and VS based on default values from being output, a specific system control register RGij may be configured to not output the horizontal synchronization signal HS or vertical synchronization signal VS. When such a mask setting is implemented, the output terminal for the horizontal synchronization signal HS and the output terminal for the vertical synchronization signal VS of the VDP circuit 52 can maintain a fixed value of H level or L level.

Next, a specific system control register RGij is set to allow V blank interrupts (SS35). As a result, in this embodiment, the VBLANK start interrupt shown in Figure 22(c) occurs in response to the V blank start timing, which occurs every 16.667 mS = 1/60 seconds. This V blank interrupt timing determines the start timing of the regular processing (ST5 to ST14) of the performance control CPU 63, and also indicates the start timing of the display period for the display circuits 74A and 74B (the end timing of the previous display period).

Next, predetermined operating parameters (address values) are written to predetermined display registers RGij to specify the vertical and horizontal display start positions for each frame buffer FBa and FBb (SS36). As a result, the valid data areas whose vertical and horizontal dimensions were specified in step SS34 are defined on the frame buffers FBa and FBb. Here, the vertical and horizontal display start positions are relative address values in each index space; in the example shown in Figure 22(e), the display start position is (0,0).

Here, "display area" refers to the index space (frame buffers FBa and FBb) from which display circuits 74A and 74B should read image data to drive display devices DS1 and DS2, and refers to either of the double buffers in frame buffers FBa and FBb, which each have a double buffer structure. However, display circuits 74A and 74B actually read image data only from the "valid data area" identified in steps SS30 and SS36 in display area (0) or display area (1).

Next, "display area (0)" and "display area (1)" are set in the display register RGij (DSPAINDEX) for the display circuit 74A that drives the main display device DS1 and the display register RGij (DSPBINDEX) for the display circuit 74B that drives the sub-display device DS2, respectively, to define each display area (SS37).

Although not limited in any way, in this embodiment, for frame buffer FBa, index space 254 of index number 254 in VRAM arbitrary area (c) is defined as the "display area (0)," and index space 255 of index number 255 in VRAM arbitrary area (c) is defined as the "display area (1)" (SS37).

Furthermore, for frame buffer FBb, index space 251 of index number 251 in VRAM arbitrary area (c) is set as "display area (0)," and index space 252 of index number 252 in VRAM arbitrary area (c) is set as "display area (1)" (SS37). Note that there is no particular limitation on defining the "display area" in the initialization process (SS3); the index space (display area) that the display circuit 74 should access to read image data may be toggled every operating cycle δ. Note that it is also preferable to clear the respective display areas (0) and (1) of frame buffers FBa and FBb to zero at this timing; in this case, unnatural images will not be displayed on the display device.

In this embodiment, once the initial setup including the above processes (SS30 to SS37) is complete, a predetermined prohibition value is set in the first type prohibition setting register RGij to prevent the setting value in the predetermined system control register RGij from being changed due to noise or other factors (first prohibition setting SS38).

The setting values that are prohibited from being written in the future include (1) setting values related to the display clock DCK of the display devices DS1 and DS2, (2) setting values related to the LVDS sampling clock, (3) setting values related to the selection operation of the output selection circuit 79, and (4) the synchronization relationship between the multiple display devices DS1 and DS2 (the dependency of display circuit 74B on the operating cycle of display circuit 74A). Although software processing exists to cancel the first prohibition setting, it is not used in this embodiment. However, it is preferable to use it if necessary.

Next, a predetermined prohibition value is set in the second-type prohibition setting register RGij, thereby prohibiting writing to the VDP register RGij of the initial setting system (second prohibition setting SS39). The registers that are prohibited here include the VDP register RGij related to step SP4 and steps SS30 to SS37.

On the other hand, by setting a specific prohibition value in the third type prohibition setting register RGij, it is possible to prohibit multiple VDP registers, including the VDP registers related to the setting processes in steps SS1 to SS3 (third prohibition setting). However, this is not used as a general rule in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be released at will by writing a release value to the specific release register RGij, and it is also possible to change the setting value during normal operation.

Once the above processing is complete, the next step in step SP52 of Figure 21 is to check whether the initialization of the built-in VRAM 71, which specifies the refresh cycle, has been completed by referencing the status register (4) to confirm that operation is stable (initialization has been completed successfully) (SS40).

The above process confirms that the internal VRAM 71, display circuit 74, and LVDS circuit 30 have all successfully completed initialization based on the values of status registers (1) to (4). Next, a specified value is written to the specified display register RGij (DSPACTL/DSPBCTL), causing the display circuits 74A and 74B to begin operating (SS4a). Furthermore, a specified value is written to the specified system control register RGij (SYSDSPLVDS1MD/SYSDSPLVDS2MD), causing the output data from the display circuit 74A to be output from the LVDS circuit 80 (LVDS1/LVDS2) (SS4b).

This operation is none other than the processing at timing T4 in Figure 6(e), and in this embodiment, the program is designed to execute steps SS4a and SS4b within a predetermined time τ (e.g., 20 mS) from timing T2. Then, in response to the start of operation of display circuits 74A, 74B and LVDS circuit 80 (timing T4), the clock timer TM is restarted from zero (SS4c). Note that the processing sequence of steps SS4a to SS4b is not necessarily limited. Even if steps SS4a to SS4b were executed in reverse order, useless image data would only be output from the LVDS circuit 80 for a moment, and there would be no problem because the backlight unit BL would be off.

In any case, in this embodiment, in response to the processing of steps SS4a to SS4b above, the display circuit 74 enters a V blank start state every 1/60 seconds, and the LVDS circuit (LVDS1/LVDS2) 80 operates, thereby repeating the display operation shown in Figure 15. Note that in Figure 15, the start timing and end timing of the display operation indicated by circles indicate the V blank start timing.

The horizontal reference point TH0 (= horizontal reference time) and vertical reference point (= vertical reference time) TV0 for the operation of the display circuit 74 are then defined based on this V-blank start timing, and the display circuit 74 waits without outputting image data corresponding to each pixel of the display device until the horizontal waiting time WTh has elapsed from the horizontal reference point TH0. Similarly, the display circuit 74 is configured to wait without outputting image data corresponding to each pixel of the display device until the vertical waiting time WTv has elapsed from the vertical reference point TV0.

Furthermore, because the display circuit 74B operates in synchronization with the display device 74A (SP4 in Figure 16), the start and end timing of the display operation for the sub-display device DS2 is also the same as that of the main display device DS1. Therefore, by setting the frame period for the sub-display device DS2 (519 x 867/27) shorter than the frame period for the sub-display device DS2 (1083 x 1662/108), the update process for the sub-display device DS2 is set to be completed when the V-blank starts.

After the processing of step SS4, which has the above significance, is completed, the process next waits for 300 mS based on the clock timer TM (SS5), and then transitions the control signal PWM sent to the power supply control circuit SPY from low to high (SS6). As a result, the backlight unit BL enters an illuminating state, and the liquid crystal display unit MONI, which had already started operating, begins displaying based on the image data received from the display circuit 74A. As explained above, at this timing, the display list has not yet been issued, so the contents of VRAM are displayed as is. Therefore, it is preferable to leave the processing of steps SS5 and SS6 to timer interrupt processing (see dashed lines). With this configuration, the display list DL has already been issued by timing T5, and the specified initial screen is displayed on the display device DS1.

Next, the remaining part of the main main processing, the steady-state processing that is repeatedly executed at predetermined intervals, will be explained based on Figure 22. As shown in Figure 22, the operation of the performance control CPU 63 is composed of main control processing (a), timer interrupt processing (b) that starts every 1 ms, reception interrupt processing (not shown) that starts in response to a control command CMD, VBLANK interrupt processing (c) that starts in response to a VBLANK signal generated at the start of the V-blank (vertical blanking period) of the display device DS1, and drawing abnormality interrupt processing (d) that occurs when operation freezes or an irrational instruction command is detected. Note that an explanation of the 20 μS interrupt processing will be omitted.

In the receive interrupt process, the control command CMD received from the main control unit 21 is stored in a specified receive buffer so that it can be referenced in the main control process (ST13), and the process ends. In addition, in the VBLANK interrupt process (Figure 22 (b)), the interrupt counter VCNT is incremented for each VBLANK interrupt (ST15), and at the start of the main control process, the 1/30 second operation start timing is determined based on the value of the interrupt counter VCNT, and the interrupt counter VCNT is cleared to zero (ST4).

On the other hand, as shown in Figure 22 (b), the timer interrupt process includes a process (ST18) for acquiring origin sensor signals and the like to progress the motor effect, and a process (ST19) for progressing the lamp effect. The lamp and motor effects are controlled based on a performance scenario that centrally manages all performance operations, and when the performance start time managed by the performance counter EN is reached, the motor drive table and lamp drive table are identified in the performance scenario update process (ST11).

Then, the motor performance progresses based on the identified motor drive table, and the lamp performance progresses based on the identified motor drive table. As explained above, there are also embodiments in which the DMAC circuit (first and second DMA channels) 60 functions when step ST18 is operating. Note that the motor performance progresses every 1 ms, but the lamp performance progresses at appropriate timings longer than 1 ms.

On the other hand, as shown in Figure 22(d), in the drawing abnormality interrupt processing, the status register RGij, which indicates the operating status of the drawing circuit 76, is accessed for read access to identify the cause of the interrupt. Specifically, it is identified whether the drawing abnormality interrupt is due to (1) the detection of an abnormal command (bit corruption) or (2) an operational abnormality (freeze) of the drawing circuit 76 (ST16a). If the drawing abnormality interrupt is due to the detection of an abnormal command, a predetermined value is written to a predetermined system control register RGij, thereby initializing the drawing circuit 76 (ST16b). This operation is nothing more than the individual reset operation of the reset path 4B shown in Figure 7(b).

Next, after confirming the successful completion of the individual reset operation in a specified status register RGij, the group of operating parameters that define the operation of the drawing circuit 76 are reset to the specified drawing register RGij, and processing ends (ST16c). Then, after adjusting the stack area that stores the return address (a release process that erases the return address after interrupt processing), processing proceeds to step ST13 (ST16c).

On the other hand, in the case of a drawing abnormality interrupt based on an operational abnormality of the drawing circuit 76, the process transitions to an infinite loop (ST16d), activates the WDT circuit 58, and resets the entire combined chip 50. If it is not desired to reset the CPU circuit 51, a predetermined keyword string may be output to the pattern check circuit CHK, and only the VDP circuit 52 may be reset by the reset signal RST (see FIG. 7(b)). In this case, after confirming that the reset operation of the VDP circuit 52 has been completed successfully, the process transitions to steps ST4 and ST13. To avoid missing the control command CMD as much as possible, it is better to transition to step ST13 from step ST4, including other cases.

When the entire composite chip 50 is reset, all previous effects are erased and effect control is returned to its initial state (power-on state). However, when only the VDP circuit 52 is reset, the entire series of effect control can continue, although there is a predetermined waiting time until the reset operation of the VDP circuit 52 is complete. Furthermore, because the effect control CPU 63 controls the image effects, lamp effects, and audio effects in a unified manner, there is no unnatural discrepancy between the various effects.

The initial setting process of steps SS1 to SS3 described above is executed based on the initial value setting table SETTABLE (see Figure 36), which associates the register address value of VDP register RGij with the setting value for that register RGij. Having explained the initial setting process above, we will now provide a brief explanation of the steady-state operation (intermittent operation) of the VDP circuit 52 controlled by the performance control CPU 63, based on Figures 30(a) and 31(b), before explaining the steady-state processing (ST4 to ST14).

The intermittent operation of the VDP circuit 52 is as shown in Figures 30 and 31. In an embodiment that does not use the preloader 73, as shown in Figure 30(a), the display list DLi completed by the presentation control CPU 63 is issued to the drawing circuit 76 in that operation cycle (T1), and the drawing circuit 76 completes image data in frame buffers FBa and FBb through drawing operations based on the display list DLi. The completed image data in frame buffers FBa and FBb is then output by the display circuit 74 to display devices DS1 and DS2 in the next operation cycle T1+δ, and the display screen perceived by the player is created based on the subsequent drawing operations of display devices DS1 and DS2.

On the other hand, in an embodiment using a preloader 73, as shown in FIG. 31(a), the display list DLi completed by the performance control CPU 63 is issued to the preloader 73 in its operating cycle (T1), and the preloader 73 interprets the display list DLi, performs the necessary prefetching operations, and rewrites part of the display list DLi to complete the rewrite list DL'. The prefetched CG data and rewrite list DL' are stored in appropriate locations in the DRAM 54.

Next, in the next operating cycle (T1 + δ), the drawing circuit 76 retrieves the rewrite list DL' from DRAM 54 and completes the image data in the frame buffers FBa and FBb through drawing operations based on the rewrite list DL'. Then, in the next operating cycle (T1 + 2δ), the display circuit 74 outputs the completed image data in the frame buffers FBa and FBb to the display devices DS1 and DS2, and the display screen perceived by the player is created based on the subsequent drawing operations of the display devices DS1 and DS2.

The above provides an overview of the intermittent operation of the VDP circuit 52. To achieve the operation shown in Figures 30 to 31, the performance control CPU 63 performs initial processing (SS1 to SS3), then repeatedly references the value of the interrupt counter VCNT, waiting for the operation start timing to be reached. When the operation start timing (the start timing of every other V blank) is reached, the interrupt counter VCNT is cleared to zero (ST4).

After that, steady-state operation begins. In this embodiment, first, it is determined whether the operation start conditions for starting steady-state operation are met (ST5). The timing for this determination is the timings T1, T1+δ, T1+2δ, ... shown in Figures 30 and 31, i.e., the start timing of the vertical blanking period (VBLANK) of display device DS1. The display timing of display device DS2 is set during initial setup (ST3) so that it is subordinate to the display timing of display device DS1.

The operation start condition determined at the start timing of the vertical blanking interval (VBLANK) differs depending on whether or not the preloader 73 is used. Therefore, we will first describe an embodiment (Figure 22) that does not utilize the preloader 73. In this case, the circuit configuration and program are designed so that the internal operation of the VDP proceeds as shown in the time chart of Figure 30(a). That is, based on the display list DL1 completed in the operation cycle (T1), the drawing circuit 76 should complete its drawing operation within that operation cycle (T1 to T1 + δ). However, it is possible that the drawing operation will not be completed within that operation cycle (T1 + 2δ to T1 + 3δ), as in the case of display list DL3 completed in the operation cycle (T1 + 2δ) of Figure 30(a). Furthermore, it is possible that an underrun error has occurred in the display circuit 74, in which display data generation is unable to keep up with the display timing.

The determination process in step ST5 takes such a situation into consideration, and the performance control CPU 63 accesses the status register RGij (a type of control register group 70) that indicates the operating state of the drawing circuit 76, and determines at the timing of step ST5 whether the drawing circuit 76 has completed the necessary operations and whether an underrun abnormality exists. The presence or absence of an underrun abnormality is determined based on the underrun counters URCNTa to URCNTc. Also, in an embodiment that does not utilize the preloader 73, for example, at timing T1+δ in Figure 30(a), the status information of the drawing register related to the drawing circuit 76 is read and accessed to confirm that the drawing operation based on the display list DL1 has ended.

If the operation start conditions are not met (abnormal/non-conformance), the abnormality flag ER, which counts the number of abnormalities, is incremented and steps ST6 to ST8 are skipped. The abnormality flag ER, along with the other serious abnormality flags ABN, is determined in steps ST9 and ST10. Assuming that the serious abnormality flag ABN is reset, if the number of consecutive abnormalities is not high (ER≦2), the performance command analysis process is executed (ST13), just as in normal cases.

In the case of an underrun abnormality, steps ST6 to ST8 are similarly skipped. Then, a predetermined clear value is written to a predetermined system control register RGij, thereby initializing the display clock DCK (frequency) and the display circuit 74 (ST10c). After confirming that this initialization process has completed successfully, the values of the group of system control registers RGij that determine the frequency of the display clock DCK and the operation of the display circuit 74 are reset to their predetermined values (ST10c), and then the performance command analysis process is executed (ST13).

The effect command analysis process (ST13) determines whether a control command CMD has been received from the main control board 21, and if a control command CMD has been received, analyzes the control command CMD and executes the necessary processing (ST13). The necessary processing here includes preparation processing for the start of a new variable effect based on a control command CMD that instructs the start of a variable effect, and initiation processing for an error notification based on a control command CMD that indicates the occurrence of an error. Next, a clear pulse is output to the WDT circuit (ST14), and processing returns to step ST4.

The above describes the case where there is a minor underrun error, or when the operation start conditions are not met and the error flag ER is ER≦2. In such cases, the process of toggling the display area read by the display circuit 74 (ST6) and the process of creating a display list (ST7) are skipped during that operation cycle, and the performance scenario does not proceed (see ST8-ST12). This is to prevent the output of incomplete image data from frame buffers FBa and FBb. Therefore, for example, during the operation cycle (T1+3δ) in Figure 30(a), the image performance does not proceed, and a frame drop occurs in which the original screen (the screen based on DL2) is redisplayed.

To avoid frame drops, it is possible to configure the system to wait until the operation start conditions are met. However, since there are many control processes (ST6 to ST12) that the performance control CPU 63 must execute and it is necessary to ensure time for each process, in this embodiment, frame drops occur when the operation start conditions are not met.

However, even if a frame is dropped, the image effects are only delayed by about 1/30 to 2/30 of a second compared to the lamp and motor effects that proceed through interrupt processing (Figure 22 (b)), and the player will not notice this. Furthermore, when a frame is dropped, the effect scenario processing (ST11), which includes the effect counter EN update processing, and the audio progression processing (ST12) are also skipped, so there is no risk of delays in the start timing of image effects, audio effects, lamp effects, and motor effects in the reach effects, preview effects, and bonus effects that begin thereafter.

In other words, the performance scenario centrally manages the start timing of image, audio, lamp, and motor effects, as well as the performance content to be executed thereafter. The start timing is controlled by the performance counter EN, which is updated only under normal conditions, so the various effects never become out of sync. For example, if there is a performance that combines explosion sounds, explosion images, prop movement, and lamp flashing, each of the above performance actions will start correctly and in sync, even after a frame drop occurs.

The above describes relatively minor abnormalities, but if the serious abnormality flag ABN is set, if there are many consecutive abnormalities (ER>2), or if an underrun abnormality occurs repeatedly, an infinite loop state is entered after the judgment in step ST10 (ST10b). As a result, the timing operation of the WDT circuit 58 progresses, and the composite chip 50 including the performance control CPU 63 is reset due to an abnormality. After that, the initial processing (SS1-SS3) is re-executed, which is expected to resolve the root cause of the abnormality.

This reset operation is performed by activating the WDT circuit 58, so the entire composite chip 50, including the CPU circuit 51, is reset (Figure 7(b)). Therefore, to avoid resetting the CPU circuit 51, it is also preferable for the performance control CPU 63 to output a predetermined keyword string (e.g., three 1-byte data items) to the pattern check circuit CHK and output a reset signal RST to the VDP circuit 52 (see ST100 in Figure 36). In this case, after confirming that the reset operation of the VDP circuit 52 has completed successfully (ST101), the process will proceed to steps ST4 and ST13.

In any case, when this abnormality occurs, the audio circuit SND is also reset, and the image effects, audio effects, lamp effects, and motor effects all return to their initial states. However, these reset operations have no effect on the main control unit 21 or payout control unit 25, so there is no risk of the jackpot state disappearing or prize balls disappearing.

The above describes abnormal situations, but in reality, even minor abnormalities rarely occur. After processing in step ST5, the "display area" of frame buffers FBa and FBb, which store the image data to be read by display circuit 74A and display circuit 74B, is toggled (ST6) based on the settings in the specified display register RGij (DSPACTL/DSPBCTL). As explained earlier, "display area (0)" and "display area (1)" are defined in advance in the initialization process (ST3). Therefore, in the processing in step ST6, it is determined whether the current "display area" for frame buffers FBa and FBb is display area (0) or display area (1).

By executing step ST6, the display circuit 74A alternately reads image data from index space 254 (display area (0)) and index space 255 (display area (1)) for each operation cycle δ to drive the display device DS1. Similarly, the display circuit 74B alternately reads image data from index space 251 (display area (0)) and index space 252 (display area (1)) for each operation cycle δ to drive the sub-display device DS2. As explained above, the actual READ access by the display circuit 74 is limited to the valid data area in display area (0)/display area (1).

In any case, in this embodiment, the "display area" switches with each operating cycle, so the display circuits 74A and 74B begin output processing to the display devices DS1 and DS2 for the image data completed by the drawing circuit 76 in the previous operating cycle. However, since the processing of step ST5 begins at the start of the vertical blanking period (V blank) of the main display device DS1, the image data output processing actually begins after the vertical blanking period has ended. In Figure 30(a), the arrows in the display circuit column indicate the operating cycle of this output processing.

Once the processing of step ST6, which has the above significance, is completed, the performance control CPU 63 then completes a display list DL that specifies the image data that the display circuit 74 should output to the display device in the next operating cycle (ST7). Although not limited to this, in this embodiment, a list buffer area (DL buffer BUF) in RAM 59 is reserved and the display list DL is completed there (see Figure 13).

The display list DL is composed of a series of instruction commands listed in an appropriate order and is configured to end with an EODL (End Of DL) command. In this embodiment, to ensure smooth operation of the data transfer circuit 72, drawing circuit 76, and preloader 73, all instruction commands, including the EODL command, are limited to only those whose command length is an integer multiple of 32 bits (N > 0). As explained earlier, instruction commands consisting of an integer multiple of 32 bits may also include don't care bits.

As such, since the display list DL in this embodiment is composed only of instruction commands whose command length is an integer multiple of N (N > 0) of 32 bits, the data volume value (total amount of data) of the entire display list DL is always an integer multiple of the smallest unit of command length (32 bits = 4 bytes). Furthermore, in this embodiment, taking into account the minimum data volume Dmin of the data transfer circuit 72, the data volume value of the display list DL is adjusted to be an integer multiple (1 or more) of the minimum data volume Dmin and also an integer multiple of the smallest unit of an instruction command (4 bytes). For example, if Dmin = 256 bytes, the data volume value of the display list DL is adjusted to one of 256 bytes, 512 bytes, etc.

It would be appropriate to adjust this to 256 bytes or 512 bytes depending on the complexity of the presentation content, but in this embodiment, taking into account that there are two display devices and the sub-display device DS2 does not execute particularly complex image presentations, the data volume value of the display list DL is always adjusted to 256 bytes.

However, this method is not limited in any way, and in gaming machines with three or more display devices, or that execute complex image effects including the sub-display device DS2, the data volume value is adjusted to 512 bytes or 768 bytes. It is also preferable to adjust the data volume value of the display list DL to 256 bytes during normal effects, and to adjust the data volume value of the display list DL to 512 bytes or 768 bytes only when executing special effects.

However, in this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) in each operation cycle δ. Possible adjustment methods are a simple method (A) in which a 32-bit EODL command is followed by a 32-bit NOP (No Operation) command to fill in the missing area, or a standard method (B) in which the missing area is filled with a 32-bit NOP command and then a 32-bit EODL command is written at the end. Alternatively, a non-adjustment method (C) is also possible in which the data volume value (total data amount) of the display list DL is terminated with an EODL command without any adjustment, and dummy data is additionally transferred during operation of the data transfer circuit 72 to ensure a transfer amount that is an integer multiple of the minimum data amount Dmin.

If standard method (B) is adopted, the command counter CNT is initially set to a specified value (64-1, which corresponds to 256 bytes), and the command counter CNT is decremented appropriately each time a significant command is written to the DL buffer area BUF. Once a series of significant commands have been written, NOP commands are written until the command counter CNT reaches zero, and finally an EODL command is written. In this embodiment, the command length is limited to an integer multiple of 32 bits (N>0), so the above process is simple, and the decrement process for the command counter CNT corresponds to the integer N.

On the other hand, when using the simplified method (A), it is sufficient to first fill the entire list buffer area (DL buffer BUF) with NOP commands when creating the display list DL, so at first glance it appears to be superior to the standard method (B). Furthermore, from the perspective of simplicity, the no-adjustment method (C) also appears to be superior. However, this embodiment basically uses the standard method (B), and adjusts the actual amount of data from the beginning of the display list DL to the EODL command, that is, the amount of data up to the EODL command, to always be an integer multiple of the minimum data amount Dmin of the data transfer circuit 72.

This takes into consideration an embodiment that utilizes the preloader 73. If the simple method (A) or the adjustment-free method (C) were adopted, the actual data amount of the display list DL up to the EODL command would become a random value, causing problems when the rewrite list DL' rewritten by the preloader 73 is transferred to the DRAM 54, and when the rewrite list DL' is transferred from the DRAM 54 to the drawing circuit 76. Note that when the rewrite list DL' is transferred to the DRAM 54, the ChA control circuit 72a of the data transfer circuit 72 functions, and when the rewrite list DL' is transferred to the drawing circuit 76, the ChB control circuit 72b functions (see Figure 28). However, in either case, only the rewrite list DL' up to the EODL command is transferred.

The above explains the advantages of the standard method (B) for adjusting the data volume value of the display list DL, but in embodiments that do not use the preloader 73, the issued display list DL is simply processed by the drawing circuit 76, so there is no prohibition on using the simple method (A) or the adjustment-free method (C).

However, in the following explanation, we will assume that standard method (B) is used in principle, regardless of whether or not a preloader 73 is used, and will explain the details of the display list DL based on Figure 23.

Although not particularly limited, in this embodiment, the display list DL first contains a sequence of instruction commands (L11 to L16) related to the main display device DS1, followed by a sequence of instruction commands (L17 to L20) related to the sub-display device DS2. Furthermore, standard method (B) is adopted to adjust the data volume value of the display list DL to a fixed length (256 bytes). Note that Figure 23 also essentially shows the procedure by which the performance control CPU 63 writes instruction commands to the list buffer area of RAM 59, and the operation of the drawing circuit 76 based on the display list DL.

As shown in Figure 23, an environment setting command (SETDAVR) is written at the beginning of the display list DL, specifying the upper left base address (X, Y) in the index space IDX for the frame buffer FBa of display device DS1 (L11). As explained with reference to Figure 12(a), in this embodiment, a pair of frame buffers FBa is reserved in the arbitrary area (c) for display device DS1. Normally, the base address (X, Y) is set to (0, 0), corresponding to the valid data area for the display circuit 74, and the frame buffer FBa is used by the drawing circuit 76 from its beginning.

In Figure 12(c), the actual drawing area on the lower left is labeled L11. This means that the instruction command L11 has specified that the actual drawing area on frame buffer FBa begins at the base address (0,0) of frame buffer FBa. However, the vertical and horizontal dimensions of the actual drawing area and the index number that specifically identifies that actual drawing area have not yet been determined, and will be determined by instruction command (SETINDEX) L13, which will be described later. Note that instruction command L11 also specifies whether or not to use the Z-buffer.

Next, the environment setting command (SETDAVF) is used to set the upper left base coordinates (Xs, Ys) and the lower right diagonal coordinates (Xe, Ye) in the virtual drawing space, thereby defining a drawing area with dimensions W x H (L12). Here, the virtual drawing space is a virtual two-dimensional space with dimensions of ±8192 in the X direction and ±8192 in the Y direction, which can be used to draw using drawing command commands (such as the SPRITE command) (see Figure 12(c)).

This instruction command L12 (SETDAVF) divides the virtual drawing space into a drawing area where the drawing content is actually reflected on display device DS1, and the other non-drawing area. Furthermore, instruction command L12 (SETDAVF) associates the actual drawing area, whose start position (base address) is specified by instruction command L11, with the drawing area in the virtual drawing space.

In other words, instruction command L12 defines an actual drawing area (W x H) starting from the base address in frame buffer FBa (for which the index space is undefined) that corresponds to the drawing area in the virtual drawing space. Therefore, the drawing area specified by instruction command L12 must be the same as or smaller than the horizontal size of frame buffer FBa. Normally, the drawing area and actual drawing area are defined to have the same dimensions as the valid data area (Figure 22 (e)) for the display circuit 74.

After the drawing circuit 76 executes the instruction commands L11 and L12, only the drawing content drawn in the virtual drawing space that is included in the drawing area is reflected in the actual drawing area of the frame buffer FBa. Therefore, drawing content that extends beyond the drawing area or in the area marked as the working area in Figure 12 (c) will not be reflected in the frame buffer as is. Note that when allocating a working area in the virtual drawing space, the non-drawing area of the virtual drawing space is used.

Next, in this operation cycle, the drawing circuit 76 specifies where to draw the drawing content to be drawn based on the display list DL to be completed (L13). Specifically, for the frame buffer FBa of the double-buffered display device DS1, the index space IDX that will be the "write area" for the drawing content based on the current display list DL is specified (L13). Specifically, the SETINDEX command, which is a texture setting command, specifies (1) that the frame buffer FBa is allocated in an arbitrary area, and (2) the index number N in the arbitrary area of the index space IDX _N that will be the "write area."

If, for example, N=255 is specified by this instruction command L13, the actual drawing area corresponding to the drawing area defined in the virtual drawing space is specifically defined as the index space IDX ₂₅₅ in the frame buffer FBa having a double buffer structure.

In this embodiment, the index number of frame buffer FBa is 255 or 254 (Figure 12(a)), and either one is designated by toggling (L13). Note that this index number is the index number of the display area other than (0)/(1) designated in step ST6 of the main control processing. For example, if display area (0) is designated for display circuit 74 in the processing of step ST6, display area (1) becomes the "write area" for drawing circuit 76.

As described above, after the correspondence between the actual drawing area (logical space of W x H) and the drawing area (virtual space of W x H) is generally defined by instruction command L11 and instruction command L12, the virtual space of W x H is associated with the logical space of W x H in the specific index space IDX by instruction command L13 (SETINDEX), which specifically specifies the index space IDX.

In other words, from now on, the content that will be virtually drawn in the W x H virtual space based on a series of instruction commands will become image data in the built-in VRAM 71 (frame buffer) based on a conversion table inside the VDP that defines the correspondence between the virtual space and the real addresses in the built-in VRAM 71.

Next, an instruction command is written to execute a frame buffer clear process that fills the specified index space IDX as the "write area" with, for example, black (L14, L15). This is nothing more than a process to erase the image data written to the frame buffer FBa two operation periods ago.

Specifically, the SETFCOLOR command, which is a type of environment setting command, selects black, for example, and the RECTANGLE command, which is a primitive drawing command, specifies the rectangular area to be filled. The RECTANGLE command specifies the X and Y coordinates of the upper left and lower right corners of the drawing area set in the virtual drawing space (the virtual space corresponding to the frame buffer FBa) (see Figure 12(c)).

The above process completes the rendering preparation process, so next, command instructions are entered to render an appropriate texture, such as a still image or a single frame of video, in the virtual rendering space. Typically, the index space IDX into which the texture will be deployed is first specified using a texture setting command, the SETINDEX command, and then the TXLOAD command, a texture load command, is entered and the specified texture read from CGROM 55 is entered in the display list DL to be deployed in the specified index space IDX.

As explained above, in this embodiment, the background video is composed of IP stream video. Therefore, for example, the index space IDX into which the background video should be loaded is specified as index space IDX ₀ in page area (b) using the texture setting command SETINDEX, and then the texture loading command TXLOAD is written. The TXLOAD command must specify the starting address of the CGROM 55 (texture source address) and the data size (horizontal x vertical) after loading for the video frame to be loaded.

When the VDP circuit 52 executes the TXLOAD command, one video frame (texture) of the background video is first acquired in the AAC area (a), and then the GDEC 75, which starts automatically, expands it into the index space IDX ₀ of the page area (b). This one video frame is then drawn in the virtual drawing space. In this case, the SETINDEX command (texture setting system) may be used to set that "index space IDX ₀ of the page area (b) is the texture to be processed thereafter," but if processing is to be performed immediately following the TXLOAD command, the SETINDEX command may be omitted.

In either case, once it has been determined that "index space IDX ₀ of page area (b) is the texture to be processed subsequently," appropriate inter-rendering calculation command instructions are then entered, such as setting parameters for alpha blending. Alpha blending is a process for making the image already written in the rendering area (frame buffer FBa) transparent or semi-transparent with the image to be overwritten. Therefore, for the first rendering operation, such as for a video frame of a background video, it is not necessary to use inter-rendering calculation command instructions.

Next, the SPRITE command, which is a primitive rendering instruction command, is written to draw the "texture (one video frame of the background video) in index space IDX ₀ of page area (b)" in the appropriate location (rectangular Destination area) in the virtual rendering space. Note that the SPRITE command requires that the upper left and lower right corners of the Destination area in the virtual rendering space be specified.

This destination area is the entire drawing area (virtual space defined on the virtual drawing space) that has been previously associated with the actual drawing area (FBa) by instruction commands L11 and L12, or a portion thereof. However, since background video is usually drawn on the entire display screen, the destination area in such cases is the entire drawing area or larger. An example of a destination area that is larger than the entire drawing area is when the background video is zoomed in.

The above process completes the drawing of the video frames for the background video. Next, command instructions such as texture load, texture setting, inter-drawing calculation, and primitive drawing commands are listed in the appropriate order and overlaid on the background video to create a display list DL for drawing various textures. As explained above, a large number of videos are required for variable effects, so in that case, an index table control command (NEWPIX) is written to increase the index space IDX for page area (b) of the built-in VRAM 71.

For example, for the second IP stream video, an additional index space _IDX1 is reserved in page area (b) using the NEWPIX command, and then this index space _IDX1 is specified (SETINDEX), a command is issued to render one frame of the second video (TXLOAD), and the rendered texture is placed in an appropriate location in the rendering area (SPRITE). Normally, the destination area in this case is part of the rendering area.

The same applies to the following, and after reserving index spaces _IDXk one after another using the NEWPIX command, if multiple IP streams are drawn in the drawing area while performing appropriate alpha blending, the contents drawn in the drawing area will be sequentially stored as image data in the frame buffer FBa, which is the actual drawing area.When a plurality of N IP stream videos are drawn, a plurality of N index spaces are in operation in the page area (b).

Then, when a series of variable effects has ended, the unnecessary index spaces IDX can be deleted using the DELPIX command in order to free up the index spaces IDX that are deemed unnecessary from among the many index spaces IDX ₁ to IDX _k secured in the page area (b).

When drawing still images or I-stream video, use the SETINDEX command to specify that the AAC area (a) is the decode destination for these textures, and then execute the TXLOAD command. The texture acquired in the AAC area (a) will then be expanded into the ACC area (a) by the automatically activated GDEC75. The expanded texture can then be drawn in the appropriate location in the drawing area using the SPRITE command. Depending on whether or not the cache hit function is used, either the first AAC area (a1) or the second AAC area (a2) will be used.

In the explanation up to this point, each texture is drawn directly in the drawing area of the main display device DS1, but this is not necessarily the only possible operation. For example, by creating an appropriate drawing area that does not overlap with the drawing area already reserved for display device DS1 (Figure 12(c)), and associating this drawing area with the working area of the internal VRAM 71, an intermediate drawing area can be constructed and an appropriate rendering image can be completed. The reason for not overlapping with the drawing area for display device DS1 is that for overlapping areas, subsequent association settings take priority, and the contents drawn in that area are not reflected in the frame buffer FBa.

As shown in Fig. 12(c), the work area in this embodiment is index space IDX ₀ in arbitrary area (c). Then, at the timing of the performance using this work area, an instruction command sequence (SETDAVR, SETDAVF, SETINDEX) is written in advance to associate the drawing area for the performance image (see Fig. 12(c)) with the work area (the actual drawing area of index space IDX ₀ ). As shown in Fig. 12(c), the drawing area for the performance image is secured in an area not included in the drawing area for the main display device DS1.

Thereafter, instruction commands similar to the instruction command sequence L16 for frame buffer FBa are entered to complete an appropriate effect image in index space IDX _0. In the case of this embodiment, since the effect image is composed of a still image, an instruction command (SETINDEX) is entered to cause the decoded data to be expanded in the first AAC area (a1), and then a primitive drawing instruction command (SPRITE) is used with an appropriate location in the drawing area of index space IDX ₀ as the Destination. Note that this operation is repeated once or multiple times depending on the effect content.

Then, after positioning the index space IDX ₀ in which the effect image has been completed as a texture (SETINDEX), the effect image (texture) of the index space IDX ₀ can be drawn in an appropriate location in the drawing area of the main display device DS1 using the SPRITE command. In such a case, it is conceivable to decompose the effect image of the index space IDX ₀ into triangular drawing primitives, rotate them at an appropriate angle, and then draw them in the drawing area. The rotation angle of the texture can be associated with, for example, the reliability of the preview effect.

The above describes the instruction command sequence (L11 to L16) for completing one frame on the main display device DS1, but the same applies to the instruction command sequence (L17 to L12) for completing one frame on the sub-display device DS2. That is, the starting X and Y coordinates of the frame buffer FBb are specified (L17) and defined (usually X = 0, Y = 0), and the drawing area for the sub-display device DS2 is defined in the virtual drawing space shown in Figure 12(c) (L18).

In this embodiment, after generating image data for the main display device DS1, the process moves on to generating image data for the sub-display device DS2. This means that even if the drawing area for the sub-display device DS2 overlaps with the drawing area for the main display device DS1, there is no problem, and the drawing area can be set freely. Therefore, when developing a program to generate a display list DL, for example, if you want to apply an appropriate texture to a newly set drawing area using the SPRITE command, you can standardize the settings of the SPRITE command's operating parameters (Destination area) and other settings to a certain extent.

Once this arbitrary drawing area has been defined (L18), the index space IDX that will serve as the "write area" for the drawing content based on the current display list DL is identified for the frame buffer FBb of the double-buffered display device DS2 (L19). The index number of this index space IDX is the index number for the frame buffer FBb that does not correspond to the display area (0)/(1) specified in step ST6 of the main control process.

Then, the instruction command sequence L20 to L22 for the sub-display device DS2 is listed in the same manner as the instruction command sequence L14 to L16 for the main display device DS1. It is also possible to use the effect image completed in the index space _IDX0 .

As described above, in this embodiment, the command lengths of all instruction commands L11 to L22 that make up the display list DL are limited to integer multiples of 32 bits. As explained above, the data volume value (total amount of data) of the display list DL in this embodiment is adjusted to a fixed length (256 bytes), and the necessary number of NOP commands (L23) are added as dummy commands before terminating with the EODL command (L24). In other words, the embodiment in Figure 23 employs the standard method (B) described above.

However, even when standard method (B) is used, it is not necessarily necessary to fix the total data size of the display list DL to 256 bytes throughout all operating cycles. That is, in another embodiment, if the total data size of the display list DL excluding NOP commands exceeds 256 bytes (for example, during a special presentation period), the total data size of the display list DL is adjusted to 512 bytes or more, or N x 256 bytes, by adding NOP commands. As explained above, when standard method (B) is used, the end of the N x 256 bytes is terminated with an EODL command.

The configuration of the display list DL has been explained in detail above, but the performance control CPU 63 then issues the completed fixed-byte-length display list DL to the VDP circuit (ST7-ST8). Figure 24 is a flowchart explaining the DL issuance process (ST8 in Figure 22) in which the performance control CPU 63 directly WRITE-accesses the transfer port register TR_PORT of the transfer circuit 72 and issues a display list DL to the drawing circuit 76. The transfer port register TR_PORT is a type of data transfer register RGij that defines the operation of the data transfer circuit 72.

To execute the DL issuance process, the necessary settings must first be set in the multiple data transfer registers RGij, which define the operation of the data transfer circuit 72. Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission route within the data transfer circuit 72 are specified in the specified data transfer register RGij. While there are no particular restrictions on the settings, here, the settings are set to transfer data from the CPUIF unit 56 via the ChB control circuit 72b, and for the CPU bus control unit 72d, to execute the data transfer operation while checking the remaining capacity of its FIFO buffer (ST20). Note that in the following description, the ChB control circuit 72b may be abbreviated as "transfer circuit ChB" for convenience.

Next, the total transfer size is set in the specified data transfer register RGij. As explained earlier, in this embodiment, the total data amount of the display list DL is adjusted to an integer multiple of 256 bytes, so that value is set. Note that the total data amount = 256 x N is also an integer multiple N of the minimum data amount Dmin of the data transfer circuit 72. Typically, the multiple N is 1 or 2, but in the following explanation, N = 1 will be used.

Here, the transfer port register TR_PORT (hereinafter sometimes abbreviated as transfer port) is a 32-bit register, so the performance control CPU 63 executes a register WRITE operation on the transfer port TR_PORT every 32 bits. Therefore, the value of the management counter CN, which manages the number of register WRITEs, is initially set to 64 (ST21). Note that if the non-adjustment method (C) is used, the data transfer volume that is an integer multiple of the minimum data volume Dmin is determined at this timing, and the management counter CN is set accordingly.

The above process completes the initial settings, and next, data transfer operation via transfer circuit ChB is set to the start state (ST22), and drawing operation is started based on the setting value of a specific drawing register RGij that defines the operation of the drawing circuit 76 (ST23). As a result, the performance control CPU 63 subsequently ensures fast and smooth analysis processing by the drawing circuit 76 (display list analyzer) for instruction command sequences that perform register WRITE operations on the transfer port TR_PORT.

Furthermore, the fact that the instruction commands listed in the display list DL are limited to those with a command length that is an integer multiple of 32 bits also contributes effectively to a fast and smooth analyze process. Timings t1, t2, t3, and t4 in Figure 30(a) indicate the operation timing of step ST23. Note that because the display list DL issuance process (ST8) is completed quickly, the time required for the issuance process is not shown in Figures 30 and 31.

Next, it is confirmed whether the settings in step ST22 have worked (ST24). This is because the initial settings of each part of the data transfer circuit 72 take longer to process than the register WRITE operation (setting operation) by the performance control CPU 63, so no further instructions are given to the incomplete data transfer circuit 72. If the circuit does not start operating after waiting for a predetermined time, the serious abnormality flag ABN is set and the DL issuance process is terminated (ST25). As a result, the WDT circuit 58 then functions, and the composite chip 50 is reset as abnormal (ST10).

As mentioned above, the performance control CPU 63 may output a predetermined keyword string to the pattern check circuit CHK to abnormally reset only the VDP circuit 52 based on the reset signal RST in order to avoid resetting the CPU circuit 51.

However, since the setting in step ST22 is usually completed quickly, the CPU bus control unit 72d then checks to see if the FIFO buffer (32 bits x 130 stages) is full (ST26), and then writes instruction commands to the transfer port TR_PORT for each line in the display list DL, starting from the first line (ST28).

Then, while decrementing the management counter CN (ST29), steps ST26 to ST29 are repeated until the management counter CN reaches zero (ST30). In this embodiment, a minimum data amount Dmin is specified for the data transfer circuit 72, so the data transfer operation is executed when the minimum data amount Dmin is accumulated in the FIFO buffer, resulting in intermittent transfer operations.

In any case, in this embodiment, the DL issuance process (ST28) is completed quickly. However, if the settings in the VDP register RGij become inconsistent due to noise or other factors, the FIFO buffer full state determined in step ST26 may not be resolved even after waiting for a specified period of time. In such a case, initialization data is set in the specified VDP register RGij, the drawing circuit 76 and data transfer circuit 72 are initialized, and the serious abnormality flag ABN is set, ending the DL issuance process (ST27).

By the way, at this timing, the data transfer circuit 72 and drawing circuit 76 have already started operating and have completed a certain amount of processing, so the initialization process for the drawing circuit 76 includes (1) setting all internal parameters that may be set by the display list DL to their initial values, (2) setting all internal control circuits to their initial states, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area, while maintaining the contents of the drawing register RGij. Similarly, the initialization process for the data transfer circuit 72 includes initialization of the entire data transfer up to that point, such as clearing the FIFO buffer. As a result, the status information indicating the operating state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

Note that while the contents of the drawing register RGij were maintained in the initialization process of step ST27 described above, the contents of certain drawing registers may also be initialized. The certain drawing registers that are cleared to their initial values include (a) an execution control register that sets the start of drawing execution (see ST23 in Figure 24), (b) a status register that indicates the execution status of the drawing circuit 76, and (c) a status register that identifies the position of the display list currently being processed.

In either case, as a result of setting the serious abnormality flag ABN, the WDT circuit 58 and performance control CPU 63 then function and the composite chip 50 or VDP circuit 52 undergoes an abnormal reset (ST10a), so initializing the drawing circuit 76 and data transfer circuit 72 is not necessarily required. On the other hand, if the drawing circuit 76 and data transfer circuit 72 are initialized, recovery from the abnormality can be expected as a result, so it is also preferable to return to the processing of step ST20 and re-execute the DL issuance process without setting the serious abnormality flag ABN.

The same applies to the processing of step ST25, where it is preferable to initialize the data transfer circuit 72 and drawing circuit 76 and then return to the processing of step ST20 without setting the serious abnormality flag ABN. In such a case, however, the number of times the DL issuance processing is retried is counted, and if the number of retries exceeds a limit value, the serious abnormality flag ABN is set and the DL issuance processing is terminated.

Figure 24(b) is a confirmation diagram of a normal operating state. As shown in the figure, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the listed instruction commands, and operations based on each instruction command are executed. This operation is executed in parallel with the display list DL issuance process and the data transfer operation (ST26 to ST30) of the data transfer circuit 72.

For example, when the instruction command (TXLOAD) is executed, the necessary texture is read from CGROM 55 and stored in AAC area (a). The GDEC 75 then automatically starts up and performs a decoding operation, with the decoded data being expanded into a specified index space. Depending on the instruction command, the geometry engine 77 and other functions may also function, but in any case, the various parts of the drawing circuit 76 work together to complete the image data corresponding to the display list DL in the frame buffers FBa and FBb.

Next, we will explain the case where a display list DL is issued via the DMAC circuit 60, based on Figure 25. Although not limited in any way, we will use the third DMA channel of the first to fourth DMA channels built into the DMAC circuit 60.

In the example of Figure 25, first, a clear value is set in a specified data transfer register RGij and a specified drawing register RGij, respectively, to initialize the data transfer circuit 72 and the drawing circuit 76 (ST20). This process is the same as the error processing in step ST27 of Figure 24, in which the internal circuitry of the data transfer circuit 72, including the FIFO buffer, is initialized, the status bit of the data transfer register indicating the progress of the data transfer is set to its initial value, and the bit indicating that the entire data transfer is being initialized is set to a specified value.

The same applies to the drawing circuit 76, and includes the above-mentioned processes of (1) setting internal parameters to initial values, (2) setting the internal control circuit to an initial state, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area. The aforementioned predetermined drawing register RGij may also be initialized during the drawing circuit initialization process (ST20 in FIG. 25). Note that this initialization process may be executed first in the process of FIG. 24.

In the process of Figure 25, the specified status register RGij, which specifies the operating status of the data transfer circuit 72 and the drawing circuit 76, is then read to confirm that the initialization process has been completed successfully (ST21). If initialization is not possible, the serious abnormality flag ABN is set and the process ends (ST22). However, this situation almost never actually occurs.

Next, the transfer operation mode of the data transfer circuit 72 and the internal transmission route of the data transfer circuit 72 are set in a specified data transfer register RGij. The settings are not particularly limited, but here, the settings are set to route from the CPUIF unit 56 through the ChB control circuit 72b, and the transfer protocol to the CPU bus control unit 72d follows the settings in the DMAC circuit 60 (ST23).

Next, the total transfer size is set in the specified data transfer register RGij. As in Figure 24, the total data amount = 256. If the non-adjustment method (C) is used, the total transfer size is determined and set at this timing as an integer multiple of the minimum data amount Dmin. Next, the drawing operation of the drawing circuit 76 is started based on the value set in the specified drawing register RGij (ST25). Timings t1, t2, t3, and t4 in Figure 30(a) are also the operation timings of step ST25. Next, the DMAC circuit 60 is started to operate (ST26), and then the data transfer operation of the data transfer circuit 72 is started (ST27).

The process for starting the operation of the DMAC circuit 60 is shown in Figure 25(b). First, DMAC transfer is disabled and the process waits for the transfer of one data transfer unit (one operand) per cycle to be completed (ST40). The detailed operation is the same as the process shown in Figure 26, and is divided into the process of disabling DMAC transfer (ST53) and the subsequent wait process (ST54).

The reason for providing this processing is that (1) in other embodiments, the DMAC circuit 60 (third DMA channel) may be used in the main control processing or timer interrupt processing (Figure 22), and (2) in other embodiments that do not provide the processing of step ST5 in Figure 22, the DMAC circuit 60 that has started issuing a display list DL may not be able to complete the DL issuing operation within its operating period (δ).

In exceptional circumstances such as those described above, if new setting values (such as conflicting setting values) are additionally set for the operating DMAC circuit 60, normal DMA operation cannot be guaranteed and serious problems may occur. However, by providing the processing of step ST40, normal operation based on the subsequent setting values is guaranteed. In other words, even in a modified embodiment that is a partial modification of this embodiment, normal subsequent DMA operation can be achieved regardless of any preceding problems.

After executing the processing of step ST40, which has the above significance, the operating conditions of the DMAC circuit 60 are set (ST41). Specifically, as shown in Figure 9, cycle steal transfer mode is selected, and one operand transfer is set to two 32-bit transfers. It also specifies that the source address should be recognized as sequentially increasing because it is an address in the list buffer area (DL buffer BUF) of RAM 59, while the destination address should be a fixed value because it is the transfer port TR_PORT.

Next, the start address of the DL buffer BUF in RAM 59 is set in a predetermined operation control register REG that defines the operation of the DMAC circuit 60 (ST42), and the address of the transfer port TR_PORT, which is the transfer destination address, is set (ST43). The total transfer size, i.e., the total amount of data in the display list DL, is set to 256 bytes (ST44), and the DMA operation of the DMAC circuit 60 is started (ST45).

The explanation up to this point has been based on the assumption that the actual bit length of all instruction commands is an integer multiple of 32 bits. However, the configuration of the display list DL and instruction commands is not necessarily limited, so the following explanation will focus on such cases.

For example, even when the non-adjustment method (C) described above is used, if the total data amount X of the display list DL is an arbitrary value X that is not an integer multiple of 32 bits, in the processing of step ST44, this arbitrary value X is adjusted to an appropriate transfer amount MOD, and then the total transfer size setting process is executed. Here, the appropriate transfer amount MOD is determined based on the settings for one operand transfer and the minimum data amount Dmin (bytes) of the data transfer circuit 72.

Specifically, if the single operand transfer setting is N bytes x M times, the transfer amount MOD is adjusted to a value that is an integer multiple of N x M (bytes) and an integer multiple of Dmin (bytes). For example, if N x M = 8 x 4 and Dmin = 256, the arbitrary value X (= 300) bytes is adjusted to the transfer amount MOD (= 512) bytes.

The above explanation includes general concepts, but the DMA operation of the DMAC circuit 60 begins with a cycle steal transfer operation as shown in Figure 9, and the display list DL is transferred to the transfer port TR_PORT in 32-bit increments in this example, without interfering with CPU operation. The transferred data is then transferred to the drawing circuit 76 via transfer circuit ChB.

To achieve this operation, in this embodiment, following the processing of step ST45, the data transfer circuit 72 begins its transfer operation and ends the processing (ST27). The data transfer circuit 72 then receives a series of display list DL instruction commands from the DMAC circuit 60, with the minimum data volume Dmin as one unit, and transfers these to the drawing circuit 76. The drawing circuit 76 then executes drawing operations based on the display list DL instruction commands. Therefore, after processing step ST27, the performance control CPU 63 can begin processing step ST11 in FIG. 22, and can control audio, lamp, and motor effects in parallel with the drawing operation by the VDP circuit 52 (DL issuance processing by the DMAC circuit 60).

Figure 25(c) illustrates this operation. Prior to the DMA transfer, the drawing circuit starts operation (ST25), and the display list analyzer of the drawing circuit 76 quickly and smoothly executes the analysis process. Based on the operation of the GDEC 75, geometry engine 77, etc., one frame's worth of image data is generated in the frame buffers FBa and FBb for each of the display devices DS1 and DS2.

However, the configuration of Figure 25, in which the DL issuance process ends with the processing of step ST27, is not necessarily limited. For example, as in Figures 32 and 33, if another CPU controls the audio effects, lamp effects, and motor effects, it is preferable to check the normal operation of the DMAC circuit 60 and data transfer circuit 72 after processing step ST27. Figure 26 is a flowchart that explains the operation following step ST27 in Figure 25 and the process of checking normal operation.

First, a specific status register is referenced to confirm that the DMAC circuit 60's transfer operation has completed successfully (ST50). It is also confirmed that the data transfer circuit 72 has completed its transfer operation (ST51). This is how the DL issuance process in Figure 25 is usually completed.

On the other hand, if the operation of the DMAC circuit 60 has not been completed after waiting for a predetermined time, or if the data transfer circuit 72 has not completed its transfer operation, a clear value is set to a predetermined VDP register RGij for the drawing circuit 76 and data transfer circuit 72, and the DL issuance process is initialized (ST52). This is an operation based on the fact that the display list DL issuance process has not ended normally, and specifically, it is the same as the error processing in step ST27 of FIG. 24 and the initial processing in step ST20 of FIG. 25.

In other words, in this case too, the drawing circuit 76 has already started operating and has already completed a certain amount of processing, so the initialization process for the drawing circuit 76 includes (1) setting all internal parameters that may be set by the display list DL to their initial values, (2) setting all internal control circuits to their initial states, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area.

Next, new DMA transfer operations are prohibited (ST53), and the process waits for the ongoing transfer operation of one operand to finish (ST54). As explained earlier, in this embodiment, two 32-bit transfers are considered one operand, and this is to avoid abruptly initializing the DMAC circuit 60 while it is in operation.

Once this preparation work is complete, a clear value is set in the specified operation control register REG, which defines the operation of the DMAC circuit 60, to initialize the DMAC circuit 60 (ST52). The serious abnormality flag ABN is then set, and the DL issuance process is terminated. In this case, since the processing of steps ST52 and ST55 can be expected to recover from the abnormality, it is also preferable to return to step ST20 in Figure 25 and re-execute the DL issuance process without setting the serious abnormality flag ABN. However, the number of retries of the DL issuance process (ST23 to ST27) must be counted, and if the number of retries exceeds a limit, the serious abnormality flag ABN must be set and the DL issuance process must be terminated.

Next, the main control processing when using the preloader 73 will be described with reference to Figure 27. The processing in Figure 27 is similar to the processing in Figure 22, but differs first in the content of the start condition determination (ST5'). That is, in an embodiment using a preloader, at the start of each operation cycle, status information from the drawing circuit 76 and preloader 73 is read and accessed to confirm that the drawing operation based on display list DL1 has finished, and that the preload operation based on display list DL2 has finished (ST5').

As shown in the time chart of Figure 31(a), for example, the preloader 76 should have completed the pre-reading operation (preloading operation) during the operating cycle (T1 to T1+δ) based on the display list DL1 issued during that operating cycle (T1). Furthermore, the drawing circuit 76 should have completed the drawing operation based on the display list DL1 during the operating cycle (T1+δ to T1+2δ) based on the operation start command issued during the operating cycle (T1+δ).

Therefore, in (ST5'), the status information of the VDP register RGij related to the drawing circuit 76 and preloader 73 is read and accessed to confirm the above-mentioned normal operation. Figure 31(a) shows that normal operation is confirmed at the judgment timings of operation cycles T1, T1+δ, T1+2δ, and T1+4δ, but that the preload operation has not finished at the judgment timing of operation cycle T1+3δ.

In the event of such an abnormality, the abnormality flag ER is incremented (ER = ER + 1) and the process proceeds to step ST9. As a result, as in the example of Figure 22, a frame is dropped. In other words, the display area switching process (ST6) is skipped, and the same screen is redisplayed. The operating period (T1 + 3δ to T1 + 4δ) shown in Figure 30 (a) shows this operating state.

Furthermore, if the start condition is not met as determined in step ST5', the drawing circuit 76 is not instructed to start the drawing operation (PT10) based on the rewrite list DL', so the drawing circuit 76 is in an inactive state and no new display list is generated. Note that in Figure 31(a), timings t0, t2, and t4 indicate the operation timing of the drawing operation start instruction (PT10), or more precisely, the timing of step ST26 in Figure 28.

The above describes the case where the judgment in step ST5' is incompatible, but under normal circumstances, after toggling between the display areas of frame buffers FBa and FBb (ST6), the drawing circuit 76 is instructed to begin drawing operations based on the rewrite list DL' (PT10). Specific details are shown in Figure 28, where, under the control of the performance control CPU 63, the drawing circuit 76 retrieves the rewrite list DL' from the DL buffer BUF' in the external DRAM 54 via the data transfer circuit 72 (transfer circuit ChB) and performs drawing operations.

Prior to explaining the flowchart in Figure 28 that realizes this operation, let's examine the operation of the preloader 73. The preloader 73 has completed a look-ahead operation (preload) from the CGROM 55 based on the display list DL obtained one operating cycle ago, and the pre-read data has already been stored in a preload area allocated in the external DRAM 54. Furthermore, for texture load commands (TXLOAD) listed in the display list DL, their source addresses have been rewritten to addresses in the preload area, and these have been stored in the DL buffer BUF' in the external DRAM 54 as a rewrite list DL'.

Note that this rewrite process does not change the total amount of data in the display list DL, and the total amount of data in the rewrite list DL' is the same as that of the display list DL. Furthermore, the display list DL was created using the standard method (B), and the end of the rewrite list DL' is an EODL command, just like the display list DL.

With the above in mind, referring to Figure 28, the performance control CPU 63 first sets clear values to the specified data transfer register RGij and the specified drawing register RGij, respectively, to initialize the data transfer circuit 72 and the drawing circuit 76 (ST20). This process is identical to the process at ST20 in Figure 25. Next, it confirms that this initialization process has completed successfully (ST21), and if the initialization is not completed after a specified time has elapsed, it sets the serious abnormality flag ABN and ends the process (ST22).

Normally, the initialization of the data transfer circuit 72 and drawing circuit 76 is completed successfully, so the internal data transfer route for the data transfer circuit 72 is set to a specified data transfer register RGij (ST23). Specifically, it is set to transfer data from the external DRAM 54 to the drawing circuit 76 via the ChB control circuit 72b (ST23). Next, the starting address of the DL buffer BUF' in the external DRAM 54, which stores the rewrite list DL', is set to the specified data transfer register RGij (ST24).

Furthermore, for this rewrite list DL', the total transfer size is set in a specified data transfer register RGij (ST25). As explained above, the total data amount of the rewrite list DL' is the same as the total data amount of the display list DL, specifically, for example, 256 bytes.

Next, the drawing operation of the drawing circuit 76 is started based on the value set in the specified drawing register RGij (ST26). Timings t1, t2, t3, and t4 in Figure 30(a) are also the operation timings of step ST26. Next, the operation of the data transfer circuit 60 is started based on the value set in the specified data transfer register RGij, and the processing ends (ST27). Thereafter, the performance control CPU 63 does not particularly participate in the operation of the data transfer circuit 72 or the drawing circuit, and proceeds to the display list generation process (ST7) that will be executed in the next operating cycle.

Meanwhile, the drawing circuit 76, which begins operation at step ST26, performs drawing operations based on the rewrite list DL' and generates image data based on the rewrite list DL' in the frame buffers FBa and FBb. Note that during this operation, the drawing circuit 76 does not perform READ access to the CGROM 55, but instead performs READ access solely to the preload area, allowing the series of drawing operations to be completed quickly.

The processing content of step PT10 has been explained above. Returning to FIG. 27, after the processing of step PT11, in an embodiment utilizing the preloader 73, a display list DL to be executed in the next cycle is created based on the standard method (B) (ST7). For example, in the operating cycle (T1) shown in FIG. 31(a), a display list DL to be referenced by the drawing circuit 76 is created in the next operating cycle (T1+δ).

Next, the performance control CPU 63 issues the created display list DL to the preloader 73, not to the drawing circuit 76 (PT11). The specific operation is as shown in Figure 29. Previously, with regard to the embodiment (Figure 22) that does not use the preloader 73, we showed the case where the performance control CPU 63 issues the display list DL directly to the drawing circuit 76 (Figure 24) and the case where it issues via the DMAC circuit 60 (Figure 25). In Figure 29, almost the same operation is shown in Figures 29(b) and 29(c), except that the destination is the preloader 73.

Figure 29(a) is a flowchart explaining the operation of Figure 29(b), and is almost identical to the flowchart of Figure 24. However, it is set so that data is transferred from the CPUIF unit 56 via the ChC control circuit 72c, and that the CPU bus control unit 72d executes the data transfer operation while checking the remaining capacity of its FIFO buffer (ST20). Note that in the following description, the ChC control circuit 72c may be abbreviated as "transfer circuit ChC" for convenience.

Next, the total transfer size (e.g., 256 bytes adjusted using standard method (B)) is set in the specified data transfer register RGij, and the management counter CN is initialized to 64 (ST21). Next, the data transfer operation via the transfer circuit ChC is set to the start state (ST22), and the preload operation is started based on the set value in the preload register RGij, which defines the operation of the preloader 73 (ST23).

As a result, the preloader 73 then performs the necessary analysis (Analyze) for each instruction command written to the transfer port TR_PORT by the performance control CPU 63, and when it detects an instruction command (TXLOAD) that requires READ access to the CGROM 55, it preloads the texture and saves it in the preload area of the DRAM 54. It also saves the rewrite list DL' with the changed texture source address in the DL buffer area BUF' of the DRAM 54.

Note that timings t1, t3, and t5 in Figure 31(a) effectively represent the operation timing of step ST23 in Figure 29. However, even in this embodiment, if any abnormality occurs during the display list DL issuance process, the processes of steps ST25 and ST27 are executed. Specifically, the operation of the data transfer circuit 72 and preloader 73 is initialized, and the display list DL issuance process (ST20 to ST30) is re-executed to the extent possible. The initialization process of the preloader 73 includes erasing the incomplete rewrite list DL' and clearing the preload area where new preload data has been stored.

The above provides a detailed explanation of when the preloader 73 is used and when it is not used, but the specific operation is not particularly limited. Figure 30(b) shows an example in which the display list generated by the performance control CPU 63 is issued to the drawing circuit 76 with a delay of one operating cycle δ, rather than in the same operating cycle in which it was generated. In such an example, the drawing circuit 76 can use almost the entire time of one operating cycle (δ), thereby reducing the possibility of frame drops.

Furthermore, Figure 31(b) shows an example in which the display list generated by the performance control CPU 63 is issued to the preloader 73 one operation cycle later, rather than in the same operation cycle in which it was generated. In this case, the preloader 73 can perform preloading operations using almost the entire time of one operation cycle (δ), thereby again reducing the possibility of frame drops.

In the explanation so far, we have used a combined chip 50, but the performance control CPU 63 and VDP circuit 52 do not necessarily need to be integrated into a single element. Furthermore, in the above example, the entire performance control is controlled by a single CPU (performance control CPU 63), but the upstream CPU and downstream performance control CPU 63 may also work together to execute performance control operations.

Figures 32 and 33 are block diagrams showing such an embodiment. As shown, in this embodiment, the upstream performance control CPU controls the audio performance, lamp performance, and motor performance. Meanwhile, the downstream CPU circuit 51 controls only the image performance based on the control command CMD' received from the performance control CPU.

When this configuration is adopted, the CPU circuit 51 does not need to perform the processing of step ST12 in Figure 22(a) and the processing of Figure 22(b), and can take sufficient time to generate a complex display list DL, enabling more complex and advanced image effects such as 3D (Dimensional) to be realized. In such cases, the display list becomes larger, but in this case, the total data size of the display list DL can be adjusted to 512 bytes or more, i.e., N x 256 bytes, by adding dummy commands.

Furthermore, since the operation of the downstream CPU circuit 51 is specialized for image presentation control, it is also possible to confirm that the drawing operation is complete after the display list DL is issued. The lower part of Figure 24 shows an example of operation control in this case, and if the drawing operation is not completed after the limit time has elapsed, the serious abnormality flag ABN is set and processing ends (ST32). Note that, since the processing of the downstream CPU circuit 51 is limited to image presentation control, it is also possible to simply wait for the drawing operation to be completed in an infinite loop.

When this configuration is adopted, the start condition determination (ST5) in Figure 22(a) can be repeated for a predetermined time. Even with this configuration, as long as the delay in completing the drawing operation is not too long, the only problem that occurs is a delay in switching between display area (0) and display area (1). In other words, as shown in Figure 34(a), in one operation cycle in which the display operation is repeated twice, frames are dropped only in the first half, and normal frames are displayed in the second half.

This is also true when a preloader is used, and the start condition determination (ST5') in Figure 27(a) can be repeated for a predetermined period of time. If there is a slight delay, frames will be dropped in only the first half, as in the operation cycle T1 + 3δ shown in Figure 34(b), and normal frames will be displayed in the second half. However, if the completion of the drawing operation is significantly delayed, complete frame dropping will occur, as in the operation cycle T1 + 3δ in Figure 30(a), and if this situation continues, the WDT circuit 58 will be activated. This is also true when a preloader is not used.

Furthermore, when the control operation of the CPU circuit 51 is specialized for image rendering control, in an embodiment employing DMA transfer, as shown at the bottom of Figure 26, the completion of the drawing operation of the drawing circuit 76, the completion of the operation of the data transfer circuit 72, and the completion of the operation of the DMAC circuit 60 are determined (ST50'-ST52'). If any of the operations does not end normally, the operation of the data transfer circuit 72 and the drawing circuit 76 is initialized, and processing similar to the processing of steps ST53-ST55 (ST55'-ST57') is executed. Note that in this case as well, it is preferable to re-execute the DL issuance process a predetermined number of times.

The above describes an embodiment in which an index space with a horizontal size that perfectly matches the number of horizontal pixels of each display device is constructed as the frame buffers FBa and FBb of the main display device DS1 and sub-display device DS2. Figure 35(a) clearly illustrates this relationship, showing a case in which the drawing area (W x H) in the virtual drawing space and the valid data area (actual drawing area W x H) in the index space both match the number of horizontal and vertical pixels of the display devices.

In this correspondence relationship, the drawing operation in the virtual drawing space by the display list DL is not necessarily limited to the drawing area (W x H). For example, as shown by the left-sloping line at the top of Figure 35(a), by moving the drawing position over time for a drawing image (W' x H') that exceeds the drawing area (W x H), it is possible to move the drawing content in the actual drawing area W x H, shown by the right-sloping line at the bottom of Figure 35(a), vertically, horizontally, or diagonally as appropriate.

In order to achieve this effect, for example, an index space with a horizontal size W larger than the number of horizontal pixels of the display device may be provided, as shown in Figure 35(b). In this case, the drawing area WxH in the virtual drawing space defined by instruction command L12 (SETDAVF) in the display list DL is set larger than the actual drawing area wxh corresponding to the number of horizontal/vertical pixels of the display device. Note that the actual drawing area wxh is indicated by a right-sloping line at the bottom of Figure 35(b).

The vertical and horizontal dimensions of the actual drawing area w x h are then specified as the number of display lines and horizontal pixels of the display device in step SS30 of Figure 21, and the upper left corner point of the actual drawing area w x h is set in a specified display register as the vertical/horizontal display start position in step SS36 of Figure 21.

Meanwhile, the base address (X, Y) in the index space is set in a specified drawing register by the display list instruction command L11. As explained earlier, specifically, the environment setting instruction command L11 (SETDAVR) specifies the top left base address in the index space IDX as (0, 0), for example. Then, by moving the top left corner point of the actual drawing area w×h as appropriate during routine processing, the drawing contents of the actual drawing area W×H, indicated by the right-sloping line at the bottom of Figure 35(b), will move vertically, horizontally, or diagonally as appropriate.

As explained in relation to Figure 21, the VDP register RGij related to steps SS30 to SS37 is write-protected after initial setting (second protection setting SS39), but when the above-mentioned effect is executed, this protection is released by writing a release value to a specific VDP register RGij.

In the above embodiment, the first and second type prohibition setting registers are utilized to uniformly set certain system control registers RGij and certain VDP registers RGij for the initial setting system to a write-prohibited state (see SS38 and SS39 in Figure 21), preventing the settings of these registers from being changed thereafter due to noise or other factors. However, it is also preferable to repeat the setting process for important system control registers RGij at predetermined intervals without setting them to a write-prohibited state.

Figure 36 is a diagram explaining the processing in such a case, where the setting values to be set in the initial setting processing (SS1 to SS3) are summarized in a setting value table SETTABLE stored in control memory 53 (PROGMROM). Note that, although explanations of steps SS1 to SS3 in Figure 21 are omitted, the embodiment of Figure 21 is substantially the same as the content explained below in terms of (a) executing the initial setting processing based on the initial value setting table SETTABLE, and (b) the contents of the initial value setting table SETTABLE.

In either embodiment, the setting value table SETTABLE is composed of multiple sets (N sets), each set consisting of the register address value of a VDP register RGij and the setting value for that register RGij. Although not particularly limited, the register address value is fixed at 16 bits and the setting value is fixed at 32 bits. As each is a fixed length, the data capacity of the initial value setting table SETTABLE is 6 x N bytes (= 48t x N bits) long, and there are N VDP registers RGij.

However, whereas in the embodiment of FIG. 21, the initial value setting table SETTABLE is accessed for READ only once and all N VDP registers RGij are initialized only once, in the embodiment of FIG. 36, all N VDP registers RGij are divided into N1 VDP registers RGij that are initialized only once, and N2 VDP registers RGij that are repeatedly initialized every 1/30 seconds after the first initialization. However, even in the embodiment of FIG. 36, the processing of steps SS5 to SS6 is only executed once after power is turned on.

In the example of Figure 36, the setting values that are repeatedly initialized include (1) setting values for DMA transfer operations, (2) setting values for VRAM, (3) setting values for interrupts, (4) setting values for the display circuit 74, and (5) setting values for the drawing circuit 76.

(1) The setting values for DMA transfer operations are, for example, setting values that are prerequisites for the operating conditions specified in step ST41, and are basic setting values that are fixedly applied regardless of differences in the operating conditions in Figures 25(c) and 29(c). Specifically, these include setting values such as (a) the threshold for how much of the FIFO buffer (N stages) built into the DMA circuit 60 must be freed up before a transfer request is made to the transfer source (e.g., 1/2 of the total stages), and (b) whether or not to perform a handshake operation with the transfer destination and transfer source (e.g., No).

Furthermore, (2) the VRAM setting value includes the refresh cycle for refresh operations. By operating the built-in VRAM 71 at this refresh cycle, natural discharge of stored data is prevented. Next, (3) the interrupt-related setting value is a value that specifies the type of error that will cause an interrupt request and the output terminal of the interrupt signal (internal terminal of the built-in CPU). For example, it includes setting values such as (a) that if the drawing circuit 76 freezes, a drawing abnormality interrupt will be generated for the CPU circuit 51 (interrupt enabled state, see Figure 22(d)), and (b) that when VBLANK starts on the display device DS1, a VBLANK start interrupt will be generated for the CPU circuit 51 (see Figure 22(c)).

In this embodiment, a combined chip 50 is used in which the CPU circuit 51 and VDP circuit 52 are integrated. However, if they are separate chips, the output terminal from which the VDP circuit 52 outputs an interrupt signal is connected to the external interrupt input terminal of the CPU circuit 51.

(4) Display circuit settings include (a) the horizontal/vertical start position of each frame buffer (see SS36), (b) the horizontal synchronization signal setting for each display device, (c) the vertical synchronization signal setting for each display device, (d) the scaler setting, and (e) the number of horizontal pixels and number of display lines setting for each display device (SS30).

(5) The settings for the drawing circuit 76 include a setting value for the freeze time until a drawing abnormality interrupt occurs. This setting value is set, for example, as an integer multiple of the period of the vertical synchronization signal. As explained in Figure 22(d), if the drawing circuit 76 does not access the VRAM during the specified freeze period, the drawing circuit 76 is individually reset (ST16b), and the operating parameters for the drawing circuit 76 are reset (ST16c).

As mentioned above, in this embodiment, important setting values are repeatedly reset at predetermined intervals, so even if a bit in a setting value becomes corrupted due to noise or other factors, the abnormality is immediately corrected. Furthermore, in this embodiment, the first and second type inhibition setting registers RGij are not set to a write-protected state, as in the embodiment of Figure 21, so rewriting can be performed freely without having to go through the somewhat complicated inhibition release process.

So far, in the embodiments described above, a configuration has been described in which a drawing abnormality interrupt is generated from the drawing circuit 76 of the VDP circuit 52 to the CPU circuit 51 when (1a) the drawing circuit 76 enters an operation freeze state after a predetermined freeze time has elapsed, or (1b) the drawing circuit 76 detects an irrational instruction command in the display list DL (see FIG. 22(d)). When a drawing abnormality interrupt occurs, the cause of the interrupt is determined (ST16a in FIG. 22(d)), and processing is executed according to the determination result (ST16c to ST16d).

However, according to the inventor's experiments, drawing abnormality interrupts rarely occur, even under harsh operating conditions with a lot of noise. Therefore, in order to reduce the control burden, it is preferable to either move to a uniform infinite loop process (see Figure 27(b)) without providing interrupt cause determination processing (ST16a), or to activate the pattern check circuit CHK (see Figure 7(b)) (see ST17a in Figure 27(c)).

In this case, the WDT circuit 58 will then be activated after a predetermined time, and the entire combined chip 50 will be reset, or just the VDP circuit 52 will be reset immediately thereafter (see Figure 7(b)). If the VDP circuit 52 is reset based on the reset keyword output process (ST17a), the normal completion of the reset operation will be confirmed, and the stack area that stores the return address will be organized (ST17b), after which processing will proceed to, for example, step ST4 or ST13.

In addition, in this embodiment, an abnormality determination process (ST5 in Figures 22 and 27) is provided to determine whether the drawing circuit 76 has completed operation every 1/30 seconds. To further reduce the control burden, a drawing abnormality interrupt process (Figure 27(d)) that essentially does nothing may be provided. As shown in Figure 27(d), in this configuration, when a drawing abnormality interrupt occurs, the IRET (Interrupt Return) command is immediately executed to return to the main control process, so the drawing circuit 76 may remain frozen. However, in this embodiment, the number of frame drops is counted using the abnormality flag ER in the process of step ST5 in Figures 22 and 27, and either the WDT circuit 58 or the pattern check circuit CHK will eventually be activated. Therefore, the configuration of Figure 27(d) is essentially the same as the configurations of Figures 27(b) and 27(c).

In addition, to further reduce the control burden, it is also preferable to set the VDP circuit 52 to a drawing abnormality interrupt disabled state during initialization (see step SS3 in Figure 21). If the default state at power-on is a drawing abnormality interrupt disabled state, (a) a specific system control register RGij, which should set the enable/disable value that specifies whether abnormality interrupts are enabled or disabled, is set to a write-disabled state, or (b) a disable value is repeatedly written to the system control register RGij at predetermined intervals.

At first glance, this configuration appears to be superior to the configurations in Figures 27(b) and 27(b). However, from the perspective of versatility of the control program, it is better to (b) uniformly enable drawing abnormality interrupts for all models of this type of gaming machine, rather than (a) uniformly prohibiting them for all models. Then, for each model, select either the configuration in Figure 22(d) or one of the configurations in Figures 27(b) to (d). Note that the former configuration (a) requires (complexity) changes to the initial setting routine (see step SS3 in Figure 21) for each model.

As a further modified embodiment, it is also preferable to utilize the audio circuit SND built into the combined chip 50. Figure 37 is a block diagram showing such an embodiment. As is clear from comparing Figure 37 with Figure 7, in this embodiment, the audio processor 27 and audio memory 28 are not required, and external wiring to the audio circuit is not required for the data bus (8 bits) and address bus (2 bits) of the CPU circuit 51. In addition, since there is no transmission line for the underflow signal UF, the risk of the combined chip being erroneously reset due to noise superimposed on this UF transmission line is also avoided.

Furthermore, in this embodiment, in response to the elimination of the audio memory 28, the audio data that should be stored in the audio memory 28 is stored in the CGROM 53. Figure 38(d) illustrates the contents of the CGROM 53, which permanently stores sound ROM header information, phrase header information HD, a large number of phrase data PH that are compressed groups of audio data, and a large number of sound commands SCMD that define the operation of the audio circuit SND.

As shown in the figure, sound ROM header information is stored starting from the first address SNDst, followed by phrase header information HD of data size HDvl, stored starting from the first address HDst. Furthermore, phrase data PH of data size PHvl is stored starting from the first address PHst, and sound command SCMD of data size SCMDvl is stored starting from the first address SCMDst.

Here, sound ROM header information specifically refers to the start address HDst of the phrase header HD area, the data size HDvl of the phrase header HD area, the start address PHst of the phrase data area PH, the data size PHvl of the phrase data area PH, the start address SCMDst of the sound command area SCM, and the data size SCMDvl of the sound command area SCMD. This information is acquired by the internal circuitry of the audio circuit SND when power is turned on (see step SD4).

Furthermore, the phrase header information HD and phrase data PH are transferred to the external DRAM 54 when the power is turned on, thereby speeding up subsequent READ access (step SD6). In this way, in this embodiment, the voice processor 27 and voice memory 28 are eliminated, thereby reducing size and manufacturing costs, and overcoming the weakness of the CGROM 53, which is inexpensive and easy to increase in capacity, but has a slow access speed.

Based on the above, the initial setup process at power-on will be explained with reference to Figure 38(a). Note that this process is executed as part of step SS3 in Figure 21.

As explained with reference to Figure 7(b), when power is turned on or an abnormal reset occurs when WDT 58 is activated, audio circuit SND is hardware reset via reset path 2 (step SD1). Furthermore, if the performance control CPU 63 detects an abnormality in audio circuit SND, audio circuit SND is hardware reset via reset path 4B or 4C (step SD1). Note that the performance control CPU 63 may activate the pattern check circuit CHK, causing audio circuit SND to be hardware reset along with other circuits (72, 73, 74, etc.) (step SD1).

In either of these cases, the performance control CPU 63 then confirms that the reset operation has been completed successfully (step SD2), and then first sets the starting address SNDst of the sound data area to the system control register RGij of the audio circuit SND (step SD3). Next, by setting a predetermined value in a predetermined system control register, the sound ROM header information HD is stored in the internal circuit. Note that the sound ROM header information HD is the six elements mentioned above (HDst, HDvl, PHst, PHvl, SCMDst, SCMDvl), as shown in Figure 38 (c).

Then, it is confirmed that the processing up to this point has operated normally, and if it has not completed normally, the audio circuits are individually reset via reset path 4B or 4C. However, since normal completion can usually be confirmed, the phrase header information HD and phrase data PH are then transferred to the external DRAM 54 using the data transfer circuit 72 (step SD6). The data transfer circuit 72 is appropriately specified with the destination start address BGN, the source start address HDst, the total amount of data to be transferred (HDvl + FDvl), etc.

Next, the phrase header information HD and phrase data PH are stored in the external DRAM 54, not in the CGROM 55, by setting a predetermined system control register RGij (step SD7), and then the start address BGN (sound RAM start address) of the group of data transferred to the external DRAM 54 is set in the predetermined system control register (step SD8). After that, other initial setting processes are completed (step SD9), and audio control operation becomes possible.

As explained earlier, the sound ROM header information, i.e., six pieces of information (HDst, HDvl, PHst, PHvl, SCMDst, SCMDvl), are stored in the internal circuitry of the audio circuit SND (step SD4). The performance control CPU 63 can then specify necessary information such as phrase data using relative values relative to the sound RAM start address BGN. Upon receiving this instruction, the audio circuit SND converts the relative address value into an absolute address value and executes the necessary audio processing. Since audio data such as phrase data is accessed for read access from the external DRAM 54 rather than the CGROM 55, even complex and sophisticated audio performances can be smoothly realized.

The above provides a detailed explanation of various embodiments, but the present invention is not limited to pinball gaming machines or slot machines, and the specific descriptions do not limit the present invention in any way. In particular, the circuit configuration and operation timing of the power supply control circuit (Figure 6) for the backlight unit BL and LCD display unit MONI, as well as the corresponding control processing in Figure 21, are merely examples and do not limit the present invention in any way and can be modified as appropriate.

For example, in the embodiment, control signals PS1 and PS2 are used, but if a driver DVL having a BL_EN terminal and a PWM terminal is used as the backlight unit BL, control signal PS1 is not particularly required. Also, since control signals STBY and PWM are used, control signal PS2 can also be omitted. If control signals PS1 and PS2 are omitted, power supply voltages of 12V and 5V will be supplied to the backlight unit BL and the liquid crystal display unit MONI from the time the power is turned on.

However, to accommodate a liquid crystal display unit MONI that requires significant image signal transmission quickly (e.g., within 20 ms) after power-on, it is preferable to use control signal PS2 to delay the timing at which the supply of 5V power is initiated. Figure 47 is a time chart illustrating such an embodiment, showing an embodiment in which control signal PS1 is omitted and the supply of 5V power to the liquid crystal display unit MONI is initiated in synchronization with timing T4, when the LVDS circuit 80 begins outputting the output from display circuit 74. Even in this case, if the backlight unit BL is turned on with a delay of an additional 300 ms from timing T4, for example, using a timer interrupt, the risk of an unnatural image being displayed can be eliminated, even without clearing frame buffers FBa and FBb to zero.

In addition, in the embodiments described so far, a considerable waiting time (>1000 + 300 mS) is set before the backlight turns on, but it would also be preferable to eliminate the 1000 mS waiting time and advance as far as possible the timing at which the LVDS circuit 80 starts outputting the output from the display circuit 74. For example, as shown in FIG. 48, it would also be preferable to execute step SS4 (SS4a + SS4b), which starts operation of the display circuit 74 and the LVDS circuit 80 (LVDS1/LVDS2), following the operation of step SP45, which sets up the Dual Link of the LVDS circuit and performs other settings. As explained above, the order in which steps SS4a and SS4b are executed is arbitrary.

In this case, the process of step SS4 is executed without executing the process of step SS3, resulting in the transmission of a meaningless image signal. However, as long as the backlight unit BL is off, no particular problems arise. In other words, when the backlight unit BL is off, as long as the processes of steps SP41 to SP44 are executed first, the display operation-related processes executed in steps SP4 to SP10 can be rearranged in any order.

In particular, the dual link setting and other setting processes (SP41) for the LVDS circuit 80 (LVDS1/LVDS2) can be performed together at step SP54 in FIG. 21, rather than at step SP4 in FIG. 16. The combined setting process includes setting the data to be output from the LVDS1 circuit/LVDS2 circuit of the dual link LVDS circuit 80 to be the output (ODD/EVEN) of the display circuit 74. Furthermore, when step SP54 is executed, a setting may be made in a specified display register RGij (DSPACTRL) or a specified system control register RGij (SYSDSPLVDS1MD, SYSDSPLVDS2MD) to indicate that the display circuit 74 and LVDS circuit 80 should start operating.

Also, at the register setting timing of step SP54, it is preferable to set a specific system control register RGij (SYSDSPLVDSLNK, SYSDSPLVDS1CFG1, SYSDSPLVDS2CFG1) to output data from the display circuit 74 via LVDS (see SP4), and then configure the display circuit 74 and LVDS circuit 80 to start operation at the timing of step SS4. Note that steps SP42 to SP44 and step SP46 may be executed immediately before timing T4 in Figure 47, and then the output operation of the LVDS circuit 80 (SS4) may be started.

However, as mentioned above, the processing of steps SP46 to SP47 related to the external DRAM (DDR) 54 must always precede the processing of step SP8.

Furthermore, with regard to the power-on reset operation, the power-on reset operation shown in Figure 16 is initiated based on the information in the vector table VECT allocated from address 0x00000000 onwards in the control memory 53, but it is also preferable to set the HBTSL terminal to high level and place the vector table VECT in the leading area of the CGROM 55. Figures 39(a) and 39(b) show the address map for such a case, with the address space CS0 of the performance control CPU 63 allocated in part (leading area) of the CGROM 55.

The main body of CGROM 55 is not accessed (cannot be accessed) by the performance control CPU 63, and is accessed exclusively by the VDP circuit 52, so it is not located in the address space CSi. As explained above, the main body of CGROM 55 can also be configured with multiple memory devices. In such cases, by dividing it into device sections SPA0 to SPA1 by processing step SP20 in Figure 18(a), optimal READ access suited to the characteristics of the memory devices becomes possible.

In any case, when the HBTSL terminal is set to the H level, the memory type and bus width (64/32/16 bits) of the CGROM 55 must be specified in advance based on the fixed input values to the 2-bit HBTBWD terminal and the 4-bit HBTRMSL terminal.

In this embodiment, following the vector table VECT, bus parameters for optimizing read access from CGROM 55 must be stored in the leading area of CGROM 55. Although not essential, it is also preferable to store obfuscation parameters for deciphering the performance control program if it has been obfuscated to make illegal analysis of the program more difficult.

When this configuration is used, after a power reset, the following operations 1 to 4 are automatically executed during the reset assertion period without going through program processing. First, the bus width of address space CS0 is determined based on the value input to the HBTRMSL terminal, and the memory type is automatically determined based on the value input to the BTBWD terminal and set in the specified VDP register RGij (operation 1). In this case, memory types are broadly divided into memory elements that use a parallel I/F (interface) format and memory elements that use a sequential I/F format.

Next, the obfuscation parameters stored in CGROM 55 are loaded, and the information required to remove the obfuscation is automatically set in the internal circuit (operation 2). Furthermore, the bus parameters stored in CGROM 55 are automatically acquired in the VDP register RGij (operation 3). Note that operation 3 corresponds to the program processing of step SP63 in Figure 19, and is automatically executed by the internal circuit.

Finally, to put into effect the bus parameters set in operations 1 to 3, the internal circuitry automatically executes the operation corresponding to the program processing in step SP64 in Figure 19 (operation 4). Then, once the bus parameter settings have been put into effect, the program counter PC and stack pointer SP are automatically set based on the information in the vector table, and execution of the boot program (initial setting program) begins.

The configuration shown in Figure 39(a) eliminates the need for the program processing in step SP1 in Figure 16(a) and automatically executes operations 1 to 4, significantly reducing the program processing burden. Also in this case, programs and data from vector handler Vopt onwards are transferred to the appropriate RAM area based on the operation of the initial setting program Pinit.

The programs and data following the vector handler Vopt do not necessarily need to be stored in the first area of the CGROM 55; they may be stored in the control memory 53, for example (Figure 39 (b)). Furthermore, the programs and data following the vector handler Vopt do not necessarily need to be transferred to the RAM area; if they are not transferred, the memory section initialization process in the initialization setting program (SP8 in Figure 16) is not required.

Furthermore, it is not necessary to match the V blank timing with the timing at which significant image data transmission ends. In other words, there is no need to end image data transmission at the timing of the bottom left corner (circle) of the display area shown in Figure 15(f). In short, it is sufficient to meet the specifications for the waiting time WTh/WRv and the horizontal/vertical synchronization signals HS/Vs required by the display device.

Figure 41(a) is a diagram illustrating such an embodiment, showing, for example, the operation of the display circuit 74A. In this embodiment, too, the frequency F _dot of the dot clock DCK is specified as 108 MHz in accordance with the specifications of the main display device DS1. Furthermore, in order to make the frame rate FR equal to 1/60 seconds, it is necessary to set THc x TVl / F _dot = 1/60. Here, as in the case of Figure 15(f), the number of horizontal synchronization cycles THc is set to 1662 clocks, and the number of vertical synchronization lines TVl is set to 1083 lines.

In addition, in the illustrated embodiment, the horizontal synchronization signal HS and vertical synchronization signal VS are output in accordance with the display device specifications so as to be compatible with general display devices. In the illustrated example, the pulse width of the horizontal synchronization signal HS is 100 clocks, the horizontal front porch FPh is designed to be 110 (= 10 + 100) clocks, and the horizontal back porch BPh is designed to be 172 clocks. In addition, the pulse width of the vertical synchronization signal VS is 10 lines, the vertical front porch FPv is designed to be 20 (= 10 + 10) lines, and the vertical back porch BPv is designed to be 291 lines.

However, in the embodiment shown in Figures 41(a) and (b), the vertical wait time WTv is set to 49 lines and the horizontal wait time WTh is set to 372 clocks in order to complete the output operation before the V blank start timing indicated by the circle. Therefore, according to this embodiment, the V blank start timing arrives 10 lines (154 μS) after the image update process for one frame is completed, ensuring image update process under any operating conditions (see Figure 41(b)).

This type of operation is particularly suitable for display circuits that operate in synchronization with other display circuits, such as display circuits 74B and 74C that operate in conjunction with display circuit 74A. Figures 41(c) to 41(e) are diagrams that explain this point, showing a case where the V blank period T2 in display circuit 74B is longer than the V blank period T1 in display circuit 74A (T1<T2).

In such a case, if the V blank period T1 of display circuit 74A is operated in conjunction with display circuit 74A, the V blank will begin before the output of image data in display circuit 74B is completed, which could result in image loss or unnatural display behavior (Figure 41(d)). On the other hand, if display circuit 74B is operated independently, it will not be possible to match the operating timing of the drawing circuit, which is synchronized with the operation of display circuit 74A.

Therefore, if the V blank period T2 of display circuit 74B, which accompanies the operation of display circuit 74A, is longer than the V blank period T1 of display circuit 74A, then, as in the case of Figures 41(a) and (b), the wait time (vertical blank period) should be set short so that there is sufficient time after image data is output in display device B. In this case, unless the wait time is set extremely short, display operation will be achieved without any problems on a typical LCD display device.

For example, even if the V blank period T3 of display circuit 74B accompanying the operation of display circuit 74A is shorter than the V blank period T1 of display circuit 74A, an extra waiting period will occur after the V blank period T3, but as long as the overall waiting time is not extremely long, the display operation will be realized without any problems.

Although the embodiments of the present invention have been described in detail above, the specific descriptions do not limit the present invention in any way. For example, although the embodiments have been described primarily in terms of dual link transmission lines (a pair of LVDS transmission lines), it is also preferable to employ a single link transmission line (a single LVDS transmission line) to simplify the equipment configuration.

In the case of a single-link transmission path, if the dot clock DCK frequency is 108 MHz, the LVDS clock CLK frequency will also be 108 MHz. In this case, too, it is preferable that the dot clock DCK and LVDS clock CLK share a common supply source, oscillator OSC2, and be generated using the same generation process.

In addition, unlike the previous embodiment, it is also advantageous to simplify the circuit configuration by sharing the source of the system clock for the VDP circuit 52 and the CPU operating clock for the CPU circuit 51 as a single oscillator OSC2. Furthermore, if the multiplication ratio of the PLL circuit is commonly set based on the setting value of a common setting terminal (a 3-bit PLLMD terminal), this eliminates the need for frequency setting processing, making it even more effective.

In this case, although it goes against the desire to speed up the CPU operating clock somewhat, it is preferable to use a system clock with the highest frequency allowed by the internal circuitry of the VDP circuit 52 and set the CPU operating clock at the same frequency.

For example, if the oscillation frequency of oscillator OSC2 is 40 MHz, setting the setting terminal (3-bit PLLMD terminal) to 5 allows the system clock and CPU operating clock to be set to a common frequency of 200 MHz (= 40 MHz x 5). This configuration not only eliminates the need for oscillator OSC1, simplifying the circuit configuration, but also obviating the need for somewhat complicated setting processes in the VDP register. Another advantage is that the operating cycles of VDP circuit 52 and CPU circuit 51 match.

Finally, let's clarify the video effects. As explained above, in this embodiment, most of the change effects are realized using video, not still images. Also, during change effects, multiple videos run in parallel, except in special cases such as when the screen goes black.

<Initial processing>
In order to execute video effects, in this embodiment, an AAC area and a page area are secured during the initial processing after power-on (SS1 in Figure 21), and one or more index spaces identified by index numbers are secured within the page area.

Specifically, one or more page areas each an integer N times the basic size of the unit space (4096 bits x 128 lines) are secured, and each is assigned a unique index number (SS2 in Figure 21). In this example, one pixel is represented by 32 bits (ARGB8888), so the unit space of the page area is 128 pixels x 128 lines.

As explained above, index space within a page area can be released or added as needed, so new index space can be generated within the page area when needed for variable effects.

In this embodiment, the AAC area secured during initial processing is used as a decoding area for still images and I-stream video. In this case, when the size of the texture (one video frame or still image) after expansion is specified using the load command TXLOAD, which specifies memory read of the image material (texture), the starting address and horizontal size of the decoding area are automatically secured in the AAC area.

<IP Stream Video Playback During Steady Operation>
After the above initial processing, one or more video effects are executed at appropriate timing. Here, the display list DL that instructs the playback of IP stream video requires the following commands CM1 to CM5 as instruction commands to the drawing circuit.

Figure 43 (a) illustrates the main parts of the display list DL, and is a reprint of the instruction command sequence L16 in Figure 23. Below, an example will be described in which a page area is used as the decode area, but an arbitrary area can also be used; in this case, simply read "page area" as "arbitrary area." However, the index space for a page area is an arbitrary horizontal size x vertical size of 2048 lines, which results in wasted space in the vertical direction.

(1) Texture command SETINDEX (CM1)
First, the texture command SETINDEX (CM1) specifies whether to use an arbitrary area or a page area as the decode area, but in the case of IP stream video, in this embodiment, the index space i of the page area is used. More specifically, the texture command SETINDEX with the necessary operation parameters added is written in the display list DL to select "page area" and "texture" and to specify the index number i that specifies the index space to be used.

When using a custom area, use the texture command SETINDEX to select "custom area" and "texture" and specify the index number i that identifies the index space of the custom area.

(2) Load command TXLOAD (CM2)
Next, a load command TXLOAD (CM2) that specifies a memory read of the material is used to specify that the required texture (unit frame that makes up the video) be loaded from CGROM. Specifically, the load command TXLOAD with the required operational parameters added is written in the display list DL. The VDP circuit 52 then loads the specified texture from a specified area in CGROM, decodes it, and expands the decoded data into index space i of the page area.

The operational parameters added to the load command TXLOAD include (1) whether the texture (the unit frames that make up the video) should be decoded as the first frame or as a subsequent frame, (2) the horizontal size of the texture after it has been expanded, (3) the vertical size of the texture after it has been expanded, and (4) the source address of the texture (the starting address of the CGROM where the texture is stored).

(3) Basic information set command SETTXATR (CM3)
Next, a basic information set command SETTXATR (CM3) with necessary operation parameters added is written in the display list DL to set basic information about this texture, such as the texture color mode being ARGB8888 mode (1 pixel is 32 bits long).

In addition, the necessary information is set for blending between pixels. Blending refers to the calculation of mixing the RGB values that define the color of each pixel, and the alpha values that define transparency, etc., with pixels that have already been drawn to a frame buffer, etc. In this example, multiple videos are always running in parallel during the variable effects, so alpha blending calculations for transparency, etc. are required.

(4) Inter-pixel blending calculation command (CM4)
For this reason, the display list DL describes a command (CM4) for the inter-pixel blending calculation system to which necessary operation parameters are added, and the necessary operation parameters specify the α blending calculation formula and other elements.

(5) Sprite Command SPRITE (CM5)
Next, in order to paste the texture developed in index space i into the appropriate position in the virtual rendering space (see FIG. 12(c)), a sprite command SPRITE (CM5) with the necessary operation parameters added is written in the display list DL. This sprite command SPRITE specifies the upper left vertex (X0, Y0) and lower right vertex (X1, Y1) of the virtual rendering space, which identify the destination of the texture to be pasted.

Furthermore, for the texture to be pasted into the rectangular area specified by the upper left vertex (X0, Y0) and lower right vertex (X1, Y1), the UV values in the texture UV coordinate space, i.e. (U0, V0) and (U1, V1), are specified. Note that the texture to be pasted has already been specified with the texture command SETINDEX, so there is no need to specify the texture itself again.

Also, instead of the sprite command SPRITE, you can use the triangular polygon command TRIANGLE to draw a tilted texture. However, the tilt/rotation preview effects for the triangular polygon command TRIANGLE will be discussed later.

<Playback of I-stream video during steady operation>
In the case of I-stream video, just as in the case of still image playback, it is sufficient to load the texture to be decoded (unit frames that make up the I-stream video) into the AAC area. In other words, the texture command SETINDEX (CM1) is not required, and the display list DL has the following configuration. Note that commands CM3 and CM4 are also normally required, but their description is omitted to avoid redundancy.

(1) Load command TXLOAD (CM2)
A load command TXLOAD with operation parameters added is written in the display list DL to specify that a texture (a unit frame that constitutes an I-stream video) is to be loaded from a specified area in the CGROM to the AAC area. The VDP circuit 52 then automatically decodes the loaded texture and expands the decoded data into the automatically allocated space in the AAC area. (2) Sprite command SPRITE (CM5)

Next, in order to paste the texture developed in the automatically allocated space of the AAC area into the appropriate location in the virtual drawing space, a sprite command SPRITE with the necessary operational parameters added is written in the display list DL. As explained above, the sprite command SPRITE specifies the upper left vertex and lower right vertex of the virtual drawing space, which identify where the texture will be pasted.

Instead of the sprite command SPRITE, you can also use the triangular polygon command TRIANGLE to draw the texture in a tilted orientation.

If you want to scale a texture, simply write the complement command SETTXSMPLNG before the sprite command SPRITE. The complement command SETTXSMPLNG specifies the texture sampling method (point sampling/bilinear filtering), and the interpolation process to be used when scaling the texture will be specified.

Enlargement and reduction are performed automatically based on the upper left and lower right vertices of the virtual drawing space specified by the sprite command SPRITE. In other words, enlargement or reduction is performed automatically based on the size of the rectangular space defined by the upper left and lower right vertices. If point sampling is selected, enlargement is performed simply in a mosaic pattern, and reduction is performed by thinning out pixels. On the other hand, if bilinear filtering is selected, the information for unspecified pixels becomes a weighted average of the information for specified surrounding pixels.

<Slight fluctuation and enlargement/reduction of reserved images>
In the gaming machine of this embodiment, when more than four winning balls enter the pattern starting hole, the variable effect is put on hold, and a reserved image (a still image sprite or an I-stream or IP-stream video) indicating the number of reserved balls is displayed on the display device.

In this case, it is desirable from a presentation standpoint to subtly move the pending image up and down and left and right, rotate it, and enlarge/reduce it to indicate the result of the lottery, whether it is a jackpot or not. By adopting such a configuration, a variety of presentations are possible by simply preparing a single still image or video, and the amount of CG data can be reduced.

Rotation of a reserved image (a still sprite or streaming video) is performed using the triangular polygon command TRIANGLE. On the other hand, slight changes and zooming in/out effects are achieved by specifying the paste position and paste area of the reserved image (a still sprite or streaming video) using the sprite command SPRITE. When zooming in/out, the complementary command SETTXSMPLNG must be written in the display list before the sprite command SPRITE.

<Dialogue preview>
The dialogue preview effect refers to a preview effect in which the dialogue sound effect starts a predetermined time after the dialogue text starts to be displayed. By deliberately delaying the sound effect, the impact of the preceding text display can be increased.

In this dialogue video presentation, a group of dialogue characters is displayed one character at a time or one unit at a time in order. Note that a character image may be displayed prior to the start of displaying a group of dialogue characters. It is also preferable to allow a predetermined silent period after the dialogue characters start to be displayed before starting to output the dialogue sounds.

Alternatively, a character image may be displayed after the dialogue text is displayed. In this case, after the dialogue text starts to be displayed, a predetermined time delay is given before the dialogue sound is produced, and then the character image is displayed. In this case, it is preferable that the audio production corresponding to the dialogue text that is performed first corresponds to the character image that is displayed afterwards. Alternatively, after the audio production is performed, a predetermined silent period may be set before the character image is displayed.

When dialogue previews are performed with IP stream video, the display list DL issued prior to the audio preview contains at least the following commands:

First, the texture command SETINDEX (CM1) sets the load destination for the texture (e.g., the constituent frames of an IP stream video) to, for example, a page area.

Next, the TXLOAD command (CM2) loads the texture (the unit frames that make up the video) from CGROM into the page area, and sets the necessary information for the alpha blending calculation (CM3, CM4). Finally, the texture loaded into the page area is pasted into a specified rectangular area in the virtual drawing space using the sprite command SPRITE (CM5). It is preferable to change the video playback position by appropriately moving the rectangular area where the texture is pasted.

When a dialogue preview is performed using IP stream video, the load command TXLOAD, the supplementary command SETTXSMPLNG, and the sprite command SPRITE are used. If there is no scaling processing, the supplementary command SETTXSMPLNG is omitted.

<Blackout Notice>
The blackout notice refers to an effect in which, during a series of variable effects, the entire display screen suddenly changes from its previous display mode, and a blackout image appears, making the entire screen or almost the entire screen pitch black. This notice effect includes a first mode in which, after the preceding video effect has ended, a display list DL that displays a blackout image for a predetermined time is issued, and then a subsequent development video effect starts as a notice of the development of the preceding video, and a second mode in which a blackout image appears as part of the video at the start of the development video effect, without using a display list DL that displays a blackout image.

It may also be configured to execute a predetermined effect suggesting the likelihood of winning while the blackout image is displayed. Furthermore, the blackout image is not limited to one in which almost the entire display screen goes completely black, but may also be a visibility-reducing image that reduces the visibility of the previous display screen. Specifically, it is a transparent black image.

Figure 43 (b) illustrates the configuration of a display list DL that realizes the blackout image of the first mode. First, the endpoint address in the index space is identified for the frame buffer FBa allocated in an arbitrary area (L11). The drawing area of the display device DS1 is defined in the virtual drawing space (L12). Specifically, the coordinates of the upper left base point and lower right base point of the virtual drawing space are set in specified registers.

Next, the index number of the frame buffer FBa to be used in this cycle is toggled to identify it (L13). The SETFCOLOR command is then used to set the color black (L14), and a rectangle drawing command (RECTANGLE) is used to specify that the entire drawing area of display device DS1 should be filled with black (L15).

This is exactly the same as the instruction commands L11 to L15 shown in Figure 23, and normally the commands in Figure 43(a) are listed afterwards, but in the case of a blackout image, the required number of NOP commands are then written, followed by an EODL command, adjusting the total data size including the EODL command to an integer multiple of 4 x 64 bytes.

It is also preferable to superimpose one or more video effects onto the blackout image, in which case the instruction commands CM1 to CM5 shown in Figure 43(a) are additionally written.

In the case of the blackout announcement of the second mode, the video frames that realize each of the preceding video effects and the subsequent video effects are specified by the instruction commands CM1 to CM5 shown in Figure 43 (a).

<Zoom Up/Down Preview>
The zoom preview refers to a presentation in which an appropriate character moves appropriately on the display screen while being zoomed up or down (see FIG. 44(a)). While such a zoom preview can be realized with a still image of a character, this embodiment uses a character with a changing facial expression and movement throughout its body, making it a moving image presentation.

In Figure 44(a), for convenience, the characters appearing in the zoom preview are represented by a still-image-like "A," but in reality, the "A" will be replaced by a human or animal character with moving facial expressions and limbs.

Continuing with the above explanation, for example, a 3-second video at 30 fps (frames per second) is made up of 30 x 3 = 90 video frames FR1 to FR2n-1, in which the zoom preview character is zoomed in and then zoomed down.

The display list DL that draws each of the 90 video frames FRi is configured as shown in Figure 23 or Figure 43(a), so the loaded texture (video frame depicting the zoom preview character) is pasted at the appropriate location in the virtual drawing space using the sprite command SPRITE. Therefore, the zoom preview character can be moved on the display screen simply by moving the paste position designation as appropriate. Note that because the zoom up/down operation is realized as a video, there is no need for enlargement/reduction control in the display list.

On the other hand, if you want to create a zoom preview character using a single still image, you can use the sprite command SPRITE to appropriately enlarge or reduce the rectangular space defined by the upper left and lower right vertices of the virtual drawing space.

<Tilt/Rotation Notice>
The tilt/rotation notice means, for example, tilting or rotating the original images FR1 to FR2n-1 in an upright state as shown in Fig. 44(a). In Fig. 44(b), for example, N zoomed-in video frames FR1 to FRn are rotated clockwise in sequence.

To achieve this type of tilt/rotation preview, a rectangular image (the texture that makes up the still image or video frame FRi) must be divided into triangular polygons, and each triangular polygon must be attached in an upright or tilted position in the appropriate location in the virtual rendering space using the triangle polygon command TRIANGLE (CM5).

In the following explanation, for convenience, we will assume that rectangular images (still images or video frames FRi) are not enlarged or reduced, but by setting the coordinate position appropriately, they can also be enlarged or reduced. In this case, even more diverse effects can be achieved without increasing the amount of CG data.

Now, Figure 45(c) shows a rectangular image (still image or video frame FRi) consisting of horizontal W x vertical H pixels with four vertices, divided into a first polygon and a second polygon. In this example, the execution of a single triangular polygon command, TRIANGLE, renders the four vertices together in an upright or tilted state.

However, to achieve this, the operational parameters that should be added to the triangular polygon command TRIANGLE include the number of vertices of the polygon to be drawn with one triangular polygon command (information 1), a setting for whether to draw only the shape or include texture (information 2), the polygon drawing method for the triangular polygon (information 3), the XY coordinates of each vertex in the virtual drawing space (information 4), and the UV values in the UV coordinate space of the texture corresponding to information 4 (information 5).

In this example, one triangular polygon command draws four vertices of a rectangle and attaches a texture (video frame) to them, so information 1 specifying the number of vertices = 4, information 2 specifying that a texture is included, information 4 which is the XY coordinate values for the four vertices, and information 5 which is the UV values are specified.

The drawing methods available are (1) triangle fan drawing, which sets a common vertex for all triangular polygons; (2) triangle strip drawing, which draws the final drawing edge and the triangle enclosed by the specified vertices that follow; and (3) triangle list drawing, which draws triangular polygons independently.

As shown in Figure 45(c), in the triangle strip drawing method, vertices are drawn in the order vertex 0 → vertex 1 → vertex 3, followed by vertex 3 → vertex 1 → vertex 2. On the other hand, in the triangle fan drawing method, vertex 1 of the common vertex is selected and drawn in the order vertex 1 → vertex 3 → vertex 0, followed by vertex 1 → vertex 2 → vertex 3.

However, since the rectangular image in question here is a two-dimensional 2D image, not a stereoscopic 3D image, there is no issue with culling, which removes unnecessary parts, so it makes no difference which method is selected, but in this example, triangle strip rendering is selected. Note that although the term rectangular image is used in this specification, it is a rectangle that includes transparent parts, and it goes without saying that the image outline is not necessarily rectangular.

Based on the above, the operation of the performance control CPU 63, which calculates the operation parameters of the triangular polygon command TRIANGLE, will be explained with reference to Figure 45 (a). First, the four vertices are identified when the center of a rectangular image consisting of W horizontal x H vertical pixels is placed at the origin of the virtual drawing space (ST61).

As shown in Figure 12(c), in the virtual drawing space, the X coordinate is positive in the right direction from the origin, and the Y coordinate is positive in the downward direction from the origin, so the coordinates (x, y) of the four vertices are vertex 0 (-W/2, -H/2), vertex 1 (W/2, -H/2), vertex 2 (W/2, H/2), and vertex 3 (-W/2, H/2).

Next, the four vertices after rotating the rectangular image at the origin position clockwise by the rotation angle θ are calculated using a matrix operation using the rotation matrix in Figure 45(b) (ST62). Note that the clockwise direction in the rotation matrix corresponds to the counterclockwise direction in the virtual rendering space, so the rotation angle is actually -θ. This rotation angle is always the rotation angle from the upright texture, regardless of the progression of the animation. In other words, even when rotating the texture at a constant speed by a rotation angle θ1, the rotation angle must not be a constant value θ1, but must be increased sequentially, for example, θ1 → 2*θ1 → 3*θ1 → 4*θ1 → 5*θ1, etc.

Next, the four vertices (X, Y) calculated in step ST62 are moved to the desired destination (ST63). Specifically, if the destination coordinate value of the center point of the rectangular image is (X0, Y0), the calculations X = X + X0 and Y = Y + Y0 are performed for each of the four vertices to determine the coordinates of the four vertices after rotation.

Finally, the operation parameter (4) of the triangular polygon command TRIANGLE is added, and correspondingly, the operation parameter (5) is added, which is the coordinate values of the four vertices in the UV coordinate system for the upright rectangular image (texture). The same applies to information (1) to (4).

Note that the movement parameters (4), which are the X and Y coordinates of each vertex in the virtual rendering space, change appropriately as the video progresses, and the displayed content of the rectangular image (texture) also changes. However, in this embodiment, the vertical and horizontal dimensions of the texture in the upright state do not change, so the movement parameters (4) always remain the same.

In this embodiment, the above calculations are performed each time a tilt/rotation preview effect is displayed. This is somewhat cumbersome for the effect control CPU 63, so it is also possible to specify only the texture rotation angle and placement position to the VDP circuit 52.

However, adopting such a configuration requires the VDP circuit 52 to perform rotation matrix calculations, increasing the calculation load. Therefore, in this embodiment, to reduce the calculation burden on the VDP circuit 52, which also requires other complex arithmetic operations, the performance control CPU 63 calculates the coordinate position.

However, for the performance control CPU 63 to perform matrix calculations, not only does it require that trigonometric function calculation routines (libraries for trigonometric functions) be stored in memory 53, but it also requires a certain amount of processing time, so it is preferable to devise a way to speed up the calculation process.

Figure 45(d) shows an example in which the calculation load is reduced, and the necessary calculations are performed based on the distance (radius r) from the center point of the rectangular image to each vertex, and the reference angle α of the four vertices of the texture when placed at the origin (see Figure 45(e)).

First, determine the radius r of the four vertices of the texture and the reference angle α when the center of a rectangular image consisting of W horizontal x H vertical pixels is placed at the origin of the virtual rendering space (ST71).

Next, the coordinate values of the four vertices when rotated counterclockwise by the rotation angle θ are calculated based on the transformation formula in Figure 45(f) (ST72). The calculation process for the transformation formula in Figure 45(f) is shown in Figure 46.

Next, if the destination coordinate values of the four vertices (X, Y) calculated in step ST72 are (X0, Y0), the calculations X = X + X0 and Y = Y + Y0 are performed for each of the four vertices to determine the coordinates of the four vertices after rotation (ST73).

Finally, the operation parameters (1) to (5) are added to complete the triangular polygon command TRIANGLE, which is then added to the display list DL (ST74).

While Figures 45 and 46 show an example of a vertically long rectangular image (texture) in an upright position, if the texture is formed into a square, the root symbol SQR can be used, resulting in H = W = r * SQR(2), simplifying the conversion formula in Figure 45(f). Furthermore, because of the relationship Cos(θ) = Sin(90 + θ), the conversion formula in Figure 45(f) can be expressed using only the radius r, rotation angle θ, and sine function value.

It is therefore preferable to prepare a SIN table (see Figure 46(c)) that stores each Sin function value for rotation angles of -180 degrees to 0 degrees to 180 degrees. In this case, there is no need to store trigonometric function calculation routines in memory 53, and the processing speed of trigonometric function calculations can be increased.

Although the present invention is not limited to the specific details, it is preferable that the frequency (F _dot ) of the display clock that determines the operation of the display circuit be defined prior to the data generation process (SS4a) and the data output process (SS4b). It is also preferable that a setting process for the LVDS circuit be executed prior to the data output process (SS4b). It is also preferable that the LVDS signal be transmitted to the display circuit via a single LVDS transmission line or a pair of LVDS transmission lines.

In either configuration, the display device is configured to include a display drive circuit (MONI) that drives a group of display elements that make up the display screen based on the LVDS signal, and a lighting circuit (BL) that illuminates the display screen, and it is preferable that the data generation process (SS4a) and the data output process (SS4b) are executed before the lighting circuit (BL) begins its lighting operation. Here, it is preferable that the image control means controls the operation of the lighting circuit (BL) using multiple control signals.

Preferably, the image control means, prior to the start of the illumination operation, defines a horizontal period (TH) required for the display drive circuit (MONI) to draw one line of display elements based on the number of horizontal cycles (THc) of a display clock that defines the operation of the display circuit. The horizontal period (TH) is preferably divided into a timing when image data is transmitted and a timing when image data is not transmitted, and prior to the start of the illumination operation, the image control means defines a predetermined number of lines (TVl) for the operation of the display drive circuit (MONI), and the number of lines (TVl) is preferably defined as FR = THc × TVl / F dot based on the horizontal period (TH), an update period (FR) required for the display drive circuit (MONI) to update one frame of image, and a frequency (F _{dot )} of a display clock that defines the operation of the display circuit.

Next, Figure 49 illustrates yet another embodiment for achieving motor effects. In this example, motor effects are achieved without using the SMC circuit 78 or the input/output circuit 64s. This motor effect is achieved by four motor drivers DV1-DV4 that drive four stepping motors MO1-MO4, and a sensor board 86 that serially transmits sensor signals SEN from the origin sensor and other devices to the CPU circuit 51.

The operation of motor drivers DV1 to DV4 is controlled by the performance control CPU 63 of the CPU circuit 51, which executes the performance control program, but motor drivers DV3 to DV4 are driven and controlled by a motor controller 85, which operates based on instructions from the performance control CPU 63. Note that in this specification, drive control is a concept that includes rotation drive, which advances the rotational position, and stop drive, which maintains the stop position.

As explained above, the VDP circuit 52 of the composite chip 50 has a built-in SMC circuit 78 (Serial Motor Controller), and it would be ideal to use this SMC circuit 78 to drive the motor drivers DV1 to DV4. However, in this embodiment, a higher performance motor controller 85 is used, which not only significantly reduces the control burden on the performance control CPU 63, but also achieves high-speed, advanced motor performance.

In other words, in this embodiment, the stepping motors MO3 to MO4 are driven to rotate appropriately to perform preview effects such as sudden starts or stops of props, or preview effects that move props at speeds faster than natural falling. Even when performing these innovative motor effects, drive control is achieved that prevents problems such as step-out. Here, step-out refers to a phenomenon in which the motor does not rotate normally in response to the step pulses (input pulse signals received by the stepping motor) output by the motor driver DV, and can occur during overload or sudden speed changes.

The circuit configuration of Figure 49, which achieves the above effects, will be described in detail below. First, stepping motors MO1 to MO4 are all bipolar stepping motors, with bidirectional drive currents flowing through the A-phase and B-phase motor windings (bipolar drive). While cited references 5 and 6 use unipolar motors primarily for the purpose of simplifying the drive circuit, this embodiment employs a bipolar motor, which can obtain higher output torque than a unipolar motor for the same power consumption.

In accordance with the above configuration, motor drivers DV1 to DV4 that drive each motor all incorporate drive circuits capable of bipolar drive. They also have internal circuits that can execute constant current control between the maximum current MAX and the minimum current MAX-δ in 100% drive mode. Motor drivers DV1 to DV2 are controlled by an SIO port 61 (serial port) and a PIO port 62 (parallel port) built into the CPU circuit 51, while motor drivers DV3 to DV4 are controlled by a motor controller 85. The motor controller 85 is controlled by the SIO port 61, PIO port 62, and a compare match timer CMT built into the CPU circuit 51.

Figure 50(a) illustrates the internal configuration of the SIO port 61 built into the CPU circuit 51. The SIO port 61 is configured to be capable of SPI (Serial Peripheral Interface)-based, i.e., three-wire serial transmission and reception synchronized with the shift clock SCK. The SIO port (serial port) 61 is made up of a total of six identical circuits (CH0 to CH5), with the serial port SIO_0 of CH0 connected to the motor drivers DV1 and DV2 and the sensor board 86 via a first SPI communication path. Meanwhile, the serial port SIO_1 of CH1 connected to the motor controller 85 via a second SPI communication path.

First, regarding the internal configuration of the SIO port 61, as shown in Figure 50(a), for each of CH0 to CH5, the SIO port 61 is comprised of an 8-bit transmit shift register SCTSR that transmits serial data TXD, an 8-bit receive shift register SCRSR that receives serial data RXD, a 16-stage FIFO data register SCFTDR that can store up to 16 bytes of transmit data, a 16-stage FIFO data register SCFRDR that can store up to 16 bytes of receive data, a baud rate generator BGN that can generate a shift clock SCK of any frequency, a transmit/receive controller CTL that operates the internal circuitry of the SIO port 61 based on various control parameters set by the performance control CPU 63, and an interface circuit BUSIF that relays various data when the performance control CPU 63 accesses the transmit/receive controller CTL.

In this embodiment, the performance control CPU 63 is initially configured to automatically transfer the N*8-bit transmission data stored in the FIFO data register SCFTDR to the transmission shift register SCTSR each time an 8-bit serial transmission process is completed, and to continue the serial transmission process until the FIFO data register SCFTDR is empty. Also, the received data serially received by the reception shift register SCRSR is initially configured to be accumulated in the FIFO data register SCFRDR each time it reaches 8 bits.

The transmission/reception controller CTL is configured to be able to output various interrupt signals to the performance control CPU 63, such as an overrun error BRI, a reception error ERI indicating a framing error or parity error, a reception FIFO data full RXI, and a transmission FIFO data empty TX1.

In the following explanation, the serial port 61 for CH0 will be referred to as SIO_0, and the serial port for CH1 will be referred to as SIO_1. Figure 50(b) illustrates the connection relationship between the serial port SIO_0 and the motor drivers DV1-DV2 and the sensor board 86.

The serial port SIO_0 operates based on the operating parameters set in the transmission/reception controller CTL by the performance control CPU 63. Specifically, the transmission shift register SCTSR serially transmits the drive data SDATA, which is up to 2 x 8 bits long and stored in the FIFO data register SCFTDR by the performance control CPU 63, in 8-bit increments synchronized with the shift clock SCK. In this embodiment, the baud rate of the serial port SIO_0 is set to, for example, 250 kbps, and the transmission time for 16-bit drive data SDATA is 16/(250 * 10 ³ ) = 0.064 ms.

In this embodiment, motors MO1 and MO2 are two-phase excited, and each 8-bit drive data SDATA consists of 4-bit excitation data (PHASE instruction) that instructs each motor MO1 or MO2 to advance by one step, and a 4-bit setting value (current instruction value) that specifies the drive current to be passed through motor windings A and B.

Then, each motor driver DV1, DV2 outputs a drive signal corresponding to the excitation data (4 bits) contained in the drive data SDATA (8 bits) received from the serial port SIO_0 to each motor MO1, MO2 in synchronization with the stepping clock LATCH received from the PIO port 62, driving the motors with a drive current corresponding to the current command value (4 bits) specified in the drive data SDATA. The current command value (4 bits long) allows for 16 different current commands, including 0%, and the output torque increases in proportion to the drive current based on the current command value. In this sense, the current command value represents the torque setting.

In this embodiment, the drive data SDATA and the stepping clock LATCH are output every 1 ms, so motors MO1 and MO2 rotate one step at a maximum of every 1 ms. Furthermore, because drive data SDATA can be updated every 1 ms, motors MO1 and MO2 can operate at a maximum of 1000 steps per second.

On the other hand, if you want to rotate each motor MO1, MO2 slowly, you can output the same unupdated drive data SDATA multiple times in succession, or provide a waiting period during which drive data SDATA or shift clock SCK are not output. When outputting the same drive data multiple N times in succession, it is preferable to reduce the current command value during stop drive from the second to (N-1)th times compared to the current command value during the first time. This is because, while output torque increases in proportion to the drive current, power consumption also increases significantly in response to the drive current, and so unnecessary power consumption during stop drive is suppressed.

In this embodiment, 16 shift clocks SCK are output every 1 mS, and as shown in Figures 49 and 50(b), the 16 shift clocks SCK are supplied in common to motor driver DV1, motor driver DV2, and sensor board 86.

As shown in Figure 51(a), the sensor board 86 is equipped with a shift register 90 whose internal configuration is shown in Figure 51(b). After receiving the latch signal LOAD, the shift register 90 serially transmits a total of 8 bits of sensor signal SEN in synchronization with the shift clock SCK. Therefore, in this embodiment, the serial port SIO_0 acquires the 8-bit sensor signal SEN based on the first 8 shift clocks SCK out of a total of 16 shift clocks SCK output by the serial port SIO_0 every 1 ms. The sensor signal SEN includes an origin sensor signal indicating that the reference point on the rotation axis of each motor MO1, MO2 has passed a predetermined origin position, and a sensor signal CHK indicating that the reel has reached a predetermined position.

Next, Figure 50 (c) illustrates the connection relationship between serial port SIO_1 and motor controller 85. In this embodiment, motor controller 85 outputs a step clock (pulse signal) to driver DV3 and driver DV4, respectively, and motors MO3 and MO4 rotate stepwise in synchronization with the received step clock. Furthermore, the motor driver 85 is configured to acquire a sensor signal CHK indicating the rotational position of each motor MO3 and MO4 and when the reel has reached its target position.

The motor controller 85 receives various control data MOSI from the serial port SIO_1 in synchronization with the shift clock SCK received from the serial port SIO_1, while serially transmitting the sensor signal MISO to the serial port SIO_1. The motor controller 85 also receives an operating signal SS generated by the compare match timer CMT. This operating signal SS indicates that the motor controller 85 and serial port SIO_1 are currently performing serial transmission and reception operations.

As shown in the upper left of Figure 49, the compare match timer CMT starts counting the reference clock under the control of the performance control CPU 63, and is configured to output a compare match interrupt signal when the count value reaches a predetermined upper limit value MX. Upon receiving the interrupt signal, the performance control CPU 63 ends the counting operation of the compare match timer CMT.

The above operation is repeatedly executed every 1 ms under the control of the performance control CPU 63, and the operating signal SS, which indicates that the counting operation is in progress, is logically inverted and transmitted to the motor controller 85. Here, the pulse width of the operating signal SS is determined to an optimal value within 1 ms, corresponding to the time required for serial transmission and reception processing by CH1's serial port SIO_1. In this sense, the operating signal SS is also the operating signal of serial port SIO_1, and its pulse width is determined by the product of the pulse period of the reference clock and the upper limit value MX of the compare match operation.

Although not particularly limited, the baud rate of the shift clock SCK for the serial port SIO_1 is also set to 250 kbps. In this embodiment, the control data MOSI, which is serially transmitted intermittently, is limited to a maximum of 16*8 bits in accordance with the storage capacity of the FIFO data register SCFTDR, and the transmission time of the drive data MOSI is limited to a maximum of 16*8/(250* ¹⁰³ ) = 0.512 ms. Since 32 shift clocks SCK are required to acquire the origin sensor signal, the operating time for serial reception is 32/(250* ¹⁰³ ) = 0.128 ms. In this embodiment, taking into account the operating cycle of 1 ms, a single serial transmission is limited to a length of 16*8 bits; however, it is possible to set a longer length by increasing the baud rate.

The control data MOSI includes a series of instruction data INS1 that defines the series of operations of the stepping motors MO3 and MO4, and current instruction data INS2 that defines the maximum value MAX of the drive current to be passed through the drive windings. Binary signals SETx and SETy generated based on the current instruction data INS2 are supplied to the setting circuit LMT, which outputs an analog signal of a predetermined level. Based on this, motor drivers DV3 and DV4 perform constant current control operation within the range of minimum value MAX-δ and maximum value MAX in 100% drive mode. Note that a drive mode below 100% (standby operation mode) can also be adopted, but this will be discussed later.

Generally, when a stepping motor is rotated at high speed, the rise time when the drive current is switched is delayed, resulting in a decrease in output torque. However, in this embodiment, a motor drive voltage (35V) that is more than 10V higher than the motor's maximum rated voltage (24V) is applied, while constant current control is implemented to chop this motor drive current, thereby achieving stable high-speed rotation.

Figure 52(a) is a block diagram showing the internal configuration of motor drivers DV1 and DV2. As shown in the figure, motor drivers DV1 and DV2 have an SCK terminal that receives a shift clock SCK from the serial port SIO_0, an RCK terminal that receives a stepping clock LATCH from the PIO port 62, an SI terminal that receives control data SDATA from the serial port SIO_0, an SCLR terminal and a STANDBY terminal that receive a reset signal RESET from the PIO port 62, VREF_A terminal and VREF_B terminal that receive an analog signal that defines the maximum current MAX in 100% constant current control, an OSCM terminal that receives a signal that defines the frequency of the internal clock for constant current control, a VM terminal that receives a motor drive voltage of 35V, a VCC terminal that outputs a constant voltage of 5V generated by stepping down the DC voltage of 35V received from the VM terminal, RS_A terminal and RS_B terminal to which current detection resistors RS_A/RS_B (for example, 0.33 Ω) for constant current control are connected, and an OUT_A terminal that outputs a drive current to the A-phase winding of the stepping motor. It consists of a ± terminal, an OUT_B ± terminal that outputs drive current to the B-phase winding of the stepping motor, and a G- terminal that receives an L-level voltage to enable the internal circuitry to operate.

As shown in the figure, a 33 μF conductive polymer capacitor is connected to the VM terminal, which receives a DC voltage of 35 V. As explained earlier, in this specification, a conductive polymer capacitor refers to a hybrid capacitor in which an electrolyte made by combining a conductive polymer and an electrolyte is used instead of the electrolyte used in an aluminum electrolytic capacitor. This conductive polymer capacitor has a rated voltage of 50 V and is a cylindrical surface-mount product with a diameter of 6.3 mm and a height of 7.7 mm.

When powered at 5V, the capacitance is maintained at less than -10% of the nominal value (33μF). The nominal equivalent series resistance (ESR) is 40mΩ.

Unlike typical circuit configurations, the drivers DV1 and DV2 in Figure 52 do not connect ceramic capacitors in parallel with electrolytic capacitors, but instead place a single capacitor for each motor driver (DV1, DV2), thereby achieving the desired smoothing and decoupling functions and not consuming space for other circuit elements. In other words, no additional smoothing capacitors or decoupling capacitors are placed within a radius of at least 20 mm from the conductive polymer capacitor.

The top surface of the surface-mounted cylinder is marked with the number "33" indicating the capacitance and the symbol "H" indicating the rated voltage of 50V, and the direction of the negative polarity is identified with a black symbol, making it easy to visually check the components on the board.

As shown in the diagram, motor drivers DV1 and DV2 are comprised of a torque control unit (torque control, VREF comp, Bridge A NF level set) that controls the output torque based on the voltage at the RS_A and RS_B terminals, an 8-bit shift register, a constant voltage generator (VCC_REG), a central control unit (Main control Logic), an oscillator (Internal oscillator) for the internal clock, a bridge driver circuit (Motor output stage Bridge A/B), an overheat detection circuit (TSD), an overcurrent detection circuit (ISD), and a 35V power-on reset circuit (POR).

To drive a motor driver with the circuit configuration described above, the control data SDATA (8 bits) supplied to the SI terminal consists of excitation data (4-bit PHASE instruction) that indicates one step of forward movement, and a current instruction value (4 bits) that specifies the drive current to be passed through motor windings A and B.

Furthermore, after receiving the low-level reset signal RESET at power-on, the SCLR and STANDBY terminals remain high, allowing the internal circuitry to operate steadily. As shown in the diagram, the G- terminal is constantly low, allowing the above-mentioned reset operation to occur after power-on.

In addition, the VREF_A and VREF_B terminals are supplied with an instruction voltage obtained by dividing the constant voltage of 5V output from the VCC terminal. In this embodiment, in 100% drive mode, the maximum current MAX under constant current control is set to, for example, 545mA.

As explained earlier, the current instruction value contained in the control data SDATA is 4 bits long, and the maximum current value can be set to 16 levels, including 0%. Therefore, based on this setting value, the actual maximum current can be set to a current value other than 100% of the MAX value, such as 94%, 86%, ... or 5% of the MAX value. For this reason, in the explanation of constant current control below, the maximum current in the arbitrary % drive mode will be referred to specifically as the current upper limit value NF. For example, the current upper limit value NF in the N% drive mode has a relationship with the maximum current MAX of MAX * N/100.

As explained above, in this embodiment, during low-speed rotation when the same drive data is output N times in succession during a 1 ms operating cycle, the current command value for the first and Nth times is set to 100%, and the current command value for the second through N-1th times is suppressed to, for example, 25%, thereby suppressing power consumption. In this case, the current upper limit value NK is NF = 0.25 * MAX relative to the maximum current MAX, so power consumption is significantly suppressed (by approximately 6.2%).

As shown in Figure 52, a 2.7 kΩ resistor that supplies a constant voltage of 5 V and a 330 pF capacitor connected to the ground line are connected to the OSCM terminal, setting the frequency of the internal clock that manages constant current control to approximately 1578 kHz. The internal clock frequency determines the detection period for the drive current, and for constant current control of the motor drive current, it is preferable to set it to 1300 kHz to 1800 kHz in Control Method 1, which will be described later.

As explained above, the motor drive current is controlled to increase or decrease between the maximum value MAX and the minimum value MAX-δ as a constant current control in 100% drive mode. Here, the constant current control period (chopping period T _chop ) can be set appropriately, but in this type of motor performance, in order to control the motor drive current to a constant current, in control method 1 described later, it is preferable to set the chopping period T _chop = 8 to 12 μS, and in this embodiment, the chopping period T _chop for constant current control is set to 10 μS.

As shown in Figures 52(b) and 52(c), in this embodiment, in 100% drive mode, the motor drive current begins to increase from the start of the chopping cycle, and after reaching a MAX value of 545 mA, it continues to decrease until the start of the next chopping cycle. As explained above, if a drive mode is selected that is less than 100% drive mode, the MAX value will be appropriately reduced, thereby reducing power consumption.

Next, Figures 52(d) and 52(e) are circuit diagrams showing the Bridge A and Bridge B drive circuits that drive drive windings A and B, and show the internal configuration of the bridge drive circuits (Motor output stage Bridge A/B), current detection resistors RS_A/RS_B, and a motor drive voltage of 35V. As shown, both drive circuits configure an H-bridge that achieves bipolar drive using P-type MOS transistors U1 and U2 on the high-voltage side and N-type MOS transistors L1 and L2 on the low-voltage side.

In this example, the A-phase winding and B-phase winding of the bipolar stepping motor each have a winding inductance value of, for example, 4.2 mH and an internal resistance of 21 Ω. Therefore, when the motor drive voltage is 35 V, the steady-state current (DC current in saturated state) flowing through each winding is 35/21 = 1.7 A, which significantly exceeds the rated current (1 A) of this motor. However, in this example, constant current control is implemented to limit the maximum current to 545 mA, thereby avoiding torque degradation and achieving high-speed rotation of the stepping motor.

53(a) is a diagram explaining the operation of the bridge drive circuit (Motor output stage Bridge A/B), showing the coil charging operation CHARGE, the coil slow discharging operation, and the coil fast discharging operation in one chopping period T _chop . As shown in the figure, the slow discharging operation is an operation in which the coil current is discharged via the low-voltage side transistors L1 and L2, while the fast discharging operation is an operation in which a transistor that was in the OFF state during the charge operation is turned on and a transistor that was in the ON state is turned off.

Slow discharge is superior to fast discharge in that it has a smaller current ripple and a larger average current, but when slow discharge is used, normal operation cannot be guaranteed at high speeds above a certain level. Therefore, in this embodiment, in order to rotate the stepping motor at high speeds, the coil discharge current is optimized by combining slow discharge, which has a high average current, with fast discharge, which is suitable for high-speed operation.

In this embodiment, the stepping motor is driven bipolarly, so the operating state of the transistor switches appropriately between the ON/OFF state of Figure 53 (b) which realizes the rightward driving current of Figure 53 (a) and the ON/OFF state of Figure 53 (c) which realizes the leftward driving current.

Based on the above, to further explain the charging and discharging operations shown in Figure 53(a), during CHARGE operation, transistors U1 and L2 on the high-voltage and low-voltage diagonal sides of the H-bridge are turned ON, while transistors U2 and L1 on the opposite diagonal are turned OFF. If the inductance L of the coil winding is 4.2 mH and the internal resistance R is 21 Ω, then the reciprocal of the coil's time constant, R/L, is 5000 (the time constant is 0.2 mS).

Therefore, if the initial coil current at the start of the CHARGE operation is _I0 and the motor drive voltage is 35V, then the coil current I at elapsed time t from the start of the CHARGE operation is I=E/R+(I0 _- E/R)*EXP(-5000*t), and if _I0 =0.5[A], then I≈1.67-1.17*EXP(-5000*t)[A]. Note that the current detection resistance RS_A/RS_B is, for example, 0.33Ω, which is significantly lower than the internal resistance R=21Ω and can be ignored.

On the other hand, if the initial coil current at the start of slow discharge is _I0 , the coil current I at elapsed time t from the start of slow discharge operation is I = _I0 * EXP(-5000 * t), and if _I0 = 0.5 [A], then I ≈ 0.5 * EXP(-5000 * t) [A]. Also, if the initial coil current at the start of fast discharge is _I0 , the coil current I at elapsed time t from the start of fast discharge operation is I = -E/R + ( _I0 + E/R) * EXP(-5000 * t), and if _I0 = 0.5 [A], then I ≈ -1.67 + 2.17 * EXP(-5000 * t) [A].

53(c) shows the discharge curves for slow discharge and fast discharge, showing fast discharge in which the current decreases rapidly from an initial current I ₀ = 0.5 A, and slow discharge in which the current decreases slowly, as shown by the dashed line. Incidentally, in this embodiment, the stepping motor is driven bipolarly, so the direction of the coil drive current is switched by the fast discharge operation, and in fast discharge, the coil drive current shifts from 0.5 A to -0.5 A in about 0.12 ms after the start of the discharge operation.

In this embodiment, the maximum current MAX in 100% drive mode is set to 545 mA, but in Figure 53 (c), the amplitude range of the maximum current indicated by the large arrow is set to ±500 mA for ease of illustration. Furthermore, for the constant current control performed between 500 mA and the minimum current very close to this, the amplitude range is shown by the small arrow.

Figure 54(a) is a time chart illustrating constant current control operation that combines the CHARGE operation, SLOW operation, and FAST operation described in Figure 53(a), and shows the increase and decrease in drive current Iout.

Figure 54(a) illustrates control method 1 employed by motor drivers DV1 and DV2 in Figure 52, with control progressing in the order of CHARGE → SLOW → FAST in one chopping cycle T _chop . In the illustrated operation, the chopping cycle T _chop , like in Figure 52(b), is 10 μS, equivalent to 16 internal clocks with a frequency of about 1.6 MHz. As explained above, when control method 1 is employed, it is preferable to set the chopping cycle T _chop to about 8 to 12 μS.

In the illustrated control method 1, during CHARGE operation, after the drive current Iout reaches the upper current limit NF, the system transitions to SLOW operation, and in this example, when the number of remaining clocks reaches six, the system transitions to FAST operation. This control method 1 has the advantage of ensuring a fixed operating time for FAST operation. It goes without saying that this control method 1 can also be used for the motor drivers DV3 and DV4 shown in Figure 57.

Next, Figure 54(b) shows control method 2, in which control is transitioned in the order of CHARGE → FAST → SLOW in one chopping cycle T _chop . In the illustrated operation, the chopping cycle T _chop is 13.56 μS, which corresponds to 16 internal clocks with a frequency of approximately 1.18 MHz. Although not particularly limited, when control method 2 is adopted, it is preferable for this type of motor control to have a constant current control cycle (chopping cycle) of approximately 6 to 25 μS.

In CHARGE operation, after the drive current Iout reaches the upper current limit NF, the system first switches to FAST operation, and then switches to SLOW operation once it drops to a predetermined threshold TH. This control method 2 has the advantage of being able to fix the starting current for SLOW operation using threshold TH, ensuring the required average current. However, to avoid delays in detecting the upper current limit and threshold, the internal clock should be set to 640 kHz to 2400 kHz.

In this control method 2, it is not necessary to set the threshold value TH to a fixed value; it is preferable to change the threshold value TH appropriately in response to the current attenuation situation, etc., so that a predetermined average current is maintained. This control method 2 is used in the motor drivers DV3 and DV4 shown in Figure 57, but it goes without saying that control method 2 may also be used in place of control method 1 in the motor drivers DV1 and DV2 shown in Figure 52.

Figure 55 shows a detailed view of a portion of the motor driver to explain the structure of the control data SDATA that is serially transmitted to motor drivers DV1 and DV2. Specifically, Figure 55 shows the torque control section (torque control, VREF comp, Bridge A NF level set), 8-bit shift register, and main control logic from Figure 52.

As explained above, the control data SDATA includes excitation data (4-bit PHASE instruction value) that indicates one step of advancement, and a 4-bit current instruction value that specifies the drive current to be passed through motor windings A and B. This 8-bit data is then converted to parallel and stored in a storage register, after which it is latched in the input circuit (Logic input gate) in synchronization with the advancement clock LATCH and supplied to the central control unit (Motor Control Logic).

The central control unit (Motor Control Logic) generates a PHASE signal based on the excitation data (4 bits) and determines the current upper limit NF for constant current control based on the current command value (4 bits). Here, the current upper limit NF corresponds to the maximum current MAX in 100% drive mode, but in drive modes below 100%, it becomes the current upper limit corresponding to the drive mode.

Since output torque corresponds to the drive current flowing through the coil windings, a higher drive current is advantageous in that it increases output torque, but maintaining a stopped state does not require that much output torque. Therefore, in this embodiment, as explained above, the current upper limit value NF is switched as needed to reduce unnecessary power consumption.

The 4-bit excitation data included in the control data SDATA can be used to select an appropriate excitation mode, such as two-phase excitation or one-two-phase excitation. In this embodiment, however, the stepping motors MO1-MO2 are two-phase excited. As is clear, when the same excitation data is repeatedly transmitted serially, the stepping motor does not move in steps (advance) but is instead driven to a stop to maintain its stopped state. Therefore, as explained above, during this stop-drive operation, the current command value (4 bits) is reduced to reduce power consumption.

The stop drive continues to be performed as constant current control based on the upper limit value NF even after serial transmission of the excitation data (4-bit PHASE instruction value) has ceased. Also, even if only the stepping clock LATCH is supplied periodically after transmission of the excitation data has ceased, the stop drive is repeated using constant current control based on the excitation data and current instruction value stored in the storage register.

Fig. 56 shows the relationship between the drive data DATA, shift clock SCK, and stepping clock LATCH received by motor drivers DV1/DV2 from serial port SIO_0, and the A-phase and B-phase drive currents Iout output by motor drivers DV1-DV2 to stepping motors MO1/MO2. The drive currents are constant-current controlled by control method 1 described in Fig. 53, and the operating state of constant-current control with a chopping period T _chop =10µS is shown in a sawtooth pattern.

In the illustrated example, the PHASE signal changes from HH: current vector A → LH: current vector B → LL: current vector C → HL: current vector D for phases A and B in response to the transition of the excitation data (4 bits), achieving clockwise rotation CW. Furthermore, the current command values (4 bits) are all 1111, and stepping motors MO1/MO2 are operating in 100% drive mode at this timing.

As explained earlier, serial port SIO_0 outputs the shift clock SCK at a baud rate of 250 kbps, so serial transmission of the excitation data (4 bits) and current instruction value (4 bits) is completed in 32 μS. On the other hand, PIO port 62 outputs the stepping clock LATCH every 1 ms, so in Figure 56, there is actually a large gap of approximately 968 μS (= 1000 - 32) between each of current vectors A, B, C, and D.

Figure 57 is a block diagram showing the internal configuration of motor drivers DV3-DV4. As shown in the figure, motor drivers DV3/DV4 are configured with DMODE0-DMODE2 terminals that receive excitation mode setting data (3 bits), a CW/CCW terminal that specifies the rotation direction, a CLK terminal that receives a stepping clock, a RESET terminal that receives a reset signal, an ENABLE terminal that receives a command to enable/disable motor drive operation, RSA and RSB terminals to which detection resistors (e.g., 0.33 Ω) are connected for detecting the motor drive current, VREFA and VREFB terminals that receive a setting voltage that determines the upper current limit NF for constant current control, a VM terminal that receives a 35V motor drive voltage, a VCC terminal that outputs an internally generated constant voltage of 5V, an OSCM terminal that determines the internal clock, an MO terminal that can monitor the progress of the PHASE signal, an LO terminal that can monitor internal error states, and OUTA± and OUTB± terminals that output the drive current Iout.

Motor drivers DV3/DV4 are comprised of an oscillator circuit (Motor Oscillator, OSC-Clock Converter) that generates an internal clock based on the elements connected to the OSCM terminal, a constant voltage circuit (VCC Regulator) that generates a constant voltage of 5V based on the 35V drive voltage received at the VM terminal, a current control circuit (Current Reference Setting, Current Level Set) that determines the upper limit current NF for constant current control based on the voltage received at the VREFA and VREFB terminals, a signal restoration circuit (Signal Decode Logic) that generates internal signals corresponding to various external commands, a pair of monitoring circuits (Current Comp) that monitor the motor drive current Iout for phases A and B, a pair of drive circuits (H-bridge) that drive drive windings A/B, an overheat detection circuit (TSD), an overcurrent detection circuit (ISD), a 35V power supply power-on reset circuit (Power-On Reset), and a central control unit (Motor Control Logic) that controls the operation of each component.

As shown in the figure, the VM terminal, which receives a DC voltage of 35V, is connected to the same 33μF conductive polymer capacitor as in Figure 52. That is, a hybrid capacitor in which an electrolyte made from a combination of conductive polymer and electrolyte is used instead of the electrolyte of an aluminum electrolytic capacitor. As in Figure 52, this conductive polymer capacitor also has a rated voltage of 50V and is a cylindrical surface-mount device with a diameter of 6.3mm and a height of 7.7mm. The desired decoupling operation can be achieved by simply placing a single capacitor for each motor driver (DV3, DV4). The capacitance value "33", the symbol "H" indicating a rated voltage of 50V, and the black symbol indicating negative polarity are the same as those explained in Figure 52.

Meanwhile, the OSCM terminal is connected to a 5.1 kΩ resistor connected to a constant voltage of 5 V and a 270 pF capacitor connected to ground, and the frequency of the internal clock that manages constant current control is set to 1.18 MHz. Therefore, in this embodiment, the chopping frequency is, for example, 1.18/16 = 73.75 kHz, and constant current control is performed with a chopping period of 13.56 μS.

The VREFA and VREFB terminals are also configured to receive voltages corresponding to the upper current limit setting signals SETx and SETy (see Figure 49) received from the motor controller 85 via the setting circuit LMT (see Figure 49). Specifically, the voltage divider circuit is configured so that the set voltage when the electronic switch SW of the setting circuit LMT is ON is 0.78V, while the set voltage when the electronic switch SW is OFF is 0.1685V.

Motor drivers DV3/DV4 are configured to determine the upper current limit NF for constant current control in accordance with the set voltage of 0.78/0.16V. In this embodiment, the upper current limit NF is approximately 473mA/102mA for both phases A and B, corresponding to the ON/OFF state of the switch circuit SW.

In accordance with the above circuit configuration, in this embodiment, for example, during constant current control of the motor during performance, the motor is driven and controlled so that the upper current limit NF is 473 mA. However, during standby operation before the start of the motor performance, for example, standby control is performed so that the upper current limit NF is 102 mA, which is less than one-quarter of the previous value, thereby reducing unnecessary power consumption. Incidentally, power consumption during standby control is, in principle, approximately 4.65% of that during drive control.

Next, the DMODE0 to DMODE2 terminals, which specify the excitation method, are configured to be able to supply 3-bit setting data. Furthermore, motor drivers DV3/DV4 are configured to allow specification of not only two-phase excitation (see Figure 58(a)), which changes the drive current Iout in a rectangular shape, but also one-two-phase excitation (see Figure 58(b)), which inserts a 0% drive state to slightly soften the pulse waveform, and microstep excitation, which changes the current upper limit NF in multiple steps between +100% drive and -100% drive, to change the drive current Iout in an approximately sinusoidal wave shape.

Here, the closer the drive current Iout is to a sine wave, the smoother the rotation of the stepping motor, which is an advantage. However, unlike precision machinery, it is understood that the smooth rotation of this type of gaming machine is not necessary for the role-playing effects of this type of gaming machine. Also, rather than reducing the step angle and achieving smooth rotation, it is more effective for the motor's performance to increase the step angle and achieve high-speed rotation.

In this embodiment, the stepping motor is excited in two phases or one-two phases based on the setting data supplied to the DMODE0 to DMODE2 terminals. To rotate the motor at high speed, two-phase excitation, which has a larger step angle, is more advantageous than one-two phase excitation. While the setting data can be a control value processed by software, in this embodiment it is a fixed value set by hardware, and whether two-phase excitation or one-two phase excitation is used is specified for each gaming machine model.

However, in the following explanation, the DMODE0 to DMODE2 terminals of motor drivers DV3/DV4 are supplied with fixed setting data (001), causing the stepping motor to undergo two-phase excitation each time it receives a stepping clock CLK from the motor controller 85. In other words, motor drivers DV3/DV4 will operate as shown in Figure 58(a).

Next, the CW/CCW terminal, CLK terminal, and ENABLE terminal are each supplied with one-bit direction data, a stepping clock CLK for moving the stepping motor one step, and an enable signal ENABLE that enables drive operation from the motor controller 85. The RESET terminal is constantly at L level, and is always enabled via an internal NOT circuit (see Figure 49).

Figures 58(a) and 58(b) show the stepping clock CLK and the drive current Iout for the A-phase winding and B-phase winding during two-phase excitation and one-two-phase excitation. When clockwise rotation (CW) is instructed, the driver's internal circuitry operates so that the drive current Iout shifts to the right on the time axis in response to the stepping clock CLK. On the other hand, when counterclockwise rotation (CCW) is instructed, the driver's internal circuitry operates so that the drive current Iout shifts to the left on the time axis in response to the stepping clock CLK. In other words, the current level and direction of the drive currents Iout(a) and Iout(b) shift each time a stepping clock CLK is received. As shown, in two-phase excitation, the current direction changes each time a stepping clock CLK is received. In 1-2 phase excitation and microstep excitation (not shown), the current level changes each time a stepping clock CLK is received.

Here, the stepping clock CLK is supplied at an appropriate timing and speed from the motor controller 85. The stepping clock CLK corresponds to the step angle θ of the stepping motor, and each time the stepping motor receives a step clock CLK, it rotates by one step angle θ [degree]. Therefore, when N stepping clocks CLK are received, the stepping motor will rotate by N*θ [degrees], and the stepping motor will rotate by an angle corresponding to the number of step clocks CLK.

Here, if N stepping clocks CLK are supplied over a time T, it will take time T [seconds] to rotate N*θ [degrees], and the rotational angular velocity will be N*θ/T [degrees per second]. The stepping motor used in this example is two-phase excited, and the step angle θ is, for example, 7.5 degrees, so 48 (= 360/7.5) stepping clocks CLK are required for one rotation of the motor.

Therefore, if the pulse speed of the stepping clock CLK is V [PPS (Pulse Per Second)], the 48 pulses CLK required for one rotation of the motor are supplied at 48/V [S], so the motor will rotate at 60*V/48 revolutions per minute, which converts to a motor rotations per minute (rpm) of 60*V/48 [rpm].

Incidentally, in these motor drivers DV3/DV4, constant current control is also performed based on the current upper limit value NF. However, as explained in relation to Figure 57, in this embodiment, the current upper limit value NF is set to either 473 mA or 102 mA depending on whether drive control is being performed during a moving performance or standby control is being performed before the start of a moving performance, and is configured to be changed appropriately by the motor controller 85.

Figure 58(c) shows the operation of constant current control when, for example, transitioning from standby control to drive control, and shows that in either control state, constant current control of CHARGE → FAST → SLOW is executed based on control method 2 shown in Figure 54(b). On the other hand, Figure 58(d) shows the case when, for example, transitioning from drive control to standby control is executed, and in this case too, constant current control of CHARGE → FAST → SLOW is executed based on control method 2 shown in Figure 54(b).

Even if the stepping clock CLK is interrupted, motor drivers DV3/DV4 continue constant current control based on the specified upper limit current NF, so motors MO3 and MO4 are driven to a stopped state.

Next, Figure 59 is a block diagram showing the internal configuration of the motor controller 85, which controls the operation of motor drivers DV3/DV4. The motor controller 85 is configured with four internal circuits (circuits surrounded by dashed lines in Figure 59) that have the same configuration and control four motor drivers. When controlling four motor drivers, each motor driver drives four stepping motors, and for convenience, the rotation axes of each motor are referred to in this specification as the X-axis, Y-axis, Z-axis, and U-axis.

In accordance with this representation, the motor controller 85 includes identically configured X-axis, Y-axis, Z-axis, and U-axis circuits, all of which are enclosed by dashed lines in Figure 59; however, in this embodiment, only the X-axis and Y-axis circuits are used.

Here, the X-axis circuit drives and controls motor driver DV3, which drives stepping motor MO3, and the Y-axis circuit drives and controls motor driver DV4, which drives stepping motor MO4. The operation of the X-axis circuit and Y-axis circuit is controlled by performance control CPU 63 via serial port SIO_1.

Considering the above, if we examine the circuit configuration in Figure 59, we can see that the motor controller 85 receives control data MOSI serially from serial port SIO_1 in synchronization with the shift clock SCK, while also serially transmitting the sensor signal MISO to serial port SIO_1. It also receives a reset signal RESET from PIO port 62, and receives an operating signal SS, the valid period of which is low, from the compare match timer CMT.

The X-axis circuit of the motor controller 85 also sends a stepping clock OUTx (CLK), a setting signal SETx that specifies the upper limit current, direction instruction data DIRx that specifies the direction of rotation (CW/CCW), and an operation enable signal ENABLEx to the motor driver DV3. Meanwhile, the Y-axis circuit of the motor controller 85 sends a stepping clock OUTy (CLK), a setting signal SETy that specifies the upper limit current, a direction binary signal DIRy that specifies the direction of rotation, and an operation enable/disable command ENABLEy to the motor driver DV4.

Here, when the operation enable signals ENABLEx and ENABLEy are at L level, the outputs of all four MOS transistors that make up the H-bridge of the drive circuit built into motor drivers DV3/DV4 go into the HiZ state, prohibiting motor drive. Therefore, prior to the start of motor performance by stepping motors MO3/MO4, the performance control CPU 63 must send specified control data to motor controller 85, and control the motor controller 85 to output H-level operation enable signals ENABLEx and ENABLEy to motor drivers DV3/DV3. However, to avoid complexity, it is sufficient to perform the above operation only once when power is turned on, and such an embodiment will be described below.

Returning to FIG. 59 to continue the explanation of the motor driver 85, the motor controller 85 is configured to be capable of both SPI (Serial Peripheral Interface) communication and ^I2C (Inter-Integrated Circuit) communication with the CPU circuit 51, but in this embodiment, as explained at the beginning, serial transmission and reception operations are performed using SPI communication.

The motor controller 85 is configured to have an SCL terminal and an SDA terminal that function during ^I2C communication, DS0-DS1 terminals that receive a device selection number, an SS terminal that receives an operating signal SS, an SCK terminal that receives a shift clock SCK, a MOSI terminal that receives control data MOSI, an MISO terminal that outputs a sensor signal MISO, a CSTA terminal that indicates the simultaneous start of multiple motors (all or some of the X/Y/Z/U axes), an INT terminal that indicates that an interrupt has been activated, an RST terminal that receives a reset signal, a CLK terminal that receives a reference clock that determines internal operation, and an IFSEL terminal that determines whether the serial communication operation mode is SPI or ^I2C .

As shown in the figure, the DS0-DS1 terminals are fixed to, for example, 00, so the device number assigned to this motor controller 85 is 0. In this embodiment, multiple motor controllers 85 can be connected in parallel to a single serial port SIO_1, and the device number is used to identify any one motor controller.

In this embodiment, the IFSEL terminal is fixed to the H level, causing the motor controller 85 to operate in SPI mode. Therefore, the SCL and SDA terminals are not enabled in this embodiment. However, it is of course possible to operate in ^I2C mode, and the following operations can be realized in ^I2C mode as well.

As shown in the diagram, the CLK terminal is supplied with a reference clock with a frequency of approximately 9.8 MHz generated by the oscillator circuit. The RST terminal is supplied with a reset signal RESET from the PIO port 62, and the SS terminal is supplied with an operating signal SS from the compare match timer CTM. The SCK and MOSI terminals output the shift clock SCK and control data MISO from the corresponding circuit of serial port SIO_1, and the sensor data MISO is serially transmitted from the MISO terminal to the receive shift register SCRSR of serial port SIO_1.

Next, we will explain the X-axis circuit of the motor controller 85. As shown in Figure 59, the X-axis circuit is composed of an OUTx terminal that outputs a stepping clock CLK to the motor driver DV3, a DIRx terminal that outputs direction indication data, a P2x terminal that outputs an operation enable signal ENABLEx, and a P3x terminal that outputs an upper limit current setting signal SETx.

The X-axis circuit also has a P0x terminal that receives an origin sensor signal indicating whether the reel driven by motor MO3 is at the origin position, and a P1x terminal that receives a destination position sensor signal indicating whether the reel has reached the destination position.

The Y-axis circuit has the same configuration as the X-axis circuit described above, except that the motor driver changes from DV3 to DV4 and the stepping motor changes from MO3 to MO4. While the Z-axis circuit and U-axis circuit are not used in this example, using them would allow the four stepping motors to be driven and controlled synchronously or independently.

The motor controller 85 has built-in general-purpose input/output ports capable of input/output operations, corresponding to the P0x, P1x, P2x, and P3x terminals mentioned above. It also has a built-in general-purpose port control circuit that causes the general-purpose input/output ports to perform the necessary input/output operations based on commands from the performance control CPU 63. Since the general-purpose input/output ports can be used as both input and output ports, in this embodiment, the P0x and P1x terminals are initially set as input terminals for the general-purpose input ports P0 and P1, and the P2x and P3x terminals are initially set as output terminals for the general-purpose output ports P2 and P3.

The motor controller 85 also includes multiple registers that can arbitrarily set the number of output clocks of the stepping clock CLK output from the OUTx terminal, the output clock period (clock speed of the stepping clock CLK), and other parameters. The motor rotation speed is determined by the clock speed of the stepping clock CLK, and the rotation angle is determined by the number of output pulses of the stepping clock CLK, but the motor controller 85 is configured to be able to output any number of stepping clocks at any clock speed based on instructions from the performance control CPU 63.

As explained above, motor drivers DV3/DV4 rotate motor MO3 by one step for each stepping clock CLK, so the rotation angle of motor MO3 is determined by the number of output clocks, and the rotation speed of motor MO3 changes according to the output cycle of the stepping clock CLK.

By the way, motor controller 85 allows for arbitrary acceleration and deceleration control, and not only rectangular drive (Figure 60(a)) without acceleration and deceleration control is possible, but also trapezoidal drive shown in Figure 60(b). Rectangular drive shown in Figure 60(a) is used when the motor rotation speed is relatively slow, and the pulse speed of the stepping clock CLK (corresponding to the pulse output period) always matches the starting pulse speed from the start of rotation to the end of rotation. Furthermore, rectangular drive is simple to control and can be handled by program processing by the CPU, so it is used not only for motors MO3 and MO43, but also for driving motors MO1 and MO2 via serial port SIO_.

On the other hand, trapezoidal drive, shown in Figure 60 (b), is used when the motor rotation speed is high, in which the pulse speed of the stepping clock CLK gradually increases linearly from the starting pulse speed until it reaches the target value of the running pulse speed. After that, after rotating the required amount at the running pulse speed, the pulse speed of the stepping clock CLK gradually decreases linearly from the running pulse speed until it reaches the starting pulse speed and the motor stops. This trapezoidal drive prevents sudden starts and stops of motor rotation, making it possible to prevent abnormal operation such as loss of synchronization.

As shown, the pulse speed increases linearly in three or more stages, and then decreases linearly in three or more stages. This type of trapezoidal drive requires complex changes to the pulse period of the stepping clock CLK, as shown in Figure 60(b), and is not easy to achieve through CPU program processing. Therefore, in this embodiment, by utilizing the motor controller 85, high-speed rotation of each motor is achieved while avoiding sudden starts and stops of motors MO3 and MO4 without increasing the control burden on the CPU. As will be described later, in this embodiment, during a specified performance, a specified prop is lowered/raised at a speed faster than natural falling.

As shown in Figure 60 (c), rectangular drive requires specifying not only the number of output pulses but also operating parameters such as the start and end speed FL, target speed FH, acceleration rate, and deceleration rate. These operating parameters are set by the performance control CPU 63 in the built-in registers described below.

As shown in Figure 59, the built-in registers of the motor controller 85 include N first-type registers, M second-type registers, and N pre-registers in which values can be preset for the first-type registers. When a motor operation based on the first-type register is completed, the corresponding pre-register value is automatically transferred to the first-type register, making it possible to start a new motor operation. Therefore, in this embodiment, after setting operating parameters in the first-type registers, a series of motor operations can be quickly set by setting operating parameters in the pre-registers for subsequent motor operations as well.

The first-type registers and pre-registers each contain six registers that can specify the target speed FH: register RFH (R1), which sets the target speed FH; register RUR (R2), which specifies the acceleration rate; register RDR (R3), which specifies the deceleration rate; register RDP (R4), which specifies the slow-down point; register RWV (R5), which specifies the number of output pulses; and operating mode (R6). The slow-down point refers to the timing at which the deceleration process begins, while register RDP specifies the number of pulses used to execute the deceleration operation. Register RDP, which specifies the slow-down point, and register RDR, which specifies the deceleration rate, are used alternatively; when the deceleration rate is specified, the slow-down point is automatically determined.

The above-mentioned operating parameters can be set in the Type 1 register and pre-register, so not only the operating mode after a mid-stop, but also the target speed, acceleration rate, deceleration rate, and number of output pulses for restarting the rotation can be reserved and set in the pre-register.

Next, the second-type registers include register RFL, which specifies the initial speed FL when the motor starts rotating and the final speed FL before it stops, as well as register RMD and environment setting register RENV, which can set the motor's operating mode. Here, motor operating modes include continuous movement in the clockwise direction (MD1), continuous movement in the counterclockwise direction (MD2), relative movement in the clockwise direction (MD3), relative movement in the counterclockwise direction (MD4), CW positioning movement, which moves in the clockwise direction until sensor detection (MD5), CCW positioning movement, which moves in the counterclockwise direction until sensor detection (MD6), and timer movement, which moves for a period of time specified by a timer (MD7). Setting specific operating parameters in mode setting register RMD specifies one of the motor's modes (MD1) through (MD7).

In this embodiment, the sensors that are detected in operation mode (MD5) and operation mode (MD6) include an origin sensor that indicates whether the reel is located at the origin position, and a destination position sensor that indicates whether the reel is located at the destination position. Therefore, according to this embodiment, a return operation toward the origin position and a forward operation toward the destination position can be defined as one operation mode. In operation mode (MD5) and operation mode (MD6), the robot continues to rotate at the operating speed set in speed register RFH, and then, when a sensor signal is detected, it outputs the number of pulses set in pulse count register RWV and stops.

On the other hand, in relative movement in operation mode (MD3) or operation mode (MD4), the operating speed is specified by speed register RFH, and the number of pulses set in pulse count register RWV is output before stopping. In this case, trapezoidal drive is also possible in addition to rectangular drive. In the case of trapezoidal drive, rotation begins in the manner set by acceleration rate register RUR, rotates at the operating speed specified by speed register RFH, and then ends in the manner set by deceleration rate register RDR. Note that with trapezoidal drive, operation excluding only acceleration control (instant start + deceleration stop) or operation excluding only deceleration control (acceleration start + instant stop) is also possible.

Furthermore, in the continuous movement specified in operation mode (MD1) or operation mode (MD2), rotation continues at the operating speed specified in speed register RFH, and rotation ends upon receiving a stop command. In either operation mode, operation begins upon receiving a start command. In other words, the motor controller 85 is configured to operate upon receiving various commands, including start commands and stop commands, from the performance control CPU 63.

Here, the commands that the performance control CPU 63 can output to the motor controller 85 include, in addition to the stop command (CM0), multiple start commands (CM1) with different start modes, multiple remaining amount start commands (CM2) with different start modes, multiple speed change commands (CM3) with different change modes, and an output command (CM4) that outputs specified data from a general-purpose output port. In this embodiment, this output command (CM4) is used to output an enable signal ENABLEx and a current upper limit setting signal SETx to the general-purpose output ports P2 and P3.

In the relative movement operation modes specified in operation mode (MD3) and operation mode (MD4), the number of remaining pulses is managed by the built-in remaining pass counter REST. The performance control CPU 63 can also stop the motor midway at an appropriate timing by reading the number of remaining pulses from the remaining pass counter REST. The remaining amount start command specifies the restart after this midway stop.

The environment setting register RENV included in the second-type register is configured to allow setting of a count-up time TCUP and a count-down time TCDW, which realize the count-down control described below in relation to Figure 60(d). One of four options can be selected for both the count-up time TCUP and the count-down time TCDW.

The above describes the various registers that the performance control CPU 63 can access for WRITE, but there are also status registers and other registers that indicate the operation of the motor controller 85, and by appropriately accessing these registers for READ, the performance control CPU can grasp the operating status of the motor controller 85.

Figure 61(a) shows the timer interrupt processing executed every 1 mS by the performance control CPU 63, and is a detailed version of the processing in Figure 22(b). Figure 62 is a time chart explaining the serial transmission procedure to the motor controller 85 based on the processing in Figure 61(a).

The 1 ms timer interrupt process first outputs a pulsed latch signal LOAD to the sensor board 86, and outputs a stepping clock LATCH to motor drivers DV1 and DV2 (RT1). The shift register 90 on the sensor board 86 then latches the sensor signal upon receiving the latch pulse LOAD. Motor drivers DV1 and DV2 then rotate/stop motors MO1 and MO2 based on the 8-bit data (current command value + PHASE setting) acquired during the previous timer interrupt.

Next, the performance control CPU 63 stores the previous data already acquired in the data register SCFRDR of the serial port SIO_0 in a specified area of memory (R2). In this way, in this embodiment, the serial data received serially in response to the previous timer interrupt is acquired from memory at the time of the next timer interrupt, so the first acquired data (RT2) after power-on is naturally ignored. As explained at the beginning, the serial data received serially in the receiving shift register SCRSR is initially set to automatically accumulate in the FIFO data register SCFRDR, which has a FIFO structure, every time it reaches 8 bits.

Next, it is determined whether motors MO1 and MO2 are currently performing a motor effect (RT3). If motors MO1 and/or MO2 are currently performing a motor effect, drive data SDATA (16 bits) for step rotation of motors MO1 and MO2 is set in the FIFO data register SCFTDR of serial port SIO_0 (RT4). The drive data SDATA (16 bits) is made up of 8 bits for each of motors MO1 and MO2: a PHASE setting value (4 bits) and a current instruction value (4 bits), for a total of 16 bits.

As explained earlier, drive data SDATA does not necessarily need to be updated every 1 mS; if the motor rotation speed is slow, the same PHASE setting value can be used multiple times, N times. In this case, the N PHASE setting values are always the same, but it is preferable to set the current instruction value from the second to the (N-1)th time to a suppression level of, for example, 25% drive. At this suppression level, power consumption is theoretically 1/16 = 6.25%.

In addition, to realize the operation shown in Figure 60(d) described below, before starting a series of rotation operations, drive data SDATA consisting of a PHASE setting value (transmitted value at the final rotation) that maintains the stopped state and an upper limit current instruction value (100% drive) is set in the FIFO data register SCFTDR.

For example, when motors MO1 and MO2 start rotating in sync, the aforementioned 8-bit drive data SDATA, totaling 16 bits, is prepared in the FIFO data register SCFTDR. Then, prior to the start of rotation, this drive data SDATA is serially transmitted multiple times, executing an upper-level stop drive. Note that this operation is intended to absorb the inertia of the reel and prevent problems such as stepping out, and is therefore not necessary for reels that start at low speeds or lightweight reels.

On the other hand, if motors MO1 and MO2 are not currently performing motor effects, drive data SDATA for stop drive is set in the FIFO data register SCFTDR for motors MO1 and MO2 that are in a stopped state (RT5). Drive data SDATA for stop drive consists of the PHASE setting value (previously transmitted value) that maintains the stopped state and the current instruction value for the suppression level (e.g., 25% drive).

In this case, to achieve the operation shown in Figure 60(d), rather than immediately transmitting the suppression level current command value, drive data SDATA consisting of the PHASE setting value (previously transmitted value) to maintain the stopped state and the upper limit level current command value (100% drive) is transmitted in advance an appropriate number of times, and the upper limit level stop drive is performed. This operation is also to absorb the inertia of the reel, so it is not necessary for reels that stop slowly or are lightweight.

Next, the performance control CPU 63 starts serial transmission/reception processing of the serial port SIO_0 for the drive data SDATA (16 bits) set in the FIFO data register SCFTDR of the serial port SIO_0 (RT6). As a result, the serial port SIO_0 outputs a total of 16 shift clocks SCK until the FIFO data register SCFTDR becomes empty, and the 16-bit transmission data (drive data SDATA) is transferred to the motor drivers DV1 and DV2 in synchronization with these shift clocks SCK.

As explained in Figure 56, the drive data SDATA sent at this timing is executed by the stepping clock LATCH output at the next timer interrupt.

The shift clock SCK is also supplied to the sensor board 86. Synchronized with the first eight shift clocks SCK, the sensor signal SEN is serially received by the receive shift register SCRSR of the serial port SIO_0, and the received data is stored in the FIFO data register SCFRDR. Since a total of 16 shift clocks SCK are output, the stored data is 16 bits long. However, only the first eight bits are valid sensor signal SEN, and the remaining eight bits are useless 00H (see Figure 51(b)).

In this embodiment, the baud rate is 250 kbps, so 16 shift clocks SCK is approximately 16/250 k = 0.064 mS, and with a timer interrupt operating period of 1 mS, processing is completed in an extremely short time (see the upper part of Figure 63). Also, the performance control CPU 63 only starts the serial transmission process (R6) and does not wait for the serial transmission to be completed, so the processing of steps R1 to R6 is completed in an instant. Furthermore, the fact that the serially received data is left to the next timer interrupt processing also contributes to shortening the processing time.

By the way, after the CH0 motor performance has ended, as shown by the dashed line in Figure 61, the processing of steps RT4 and RT6 may be skipped without executing the processing of step RT5. In this case, motors MO1 and MO2 are repeatedly stopped and driven by constant current control based on the final PHASE setting value and current setting value.

Once the above processing of serial port SIO_0 is complete, the performance control CPU 63 activates the compare match timer CMT, causing it to begin outputting an operating signal SS with a pulse width of, for example, approximately 0.8 ms (RT7). As shown in the upper left of Figure 49, the compare match timer CMT transitions the operating signal SS to H level in response to the start of the clock signal count operation, and is initially configured to then generate a CMT interrupt when the count result reaches a predetermined upper limit value MX.

Then, during the CMT interrupt processing, the performance control CPU 63 stops the counting operation of the compare match timer CMT, causing the operating signal SS to return from H level to L level. As described above, the performance control CPU 63 is only concerned with the rising edge and falling edge of the operating signal SS, so there is no risk of it having a negative impact, such as taking away processing time from other performance control processes.

After raising the in-operation signal SS to H level, the performance control CPU 63 acquires the sensor signal MISO from the motor controller 85 (RT8). Figure 62(a) is a time chart showing this acquisition procedure, which synchronizes with eight shift clocks SCK, setting device numbers S7-S6 = 00, operation type S5-S4 = 11, and read target UZYX axes S3-S0 = 0010 or S3-S0 = 0001 to specify that the sensor signal for the X or Y axis of the motor controller 85 with device number 00 is to be acquired.

Next, in synchronization with the eight subsequent shift clocks SCK, the sensor signal for motor MO3 (X-axis) (or the sensor signal for motor MO4 (Y-axis)) is acquired. In other words, by repeating the operation of Figure 62(a) twice, sensor signals for the X and Y axes are acquired. As shown in Figure 59, of the general-purpose input/output ports, only port P0 (P0x terminal, P0y terminal) and port P1 (P1x terminal, P1y terminal) are set as input ports, so of the received data D7 to D0, only D1 and D0 are significant. The performance control CPU then stores the acquired sensor signals D1 and D0 in an appropriate location in memory and uses them in subsequent motor performances.

However, as explained above, the operating modes that the performance control CPU 63 can specify to the motor controller 85 include CW positioning movement (MD5), which moves in the CW direction until sensor detection, and CCW positioning movement (MD6), which moves in the CCW direction until sensor detection. Therefore, the performance control CPU 63 does not need to specifically grasp the sensor signal, and therefore the processing of step RT8 can be omitted.

In any case, next, the performance control CPU 63 sets up to 8 x 16 bits of control data MOSI that specifies the motor operation of motors MO3 and MO4 in the FIFO data register SCFTDR of serial port SIO_1 based on whether or not a motor performance is being performed by motors MO3 and MO4 (RT9). If a motor performance is being performed, control data for the performance rotation drive that achieves this is set in the FIFO data register SCFTDR, but if a motor performance is not being performed, control data for standby stop drive that suppresses the upper limit value NF in constant current control is set.

Once steps RT8 and RT9 have been completed, serial transmission processing of serial port SIO_1 begins (RT10). Figures 62(b) and 62(c) illustrate the steps for serially transmitting control data MOSI from serial port SIO_1 to motor controller 85.

First, Figure 62(b) is a time chart showing the output procedure when the enable signal ENABLE and the setting signal SET are output from the general-purpose output ports P2 and P3. As shown, by synchronizing with eight shift clocks SCK, and setting device numbers S7 to S6 = 00, operation type S5 to S4 = 10, and write target UZYX axes S3 to S0 = 0010 or S3 to S0 = 0001, it is specified that a control signal for the X axis (motor driver DV3) or Y axis (motor driver DV4) of the motor controller 85 with device number 00 is to be output.

Next, in synchronization with the next eight shift clocks SCK, a control signal for motor driver DV3 (or a control signal for motor driver DV4) is output. In this case, the operation of Figure 62(b) is repeated twice to complete the output of the X-axis and Y-axis control signals. As shown in Figure 59, of the general-purpose input/output ports, only port P2 (P2x terminal, P2y terminal) and port P3 (P3x terminal, P3y terminal) are set as output ports, so of the output data D7 to D0, the only significant data are D3 (= SET) and D2 (= ENABLE).

As explained above, in this embodiment, the upper current limit value NF of the constant current control is controlled in two stages: H level for rotational drive and L level for stop drive, depending on the H/L level of the setting signal SET. SET is controlled to H level during special effects performance, and SET is controlled to L level during performance standby.

Next, Figure 62(c) is a time chart explaining the process of sending commands that define the operation of the motor controller 85 and the process of setting operating parameters in the built-in registers. The various commands (CM1) to (CM4) that define the operation of the motor controller 85 are all 8-bit, so the processing in the upper part of Figure 62(c) is completed. That is, when sending a command, device numbers S7 to S6 = 00, operation types S5 to S4 = 00, and command target UZYX axes S3 to S0 = 00** are first serially sent in synchronization with eight shift clocks SCK, thereby notifying the user that a command will be sent to the X-axis (MO3) and/or Y-axis (MO4) of the motor controller 85 with device number 00.

Next, 8-bit command data is transmitted in synchronization with the following eight shift clocks SCK. If S3 to S0 = 0001, the command is for the X axis (MO3); if S3 to S0 = 0010, the command is for the Y axis (MO4); and if S3 to S0 = 0011, the command is for both the X and Y axes (MO3 + MO4).

The above explains command transmission, but when setting operating parameters in various registers, the processing in the lower section of Figure 62(c) is required following the upper section, since register numbers are 8 bits long and operating parameters are 16 bits long. Specifically, when setting operating parameters in registers, first, in synchronization with eight shift clocks SCK, device numbers S7-S6 = 00, operation types S5-S4 = 00, and command target UZYX axes S3-S0 = 00** are serially transmitted, thereby notifying the user that the register setting values for the X axis (MO3) and/or Y axis (MO4) of the motor controller 85 with device number 00 will be transmitted.

Next, an 8-bit register number is transmitted in synchronization with eight shift clocks SCK. Then, the setting value (16-bit operating parameter) for the register identified by the register number is serially transmitted in synchronization with 16 shift clocks.

The bottom part of Figure 63 shows the serial receive processing on serial port SIO_1, followed by the serial transmit processing. A total of 16*2 shift clocks SCK are required for serial receive of the X and Y axes, and 8*16 shift clocks SCK are required for serial transmission of the 8*16-bit control data MOSI. Therefore, when operating at a baud rate of 250 kbps, the processing time is 10*16/250 k = 0.645 mS, meaning that all processing is completed in about half the 1 mS timer interrupt cycle.

However, the performance control CPU 63 only starts the serial transmission process and ends it (R11), and does not wait for the serial transmission to be completed, so the processing of steps R7 to R11 is completed in an instant.

Figure 64 (a) shows stepping motors MO3 and MO4 driven by motor drivers DV3 and DV4, a spiral shaft BAR driven to rotate by the motors MO3 and MO4, a reel AMU on which a screw groove GV corresponding to the thread of the spiral shaft BAR is provided along with a guide groove, and a guide member GD that grips the guide groove GV of the reel AMU and guides the linear movement of the reel AMU.

The guide groove GV of the reel AMU is held by the guide member GD so that it can move linearly, and the reel AMU moves linearly in response to the rotation of the spiral shaft BAR. Here, the spiral shaft BAR and guide member GD are arranged on the left and right sides of the game board in a vertically concealed state, and the reel AMU is waiting in a concealed state at the top left and right of the game board in its origin position. In the illustrated example, the two reels AMU, AMU are separate and can move independently, but it is also preferable to connect the two reels.

As explained earlier, stepping motors MO3 and MO4 are both two-phase excited with a step angle θ of 7.5 degrees. Since 360/7.5=48, each motor MO3 and MO4 will rotate once upon receiving 48 stepping clocks CLK. Meanwhile, the rotational pitch of the spiral shaft BAR, which rotates in response to the rotation of motors MO3 and MO4, is 24 mm, and the reel AMU moves L=24 mm in response to one motor rotation.

Therefore, to achieve a travel distance of TOTAL [mm], the motor must rotate TOTAL/L = TOTAL/24 [times], and the number of steps of the stepping clock CLK required for this rotation is TOTAL/24 * 48 = TOTAL * 2. Here, if the pulse speed of the stepping clock CLK is PS [PPS: pulses per second], then the time required to output the number of steps TOTAL * 2 is TOTAL * 2/PS [seconds].

In this embodiment, the pulse speed PS of the stepping clock CLK can be stably output up to approximately 2900 pps. For example, when the pulse speed PS = 2900 pps, the time T [seconds] required to achieve a movement distance TOTAL [mm] is TOTAL * 2/PS = TOTAL/1450 [seconds]... (Equation 1). In this embodiment, the movement speed of the reel corresponding to a pulse speed PS = 2900 pps is 2900/48 * 24 = 1450 mm/s, which is greater than 1 m/s.

Free fall is independent of the weight of the object, and the relationship fall distance = 1/2 * g * ^t2 holds. Here, g = gravitational acceleration, and t = fall time. Therefore, for example, the time T required for a 30 cm free fall is 0.3 = 1/2 * g * T2, ^so T = SQR (0.6/9.8) ≒ 0.247 seconds. Here, assuming TOTAL = 300 mm, the travel time of the accessory AMU is calculated using the above formula 1 as TOTAL / 1450 ≒ 0.207 seconds. This confirms that, according to this embodiment, the accessory AMU can be moved at a higher speed than a free fall if the travel distance is approximately 30 cm. Note that the fall speed during free fall is 1 m/s when passing 51 cm.

Figure 64 (b) is a diagram illustrating an example of a motor effect using motor MO3 and/or motor MO4, showing the action of the reel AMU suddenly falling at a speed exceeding the free fall speed, bouncing back to a stop. This action consists of (1) a return-to-origin action, (2) a standby action, (3) a sudden drop action, (4) a bounce-up action, and (5) a bounce-down action.

First, for the origin return operation, an operation mode (MD6) in which the actuator moves in the CCW direction until the sensor detects the movement can be used, but here, an operation mode (MD4) in which the actuator moves for positioning in the CCW direction is used. Next, for the sudden drop operation, an operation mode (MD3) in which the actuator moves for positioning in the CW direction is used. Of course, an operation mode (MD5) in which the actuator moves in the CW direction until the sensor detects the movement can also be used.

In either case, the operating speed for the sudden drop operation (3) is set to 2900 pps, so the AMU reel moves at a speed faster than free fall. The number of pulses set in the pulse count register RWV is 600 pulses, and the total movement distance is 600/48*24=300 mm. Furthermore, trapezoidal drive is used, and by specifying a predetermined acceleration rate and deceleration rate, optimal acceleration and deceleration times are ensured. Therefore, problems such as step-out do not occur even when moving at high speeds.

The following bounce-up operation (4) and bounce-down operation (5) use an operation mode (MD4) for positioning movement in the CCW direction and an operation mode (MD3) for positioning movement in the CW direction. These operation speeds are low at around 500 pps, so rectangular drive is used, with each step count of 50 pulses, producing a bouncing movement of around 25 mm.

As described above, in this embodiment, by utilizing the motor controller 85, the control burden on the performance control CPU 63 is reduced and complex, advanced motor performances are possible. Furthermore, even when the props are moved at high speed, by ensuring sufficient acceleration and deceleration times, problems such as loss of synchronization can be prevented.

However, the motor drivers DV3 and DV4 used in this embodiment have a circuit configuration as shown in Figure 57 for their VREFA and VREFB terminals, so unlike the motor drivers DV1 and DV2, the upper limit value NF of the output current Iout cannot be controlled in multiple stages. On the other hand, because an upper limit current setting circuit LMT is provided, the upper limit current NF can be controlled at any timing by controlling the electronic switch SW to turn ON/OFF using a 1-bit setting signal SET (see Figure 57).

In this embodiment, the upper limit current NF is set to H level (473 mA) only when motors MO3 and MO4 are performing special effects, and in other standby states, the electronic switch SW is set to OFF, maintaining the upper limit current NF at L level (102 mA).

In another embodiment, unnecessary power consumption is reduced by appropriately controlling the upper limit current NF even during the performance of the special feature. Specifically, the environment setting register RENV of the motor controller 85 is used to execute the countdown control shown in Figure 60 (d). As explained above, the environment setting register RENV is configured to allow the count-up time TCUP and the count-down time TCDW to be set.

In this embodiment, when a start command is issued, the setting signal SET transitions to H level, the upper limit current NF is set to H level (473 mA), the count-up time TCUP is set, and the TCUP count-down operation begins. The motor controller 85 is configured so that the start command is not executed until the count-down operation is complete, and begins outputting a series of pulses after a specified waiting time (count-down time) has elapsed.

Meanwhile, in response to the issuance of the start command, the setting signal SET immediately transitions to H level, causing the corresponding stepping motors MO3/MO4 to transition from the standby mode with a low upper limit current NF to a drive mode with a high upper limit current NF. However, since a new stepping clock CLK has not yet been output at this timing, motors MO3/MO4 remain stopped, but their drive in the stopped state transitions from low current drive to high current drive (see Figure 58 (c)).

Then, when a new stepping clock CLK is output, motors MO3/MO4 will rotate stepwise in a stable, high-current drive state. A specified level of output torque is always required when rotation begins, but in this embodiment, high-current drive is initiated in advance, so there is no shortage of output torque, and even devices with large inertia can be started smoothly.

After that, when motors MO3/MO4 have completed their specified rotational operation, a stop command is issued. In response to this, the countdown time TCDW in the environment setting register RENV is set and the TCDW countdown operation begins. The performance control CPU 63 then reads and accesses the environment setting register RENV every 1 ms, and once it has confirmed that the TCDW countdown operation has ended, it transitions the setting signal SET to L level and reduces the upper limit current NF to L level (102 mA). It is also preferable to start an interrupt process in response to the end of the TCDW countdown operation; in this case, there is no need to read and access the environment setting register RENV every 1 ms.

In any case, the above countdown control is intended to reliably stabilize the stopped state even when the inertia of the reel is large, and by stopping and driving the motor at a high current for a predetermined period of time, the stopped state of the reel is stabilized. Since the countdown control is primarily performed to absorb the inertia of the reel AMU, the count-up time TCUP and count-down time TCDW set in the environment setting register RENV are set appropriately according to the weight of the reel AMU, etc. Furthermore, instead of the above method of setting the count-up time TCUP in response to a start command, the count-up time TCUP can also be set before the start command is issued. In this case, the output of the stepping clock CLK will begin in response to the issuance of the start command.

The above describes an embodiment of the present invention, but the specific description does not particularly limit the present invention. For example, the CPU circuit 51 may directly control the drivers DV3 and DV4 without going through the motor driver 85. Also, while Figure 63 describes an example in which the reel AMU moves linearly in response to the rotation of the spiral shaft BAR, this is not limited to this, and a transmission mechanism using a rack, which is a circular gear, and a pinion, which is a flat material that meshes with the circular gear, may also be used. Furthermore, the movement of the reel is not necessarily limited to linear movement. The reel may be rotated, or non-linear reciprocating movement of the reel, such as reciprocating movement along an arc trajectory, is also suitable.

Furthermore, while trapezoidal drive, which has acceleration and deceleration times and is suitable for high-speed operation, and constant-speed operation (rectangular drive) with instant start and instant stop, which is suitable for low-speed operation, have been described, this is not particularly limited. For example, constant-speed start operation with zero acceleration time, and instant stop operation with zero deceleration time are also suitable. Furthermore, while trapezoidal drive involving the motor controller 85 has been described, for example, in the configuration of Figure 50(b), the performance control CPU 63 may execute trapezoidal drive in addition to rectangular drive. The same applies to constant-speed start operation and instant stop operation.

The above explains how to use a stepping motor to create special effects. However, depending on the type of gaming machine, there may be cases where you want to create a preview effect in which the rod-shaped special effect vibrates finely up, down, left, and right. In such cases, it is possible to use a cam material to make the rod-shaped special effect move back and forth, but as long as a cam material is used, it is not possible to create a variety of preview effects that change the vibration amplitude or vibration intensity of the rod-shaped special effect.

In the example shown in Figure 65, a brushed DC motor MOa and a rack and pinion mechanism are used to create a preview effect in which a rod-shaped device rotates back and forth. Here, the DC motor MOa is driven by a motor driver DV5, the internal configuration of which is shown in Figure 52, and the vibration amplitude and intensity can be changed as desired, as described below.

Note that Figure 65(b) shows a rack RA that rotates synchronously with the DC motor MOa, and a pair of pinions PN1, PN2 that mesh with the rack RA and move linearly, but of course a single pinion PN1 would suffice. Also, as shown in Figure 65(a), the motor driver DV5 can drive not only the DC motor MOa, but also the DC motor MOb.

However, the following describes an embodiment in which the motor driver DV5 drives only the DC motor MOa, and the pair of pinions PN1, PN2 reciprocates based on a single rack RA.

Motor driver DV5 has the internal configuration shown in Figure 52(a) and performs constant current control with a constant current control period of approximately 8 to 12 μS (see Figure 54(a)). This motor driver DV5 operates in two-phase excitation mode or one-two-phase excitation mode, outputting drive pulses OUT_A ± from the Bridge A circuit shown in Figure 52(d) and drive pulses OUT_B ± from the Bridge B circuit shown in Figure 52(e).

Figure 66 explains the circuit configuration of the Bridge A circuit and the 1-2 phase excitation mode. As shown in Figure 66(a), the four transistors that make up the Bridge A circuit are divided into P-type MOS transistors U1 and U2 and N-type MOS transistors L1 and L2, forming an H-bridge circuit.

The source terminals S of P-type transistors U1 and U2 are connected to the source terminals S of N-type transistors L1 and L2, and a drive power supply (35 V) is supplied to the drain terminals D of P-type transistors U1 and U2, with the drain terminals D of N-type transistors L1 and L2 at ground potential. Furthermore, body diodes Db are formed from the source terminals S to the drain terminals D of P-type transistors U1 and U2, and body diodes Db are formed from the drain terminals D to the source terminals S of N-type transistors L1 and L2.

Figure 66 (f) is a time chart showing the transition of the drive current Iout (A) to the DC motor MOa. The operating state transitions at predetermined reference time intervals (τ), achieving 1-2 phase excitation. Note that the reference time τ is at least 1 ms (see Figure 63). However, in this embodiment, the reference time τ is set to an integer multiple N of 1 ms (τ = N milliseconds) to ensure smooth reciprocating motion of the DC motor.

First, let's explain the CW rotation operation state 11. As shown in Figure 66(b), the motor driver DV5 appropriately turns on/off four transistors to constant-current control the rightward drive current Iout (A), causing the DC motor MOa to rotate in the clockwise (CW) direction. During this CW rotation, the motor driver DV5 executes constant-current control defined by a predetermined current upper limit NF, and the drive current repeatedly cycles through CHARGE operation → SLOW discharge operation → FAST discharge operation (see Figure 54(a)).

After the above constant current control continues for three reference times (= 3 * τ), the operating state transitions to the stopped operating state 00 shown in Figure 66(c). As shown in Figure 66(c), in the stopped operating state 00, all transistors L1, L2, U1, and U2 are turned off, and the charging current of the motor coil is fast discharged via the path shown. In other words, the regenerative current flows via the body diodes Db of transistors L1 and U2, and the DC motor MOa quickly comes to a stop.

Then, after the stop operation state 00, which lasts for a reference time (τ), the state transitions from Figure 66(c) to Figure 66(d), where the drive current Iout (A) becomes < 0. In this CCW rotation operation state 10, the drive current flows to the left in Figure 66(d), causing the DC motor MOa to rotate in the counterclockwise (CCW) direction. Even during this CCW rotation, the motor driver DV5 executes constant current control defined by a predetermined current upper limit value NF (see Figure 54(a)).

After this constant current control continues for three reference times (= 3 * τ), the operating state transitions from CCW rotation operating state 10 in Figure 66(d) to stopped operating state 01 in Figure 66(e). As shown in Figure 66(e), even in stopped operating state 01, all transistors L1, L2, U1, and U2 are turned off, and the charging current of the motor coil is fast discharged via the path shown, quickly bringing the DC motor MOa to a stopped state.

Then, after the stop operation state 01, which lasts for a reference time (= τ), it transitions again to the CW rotation operation state 11 in Figure 66 (b). This process continues in the same way, and ultimately the brushed DC motor MOa repeats the following rotational operation: CW rotation 11 (rotation time 3 * τ) → stop 00 (stop time τ) → CCW rotation 10 (rotation time 3 * τ) → stop 01 (stop time τ) → CW rotation 11 (rotation time 3 * τ) → ... In other words, the brushed DC motor MOa rotates back and forth for a rotation time of 3 * τ, and in response to this rotation, the pinions PN1 and PN2 perform linear reciprocating motion together with the rod-shaped accessories integrated with them.

Figure 66 (f) shows the transition of the drive current Iout (A), whose level changes between positive and negative as the operating state transitions every reference time (τ). As shown in the figure, the rotation time in the CW direction is 3 reference times (3 * τ), followed by a pause of 1 reference time (τ) before transitioning to CCW rotation for 3 reference times (3 * τ).

Therefore, if the reference time τ is set long, the rotation angle of the DC motor MOa increases, thereby increasing the amplitude of the reciprocating motion. Conversely, if the reference time τ is set short, a micro-vibration with a narrow amplitude is achieved. As explained above, the positive and negative current upper limit ±NF of the drive current Iout (A) can be changed in 16 steps within the range of 0% to 100%.

Figure 67 illustrates the control data SDATA, shift clock SCK, and stepping clock LATCH output from the CPU circuit 51 to achieve the reciprocating rotation operation described above. Note that Figure 67 also illustrates drive current Iout(B) in addition to drive current Iout(A), but in this embodiment, drive current Iout(B) is not used. Furthermore, the stepping clock LATCH can be output at the shortest interval of 1 mS, but here, as explained above, it is output every reference time (= τ) that is an integer multiple of 1 mS.

As explained in Figure 56, the control data SDATA consists of a 4-bit torque (upper limit current) setting value and a 4-bit PHASE setting value. Here, the torque setting value is nothing more than the upper limit current value NF in constant current control, and can be set in 16 steps from 0 to 100% (15 steps excluding 0). However, in Figure 67, for convenience of drawing, the torque setting value is standardized to 100%.

To achieve 1-2 phase excitation, the CPU circuit 51 must output the following binary values as the PHASE setting value (= control value for B and A phases): 1111 → 1100 → 1110 → 0010 → 1010 → 1001 → 1011 → 0111 → 1111. However, in this embodiment, the B phase drive current Iout(B) is not an issue, so only the A phase control value, 11 → 00 → 10 → 10 → 10 → 01 → 11 → 11 → 11..., is significant.

Here, the control value 11 realizes the CW rotation operation state 11 in Figure 66(b), the control value 00 realizes the stopped state 00 in Figure 66(c), the control value 10 realizes the CCW rotation operation state 10 in Figure 66(d), and the control value 01 is control data for realizing the stopped state 01 in Figure 66(e). Each time the stepping clock LATCH is received, each control data (A-phase control value) is executed and the DC motor MOa performs stepping operation.

The upper limit ±NF of the positive and negative values of the drive current Iout (A) can be changed in 15 steps, excluding 0, within the range of 0% to 100%. The significance of this will be explained below. First, considering a normal brushed DC motor, the Fleming force generated by passing a motor coil current I through a magnetic field is proportional to the current value I. Meanwhile, when the motor coil rotates based on this Fleming force, a back electromotive force E proportional to the rotational speed V is generated.

When a DC motor is driven at a constant voltage, the relationship VB = r*I + L*(dI/dt) + E holds between the drive DC voltage VB, coil inductance L, coil loss resistance r, coil current I, and back electromotive force E. In other words, when the coil current I increases and the rotational speed V increases, the back electromotive force E also increases accordingly, and a predetermined equilibrium point is reached between the coil current I and the rotational speed V, at which point the rotational speed V and the coil current I each become constant. When the coil current becomes constant, L*(dI/dt) = 0, and so the relationship VB = r*I + E holds.

However, in this embodiment, the DC motor MOa is driven at a constant current rather than at a constant voltage, so as long as this constant current control functions effectively, the above-mentioned equilibrium point does not occur. Furthermore, with constant current control, the coil current I is constant, so the Fleming force is also constant, achieving uniform acceleration motion with a constant acceleration α.

That is, in the configuration of this embodiment, the rotation speed V increases with the passage of time t, as shown in Figure 67(c). Here, the acceleration α in the equation V = α * t is proportional to the upper current limit value NF of constant current control. Furthermore, the movement distance L of the operating point that realizes the rotation speed V is L = 1/2 * α * ^t2 , as shown in Figure 67(d).

Based on the above, when we consider the drive current Iout (A) shown in Figure 67 (b), we can see that the acceleration α is proportional to the motor drive current I (current upper limit NF), so the higher the current upper limit NF, the more vigorously the reel will move back and forth.

Furthermore, since the movement distance of the reel is proportional to the acceleration α and also to the square of the travel time t for the forward and return trips, increasing the current upper limit NF and setting a long reference time τ will cause the reel to move back and forth at high speed over a large range of movement. On the other hand, if the current upper limit NF is increased by M times while the reference time τ is increased by 1/ ^M2 , a strong vibration can be achieved that moves back and forth over the same range of movement at high acceleration. For example, if the current upper limit NF is increased by four times and the reference time τ is reduced by half, a fourfold stronger vibration can be achieved for the same movement range.

On the other hand, the shorter the reference time τ, the smaller the amplitude of the reel, resulting in micro-vibrations. In this case, the torque (acceleration α) fluctuates in response to the upper current limit value NF, making it possible to achieve both strong and weak micro-vibrations.

As described above, by driving the brushed DC motor MOa with the motor driver DV5, which bipolarly drives the stepping motor, the rod-shaped prop can be moved back and forth at any amplitude and torque, enabling a wide variety of prop performances. Furthermore, by fixing a rod-shaped member to the rotation axis of the DC motor MOa, it is possible to realize a prop performance in which the rod-shaped prop oscillates at any amplitude and torque (see Figure 65 (c)).

Up to this point, we have mainly been talking about 1-2 phase excitation, but of course 2-phase excitation as shown in Figures 56 and 58(a) can also be used. In the case of 2-phase excitation, there is no pause as in Figures 66(c) and 66(e), and the CW rotation operation state 11 shown in Figure 66(b) and the CCW rotation operation state 10 shown in Figure 66(d) are repeated without pause. The control operation of the CPU circuit 51 is as shown in Figure 56.

The operation of two-phase excitation is shown in a time chart in Figure 67(e). With two-phase excitation, there is no pause between forward and backward movement, so the operating period of the reciprocating motion is four times the reference time τ (= 4 * τ). In other words, with two-phase excitation, the operating period of the reciprocating motion is half that of 1-2 phase excitation (= 8 * τ), allowing for faster reciprocating motion. Therefore, for example, to achieve micro-vibrations, two-phase excitation should be used rather than one-two phase excitation.

The above describes an embodiment in which the DC motor MOa rotates back and forth, but this is not particularly limited. For example, as shown in Figure 68(a), when using a cam member that is rotationally driven by the DC motor MOa and a rod-shaped accessory (vibrator) that is biased toward the cam member, it is sufficient to rotate the DC motor MOa continuously in one direction.

In this embodiment, for example, the vibration of the rod-shaped device is achieved by continuing the clockwise rotation shown in Figure 66(b). Figure 68(d) shows an operating state in which the torque setting NF, set to one of 15 levels, and the PHASE setting (11) indicating the clockwise rotation operating state shown in Figure 66(b), are activated by the stepping clock LATCH at timing t1, after which the clockwise rotation continues.

This vibration effect continues for, for example, 5 to 10 seconds, after which, at an appropriate timing, control data SDATA with a torque setting of NF=0 and a PHASE setting of 11 is sent. This control data is then executed by the stepping clock LATCH at timing t2, causing the DC motor to stop. Note that a torque setting of NF=0 means that the generated torque is zero; however, instead of setting NF=0, all transistors can be controlled to an OFF state. Specifically, this can be achieved by, for example, changing the SCLR terminal or STANDBY terminal to an L level. However, since controlling the STANDBY terminal to L will stop the built-in OSC circuit (Motor Oscillator) and output circuits (Bridge A/Bridge B), the STANDBY terminal must be returned to H for subsequent motor effects to occur.

In general, with a DC motor, there is a proportional relationship between the motor drive current and the generated torque, as shown in Figure 68(b). However, in this embodiment, the generated torque is uniquely controlled by constant current control of the motor drive current.

With this configuration, for example, in a preview performance using vibration effects, the vibration intensity of the reel can be changed by changing the torque setting value NF depending on the reliability. In this case, it is not necessary to maintain the vibration intensity at a constant value in one vibration performance, and the vibration intensity can also be changed over time. For example, in the operation example of Figure 68(e), the vibration performance starts at timing t1, and then the vibration is strengthened at timing t2, and further strengthened at timing t3.

As described above, this embodiment, which uses constant current control of the DC motor, can realize vibrations of any intensity, thereby increasing the variety of device effects. Furthermore, this configuration allows players to select whether or not to enable vibration effects and the vibration level during gameplay to suit their preferences, and the vibration effects and vibration level can also be initially set during initial setup after power-on to suit the preferences of the gaming hall.

In addition, the upper limit NF of the motor drive current is constant and does not increase in response to torque, so there is no risk of the coil windings burning out due to overheating. In other words, even if a player strongly restrains the vibrator, the drive current does not increase to increase torque, as with a normal DC motor, so there is no risk of overheating.

Incidentally, the vibration effects in this embodiment are performed using constant current control, so motor rotation accelerates over time, as shown in Figure 68 (c). The acceleration α is also proportional to the current value, so the higher the upper limit NF of the motor drive current, the greater the acceleration α and the faster the vibration, which also contributes to a more powerful role-playing effect. The vibration preview ends after, for example, 5 to 10 seconds, so even if the upper limit NF is set to a high torque setting of 100%, the DC motor rotation will not exceed its limit and speed up.

GM MOa DC Motor DV5 Driver

Claims (1)

A gaming machine provided with a driver that rotates a DC motor (excluding a stepping motor) based on a motor control signal received from an external device, and a device that moves in response to the rotation of the DC motor,
The gaming machine is characterized in that, in a driving operation state in which the DC motor should be rotated continuously in the same direction, the driver is configured to continuously execute constant current control without interruption , which repeats increasing control of the coil current of the DC motor toward an upper limit value specified by the motor control signal and decreasing control toward a decrease value (>0) lower than the upper limit value.