JP7765262B2 - Semiconductor optical element and its manufacturing method - Google Patents

Description

This disclosure relates to a semiconductor optical device and a manufacturing method thereof.

In semiconductor optical devices, a buried heterostructure (BH) structure is known in which semiconductor buried layers (BH) are provided on both sides of the mesa stripe structure to suppress lateral current diffusion and increase the relaxation oscillation frequency. Also known is a structure in which only the portion containing the multi-quantum well (MQW) is buried, rather than burying the entire mesa stripe structure, thereby increasing the optical confinement factor of the MQW (Patent Documents 1, 2, and 3).

The semiconductor optical device disclosed in Patent Document 2 has a two-tiered structure consisting of a lower mesa structure including an MQW and an upper mesa structure including a diffraction grating layer, etc. Because the upper mesa structure is wider than the lower mesa structure, the bottom surface of the upper mesa structure is exposed from the lower mesa structure.

JP 2013-165133 A JP 2018-56212 A Japanese Patent Application Laid-Open No. 2021-27310

When MOCVD (Metal Organic Chemical Vapor Deposition) is used to form the burying layer, crystals grow not only from the substrate, but also from the exposed bottom surface of the upper mesa structure. Crystal defects and voids can occur at the interface between crystals grown in different directions, resulting in a deterioration in the crystal quality of the burying layer and potentially leading to reduced reliability and performance of the semiconductor optical device.

The purpose of this disclosure is to prevent degradation of the crystalline quality of the buried layer.

The semiconductor optical device has a lower mesa structure extending in a stripe shape and consisting of multiple layers including an active layer, buried layers made of indium phosphide that embed both sides of the lower mesa structure, and an upper mesa structure extending in a stripe shape and consisting of multiple layers including a bottom layer made of a material that does not contain phosphorus, the bottom layer having a bottom surface that protrudes from the top layer of the lower mesa structure and the bottom surface being in contact with the lower mesa structure and the buried layer.

A method for manufacturing a semiconductor optical device includes the steps of: forming a mesa stripe structure having a lower mesa structure consisting of multiple layers extending in a stripe shape and including an active layer; and an upper mesa structure consisting of multiple layers extending in a stripe shape on top of the lower mesa structure and including a bottom layer, the bottom layer having a bottom surface protruding from the top layer of the lower mesa structure and made of a material that does not contain phosphorus; and, after forming the mesa stripe structure, forming buried layers made of indium phosphide by crystal growth on both sides of the lower mesa structure so that they are in contact with the bottom surfaces.

1 is a plan view of a semiconductor optical device according to a first embodiment. 2 is a cross-sectional view of the semiconductor optical device shown in FIG. 1 taken along line II-II. 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor optical device. FIG. 10 is a cross-sectional view of a semiconductor optical device according to a second embodiment. FIG. 10 is a plan view of a semiconductor optical device according to a third embodiment. 6 is a cross-sectional view of the semiconductor optical device shown in FIG. 5 taken along the line VI-VI.

Embodiments of the present invention will be specifically and in detail explained below with reference to the drawings. Components with the same reference numerals throughout the drawings have the same or equivalent functions, and repeated explanations will be omitted. Note that the size of the figures does not necessarily correspond to the magnification.

[First embodiment]
FIG. 1 is a plan view of a semiconductor optical device according to a first embodiment. FIG. 2 is a cross-sectional view of the semiconductor optical device shown in FIG. 1 taken along line II-II. The semiconductor optical device is a semiconductor laser. The semiconductor optical device has an upper electrode 10 and a lower electrode 12 on its upper and lower surfaces, respectively, and a voltage is applied (current is injected) between them. This allows laser light to be emitted from the end facet of the mesa stripe structure 14, for example, in the 1.3 μm or 1.55 μm band. A non-reflective coating film 16 made of a dielectric is formed on the end facet on the emission side. A highly reflective coating film 18 made of a dielectric is formed on the end facet on the opposite side.

The semiconductor optical device has a substrate 20 made of indium phosphide (InP). A buffer layer 22 (lower cladding layer) made of InP is layered on the substrate 20. A portion of the upper electrode 10 is located above the buffer layer 22. As a result, parasitic capacitance occurs between the upper electrode 10 and the buffer layer 22. Increasing the distance between the upper electrode 10 and the buffer layer 22 can be considered to reduce the parasitic capacitance. Note that the buffer layer 22 may be omitted.

[Mesa stripe structure]
The semiconductor optical device has a mesa stripe structure 14. At least a portion of the upper electrode 10 is on the mesa stripe structure 14. A portion of the buffer layer 22 is included in the mesa stripe structure 14 as a protruding portion. In other words, the upper surface of the buffer layer 22 is lower in the regions other than the protruding portions. The mesa stripe structure 14 has a stacked structure of at least two stages with different widths. The mesa stripe structure 14 includes, in order from the side closest to the buffer layer 22, a lower mesa structure 24 and an upper mesa structure 26 that is wider than the lower mesa structure 24.

[Lower mesa structure]
The lower mesa structure 24 extends in a stripe shape. The lower mesa structure 24 is composed of multiple layers. The lower mesa structure 24 is configured by stacking, in order from the side closest to the buffer layer 22, a lower SCH (Separate Confinement Heterostructure) layer 30, an active layer 28, an upper SCH layer 32, and a top layer 34. The active layer 28 may be MQW or bulk. The top layer 34 of the lower mesa structure 24 is made of InP, the same as the buffer layer 22. Note that the lower SCH layer 30, the active layer 28, and the upper SCH 32 have thicknesses sufficient to ensure optical characteristics, so it is difficult to change their thicknesses for other purposes.

The 3 dB bandwidth of a directly modulated semiconductor laser is limited to 1.55 fr by the relaxation oscillation frequency fr of the laser, so increasing the relaxation oscillation frequency fr is necessary to increase the speed. In a semiconductor laser having an MQW as the active layer 28, the relaxation oscillation frequency fr, the optical confinement factor per quantum well Γ _QW , the width W _a of the active layer 28, and the drive current I _m have the following relationship: Here, the drive current I _m is the current obtained by subtracting the threshold current from the injection current.

Therefore, reducing the width W _a of the active layer 28 increases the value of the optical confinement factor Γ _QW /W _a , increases the relaxation oscillation frequency fr, and improves the bandwidth f3 dB.

[Upper mesa structure]
The upper mesa structure 26 extends in a stripe shape. The upper mesa structure 26 is made of multiple layers. A bottom layer 36 of the upper mesa structure 26 is made of a material that does not contain phosphorus (P) (e.g., InGaAlAs, InAlAs, InGaAs). The bottom layer 36 has a bottom surface that protrudes from the top layer 34 of the lower mesa structure 24. The bottom surface is in contact with the lower mesa structure 24. An upper cladding layer 38 made of InP and a contact layer 40 are provided above the bottom layer 36.

[Embedding layer]
Both sides of the lower mesa structure 24 are buried with a burying layer 42. From the viewpoints of crystallinity and stress, the burying layer 42 is preferably made of the same material as the substrate 20. The burying layer 42 is made of InP. The burying layer 42 may be p-type InP, n-type InP, high-resistivity InP doped with Fe or Ru, or a stack of materials selected from the group consisting of p-type InP, n-type InP, and high-resistivity InP. The base of the burying layer 42 (the buffer layer 22 on the substrate 20) is also made of InP.

The burying layers 42 are disposed on both sides of the lower mesa structure 24, but are not adjacent to the upper mesa structure 26. In such a structure, if the width of the portion not buried with the burying layers 42 (the upper mesa structure 26) is made larger than the width of the active layer 28, the value of the optical confinement factor Γ _QW /W _a increases, leading to an increase in the relaxation oscillation frequency fr and an improvement in the bandwidth f3 dB.

As described above, the buffer layer 22 has a lower upper surface in areas other than the protrusions (part of the mesa stripe structure 14), and the buried layer 42 is thicker above those areas. If the buried layer 42 is semi-insulating, the distance between the upper electrode 10 and the buffer layer 22 above it increases, reducing parasitic capacitance.

The bottom surface (edge) of the bottom layer 36 of the upper mesa structure 26 contacts the buried layer 42. The buried layer 42 is thickest at the portion that contacts the bottom surface of the bottom layer 36 of the upper mesa structure 26. The portion of the buried layer 42 that contacts the bottom surface of the bottom layer 36 forms a convex portion.

For example, if the buried layer 42 is made of Fe-InP, the dopant contained in the lower SCH layer 30 or upper SCH layer 32 will interdiffuse with Fe. As a result, the buried layer 42 will effectively become a thin, high-resistance layer (semi-insulating layer) in the portion adjacent to the lower mesa structure 24, which can increase parasitic capacitance. Therefore, by making the buried layer 42 thicker on both sides of the lower mesa structure 24 than in other regions, the effect of increased parasitic capacitance can be suppressed. This effect is achieved by the fact that the bottom layer 36 of the upper mesa structure 26 is wider than the top layer 34 of the lower mesa structure 24.

[Insulating layer]
The side surfaces of the upper mesa structure 26 and the top surface of the buried layer 42 are covered with an insulating layer 44. The insulating layer 44 is made of, for example, _SiO2 . The upper electrode 10 is located on the surface of the insulating layer 44. The insulating layer 44 has an opening or slit above the upper mesa structure 26, and the upper electrode 10 is electrically and physically connected to the contact layer 40.

The insulating layer 44 has a contact surface with the buried layer 42. The contact surface is located lower than the bottom surface of the bottom layer 36 of the upper mesa structure 26. The insulating layer 44 does not contact the top layer 34 of the lower mesa structure 24. A portion of the buried layer 42 is interposed between the top layer 34 of the lower mesa structure 24 and the insulating layer 44.

[Method of manufacturing semiconductor optical device]
3A to 3G are diagrams illustrating a method for manufacturing a semiconductor optical device. The method for manufacturing a semiconductor optical device includes forming a mesa stripe structure 14. Forming the mesa stripe structure 14 includes forming multiple layers (FIG. 3A). The buffer layer 22 that underlies the multiple layers is made of InP. If the buffer layer 22 is omitted, the substrate 20 made of InP serves as the underlayer. From the multiple layers, the upper mesa structure 26 and the lower mesa structure 24 shown in FIG. 2 are formed.

[Multilayer formation]
The multilayer structure is formed in one continuous step or in multiple steps using metalorganic chemical vapor deposition (MOCVD). The multilayer structure includes a layer 30A that will become the lower SCH layer 30, a layer 28A that will become the active layer 28, a layer 32A that will become the upper SCH layer 32, a layer 34A that will become the top layer 34 of the lower mesa structure 24, a layer 36A that will become the bottom layer 36 of the upper mesa structure 26, a layer 38A that will become the upper cladding layer 38, and a layer 40A that will become the contact layer 40. The layer 30A that will become the lower SCH layer 30 and the layer 32A that will become the upper SCH layer 32 are formed from InGaAsP, InGaAlAs, or InAlAs. The layer 28A that will become the active layer 28 is formed from a quaternary system such as InGaAsP or InGaAlAs. The layer 34A that will become the top layer 34 of the lower mesa structure 24 is formed from InP. A layer 36A that will become the bottom layer 36 of the upper mesa structure 26 is formed from a material that does not contain phosphorus (P) (for example, InGaAlAs).

A first coating film 46 is formed on the multilayer along the mesa stripe structure 14 (optical axis direction). Here, the first coating film 46 is made of _SiO2 . The first coating film 46 is formed in a region corresponding to the upper mesa structure 26 (FIG. 2).

[Formation of upper mesa structure]
3B, etching is performed on the stacked layers that will become the upper mesa structure 26 and the layer 34A that will become the top layer 34 (FIG. 2) of the lower mesa structure 24. By etching using the first coating film 46 as a mask, the stacked layers that will become the upper mesa structure 26 and the layer 34A that will become the top layer 34 of the lower mesa structure 24 are removed, leaving behind a region that corresponds to the upper mesa structure 26. In this way, the upper mesa structure 26 is formed.

[Formation of Etching Mask]
3C, a second coating film 50 is overlaid on the first coating film 46 remaining after the previous etching. The second coating film 50 covers the top and side surfaces of the upper mesa structure 26, covers the side surfaces of the layer to be etched 34B that will become the top layer 34 of the lower mesa structure 24, and covers the top surface of layer 32A that will become the second layer (upper SCH 32) of the lower mesa structure 24. The top surface of the upper mesa structure 26 is thick because the first coating film 46 and the second coating film 50 overlap, but is thin in other regions because only the second coating film 50 is formed.

3D, the first coating film 46 and the second coating film 50 are etched to form an etching mask 48. The etching mask 48 covers the region corresponding to the upper mesa structure 26. Here, the etching mask 48 is made of _SiO2 .

When anisotropic dry etching is performed in the vertical direction on the stacked first coating film 46 and second coating film 50, etching progresses on the horizontal surfaces, removing the second coating film 50 but leaving the first coating film 46. The etching mask 48 formed in this way covers the top and side surfaces of the upper mesa structure 26 and the side surfaces of the etched layer 34B, which will become the top layer 34 of the lower mesa structure 24, exposing other areas.

The etching mask 48 has a flared shape (eaves shape) in the portion adjacent to the side of the layer to be etched 34B, which will become the top layer 34 of the lower mesa structure 24. This can be formed by patterning using a stepper or electron beam lithography system followed by anisotropic dry etching. Alternatively, it can be formed by controlling the film thickness of the second coating film 50.

[First selective etching]
3E, first selective etching (e.g., wet etching) is performed through the etching mask 48. In the first selective etching, etching reaction with respect to the top layer 34 of the lower mesa structure 24 is suppressed, while etching proceeds with respect to stacked layers that become layers other than the top layer 34 of the lower mesa structure 24. The first selective etching is performed so that a region corresponding to the lower mesa structure 24 remains.

Specifically, layer 30A, which will become the lower SCH layer 30, layer 28A, which will become the active layer 28, and layer 32A, which will become the upper SCH layer 32, are selectively etched. This allows the layers below the top layer 34 of the lower mesa structure 24 to be formed with a width narrower than that of the upper mesa structure 26. The width is determined by the etching time. The height of the etched portion is the distance between the layers of material that suppress the etching reaction (buffer layer 22 and layer to be etched 34B).

The buffer layer 22 is hardly etched. The layer to be etched 34B, which forms the top layer 34 of the lower mesa structure 24, is also hardly etched, and therefore the bottom layer 36 of the upper mesa structure 26 is also not etched. The layer to be etched 34B functions to prevent any effect on the shape of the upper mesa structure 26. As a result, a semiconductor optical device with excellent reliability and characteristics can be realized.

[Second Selective Etching]
3F, second selective etching is performed through the etching mask 48. In the second selective etching, the etching reaction with respect to the lowermost layer 36 of the upper mesa structure 26 is suppressed, while etching proceeds with respect to the layer to be etched 34B that will become the uppermost layer 34 of the lower mesa structure 24. The second selective etching is performed so as to leave a region corresponding to the lower mesa structure 24. In the second selective etching, the multi-layered underlying layer is etched.

For example, wet etching is performed using an aqueous solution (e.g., a mixture of hydrochloric acid, phosphoric acid, and water) that selectively etches InP. This etches the buffer layer 22 and the layer to be etched 34B, which will become the top layer 34 of the lower mesa structure 24. Here, the bottom layer 36 of the upper mesa structure 26 is made of a material that does not contain phosphorus (P) as a constituent element. Therefore, the etching stops at the boundary between the top layer 34 of the lower mesa structure 24 and the bottom layer 36 of the upper mesa structure 26, and the upper mesa structure 26 is not etched. Through the above process, a mesa stripe structure 14 including the upper mesa structure 26 and the lower mesa structure 24 is formed.

[Formation of buried layer]
3G, after the mesa stripe structure 14 is formed, the buried layer 42 is formed on both sides of the lower mesa structure 24 so as to contact the bottom surface of the bottom layer 36 of the upper mesa structure 26. The formation is performed by crystal growth (e.g., MOCVD).

Crystal growth is performed with the upper mesa structure 26 covered with a patterning mask 52, except for its bottom surface. Here, the etching mask 48 described above is left intact and used as the patterning mask 52. The patterning mask 52 protrudes beyond the bottom surface along the side of the upper mesa structure 26. The patterning mask 52 protrudes away from the top layer 34 of the lower mesa structure 24 at a distance from the top layer 34.

In this embodiment, while InP grows from the surface of the buffer layer 22, the bottom layer 36 of the upper mesa structure 26 is made of a material that does not contain phosphorus (P) as a constituent element, so InP does not grow from its bottom surface. Therefore, no crystal defects or cavities occur in the buried layer 42, resulting in excellent reliability and performance. Even if phosphorus is not included in the elements that make up the lower SCH layer 30, active layer 28, and upper SCH layer 32, InP still grows on the side surfaces due to the crystal plane relationship.

This embodiment is particularly effective when the buffer layer 22 (or the substrate 20 if there is no buffer layer 22), the top layer 34 of the lower mesa structure 24, and the buried layer 42 are made of the same material (InP). Here, "same material" does not include differences in guest materials (e.g., dopants), but rather means that the host material (basic material) is the same.

[Formation of insulating layer and subsequent steps]
The patterning mask 52 is removed, and then an insulating layer 44 is formed to cover the top and side surfaces of the upper mesa structure 26 and the top surface of the burying layer 42 (FIG. 2). Then, a portion of the insulating layer 44 is removed from the top surface of the upper mesa structure 26 to expose the top surface of the contact layer 40, and an upper electrode 10 is formed by vapor deposition. The upper electrode 10 is electrically and physically connected to the contact layer 40. A lower electrode 12 is also formed by vapor deposition on the bottom side of the substrate 20. In this manner, the semiconductor optical device is completed.

Second Embodiment
4 is a cross-sectional view of a semiconductor optical device according to the second embodiment. The semiconductor optical device may be any of a DFB (Distributed Feedback) laser, a DBR (Distributed Bragg Reflector) laser, and a DR (Distributed Reflector) laser. A p-type InP buffer layer 222 is stacked on a substrate 220 made of p-type InP.

The lower mesa structure 224 is composed of a p-type lower SCH layer 230, an active layer 228 which is an MQW made of undoped strained InGaAlAs, an n-type upper SCH layer 232, and an n-type InP top layer 234 of the lower mesa structure 224.

The upper mesa structure 226 is composed of, in order from the side closest to the lower mesa structure 224, a bottom layer 236, a first interlayer semiconductor layer 254 made of n-type InP, a diffraction grating layer 256 made of n-type InGaAsP, a second interlayer semiconductor layer 258 made of n-type InP, an adjustment semiconductor layer 260 made of n-type InGaAsP, an upper cladding layer 238 made of n-type InP, and an n-type contact layer 240. Note that the p-type and n-type may be reversed. The upper electrode 210 has a three-layer structure of Ti/Pt/Au from the side in contact with the contact layer 240. The lower electrode 212 is composed of an AuZn-based material.

As in the first embodiment, the bottom layer 236 of the upper mesa structure 226 is formed from a material that does not contain phosphorus (P) as a constituent element, and a buried layer 242 with excellent crystallinity can be formed using the process described in the first embodiment.

This embodiment differs from the first embodiment in that the upper mesa structure 226 includes a diffraction grating. The first interlayer semiconductor layer 254, the diffraction grating layer 256, and the second interlayer semiconductor layer 258 are provided to form a floating-type diffraction grating. The diffraction grating layer 256 has a periodic diffraction grating, and for example, a λ/4 shift structure is introduced in the direction perpendicular to the paper surface.

The semiconductor optical device achieves an improvement in the relaxation oscillation frequency fr by increasing Γ _QW /W _a in the active layer 228 by narrowing the width of the lower mesa structure 224. However, the semiconductor optical device is also a laser device, and the value of the coupling coefficient κ of the diffraction grating is an important parameter in terms of other laser characteristics as well. For example, the coupling coefficient κ affects the resistance to optical feedback and the side mode suppression ratio.

The adjustment semiconductor layer 260 is a layer provided to increase the coupling coefficient κ of the diffraction grating. The adjustment semiconductor layer 260 is made of a material with a higher refractive index than the upper cladding layer 238, and the inclusion of the adjustment semiconductor layer 260 makes it possible to adjust κ. The rest of the configuration is the same as that of the semiconductor optical device of the first embodiment.

[Third embodiment]
Fig. 5 is a plan view of a semiconductor optical device according to a third embodiment. Fig. 6 is a cross-sectional view of the semiconductor optical device taken along line VI-VI of Fig. 5. The semiconductor optical device is an EA-DFB laser (Distributed Feedback Laser Integrated with Electro-absorption Modulator) that integrates a semiconductor laser 362 and an electro-absorption modulator 364.

An n-type InP buffer layer 322 is stacked on a substrate 320 made of n-type InP. The lower mesa structure 324 is composed of a stack of an n-type lower SCH layer 330, an absorption layer 328 which is an MQW made of undoped strained InGaAlAs, a p-type upper SCH layer 332, and a top layer 334 of the lower mesa structure 324 made of p-type InP. The upper mesa structure 326 is composed of a stack of a bottom layer 336, an upper cladding layer 338 made of p-type InP, and a p-type contact layer 340, in order from the side closest to the lower mesa structure 324. Note that the p-type and n-type may be reversed.

In addition to the upper electrode 310 of the semiconductor laser 362, there is an upper electrode 366 of the electroabsorption modulator 364. The lower electrode 312 may be a common electrode for the semiconductor laser 362 and the electroabsorption modulator 364, or may be a separate electrode. The lower electrode 312 is formed on the lower surface of the substrate 320.

The semiconductor optical device has a mesa stripe structure 314 that spans both the semiconductor laser 362 and the electroabsorption optical modulator 364. A bulk waveguide structure is present between the semiconductor laser 362 and the electroabsorption optical modulator 364. Alternatively, the semiconductor laser 362 and the electroabsorption optical modulator 364 may be directly connected without including a bulk waveguide structure. The mesa stripe structure 314 is configured in two stages. The mesa stripe structure 314 of the semiconductor laser 362 has the same structure as that of the semiconductor optical device described in the second embodiment, for example.

In the electroabsorption optical modulator 364, the lower mesa structure 324 is sandwiched between buried layers 342. Narrowing the width of the absorption layer 328 increases the electric field strength per unit volume of the absorption layer 328, which is advantageous in terms of low-voltage operation. However, narrowing the width of the upper mesa structure 326 increases resistance. Therefore, by making the upper mesa structure 326 wider than the lower mesa structure 324, it is possible to increase the electric field strength of the absorption layer 328 while suppressing the increase in resistance.

In this embodiment, the bottom layer 336 of the upper mesa structure 326 is also made of a material (e.g., InGaAlAs) that does not contain phosphorus (P) as a constituent element, and a buried layer 342 with excellent crystallinity can be formed using the process described in the first embodiment.

[Overview of the embodiment]
(1) A semiconductor optical device comprising: a lower mesa structure (24) extending in a stripe shape and consisting of multiple layers including an active layer (28) or an absorption layer (328); a buried layer (42) made of indium phosphide burying both sides of the lower mesa structure (24); and an upper mesa structure (26) extending in a stripe shape and consisting of multiple layers including a bottom layer (36) made of a material not containing phosphorus, the bottom layer (36) having a bottom surface protruding from a top layer (34) of the lower mesa structure (24), the bottom surface being in contact with the lower mesa structure (24) and the buried layer (42).

Because the bottom layer 36 of the upper mesa structure 26 is made of a material that does not contain phosphorus, indium phosphide crystals are less likely to grow from its bottom surface. This prevents degradation of the crystal quality of the buried layer 42 made of indium phosphide.

(2) A semiconductor optical element according to (1), wherein the buried layer 42 has the greatest thickness at the portion contacting the bottom surface of the bottom layer 36.

(3) A semiconductor optical element according to (2), wherein the portion of the buried layer 42 that contacts the bottom surface of the bottom layer 36 is a convex portion.

(4) A semiconductor optical element according to any one of (1) to (3), further comprising an insulating layer 44 covering the side surfaces of the upper mesa structure 26 and the top surface of the burying layer 42.

(5) A semiconductor optical device according to (4), in which a portion of the burying layer 42 is interposed between the top layer 34 of the lower mesa structure 24 and the insulating layer 44, and the insulating layer 44 does not contact the top layer 34.

(6) A semiconductor optical element according to (4) or (5), wherein the insulating layer 44 has a contact surface with the buried layer 42, and the contact surface is located lower than the bottom surface of the bottom layer 36.

(7) A semiconductor optical element according to any one of (1) to (6), wherein the base of the buried layer 42 is made of indium phosphide.

(8) A semiconductor optical element according to (7), wherein the underlying layer of the burying layer 42 is a buffer layer 22 on the substrate 20.

(9) A semiconductor optical element according to any one of (1) to (8), wherein the material of the bottom layer 36 is InGaAlAs, InAlAs, or InGaAs.

(10) A method for manufacturing a semiconductor optical device, comprising: forming a mesa stripe structure (14) having a lower mesa structure (24) consisting of multiple layers extending in a stripe shape and including an active layer (28) or an absorption layer (328); and an upper mesa structure (26) consisting of multiple layers extending in a stripe shape on the lower mesa structure (24) and including a bottom layer (36), the bottom layer (36) having a bottom surface protruding from the top layer (34) of the lower mesa structure (24) and being made of a material that does not contain phosphorus; and, after forming the mesa stripe structure (14), forming buried layers (42) consisting of indium phosphide by crystal growth on both sides of the lower mesa structure (24) so as to be in contact with the bottom surface.

Because the bottom layer 36 of the upper mesa structure 26 is made of a material that does not contain phosphorus, indium phosphide crystals are less likely to grow from its bottom surface. This prevents degradation of the crystal quality of the buried layer 42 made of indium phosphide.

(11) A method for manufacturing a semiconductor optical device according to (10), in which the crystal growth is performed while the upper mesa structure 26 is covered with a patterning mask 52 except for the bottom surface.

(12) A method for manufacturing a semiconductor optical device according to (11), wherein the patterning mask 52 protrudes beyond the bottom surface along the side surface of the upper mesa structure 26.

(13) A method for manufacturing a semiconductor optical device according to (12), wherein the patterning mask 52 protrudes in a direction away from the top layer 34 of the lower mesa structure 24 at a position spaced apart from the top layer 34.

(14) A method for manufacturing a semiconductor optical device according to any one of (10) to (13), wherein the step of forming the mesa stripe structure 14 includes the steps of: depositing a multilayer that will become the upper mesa structure 26 and the lower mesa structure 24; etching the layer 34A that will become the upper mesa structure 26 and the top layer 34 of the lower mesa structure 24 so as to leave a region corresponding to the upper mesa structure 26; and etching the layer 34A that will become the upper mesa structure 26 and the top layer 34 of the lower mesa structure 24 while suppressing the etching reaction of the top layer 34 of the lower mesa structure 24. A method for manufacturing a semiconductor optical device, comprising: a step of performing a first selective etching process in which etching proceeds on stacked layers other than the top layer 34 of the lower mesa structure 24; and a step of performing a second selective etching process in which etching proceeds on the layer to be etched 34B that will become the top layer 34 of the lower mesa structure 24 while suppressing the etching reaction on the bottom layer 36 of the upper mesa structure 26; the first selective etching and the second selective etching are performed so that a region corresponding to the lower mesa structure 24 remains.

(15) A method for manufacturing a semiconductor optical device according to (14), further comprising, before the step of performing the first selective etching, a step of forming an etching mask 48 that covers the region corresponding to the upper mesa structure 26.

(16) A method for manufacturing a semiconductor optical device according to (14) or (15), wherein the layer 34A, which becomes the base on which the multilayer is formed and the top layer 34, is made of indium phosphide, and the second selective etching etches the base of the multilayer.

The present invention is not limited to the above-described embodiments and various modifications are possible. For example, the configurations described in the embodiments can be replaced with substantially the same configurations, configurations that achieve the same effects, or configurations that can achieve the same objectives.

REFERENCE SIGNS LIST 10 Upper electrode, 12 Lower electrode, 14 Mesa stripe structure, 16 Coating film, 18 Coating film, 20 Substrate, 22 Buffer layer, 24 Lower mesa structure, 26 Upper mesa structure, 28 Active layer, 30 Lower SCH layer, 32 Upper SCH layer, 34 Top layer, 34B Layer to be etched, 36 Bottom layer, 38 Upper cladding layer, 40 Contact layer, 42 Buried layer, 44 Insulating layer, 46 First coating film, 48 Etching mask, 50 Second coating film, 52 Patterning mask, 210 Upper electrode, 212 Lower electrode, 220 Substrate, 222 Buffer layer, 224 Lower mesa structure, 226 Upper mesa structure, 228 Active layer, 230 Lower SCH layer, 232 Upper SCH layer, 234 Top layer, 236 Bottom layer, 238 Upper cladding layer, 240 Contact layer, 242 Buried layer, 254 First interlayer semiconductor layer, 256 Diffraction grating layer, 258 Second interlayer semiconductor layer, 260 Adjustment semiconductor layer, 310 Upper electrode, 312 Lower electrode, 314 Mesa stripe structure, 320 Substrate, 322 Buffer layer, 324 Lower mesa structure, 326 Upper mesa structure, 328 Absorption layer, 330 Lower SCH layer, 332 Upper SCH layer, 334 Top layer, 336 Bottom layer, 338 Upper cladding layer, 340 Contact layer, 342 Buried layer, 362 Semiconductor laser, 364 Electroabsorption optical modulator, 366 Upper electrode.

Claims (14)

a lower mesa structure extending in a stripe shape and consisting of multiple layers including an active layer;
a buried layer made of indium phosphide burying both sides of the lower mesa structure;
an upper mesa structure including a plurality of layers extending in a stripe shape and including a bottom layer made of a material that does not contain phosphorus, the bottom layer having a bottom surface that protrudes from an uppermost layer of the lower mesa structure, the bottom surface being in contact with the lower mesa structure and the buried layer;
and
the buried layer has a maximum thickness in the vertical direction at a portion in contact with the bottom surface of the lowermost layer,
The semiconductor optical device has a convex portion in the buried layer that contacts the bottom surface of the lowermost layer . 2. The semiconductor optical device according to claim 1 ,
The semiconductor optical device further comprises an insulating layer covering the side surface of the upper mesa structure and the top surface of the burying layer. 3. The semiconductor optical device according to claim 2 ,
a portion of the buried layer is interposed between the uppermost layer of the lower mesa structure and the insulating layer;
The insulating layer is not in contact with the top layer. 4. The semiconductor optical device according to claim 2 ,
the insulating layer has a contact surface with the buried layer;
The contact surface is located lower than the bottom surface of the lowermost layer. 5. The semiconductor optical device according to claim 1,
The underlying layer of the buried layer is made of indium phosphide. 6. The semiconductor optical device according to claim 5 ,
The underlying layer of the buried layer is a buffer layer on a substrate. 7. The semiconductor optical device according to claim 1,
The semiconductor optical device wherein the material of the bottom layer is any one of InGaAlAs, InAlAs, and InGaAs. forming a mesa stripe structure having a lower mesa structure made of a plurality of layers including an active layer extending in a stripe shape, and an upper mesa structure made of a plurality of layers including a bottom layer extending in a stripe shape on the lower mesa structure, the bottom layer having a bottom surface protruding from the top layer of the lower mesa structure and made of a material not containing phosphorus;
After forming the mesa stripe structure, forming a buried layer made of indium phosphide by crystal growth on both sides of the lower mesa structure so as to be in contact with the bottom surface;
Including,
the buried layer is formed so as to have a maximum thickness in the vertical direction at a portion in contact with the bottom surface of the lowermost layer,
A method for manufacturing a semiconductor optical device , wherein the portion of the buried layer that contacts the bottom surface of the lowermost layer is made into a convex portion . 9. A method for manufacturing a semiconductor optical device according to claim 8 , comprising the steps of:
The crystal growth is performed in a state where the upper mesa structure, except for the bottom surface, is covered with a patterning mask. 10. A method for manufacturing a semiconductor optical device according to claim 9 , comprising:
The patterning mask protrudes beyond the bottom surface along the side surface of the upper mesa structure. 11. A method for manufacturing a semiconductor optical device according to claim 10 , comprising:
The patterning mask protrudes in a direction away from the uppermost layer of the lower mesa structure at a position spaced from the uppermost layer. A method for manufacturing a semiconductor optical device according to any one of claims 8 to 11 , comprising:
The step of forming the mesa stripe structure includes:
depositing multiple layers that will become the upper mesa structure and the lower mesa structure;
etching the stacked layer that will become the upper mesa structure and the layer that will become the top layer of the lower mesa structure so as to leave a region that corresponds to the upper mesa structure;
performing a first selective etching step in which etching of the stacked layers other than the top layer of the lower mesa structure is promoted while etching of the top layer of the lower mesa structure is suppressed;
performing a second selective etching step in which etching of the etched layer that will become the uppermost layer of the lower mesa structure proceeds while etching of the lowermost layer of the upper mesa structure is suppressed;
Including,
The first selective etching and the second selective etching are performed so as to leave a region corresponding to the lower mesa structure. 13. A method for manufacturing a semiconductor optical device according to claim 12 , comprising the steps of:
The method for manufacturing a semiconductor optical device further includes, before the step of performing the first selective etching, forming an etching mask that covers the region corresponding to the upper mesa structure. 14. A method for manufacturing a semiconductor optical device according to claim 12 or 13 , comprising the steps of:
the layer that will be the base layer on which the multilayer is deposited and the top layer are made of indium phosphide;
In the second selective etching, the underlying layer of the multilayer is etched.