JP7767906B2 - Integrated circuits and power supply circuits - Google Patents

Description

The present invention relates to integrated circuits and power supply circuits.

A known power supply circuit is a power factor correction (PFC) circuit that turns on a transistor a predetermined period of time after the inductor current becomes zero (see, for example, Patent Documents 1 to 3).

JP 2008-199896 A U.S. Patent No. 7,116,090 JP 2017-28778 A

Generally, integrated circuits that control the switching of transistors in power factor correction circuits turn on the transistors when the voltage applied to the transistors decreases after the inductor current becomes zero, in order to reduce switching losses.

However, if an integrated circuit turns on the transistor a certain period after the inductor current becomes zero, switching losses are reduced, but the inductor current becomes negative, which can cause the power factor in the power supply circuit to deteriorate.

The present invention was made in consideration of the above-mentioned problems in the conventional technology, and provides an integrated circuit and a power supply circuit that can improve the power factor in a power supply circuit.

To solve the above problem, a first aspect of the present invention provides an integrated circuit for controlling the switching of a transistor in a power supply circuit that generates an output voltage of a target level from an AC voltage, the integrated circuit comprising: an inductor to which a rectified voltage corresponding to an AC voltage is applied; and a transistor that controls the inductor current flowing through the inductor. The integrated circuit comprises: a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on the difference between a first voltage corresponding to the output voltage and a reference voltage; an on signal output circuit that outputs an on signal for turning on the transistor when the inductor current falls below a predetermined value after the transistor turns off; a delay circuit that delays the on signal for a predetermined period; a correction circuit that corrects the first command value and outputs it as a second command value for turning on the transistor for a second period longer than the first period; and a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value. The correction circuit corrects the first command value based on a third period from when the transistor turns off until the inductor current reaches the predetermined value, a ratio based on the second period, and the predetermined period.

A second aspect of the present invention provides an integrated circuit for controlling the switching of the transistor in a power supply circuit that generates an output voltage of a target level from the AC voltage, the integrated circuit comprising: an inductor to which a rectified voltage corresponding to an AC voltage is applied; and a transistor that controls the inductor current flowing through the inductor. The integrated circuit comprises: a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on the difference between a first voltage corresponding to the output voltage and a reference voltage; an on signal output circuit that outputs an on signal for turning on the transistor when the inductor current falls below a predetermined value after the transistor turns off; a delay circuit that delays the on signal for a predetermined period; a correction circuit that corrects the first command value and outputs it as a second command value for turning on the transistor for a second period longer than the first period; a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value; and a second estimation circuit that estimates the rectified voltage based on the first voltage, the second period, and a third period from when the transistor turns off until the inductor current reaches the predetermined value. The correction circuit corrects the first command value based on the first voltage, the estimated rectified voltage, and the specified period.

A third aspect of the present invention provides a power supply circuit that generates an output voltage of a target level from an AC voltage, the power supply circuit comprising: an inductor to which a rectified voltage corresponding to the AC voltage is applied; a transistor that controls the inductor current flowing through the inductor; and an integrated circuit that controls the switching of the transistor. The integrated circuit includes: a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on the difference between a first voltage corresponding to the output voltage and a reference voltage; an on signal output circuit that outputs an on signal for turning on the transistor when the inductor current falls below a predetermined value after the transistor turns off; a delay circuit that delays the on signal for a predetermined period; a correction circuit that corrects the first command value and outputs it as a second command value for turning on the transistor for a second period longer than the first period; and a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value. The correction circuit corrects the first command value based on a third period from when the transistor turns off until the inductor current reaches the predetermined value, a ratio based on the second period, and the predetermined period.

A fourth aspect of the present invention provides a power supply circuit that generates an output voltage of a target level from an AC voltage, the power supply circuit comprising: an inductor to which a rectified voltage corresponding to the AC voltage is applied; a transistor that controls the inductor current flowing through the inductor; and an integrated circuit that controls switching of the transistor. The integrated circuit includes: a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on the difference between a first voltage corresponding to the output voltage and a reference voltage; an on signal output circuit that outputs an on signal for turning on the transistor when the inductor current falls below a predetermined value after the transistor turns off; a delay circuit that delays the on signal for a predetermined period; a correction circuit that corrects the first command value and outputs it as a second command value for turning on the transistor for a second period longer than the first period; a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value; and a second estimation circuit that estimates the rectified voltage based on the first voltage, a third period from when the transistor turns off until the inductor current reaches the predetermined value, and the second period. The correction circuit corrects the first command value based on the first voltage, the estimated rectified voltage, and the specified period.

It is possible to provide an integrated circuit and a power supply circuit that can improve the power factor in a power supply circuit.

Note that the above summary of the invention does not list all of the necessary features of the present invention. Subcombinations of these features may also constitute inventions.

An example of a circuit diagram of a general AC-DC converter 10a is shown. An example of the configuration of a general power factor correction IC 35a is shown. 1 shows a conceptual diagram of the relationship between the inductor current IL1, the drain-source voltage Vds of the NMOS transistor 36, and the voltage Vo1. 10 shows the relationship between the inductor current IL1 and the input current Iin when there is no delay period for the ON signal Son1. 1 shows the relationship when the inductor current IL1 and the input current Iin are controlled based on the on-signal Son2 that is delayed with respect to the on-signal Son1. 1 is a conceptual diagram illustrating the principle by which an inductor current IL1 is corrected by a power factor correction IC according to an embodiment. 1 shows an example of a circuit diagram of an AC-DC converter 10b according to an embodiment. An example of the configuration of the power factor correction IC 35b is shown. An example of the configuration of the correction circuit 64a is shown. 10 is a conceptual diagram showing the relationship between the inductor current IL2, the drain-source voltage Vds of the NMOS transistor 36, and the voltage Vo2. An example of the configuration of the power factor correction IC 35c is shown. An example of the configuration of the correction circuit 64b is shown. 1 shows an example of a circuit diagram of an AC-DC converter 10c according to an embodiment. An example of the configuration of the power factor correction IC 35d is shown. An example of the configuration of the correction circuit 64c is shown. An example of the configuration of the power factor correction IC 35e is shown. An example of the configuration of the power factor correction IC 35f is shown. An example of the configuration of the power factor correction IC 35g is shown. An example of the configuration of the power factor correction IC 35h is shown. 1 shows an example of the configuration of a rectified voltage estimation circuit 66a. The operation of the rectified voltage estimation circuit 66a will now be described. The main waveforms in the operation of the rectified voltage estimation circuit 66a will be described. 1 shows an example of the configuration of the correction circuit 64d. 1 shows an example of the configuration of a rectified voltage estimation circuit 66b. The operation of the rectified voltage estimation circuit 66b will now be described. The operation in step S10 will be described. 10 shows waveforms for explaining the operation in step S10. 1 shows an example of the configuration of a rectified voltage estimation circuit 66c. An example of the configuration of the power factor correction IC 35i is shown.

The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

In this specification, the term "connection" is used, and unless otherwise specified, "connection" means "electrically connected." In this specification, when a voltage or signal has a low logical level, it is referred to as an L level, and when the logical level is high, it is referred to as an H level.

Figure 1 shows an example circuit diagram of a typical AC-DC converter 10a. The AC-DC converter 10a is a boost-type PFC circuit that generates a target output voltage Vout from the AC voltage Vac of a commercial power supply. The output voltage Vout generated by the AC-DC converter 10a is used to drive a load 11.

The load 11 is, for example, a DC-DC converter or an electronic device that operates on DC voltage.

<<Configuration of AC-DC converter 10a>>
The AC-DC converter 10a includes a full-wave rectifier circuit 30, capacitors 31 and 32, an inductor 33, a diode 34, a power factor correction IC 35a, an NMOS transistor 36, a body diode 37, a parasitic capacitor 38, and resistors 40 to 42.

==Input to full-wave rectifier circuit 30==
The AC power supply 20 is a commercial AC power supply for supplying an AC voltage Vac to the full-wave rectifier circuit 30. The AC voltage Vac is, for example, a voltage of 100 to 277 V and a frequency of 50 to 60 Hz.

Inductor 21 is the so-called power supply inductance of AC power supply 20 in the current Iin supplied from AC power supply 20 to full-wave rectifier circuit 30. In the figure, inductor 21 is shown on only one side of the path connecting AC power supply 20 and full-wave rectifier circuit 30, and the power supply inductance on the other side is omitted.

Capacitor 22, together with inductor 21, removes noise from the current Iin supplied from AC power supply 20 to full-wave rectifier circuit 30. Inductor 21 and capacitor 22 remove noise from the current Iin supplied to full-wave rectifier circuit 30.

==Configuration from full-wave rectifier circuit 30 to load 11==
The full-wave rectifier circuit 30 full-wave rectifies the input predetermined AC voltage Vac and outputs the rectified voltage Vr to the capacitor 31 and the inductor 33. The inductor 33 is applied with the rectified voltage Vr corresponding to the AC voltage Vac.

Capacitor 31 smoothes the rectified voltage Vr supplied from the full-wave rectifier circuit 30.

Capacitor 32, together with inductor 33, diode 34, and NMOS transistor 36, forms a boost chopper circuit. As a result, the charging voltage of capacitor 32 is boosted to a DC output voltage Vout and supplied to load 11.

The power factor correction integrated circuit (IC) 35a is an integrated circuit that controls the switching of the NMOS transistor 36 so that the output voltage Vout reaches a target level (e.g., 400 V) while improving the power factor of the AC-DC converter 10a.

The power factor correction IC 35a includes terminals CS, FB, and OUT. Note that the power factor correction IC 35a also has terminals other than terminals CS, FB, and OUT (e.g., a power supply terminal, a GND terminal, etc.), but these other terminals are omitted from the diagram.

NMOS transistor 36 is a power transistor that controls the power to load 11 of AC-DC converter 10a. NMOS transistor 36 controls inductor current IL1 that flows through inductor 33.

Note that while the NMOS transistor 36 is described as an N-type (Metal Oxide Semiconductor) transistor, it may also be a P-type transistor. Furthermore, the NMOS transistor 36 may also be another type of transistor, such as a bipolar transistor.

The gate electrode of NMOS transistor 36 is connected to terminal OUT and is controlled by voltage Vo1 from power factor correction IC 35a. NMOS transistor 36 also has a body diode 37 and a parasitic capacitor 38.

The body diode 37 is a parasitic diode formed by the pn junction between the drain and source of the NMOS transistor 36. The body diode 37 contributes to the reverse recovery characteristics. When the NMOS transistor 36 is turned off, the body diode 37 acts as a parasitic element together with the parasitic capacitor 38.

Parasitic capacitor 38 is a parasitic capacitance between the drain and source of NMOS transistor 36. In AC-DC converter 10a, when NMOS transistor 36 is turned off, a parasitic capacitance exists in the circuit that resonates with the inductance of inductor 33. Parasitic capacitor 38 is an example of a parasitic capacitance that resonates with the inductance of inductor 33.

Resistors 40 and 41 form a voltage divider circuit that divides the output voltage Vout to generate voltage Vfb. The voltage divider circuit formed by resistors 40 and 41 applies the divided voltage Vfb as a feedback voltage to terminal FB of power factor correction IC 35a.

Resistor 42 is a resistor used to detect inductor current IL1. A voltage Vcs corresponding to inductor current IL1 is generated across resistor 42. One end of resistor 42 is connected to terminal CS of power factor correction IC 35a.

Note that the AC-DC converter 10a corresponds to the "power supply circuit." The power factor correction IC 35a corresponds to the "integrated circuit." The voltage Vfb corresponds to the "first voltage."

<<Power factor correction IC 35a>>
2 shows an example of the configuration of a general power factor correction IC 35 a. The power factor correction IC 35 a includes analog-to-digital converters (ADCs) 50 and 53, an ON signal output circuit 51, a delay circuit 52, an error amplifier circuit 54, a first command value output circuit 55, a drive circuit 56, and terminals CS, FB, and OUT.

ADC 50 converts the voltage Vcs, which corresponds to the inductor current IL1 applied to terminal CS, into a digital value. For convenience, the digital value output from ADC 50 will be referred to as voltage Vcs below.

The on-signal output circuit 51 detects that the inductor current IL1 is nearly zero when the inductor current IL1 falls below a predetermined current value I0 (e.g., a few mA) that is slightly greater than zero, based on the voltage Vcs. Then, when the inductor current IL1 falls to nearly zero (hereinafter, "nearly zero" will be referred to simply as "0" (zero) where appropriate), the on-signal output circuit 51 outputs an on-signal Son1 to turn on the NMOS transistor 36. As an example, the on-signal Son1 is an H-level pulse signal.

The delay circuit 52 delays the on signal Son1 by a predetermined period Tzcd and outputs the delayed on signal Son2. The period Tzcd will be described later.

ADC 53 converts the voltage Vfb applied to terminal FB into a digital value and outputs the digital value to error amplifier circuit 54. Note that, for convenience, the digital value output from ADC 53 will be described below as voltage Vfb.

The error amplifier circuit 54 compares the voltage Vfb with the reference voltage Vref and amplifies the error between them. The error amplifier circuit 54 outputs the amplified error to the first command value output circuit 55.

The first command value output circuit 55 outputs a first command value Vc1 to the drive circuit 56 based on the amplified error (i.e., the difference between the voltage Vfb and the reference voltage Vref). The level of the first command value Vc1 (i.e., the length of the period Ton1 during which the NMOS transistor 36 is on) is set so that the AC-DC converter 10a outputs an output voltage Vout at the target level.

The drive circuit 56 is a circuit that drives the NMOS transistor 36 based on the on signal Son2 and the first command value Vc1. Specifically, when the on signal Son2 is input, the drive circuit 56 outputs an H-level voltage Vo1 for a period Ton1 corresponding to the first command value Vc1. As a result, the NMOS transistor 36 turns on.

On the other hand, when a period Ton1 corresponding to the first command value Vc1 has elapsed since the NMOS transistor 36 turned on, the drive circuit 56 outputs an L-level voltage Vo1. As a result, the NMOS transistor 36 turns off.

For convenience, details are omitted, but as an example, the drive circuit 56 includes a circuit that outputs a drive signal to turn on the NMOS transistor 36, and a buffer circuit.

==Main Waveforms in AC-DC Converter 10a==
Here, to provide an overview of the operation of a typical AC-DC converter 10a, the main waveforms in the AC-DC converter 10a will be described. Figure 3 shows a conceptual diagram of the relationship between the inductor current IL1, the drain-source voltage Vds of the NMOS transistor 36, and the voltage Vo1. Note that this description assumes that after the NMOS transistor 36 is turned off, the inductor current IL1 decreases to 0 (a predetermined value) at time t0.

At time t0, when inductor current IL1 decreases to 0, the on-signal output circuit 51 in FIG. 2 outputs an on-signal Son1 at an H level. After time t0, inductor current IL1 continues to decrease and becomes a negative value.

Here, "positive inductor current IL1" refers to a current flowing from one end of inductor 33, where full-wave rectifier circuit 30 and inductor 33 are connected, to the other end of inductor 33, where inductor 33 and NMOS transistor 36 are connected. Furthermore, "negative inductor current IL1" refers to a current flowing from the other end of inductor 33 to one end of inductor 33.

At time t0, NMOS transistor 36 turns off, and the positive inductor current IL1 decreases and reaches zero, causing resonance in inductor 33 and parasitic capacitor 38. As a result, the drain-source voltage Vds of NMOS transistor 36 decreases, and the negative inductor current IL1 (i.e., a negative inductor current IL1) flows. In the figure, the minimum value of the negative inductor current IL1 is indicated by ILnp.

Then, at time t1, which is the delay period Tzcd after time t0, the drive circuit 56 outputs a high-level voltage Vo1 based on the delayed on signal Son2. Therefore, the NMOS transistor 36 turns on.

The delay period Tzcd is set to the period from when the drain-source voltage Vds starts to decrease until it reaches its lowest point, i.e., half the resonance period. As a result, power consumption when the NMOS transistor 36 is turned on can be reduced.

At time t1, the on-signal Son2 delayed by the delay circuit 52 goes high. When the NMOS transistor 36 turns on in response to the high-level on-signal Son2, the inductor current IL1 flowing through the inductor 33 increases.

Then, based on the first command value Vc1, the drive circuit 56 keeps the NMOS transistor 36 on from time t1 until time t2, which is the time period Ton1 after time t1. At time t2, the inductor current IL2 reaches the maximum value ILp1.

After that, at time t2, the drive circuit 56 outputs an L-level voltage Vo1. This turns off the NMOS transistor 36.

Furthermore, at time t3, the inductor current IL1 decreases again and becomes 0. Here, the period that elapses from time t2 until the NMOS transistor 36 is turned off at time t3 and becomes 0 is referred to as period Toff1.

Furthermore, period Ton1 corresponds to the "first period."

==Power factor improvement and dead angle==
In the above-described AC-DC converter 10a, the power consumption when the NMOS transistor 36 is turned on can be reduced.

When the drive circuit 56 delays the on signal Son1 by a predetermined period Tzcd, a negative inductor current IL1 flows through the inductor 33 for the delay period Tzcd. During this time, when the NMOS transistor 36 is switched based on the signal So2 delayed by the drive circuit 56, the drain-source voltage Vds becomes lower than before the negative inductor current IL1 began to flow, reducing the switching loss of the NMOS transistor 36 and lowering power consumption.

In this case, the average value of inductor current IL1 decreases by the amount by which inductor current IL1 oscillates negatively during period Tzcd. When inductor current IL1 is in low phase, the overall amplitude of inductor current IL1 decreases, so the negative oscillations of inductor current IL1 contribute significantly to the average value of inductor current IL1, canceling out the contribution of inductor current IL1 on the positive side. This leads to a deterioration in power factor.

Below, we will explain in detail how the input current Iin in an AC-DC converter changes when there is and when there is no delay period. Figure 4 shows the relationship between the inductor current IL1 and the input current Iin when there is no delay period in response to the on signal Son1. In the figure, the dashed line indicates the average value of the inductor current IL1.

===If there is no delay period===
If there is no delay period, the NMOS transistor 26 is turned on when the inductor current IL1 becomes 0, and the AC power supply 20 operates in a so-called critical mode. The period during which the NMOS transistor 26 is turned on is a fixed period according to the target level.

In this case, the peak value of inductor current IL1 changes depending on the rectified voltage. As a result, the average value of inductor current IL1 (the dashed line shown in the diagram of inductor current IL1) takes the form of a positively rectified sine wave. Note that even in the low phase of inductor current IL1, the average value remains sinusoidal, but the drive circuit 56 switches when the drain-source voltage of NMOS transistor 36 is at a high value, resulting in large switching losses.

If there is a delay period
5 shows a relationship when the inductor current IL1 and the input current Iin are controlled based on the on-signal Son2 that is delayed with respect to the on-signal Son1. What is shown in FIG. 5 is an example of the inductor current IL1 and the input current Iin in the AC-DC converter 10a.

As explained in Figure 3, when the on signal Son1 is delayed by a predetermined period Tzcd, a negative inductor current IL1 flows through the inductor 33 for the delay period Tzcd.

On the other hand, the positive contribution of inductor current IL1 becomes smaller, especially at low phases (e.g., near 0°). As a result, the negative contribution of inductor current IL1 during the delay period cancels out the positive contribution of inductor current IL1 during period Ton1, and the average value of inductor current IL1 flowing through inductor 33 becomes close to zero.

The input current Iin input to the full-wave rectifier circuit 30 in Figure 1 is input in a manner that is drawn by the inductor current IL1. Therefore, in the region where the average value of the inductor current IL1 is near 0, the input current Iin also has a value near 0. This creates a region where the current value is near 0 in the low-phase region of the input current Iin.

In this way, in a power factor correction IC, the region where the input current Iin's value is close to 0 at low phase is called the dead angle. The wider the dead angle, the more the current waveform distorts from a sine wave and the worse the power factor becomes.

Figure 6 is a conceptual diagram showing the principle by which the inductor current IL1 is corrected by the power factor correction IC according to the embodiment.

In the figure, IL1 represents the inductor current associated with AC-DC converter 10a, and IL2 represents the inductor current after correction by AC-DC converters 10b and 10c of the embodiments described below in Figures 7 and 12. Vo1 represents the voltage applied to terminal OUT and the gate electrode of NMOS transistor 36 before correction by AC-DC converter 10a, and Vo2 represents the voltage applied to terminal OUT and NMOS transistor 36 after correction by AC-DC converters 10b and 10c of the embodiments described below.

As already explained in FIG. 3, the delay circuit 52 delays the on signal Son1 by the period Tzcd and outputs the on signal Son2. As a result, the drive circuit 56 supplies the low-level voltage Vo1 for the period Tzcd in addition to the period Toff1, turning off the NMOS transistor 36.

As a result, the inductor current IL1 decreases by the minimum value ILnp, creating a dead angle in the input current Iin.

==Principle of improving power factor while setting a delay period==
As described above, when the delay period is set, the inductor current IL1 becomes negative. Therefore, if the period Ton2 during which the NMOS transistor 36 is turned on is extended in the switching cycle by an amount sufficient to cancel out the negative inductor current IL1, the decrease in the inductor current IL1 can be suppressed.

In the AC-DC converter of this embodiment, which will be described later, the period Ton during which the drive circuit 56 turns on the NMOS transistor 36 is extended by a period ΔTon to form a period Ton2, and a current is supplied during the period Tzcd to cancel out the current that causes the inductor current IL1 to swing negative.

As a result, the AC-DC converter of this embodiment supplies inductor current IL2 that is corrected to the positive side to offset the current that has been applied to the negative side.

In the inductor current IL2 shown in Figure 6, the period Ton1 is corrected to period Ton2, causing the drive circuit 56 to turn on the NMOS transistor 36 for a longer period. As a result, at time t4, the inductor current IL2 reaches a maximum value ILp2 that is higher than the pre-correction maximum value ILp1.

Here, when period Ton1 is corrected to period Ton2, the period that elapses from when NMOS transistor 36 is turned off until inductor current IL2 indicates 0 is defined as period Toff.

At time t4, the drive circuit 56 turns off the NMOS transistor 36, and at time t5, after a period Toff longer than period Toff1 has elapsed, the inductor current IL2 reaches 0.

As a result, a current is supplied as inductor current IL2 such that the integral of the inductor current IL2, which was negative during period Tzcd, cancels out the integral of the increase in inductor current IL2 during periods ΔTon and Toff-Toff1 in the period when inductor current IL2 next becomes positive.

[Principle 1-1]
When the period Tzcd is a set value, the AC-DC converter of this embodiment derives the period Ton2 as follows: First, when the ON signal Son2 is delayed by the period Tzcd with respect to the ON signal Son1, the current decrease value is
ILnp×(2/π)=(Tzcd/L)×(Vout−Vr)×(2/π ² )
It is expressed as:

On the other hand, the correction value ΔTon for the period Ton1 is
ΔTon=(2/π)×(L×ILnp)/Vr
∴ΔTon=(2/π ² )×Tzcd×[(Vout−Vr)/Vr]
It is expressed as:

The voltage ratio (Vout-Vr)/Vr is calculated from the periods Ton2 and Toff as follows: (Vout-Vr)/Vr=Ton2/Toff
Therefore, the period Ton2 can be calculated as follows:

First, the voltage ratio (Vout-Vr)/Vr is estimated from the periods Ton2 and Toff.
Ton2/Toff...(1)
Next, the correction value ΔTon is calculated based on the ratio of the formula (1) and the set value Tzcd.

ΔTon=(2/π ² )×Tzcd×(Ton2/Toff)...(2)
The corrected period Ton2 is calculated using the correction value ΔTon of equation (2).

Ton2=Ton1+ΔTon...(3)
This allows an appropriate period to be calculated as the period Ton2.

[Principle 1-2]
Compared to the case of Principle 1-1, when the voltage Vout is the input value, the following estimated value Vres1 estimated from the periods Ton2 and Toff can be used as the rectified voltage Vr.

Vres1=Vout×[Toff/(Ton2+Toff)]...(4)
A voltage ratio is calculated based on the voltages Vout and Vres using the estimated value Vres1 of equation (4).

(Vout-Vres1)/Vres1...(5)
The correction value ΔTon is calculated based on the ratio of the formula (5) and the set value Tzcd.

ΔTon=(2/π ² )×Tzcd×(Vout-Vres1)/Vres1...(6)
The corrected period Ton2 is calculated using the correction value ΔTon of equation (6).

Ton2=Ton1+ΔTon...(7)
This allows an appropriate period to be calculated as the period Ton2.

[Principle 1-3]
In comparison with the case of Principle 1-2, when the voltages Vout and Vr are input values, the period Ton2 is calculated as follows: First, the voltage ratio is calculated.

(Vout-Vr)/Vr...(8)
The correction value ΔTon is calculated based on the ratio of the formula (8) and the set value Tzcd.

ΔTon=(2/π ² )×Tzcd×(Vout-Vr)/Vr...(9)
The corrected period Ton2 is calculated using the correction value ΔTon of equation (9).

Ton2=Ton1+ΔTon...(10)
This allows an appropriate period to be calculated as the period Ton2.

[Principle 2]
If the AC-DC converter records in a memory circuit the inductance L of inductor 33 and the capacitance C of a capacitor (e.g., the capacitance of parasitic capacitor 38) that resonates the inductor currents IL1 and IL2 together with the inductance L of inductor 33 as known values, the following value can be used as the period Tzcd:

Tzcd=π×√(L・C)...(11)
Using the period Tzcd of equation (11), the period Ton2 can be calculated by performing calculations similar to those of principles 1-1 to 1-3 according to the input voltage and the like.

According to Principles 1-1 to 1-3, an appropriate period Ton2 can be calculated based on the value of the period Tzcd without recording the inductance L of the inductor 33 and the capacitance C of the capacitor as known values. This allows an appropriate period Ton2 to be set based on the decrease in the inductor current IL1.

According to Principle 2, the period Ton2 can be set according to the resonance period of the inductor current IL1, which is determined by the inductance L of the inductor 33 and the capacitance C of the capacitor that resonates the inductor current IL1 together with the inductance L. This allows the period Ton2 to be set appropriately according to the decrease in the inductor current IL1.

According to Principles 1-1 and 1-2, the on-period Ton2 of the NMOS transistor 36 can be corrected appropriately to account for the decrease in inductor current IL2 that occurs due to a delay in the on-signal Son1, thereby improving the power factor. Note that the correction of the on-period Ton2 in this embodiment can be performed for each cycle from one on-period of the NMOS transistor 36 to the next on-period.

<<AC-DC converter 10b according to the first embodiment>>
Fig. 7 shows an example of the configuration of an AC-DC converter 10b of this embodiment. Components denoted by the same reference numerals as those of the AC-DC converter 10a in Fig. 1 correspond to the same components. The following mainly describes the differences between the AC-DC converter 10b and the AC-DC converter 10a.

The AC-DC converter 10b includes a full-wave rectifier circuit 30, capacitors 31 and 32, an inductor 33, a diode 34, a power factor correction IC 35b, an NMOS transistor 36, a body diode 37, a parasitic capacitor 38, and resistors 40 to 43. In other words, the AC-DC converter 10b differs from the AC-DC converter 10a in that it includes the power factor correction IC 35b and resistor 43.

Furthermore, the power factor correction IC 35b includes terminal RT in addition to terminals CS, FB, and OUT.

One end of resistor 43 is connected to terminal RT. The other end of resistor 43 is grounded. The voltage Vrt generated across resistor 43 is applied to terminal RT.

As described below in Figures 8 and 9, the power factor correction IC 35b sets the delay period Tzcd based on the voltage Vrt at the terminal RT. Furthermore, the power factor correction IC 35b appropriately sets the on-period of the NMOS transistor 36 based on the delay period Tzcd.

In other words, in power factor correction IC 35b, the period during which voltage Vo2 applied to NMOS transistor 36 via the OUT terminal exhibits a logic high level differs from that in power factor correction IC 35a. As a result, even if a delay period Tzcd is set and a period occurs during which inductor current IL2 exhibits a negative value, power factor correction IC 35b can correct the on-period of NMOS transistor 36 to compensate for the period during which inductor current IL2 exhibits a positive value. As a result, the power factor can be improved.

Terminal RT corresponds to the "first terminal." Voltage Vrt corresponds to the "second voltage."

<<Power factor correction IC 35b according to the first embodiment>>
Fig. 8 shows an example of the configuration of the power factor correction IC 35b. Note that components denoted by the same reference numerals as those of the power factor correction IC 35a in Fig. 2 correspond to the same configuration. Below, differences between the configuration of the power factor correction IC 35b and the power factor correction IC 35a will be mainly described.

Power factor correction IC 35b includes ADCs 50 and 53, an ON signal output circuit 51, a delay circuit 52, an error amplifier circuit 54, a first command value output circuit 55, a drive circuit 56, a current source 61, a delay period setting circuit 62, a detection circuit 63, a correction circuit 64a, and terminals CS, FB, OUT, and RT. In other words, in addition to the configuration of power factor correction IC 35a, power factor correction IC 35b also includes terminal RT, a current source 61, a delay period setting circuit 62, a detection circuit 63, and a correction circuit 64a.

In this embodiment, the on-signal output circuit 51 outputs an on-signal Son1 to the delay circuit 52 and also outputs the on-signal Son1 to the detection circuit 63.

In addition, the delay circuit 52 outputs a delayed on-signal Son2 to the drive circuit 56 and outputs data D (Tzcd) for the period Tzcd to the correction circuit 64a.

The drive circuit 56 also turns on the NMOS transistor 36 based on the delayed on-signal Son2, and keeps the NMOS transistor 36 on for a period Ton2 based on the second command value Vc2, which will be described later. After that, the drive circuit 56 turns off the NMOS transistor 36.

In this embodiment, the drive circuit 56 supplies the voltage Vo2 to the gate electrode of the NMOS transistor 36 and also to the detection circuit 63. As described below, the detection circuit 63 is used to detect the period Toff that elapses from when the NMOS transistor 36 is turned off until the inductor current IL2 indicates 0, based on the voltage Vo2.

==Current Source 61 and Delay Period Setting Circuit 62 (Delay Period Setting)==
The current source 61 is a bias current source that supplies a predetermined current to the terminal RT. The current supplied by the current source 61 generates a voltage Vrt proportional to the current across the resistor 43. Therefore, the voltage Vrt proportional to the current is applied to the terminal RT.

The delay period setting circuit 62 sets a predetermined period Tzcd for the delay circuit 52 based on the voltage Vrt applied to the terminal RT of the delay circuit 52. That is, in this embodiment, the period Tzcd is proportional to the resistance value of the resistor 43 and is determined based on the voltage Vrt applied to the terminal RT.

In turn, a voltage Vrt corresponding to Tzcd is applied to terminal RT for a predetermined period of time.

==Detection Circuit 63 and Correction Circuit 64a (Output of Second Command Value Vc2)==
The detection circuit 63 detects the timing at which the NMOS transistor 36 turns off based on the voltage Vo2 supplied from the drive circuit 56. The detection circuit 63 also detects the timing at which the inductor current IL2 becomes 0 after the NMOS transistor 36 turns off based on the on signal Son1.

Detection circuit 63 detects the period Toff that elapses from when NMOS transistor 36 is turned off until inductor current IL2 reaches 0, based on the timing when NMOS transistor 36 is turned off and the timing when inductor current IL2 reaches 0. Furthermore, detection circuit 63 outputs data D(Toff) corresponding to period Toff to correction circuit 64a.

The correction circuit 64a is a circuit that performs correction based on Principle 1-1. That is, the correction circuit 64a corrects the first command value Vc1 and outputs it as a second command value Vc2 for turning on Ton2 for a period longer than the period Ton1 corresponding to the first command value.

Specifically, the correction circuit 64a corrects the first command value Vc1 based on data D(Tzcd) relating to the period Tzcd, the first command value Vc1, and data D(Toff) relating to the off period, and outputs the corrected value as the second command value Vc2.

In addition, the correction circuit 64a of this embodiment corrects the first command value Vc1 based on the ratio of the period Toff from when the NMOS transistor 36 turns off until the inductor current becomes zero to the period Ton2 based on the second command value Vc2, and the period Tzcd.

The period Ton2 corresponds to the "second period." The period Toff corresponds to the "third period."

The timing when the NMOS transistor 36 turns off corresponds to the "first timing." Furthermore, the timing when the inductor current IL2 becomes 0 after the NMOS transistor 36 turns off corresponds to the "second timing."

Details of the correction circuit 64a
The configuration and operation of the correction circuit 64a will be described in more detail below. The correction circuit 64a is a circuit that embodies the correction of the period Ton2 according to Principle 1-1.

Figure 9 shows an example of the configuration of the correction circuit 64a. The correction circuit 64a includes a calculation circuit 71, a correction value output circuit 72, and a second command value output circuit 73.

The calculation circuit 71 calculates the ratio obtained by dividing the period Ton2 by the period Toff based on data D(Toff) corresponding to the period Toff input from the detection circuit 63 and the second command value Vc2 input from the second command value output circuit 73. That is, the calculation circuit 71 calculates the ratio expressed by equation (1).

Ton2/Toff...(1)
The arithmetic circuit 71 also outputs data D (Ton2/Toff) based on the ratio expressed by equation (1) to the correction value output circuit 72.

The correction value output circuit 72 calculates the correction value ΔTon expressed by equation (2) based on data D(Tzcd) corresponding to the period Tzcd, data D(Ton2/ ^Toff ), and a constant (2/π2) stored in the correction value output circuit 72. Specifically, the correction value output circuit 72 calculates the correction value ΔTon for the period Ton1 by multiplying the constant (2/ ^π2 ), the period Tzcd, and the ratio Ton2/Toff.

ΔTon=(2/π ² )×Tzcd×(Ton2/Toff)...(2)
Furthermore, the correction value output circuit 72 outputs data D(ΔTon) corresponding to the correction value ΔTon to the second command value output circuit 73 .

The second command value output circuit 73 calculates the period Ton2 expressed by equation (3). Specifically, the second command value output circuit 73 calculates the period Ton2 by correcting the period Ton1 with the correction value ΔTon based on the first command value Vc1 corresponding to the period Ton1 and the correction value ΔTon.

Ton2=Ton1+ΔTon...(3)
Furthermore, the second command value output circuit 73 outputs a second command value Vc2 corresponding to the period Ton2 to the drive circuit 56. The second command value output circuit 73 also outputs the second command value Vc2 to the calculation circuit 71. This allows the second command value output circuit 73 to set an appropriate period Ton2 for the drive circuit 56.

Note that the arithmetic circuit 71 corresponds to the "first arithmetic circuit."

<<Main Waveforms in the AC-DC Converter According to the Example>>
Here, to provide an overview of the operation of the AC-DC converter 10b according to the embodiment, the main waveforms in the AC-DC converter 10a will be described. Figure 10 is a conceptual diagram showing the relationship between the inductor current IL2, the drain-source voltage Vds of the NMOS transistor 36, and the voltage Vo2.

In accordance with Figure 3, we will assume that after NMOS transistor 36 turns off, at time t10, inductor current IL2 decreases to 0.

At time t10, when inductor current IL2 decreases to 0, the on-signal output circuit 51 in FIG. 8 outputs an on-signal Son1 at an H level. After time t10, inductor current IL2 continues to decrease and becomes a negative value.

At time t10, NMOS transistor 36 turns off, and the positive inductor current IL2 decreases and reaches zero, causing resonance in inductor 33 and parasitic capacitor 38. As a result, the drain-source voltage Vds of NMOS transistor 36 decreases, and a negative inductor current IL2 flows.

At time t11, which is the delay period Tzcd after time t10, the drive circuit 56 outputs an H-level voltage Vo2 based on the delayed on signal Son2. Therefore, the NMOS transistor 36 turns on.

When the NMOS transistor 36 turns on in response to the H-level on signal Son2, the inductor current IL2 flowing through the inductor 33 increases.

Then, the drive circuit 56 keeps the NMOS transistor 36 on from time t11 until time t13, when the period Ton2 = Ton1 + ΔTon has elapsed, based on the second command value Vc2 obtained by correcting the first command value Vc1 using the correction circuit 64c.

In Figure 10, to clearly show the period ΔTon, time t12, which is the time period Ton1 after time t11, is also shown. At time t13, inductor current IL2 reaches its maximum value ILp2.

After time t13, the drive circuit 56 outputs an L-level voltage Vo2. As a result, the NMOS transistor 36 turns off.

Furthermore, at time t14, the inductor current IL2 decreases again to 0. Here, a period Toff elapses from time t13 to time t14, when the NMOS transistor 36 is turned off, until the inductor current IL2 indicates 0. At time t14, the on signal output circuit 51 again outputs an H-level signal Son1.

As described above, in the AC-DC converter 10b of this embodiment, the NMOS transistor 36 is on from time t11 to time t13. This is a period ΔTon longer than the on period of the NMOS transistor 36 in the AC-DC converter 10a of Figure 3.

In this way, in the AC-DC converter 10b of this embodiment, the NMOS transistor 36 is turned on for a period of ΔTon, causing a positive current that offsets the contribution of the negative current value in the inductor current IL2 to flow for a long period of ΔTon + (Toff - Toff1). This reduces the period during which the current Iin is 0, eliminating the dead angle.

As a result, distortion of the waveform of current Iin from a sine wave is eliminated, improving the power factor.

<<Power factor correction IC 35c according to Example 2>>
11 shows the power factor correction IC 35c. The following mainly describes the differences between the power factor correction IC 35b and the power factor correction IC 35a. The power factor correction IC 35c includes a correction circuit 64b.

The AC-DC converter configuration with power factor correction IC 35c is the same as that of AC-DC converter 10b shown in Figure 7, except that power factor correction IC 35b is replaced with power factor correction IC 35c, with the remaining configuration remaining the same. Therefore, a diagram of the AC-DC converter is omitted.

In this embodiment, the ADC 53 converts the voltage Vfb into a digital value and inputs the converted value to the correction circuit 64b.

In this embodiment, the correction circuit 64b uses the voltage Vfb as an input value to derive the second command value Vc2.

Details of the correction circuit 64b
The calculations performed by the correction circuit 64b are described in detail below. The correction circuit 64b is a circuit that embodies the correction of the period Ton2 according to Principle 1-2.

Figure 12 shows an example of the configuration of the correction circuit 64b. The correction circuit 64b includes an estimation circuit 81, a calculation circuit 82, a correction value output circuit 83, and a second command value output circuit 84.

The estimation circuit 81 calculates the estimated value Vres1 of the rectified voltage Vr, expressed by equation (4). Specifically, the estimation circuit 81 calculates the estimated value Vres1 of the rectified voltage Vr based on data D(Toff) corresponding to the period Toff, the second command value Vc2, and the voltage Vfb corresponding to the voltage Vout.

Vres1=Vout×[Toff/(Ton2+Toff)]...(4)
The estimation circuit 81 also outputs an estimated value Vres1 based on the ratio expressed by equation (4) to the calculation circuit 82.

The calculation circuit 82 calculates the voltage ratio expressed by equation (5). Specifically, the calculation circuit 82 calculates the voltage ratio based on the voltage Vout and the estimated value Vres1, based on the voltage Vfb corresponding to the voltage Vout and the estimated value Vres1.

(Vout-Vres1)/Vres1...(5)
Furthermore, the arithmetic circuit 82 outputs data D [(Vout−Vres1)/Vres1] according to the voltage ratio to the correction value output circuit 83 .

The correction value output circuit 83 calculates the correction value ΔTon expressed by equation (6) based on data D(Tzcd) corresponding to the period Tzcd, data D[(Vout-Vres1)/Vres1], and a constant (2/ ^π2 ) stored in the correction value output circuit 83. Specifically, the correction value output circuit 83 multiplies the constant (2/ ^π2 ), the period Tzcd, and the ratio (Vout-Vres1)/Vres1 by each other to calculate the correction value ΔTon for the period Ton1.

ΔTon=(2/π ² )×Tzcd×(Vout-Vres1)/Vres1...(6)
Furthermore, the correction value output circuit 83 outputs data D(ΔTon) corresponding to the correction value ΔTon to the second command value output circuit 84 .

The second command value output circuit 84 calculates the period Ton2 expressed by equation (7). Specifically, the second command value output circuit 84 calculates the period Ton2 by correcting the period Ton1 with the correction value ΔTon based on the first command value Vc1 corresponding to the period Ton1 and the correction value ΔTon.

Ton2=Ton1+ΔTon…(7)
Furthermore, the second command value output circuit 84 outputs a second command value Vc2 corresponding to the period Ton2 to the drive circuit 56.

As described above, the correction circuit 64b can also output the second command value Vc2 with the period Ton1 corrected. This allows the power factor correction IC 35c to obtain a waveform of the inductor current IL2 similar to that shown in Figure 10.

Note that the arithmetic circuit 82 corresponds to the "second arithmetic circuit."

<<AC-DC converter 10c according to third embodiment>>
Fig. 13 shows an example of a circuit diagram of an AC-DC converter 10c according to this embodiment. Components denoted by the same reference numerals as those in the AC-DC converter 10b in Fig. 7 correspond to the same components. The following mainly describes the differences between the AC-DC converter 10c and the AC-DC converter 10b.

In addition to the components of AC-DC converter 10b, AC-DC converter 10c includes a power factor correction IC 35d and resistors 44 and 45. Furthermore, power factor correction IC 35d includes a terminal RDIV in addition to the terminals CS, FB, OUT, and RT of power factor correction ICs 35b and 35c.

One end of resistor 44 is connected to the node between capacitor 31 and inductor 33, and the other end is connected to resistor 45. Resistors 44 and 45 form a voltage divider circuit that divides the rectified voltage Vr.

The node between resistors 44 and 45 is connected to terminal RDIV. A voltage Vrdiv obtained by dividing the rectified voltage Vr is applied to terminal RDIV.

Here, terminal RDIV corresponds to the "second terminal" and voltage Vrdiv corresponds to the "third voltage."

<<Power factor correction IC 35d according to the third embodiment>>
14 shows an example of the configuration of a power factor correction IC 35d. The power factor correction IC 35d includes a correction circuit 64c and an ADC 65.

The ADC 65 converts the voltage Vrdiv, which corresponds to the rectified voltage Vr applied to the terminal RDIV, into a digital value. For convenience, the digital value output from the ADC 65 will be referred to as the voltage Vrdiv below. The ADC 65 inputs the digital value Vrdiv to the correction circuit 64c.

Details of the correction circuit 64c
The configuration of the correction circuit 64c will be described in detail below. The correction circuit 64c is a circuit that embodies the correction of the period Ton2 according to Principle 1-3.

Figure 15 shows an example of the configuration of the correction circuit 64c. The correction circuit 64c includes a calculation circuit 91, a correction value output circuit 92, and a second command value output circuit 93.

The calculation circuit 91 calculates the ratio expressed by equation (8). Specifically, the calculation circuit 91 calculates the voltage ratio based on the voltage Vfb corresponding to the voltage Vout and the voltage Vrdiv corresponding to the voltage Vr.

(Vout-Vr)/Vr...(8)
Furthermore, the arithmetic circuit 91 outputs data D[(Vout−Vr)/Vr] according to the voltage ratio to the correction value output circuit 92 .

The correction value output circuit 92 calculates the correction value ΔTon expressed by equation (9) based on data D(Tzcd) corresponding to the period Tzcd, data D[(Vout-Vr)/Vr], and a constant (2/ ^π2 ) stored in the correction value output circuit 72. Specifically, the correction value output circuit 92 multiplies the constant (2/ ^π2 ), the period Tzcd, and the ratio (Vout-Vr)/Vr to calculate the correction value ΔTon for the period Ton1.

ΔTon=(2/π ² )×Tzcd×(Vout-Vr)/Vr...(9)
Furthermore, the correction value output circuit 92 outputs data D(ΔTon) corresponding to the correction value ΔTon to the second command value output circuit 93 .

The second command value output circuit 93 calculates the period Ton2 expressed by equation (10). Specifically, based on the first command value Vc1 corresponding to the period Ton1 input from the first command value output circuit 55 and the correction value ΔTon input from the correction value output circuit 92, the second command value output circuit 93 calculates the period Ton2 by correcting the period Ton1 with the correction value ΔTon.

Ton2=Ton1+ΔTon...(10)
Furthermore, the second command value output circuit 93 outputs a second command value Vc2 corresponding to the period Ton2 to the drive circuit 56.

As described above, the correction circuit 64c can also output the second command value Vc2 with the period Ton1 corrected. This allows the power factor correction IC 35d to obtain a waveform of the inductor current IL2 similar to that shown in Figure 10.

Note that the arithmetic circuit 91 corresponds to the "third arithmetic circuit."

<<Power factor correction IC 35e according to Example 4>>
16 shows an example of the configuration of the power factor correction IC 35 e. The power factor correction IC 35 e includes a memory circuit 95 .

Power factor correction IC 35e has a configuration similar to power factor correction IC 35b, except that it includes a memory circuit 95, but does not include terminal RT, current source 61, or delay period setting circuit 62. While resistor 43 was connected to terminal RT of power factor correction IC 35b, power factor correction IC 35e does not include terminal RT, and therefore an AC-DC converter including power factor correction IC 35e does not include resistor 43 either.

The memory circuit 95 records the period Tzcd based on the inductance L of the inductor 33 and the capacitance C of the capacitor that resonates the inductor current IL2 together with the inductance L (e.g., the capacitance of the parasitic capacitor 38). Based on the inductance L and capacitance C, the memory circuit 95 records the period Tzcd that satisfies the following equation (11).

Tzcd=π×√(L・C)...(11)
Based on the period Tzcd of equation (11), the delay circuit 52 delays the ON signal Son1 and outputs the ON signal Son2. In this embodiment, the correction circuit 64a also performs correction based on data D(Tzcd) corresponding to this period Tzcd, using a process similar to the process already described in Fig. 9. This also allows the power factor correction IC 35e to perform the correction of the period Ton2 described in principle 2 of Fig. 6.

In this embodiment, the memory circuit 95 is provided inside the power factor correction IC 35e. The delay circuit 52 is connected to the memory circuit 95.

However, the memory circuit 95 may also be a memory device provided external to the power factor correction IC 35e. In this case, the delay circuit 52 is connected to an external connection terminal (not shown) of the power factor correction IC 35e. The external connection terminal (not shown) is connected to a memory device external to the power factor correction IC 35e.

Note that memory circuit 95 corresponds to the "first memory circuit."

<<Power factor correction IC 35f according to Example 5>>
17 shows an example of the configuration of the power factor correction IC 35 f. The power factor correction IC 35 f includes a memory circuit 95.

Power factor correction IC 35f has a configuration similar to power factor correction IC 35c, except that it includes a memory circuit 95, but does not include terminal RT, current source 61, or delay period setting circuit 62. Furthermore, an AC-DC converter including power factor correction IC 35f does not include resistor 43.

The storage circuit 95 sets the period Tzcd in the delay circuit 52 so as to satisfy the formula (11).
Tzcd=π×√(L・C)...(11)
The delay circuit 52 outputs an ON signal Son2 using the period Tzcd of equation (11) and outputs data D(Tzcd) to the correction circuit 64b. The correction circuit 64b outputs the second command value Vc2 based on this D(Tzcd) through a process similar to that shown in FIG. 11. This allows the power factor correction IC 35f to perform the correction of the period Ton2 described in principle 2 of FIG. 6.

In this embodiment, the memory circuit 95 is provided inside the power factor correction IC 35f, but it may also be a memory device provided outside the power factor correction IC 35f.

<<Power factor improvement IC 35g according to Example 6>>
18 shows an example of the configuration of the power factor correction IC 35g. The power factor correction IC 35g includes a memory circuit 95.

Power factor correction IC 35g has a configuration similar to power factor correction IC 35d, except that it includes a memory circuit 95, but does not include terminal RT, current source 61, or delay period setting circuit 62. Furthermore, an AC-DC converter including power factor correction IC 35g does not include resistor 43.

The storage circuit 95 sets the period Tzcd in the delay circuit 52 so as to satisfy the formula (11).
Tzcd=π×√(L・C)...(11)
The delay circuit 52 outputs an ON signal Son2 using the period Tzcd of equation (11) and outputs data D(Tzcd) to the correction circuit 64c. The correction circuit 64c outputs the second command value Vc2 based on this D(Tzcd) through a process similar to that shown in FIG. 11. This allows the power factor correction IC 35g to perform the correction of the period Ton2 described in principle 2 of FIG. 6.

In this embodiment, the memory circuit 95 is provided inside the power factor correction IC 35g, but it may also be a memory device provided outside the power factor correction IC 35g.

In each of the power factor correction ICs 35b to 35g according to the embodiment, the voltages Vcs, Vfb, and Vrdiv are AD converted by the ADCs 50, 53, and 65, and then processed to output the voltage Vo2. Here, in the power factor correction ICs 35b to 35g, some or all of the processing performed after AD conversion by the ADCs 35, 53, and 65 may be performed by software. Specifically, instead of the power factor correction IC 35a, it may be performed by a microcomputer or a DSP with a core and memory.

<<Power factor correction IC 35h according to Example 7>>
19 shows an example of the configuration of a power factor correction IC 35h. The power factor correction IC 35h is an IC used in the AC-DC converter 10b in FIG. 7, similar to the power factor correction ICs 35b and 35c.

The power factor correction IC 35h includes ADCs 50 and 53, an ON signal output circuit 51, a delay circuit 52, an error amplifier circuit 54, a first command value output circuit 55, a drive circuit 56, a current source 61, a delay period setting circuit 62, a detection circuit 63, a correction circuit 64d, and a rectified voltage estimation circuit 66. The power factor correction IC 35h further includes terminals RT, CS, FB, and OUT.

That is, compared to the power factor correction IC 35b in FIG. 11, the power factor correction IC 35h includes a correction circuit 64d instead of the correction circuit 64b, and also includes a rectified voltage estimation circuit 66.

The rectified voltage estimation circuit 66 of the power factor correction IC 35h estimates the rectified voltage Vr using a method different from that of the estimation circuit 81 of the correction circuit 64b in FIG. 12, and outputs the estimated value Vres2. The rectified voltage estimation circuit 66 estimates the rectified voltage Vr based on the voltage Vfb, the period Ton2, and the period Toff from when the NMOS transistor 36 turns off until the inductor current IL becomes zero.

In addition, the correction circuit 64d calculates a correction value ΔTon for the period Ton1 for turning on the NMOS transistor 36 based on the estimated value Vres2 estimated by the rectified voltage estimation circuit 66, and outputs a command value Vc2 corresponding to the period Ton2 for turning on the NMOS transistor 36.

Here, the rectified voltage estimation circuit 66 corresponds to the "second estimation circuit."

Figure 20 shows an example of the configuration of a rectified voltage estimation circuit 66a. The rectified voltage estimation circuit 66a is one embodiment of the rectified voltage estimation circuit 66 in Figure 19.

Overview of the Rectified Voltage Estimation Circuit 66a
Here, the rectified voltage Vr is a voltage obtained by full-wave rectifying the AC voltage Vac, from which noise has been removed, using the inductor 21 and capacitor 22 in the AC-DC converter 10b in Fig. 7. The rectified voltage Vr is expressed as Vr = |Vrp × sin(ω × t + θ)|, where Vrp is the amplitude, ω is the frequency, and θ is the waveform sin(ω × t + θ).

However, when ω×t+θ is a phase angle close to 180m degrees (m is an integer), the waveform sin(ω×t+θ) becomes small. For example, when it is ±10+180m degrees, the rectified voltage Vr and input current Iin become "low phase."

In this case, a deviation may occur in the proportional relationship previously established between the output voltage Vout and rectified voltage Vr of inductor 33 L and the periods Ton2 and Toff1. For example, resonance between the inductance L of inductor 33 and the parasitic capacitance of NMOS transistor 36 or the like may lengthen the period Toff, and the effect of resonance becomes greater at low phases. As a result, a deviation may occur in relationship equations such as (Vout - Vr)/Vr = Ton2/Toff or Vres1 = Vout x [Toff/(Ton2 + Toff)].

On the other hand, when ω×t+θ is a phase angle close to 90+180m, the deviation in the relationship between the output voltage Vout and rectified voltage Vr and the periods Ton2 and Toff1 becomes smaller. For example, when the phase angle is between 80 and 110+180m degrees, the rectified voltage Vr and input current Iin become "high phase."

Therefore, the rectified voltage estimation circuit 66a estimates the amplitude Vrp of the rectified voltage Vr when ω×t+θ is a phase angle close to 90+180m degrees. In particular, the rectified voltage estimation circuit 66a estimates the amplitude Vrp of Vr when the period Toff reaches a peak value Toffp in a half cycle of the rectified voltage Vr.

The rectified voltage estimation circuit 66a multiplies the amplitude Vrp estimated using equation (15) by the separately estimated waveform sin(ω × t + θ) at the peak value Toffp of the period Toff. This allows the rectified voltage estimation circuit 66a to accurately estimate the rectified voltage Vr even when the rectified voltage Vr is in low phase.

===Configuration of rectified voltage estimation circuit 66a===
The rectified voltage estimation circuit 66 a includes a peak determination circuit 111 a , an amplitude estimation circuit 112 , a frequency estimation circuit 113 a , a phase output circuit 114 , and an output circuit 115 .

The peak determination circuit 111a detects the peak value of the period Toff corresponding to the command value Vc2 each time the period Toff reaches a peak, based on the period Toff data D(Toff) output by the detection circuit 63 in Figure 18. The peak determination circuit 111a also outputs a pulsed signal θinp that goes to an H level each time the period Toff reaches a peak, as a determination result.

The peak determination circuit 111a determines, for example, the inflection point where the change in time of the period Toff changes from positive to negative as the peak.

The amplitude estimation circuit 112 estimates the amplitude Vrp of the rectified voltage Vr based on the voltage Vfb, the peak value Toffp, and the command value Vc2 corresponding to the period Ton2.

Here, when the NMOS transistor 36 is turned on for the period Ton2, the relationship shown in equation (12) holds between the maximum value ILp2 (see FIG. 10) of the inductor current IL2 flowing through the inductor 33 having the inductance L and the amplitude Vrp, which is the maximum value of the rectified voltage Vr.
ILp2=(Vrp×Ton2)/L...(12)

Furthermore, the NMOS transistor 36 is turned off for the peak value Toffp of the period Toff, and the inductor current IL2 becomes zero.

Here, the higher the phase angle of the rectified voltage Vr and the inductor current IL2, the longer the period Toff from when the NMOS transistor 36 is turned off until the inductor current IL2 becomes zero. For example, when the phase angle is 90 degrees (or 270 degrees, 450 degrees, etc.), the rectified voltage Vr reaches its maximum amplitude Vrp. At this time, the inductor current IL2 also increases, so the period Toff from when the NMOS transistor 36 is turned off until it becomes zero also reaches its peak value Toffp. Therefore, at the phase angle at which the rectified voltage Vr reaches its amplitude Vrp, the period Toff also reaches its peak value Toffp.

In this case, equation (13) holds between the peak value Toffp, the inductance L of the inductor 33, the maximum value ILp2 of the inductor current IL2, the output voltage Vout, and the amplitude Vrp of the rectified voltage Vr.
Toffp=(L×ILp2)/(Vout-Vrp)...(13)

Based on equations (12) and (13), the amplitude estimation circuit 112 estimates the amplitude Vrp, assuming that the amplitude Vrp satisfies equation (14).
Vrp=Vout/(1+(Ton2/Toffp))...(14)

The frequency estimation circuit 113a estimates the frequency ω of the rectified voltage Vr by timing the period between multiple peak values Toffp based on the H-level signal θinp. Here, the period between peak values Toffp is a half-cycle Tin, which corresponds to a phase angle of 180 degrees of the rectified voltage Vr. As will be described in more detail below, the frequency estimation circuit 113a can estimate the frequency ω using the relational expression frequency ω = 2π/2Tin by timing the half-cycle Tin.

The phase output circuit 114 outputs the phase θ of the rectified voltage Vr based on the H-level signal θinp and the estimated frequency ω.

Specifically, in response to the H-level signal θinp, the phase output circuit 114 measures the elapsed time since the period Toff reached its peak value Toffp. The phase output circuit 114 calculates the phase angle of the rectified voltage Vr by considering the timing at which the period Toff reached its peak value Toffp as the timing at which the phase angle of the rectified voltage Vr reaches 90±180m degrees. In particular, based on the elapsed time from the timing at which the phase angle of the rectified voltage Vr reaches 90±180m degrees, the phase output circuit 114 calculates that the phase angle of the rectified voltage Vr is (elapsed time/half cycle Tin)×180 degrees. As a result, the phase output circuit 114 outputs information about the phase θ of the rectified voltage Vr.

The output circuit 115 outputs an estimated value Vres2 of the rectified voltage Vr based on the estimated amplitude Vrp, the estimated frequency ω, and the phase information. Furthermore, the output circuit 115 includes a waveform output circuit 121 and a multiplication circuit 122.

Here, the waveform output circuit 121 outputs the waveform |sin(ω×t+θ)| of the rectified voltage Vr based on the estimated frequency ω and phase information. Furthermore, the multiplication circuit 122 outputs the rectified voltage Vr = |Vrp×sin(ω×t+θ)| calculated by multiplying the estimated amplitude Vrp by the waveform |sin(ω×t+θ)|.

===Operation of the Rectified Voltage Estimation Circuit 66a===
The operation of the rectified voltage estimation circuit 66a will be described with reference to Figures 21 and 22. Figure 21 is a flowchart illustrating the operation of the rectified voltage estimation circuit 66a, and Figure 22 illustrates the main waveforms in the operation of the rectified voltage estimation circuit 66a. For convenience of illustration, the peak value Toffp of the period Toff is shown as the same value in Figure 22.

In the following explanation, we will assume that this is time t23, which is after time t22 in Figure 22.

Note that hereafter, the peak values Toffp of Toff at times t21 and t22 will be referred to as peak values Toffpk-1 and Toffk. Here, Toffpk-1 is the (k-1)th peak value, and Toffk is the kth peak value (k is a natural number greater than or equal to 2).

The amplitude estimation circuit 112 estimates the amplitude Vrpk of the rectified voltage Vr based on the voltage Vfb corresponding to the voltage Vout, the second command value Vc2 corresponding to the period Ton2, and, for example, the peak value Toffk at time t22 (S1). Here, since the amplitude Vrp satisfies equation (14), the amplitude Vrpk at time t22 is estimated as Vrpk = Vout/(1 + (Ton2/Toffpk)).

The frequency estimation circuit 113a estimates the frequency ωk of the rectified voltage Vr based on, for example, the period between time t21 when the k-1th peak value Toffpk is determined and time t22 when the kth peak value Toffpk is determined (S2).

Specifically, the frequency estimation circuit 113a starts timing in response to the H-level signal θinp, and measures the period Tin until the next H-level signal θinp is input.

The frequency estimation circuit 113a then determines this period as the half-cycle Tink of the kth rectified voltage Vr, calculates the kth frequency ωk using ωk = 2π/(2 × Tink), and outputs the frequency ωk data.

Note that, here, the frequency estimation circuit 113a estimates the frequency ωk based on the time of the k-1th peak value Toffpk-1 and the time of the kth peak value Toffpk each time a peak value is determined, but this is not limited to this. For example, the frequency estimation circuit 113a may use the average value of multiple frequencies estimated in the past as the estimation result.

In addition, the frequency of the AC voltage Vac is generally a predetermined specified frequency (e.g., 50 Hz or 60 Hz). Therefore, the frequency estimation circuit 113a may select the specified frequency closest to the estimated frequency and output the selection result to the waveform output circuit 121 as the frequency ωk.

The phase output circuit 114 outputs information about the phase θk of the rectified voltage Vr at time t23 (S3).

Specifically, in response to the H-level signal θinp, the phase output circuit 114 starts timing by assuming that the phase angle of the rectified voltage Vr has reached 90+180k degrees at time t22.

Here, the phase output circuit 114 can read the half-period Tink from the frequency ωk output by the frequency estimation circuit 113a. Therefore, the phase output circuit 114 can calculate the phase angle of the rectified voltage Vr from time t22 onwards as (elapsed time t/Tink) x 180 degrees.

As a result, the phase output circuit 114 outputs information about the phase θk of the rectified voltage Vr at time t23, for example.

Next, the waveform output circuit 121 outputs the waveform |sin(ωk×t+θk)| of the rectified voltage Vr based on the information on the wave number ωk and phase θk (S4). Furthermore, the multiplication circuit 122 outputs the estimated value Vres2 = |Vrpk×sin(ωk×t+θk)|, calculated by multiplying the amplitude Vrpk by the waveform |sin(ωk×t+θk)|. As a result, the rectified voltage estimation circuit 66a outputs the estimated value Vres2 (S5).

===Configuration of correction circuit 64d===
23 shows an example of the configuration of the correction circuit 64d. The correction circuit 64d includes an arithmetic circuit 131, a correction value output circuit 132, and a second command value output circuit 133.

The calculation circuit 131 calculates the ratio (Vout - Vres2)/Vres2 based on the estimated value Vres2 of the rectified voltage Vr and the voltage Vfb corresponding to the voltage Vout, and outputs data D[(Vout - Vres2)/Vres2] relating to the ratio.

The correction value output circuit 132 calculates the correction value ΔTon based on the data D(Tzcd), the data D[(Vout-Vres2)/Vres2], and a constant (2/π ² ) stored in the correction value output circuit 132. The correction value output circuit 132 outputs the correction value ΔTon based on ΔTon=(2/π ² )×Tzcd×(Vout-Vres2)/Vres2.

The second command value output circuit 133 outputs a period Ton2 based on the command value Vc1 corresponding to the period Ton1 and the correction value ΔTon, where Ton2 = Ton1 + ΔTon.

Here, the arithmetic circuit 131 corresponds to the "third arithmetic circuit."

As described above, in the correction circuit 64d, the period Ton2 is calculated based on the estimated value Vres2 of the voltage Vr when the period Toff reaches its peak and the phase angle is close to 90±180 m°. Therefore, even when the phase angle is low, an appropriate period Ton2 is set to offset the negative value of the inductor current Il2 in Figure 6.

The drive circuit 56 of the power factor correction IC 35h in Figure 19 can output a signal Vo2 to turn on the NMOS transistor 36 based on the period Ton2. This allows the AC-DC converter including the power factor correction IC 35h to eliminate the dead angle of the inductor current IL2 and improve the power factor.

===Configuration of rectified voltage estimation circuit 66b===
24 shows an example of the configuration of a rectified voltage estimation circuit 66b, which is one embodiment of the rectified voltage estimation circuit 66 shown in FIG.

The rectified voltage estimation circuit 66b includes a peak determination circuit 111b, an amplitude estimation circuit 112, a frequency estimation circuit 113b, a phase output circuit 114, an output circuit 115, and a memory circuit 116. That is, the rectified voltage estimation circuit 66b differs from the rectified voltage estimation circuit 66a in that it includes a peak determination circuit 111b instead of the peak determination circuit 111a, a frequency estimation circuit 113b instead of the frequency estimation circuit 113a, and a memory circuit 116.

When the peak determination circuit 111b determines a new peak value (e.g., the kth peak value Toffpk) based on the recorded half period Tin, it performs a selection process to determine whether or not to use the new peak value Toffk in subsequent estimations.

Here, the timing corresponding to the peak value Toffpk is T2, and the timing corresponding to the previous (i.e., kth) peak value Toffpk-1 is T1.

The peak determination circuit 111b compares, for example, an average value Tave of the multiple half periods Tin stored in the memory circuit 116 (described later) with T2-T1,
Determine the peak.

When T2-T1 is within a certain percentage (for example, 20%) of the average value Tave, the peak determination circuit 111b determines that the peak value Toffpk should be used for subsequent estimation. On the other hand, when T2-T1 is outside this range, the peak determination circuit 111b uses the value of the period Toff, which is half a cycle Tin after T1, as the peak value for subsequent estimation instead of Toffpk.

Note that although the peak determination circuit 111b uses the average value Tave, it may also use the value of the half period corresponding to the specified frequency (50 Hz or 60 Hz) selected based on the average value Tave.

Each time the frequency estimation circuit 113b estimates a frequency, it stores half the period corresponding to the estimated frequency as the half period Tin in the memory circuit 116.

The memory circuit 116 records the half-period Tin of the rectified voltage Vr. The operation of these circuits included in the rectified voltage estimation circuit 66b will be described in detail below with reference to Figures 25 to 27.

===Operation of the Rectified Voltage Estimation Circuit 66b===
Fig. 25 explains the operation of the rectified voltage estimation circuit 66b. The flowchart in Fig. 25 differs from Fig. 21 in that it includes steps S10 and S11.

Details of Step S10
The operation of the rectified voltage estimation circuit 66a will be described with reference to Figures 26 and 27. Figure 26 is a flowchart illustrating the operation of the rectified voltage estimation circuit 66a in step S10, and Figure 27 shows waveforms for illustrating the operation of the rectified voltage estimation circuit 66a.

For ease of illustration, in Figure 27, the peak value Toffp for the period Toff is shown as the same value except for that at t33. The peak value at time t31 is the (k-2)th peak value Toffpk-2, and the peak values at times t32 and t33 are the (k-1)th peak value Toffpk-1 and the kth peak value Toffpk, respectively (where k is a natural number greater than or equal to 3).

When the peak determination circuit 111b determines the kth peak value Toffpk, it calculates the period T2-T1 between the timing T2 (time t33) of the peak value Toffpk and the timing T1 (time t32) when the previous (i.e., the k-1th) peak value Toffpk-1 was determined (S21).

Here, the kth peak value Toffk corresponds to the "first peak value," and the k-1th peak value Toffpk-1 corresponds to the "second peak value."

The peak determination circuit 111b reads the value of the half period Tin for the past peak recorded from the memory circuit 116b and calculates the average value Tave. Furthermore, it determines whether the period T2-T1 is within 20% of the period Tave (S22). That is, the peak determination circuit 111b determines whether 0.8Tave≦T2-T1≦1.2Tave is satisfied. If it is within the 20% range, proceed to S24; if it is not within the 20% range, proceed to S23.

In Figure 27, the kth peak value Toffpk is the peak Toffpk determined at t33. This peak occurs, for example, when there is a sudden change in the AC voltage Vac or the state of the load 11 connected to the AC-DC converter.

Here, if time t33 is T2 and time T32 is T1, T2 - T1 does not satisfy 0.8Tin ≦ T2 - T1 ≦ 1.2Tin. Therefore, in the example of Figure 27, processing proceeds to step S23.

Here, the 20% ratio is an example, and this ratio is not limited to 20% and may be set to 30% or 10%. In each of these cases, the peak determination circuit 111b determines whether the period T2-T1 is within the range 0.7 Tave≦T2-T1≦1.3 Tave, or whether it is within the range 0.9 Tave≦T2-T1≦1.1 Tave. Note that 20% corresponds to a "predetermined ratio" from the "half cycle."

In the example of Figure 27, because 0.8Tin≦T2-T1≦1.2Tin is not satisfied, the peak determination circuit 111b does not output the peak value Toffpk at time t33. Instead, the peak determination circuit 111b outputs Toff at time t34, which is half a cycle Tin after time t33 (timing T1), as the peak value (S23).

As a result, the peak determination circuit 111b determines that the peak at t33 in Figure 27 is an outlier peak caused by noise or the like. In this way, the peak determination circuit 111b can execute peak value selection processing that does not output outlier peak values. After S23, processing S10 ends.

On the other hand, if 0.8Tin≦T2-T1≦1.2Tin is met (which is not the case in the example of Figure 27), the peak determination circuit 111b outputs the peak value Toffpk (S24). After S24, process S10 ends.

When process S10 is completed, processes S1 and S2 in Figure 25 are performed. These processes are similar to the processes of the steps referenced by the same reference numerals in Figure 21. However, in the example of Figure 27, Toff at time t34 is output as the peak value in S23, and this value is also used as Toffpk in S1.

After S2, the frequency estimation circuit 113b stores half the period corresponding to the estimated frequency ωk as a half period Tink in the memory circuit 116 (S11). The subsequent steps S3 to S5 are similar to the steps referenced by the same reference numerals in Figure 21.

As described above, the rectified voltage estimation circuit 66b can exclude, as an outlier, a peak value Toffpk that occurs due to, for example, a sudden change in the AC voltage Vac or load. Therefore, in the rectified voltage estimation circuit 66b, the peak determination circuit 111b more accurately determines the peak value Toffp of the period Toff, and the estimation of the rectified voltage Vr based on the period Toffp also becomes more accurate.

This allows the correction circuit 64d to appropriately set the period Ton2 during which the NMOS transistor 36 is turned on, allowing the AC-DC converter including the power factor correction IC 35h to improve the power factor.

===Configuration of rectified voltage estimation circuit 66c===
28 shows an example of the configuration of a rectified voltage estimation circuit 66c, which is one embodiment of the rectified voltage estimation circuit 66 shown in FIG.

The rectified voltage estimation circuit 66c includes a peak determination circuit 111a, an amplitude estimation circuit 112, a frequency estimation circuit 113a, a phase output circuit 114, an output circuit 115, and a memory circuit 117. That is, the rectified voltage estimation circuit 66c differs from the rectified voltage estimation circuit 66a in that it includes a memory circuit 117 connected to a waveform output circuit 121.

In the rectified voltage estimation circuit 66c, the operation of the waveform output circuit 121 after the frequency estimation circuit 113a outputs the frequency ω and the phase output circuit 114 outputs the phase information differs from that of the rectified voltage estimation circuit 66a.

The memory circuit 117 stores a table TB|sin(ω×t+θ)| of waveform data |sin(ω×t+θ)| of the rectified voltage Vr with normalized amplitude Vrp.

The waveform output circuit 121 can therefore read the waveform data table TB |sin(ω×t+θ)| from the memory circuit 117 based on the frequency of the rectified voltage Vr (e.g., 50 Hz or 60 Hz) and information about the input phase detected from the timing when the period Toff reaches its peak value Toffp. This allows the waveform output circuit 121 to output the waveform data |sin(ω×t+θ)| of the rectified voltage Vr. In this way, the output circuit 115 uses the waveform data |sin(ω×t+θ)| to output the estimated value Vres2 of the rectified voltage Vr.

The operation of the other circuits in the rectified voltage estimation circuit 66c is the same as that of the rectified voltage estimation circuit 66a.

In the rectified voltage estimation circuit 66c, the waveform output circuit 121 can acquire waveform data from the memory circuit 117, reducing the amount of calculations required in the power factor correction IC 35h.

The rectified voltage estimation circuit 66c also properly estimates the rectified voltage Vr, and the correction circuit 64d can set the period Ton2 based on the estimated value Vres2. Therefore, even when using the rectified voltage estimation circuit 66c, an AC-DC converter including a power factor correction IC 35h can improve the power factor.

Here, memory circuit 117 corresponds to the "second memory circuit."

<<Power factor correction IC 35i according to Example 8>>
29 shows an example of the configuration of the power factor correction IC 35i. The power factor correction IC 35i includes ADCs 50 and 53, an ON signal output circuit 51, a delay circuit 52, an error amplifier circuit 54, a first command value output circuit 55, a drive circuit 56, a detection circuit 63, a correction circuit 64d, a memory circuit 95, and a rectified voltage estimation circuit 66. The power factor correction IC 35i also includes terminals CS, FB, and OUT.

The power factor correction IC 35i can be used in the same AC-DC converter as the power factor correction IC 35f in Figure 17. In the power factor correction IC 35i, as in the power factor correction IC 35f, the memory circuit 95 sets the period Tzcd that satisfies equation (11).

Compared to the power factor correction IC 35f, the power factor correction IC 35i includes a correction circuit 64d instead of the correction circuit 64b, and also includes a rectified voltage estimation circuit 66. That is, in the power factor correction IC 35i, similar to the power factor correction IC 35h in FIG. 19, the rectified voltage estimation circuit 66 estimates the rectified voltage Vr and outputs the estimated value Vres2.

Furthermore, the correction circuit 64d calculates a correction value ΔTon for the period Ton1 for turning on the NMOS transistor 36 based on the estimated value Vres2, and outputs a command value Vc2 corresponding to the period Ton2 for turning on the NMOS transistor 36.

In the power factor correction IC 35i, similarly to the power factor correction IC 35f of FIG. 17, the memory circuit 95 sets the period Tzcd that satisfies the formula (11) in the delay circuit 52.
Tzcd=π×√(L・C)...(11)

In the power factor correction IC 35i, even when the memory circuit 95 sets the delay period Tzcd, the correction circuit 64 can appropriately set the period Ton2 based on the estimated value Vres2, just like the power factor correction IC 35h. Therefore, an AC-DC converter including the power factor correction IC 35i can also eliminate the dead angle of the inductor current IL2 and improve the power factor.

In each of the power factor correction ICs 35h and 35i, the voltages Vcs and Vfb are AD converted by the ADCs 50 and 53, and then processing is performed up to outputting the voltage Vo2. Here, in the power factor correction ICs 35h and 35i, some or all of the processing performed after AD conversion by the ADCs 35 and 53 may be performed by software.

===Summary===
The AC-DC converters 10b and 10c and the power factor correction ICs 35b to 35g of this embodiment have been described above.

In power factor correction ICs 35b to 35g, the on-signal Son1 of NMOS transistor 36 is delayed to reduce switching loss in NMOS transistor 36. This configuration allows the on-period Ton2 of NMOS transistor 36 to be properly corrected to account for the decrease in inductor current IL2 that occurs due to the delay in on-signal Son1, thereby improving the power factor.

The power factor correction ICs 35b to 35d also include a terminal RT to which a voltage Vrt corresponding to the predetermined period Tzcd is applied, and a delay period setting circuit 62 that sets the predetermined period Tzcd in the delay circuit 52 based on the voltage Vrt.

This allows the period Tzcd to be set appropriately as the delay period relative to the delay period set according to the voltage Vrt generated at terminal RT.

In addition, power factor correction ICs 35b to 35d include a current source 61, which is a bias current source that supplies a predetermined current Tzcd to terminal RT, and resistor 43 is connected to terminal RT.

This allows the period Tzcd to be set as a delay period according to the resistance value of resistor 43 provided externally to power factor correction ICs 35b to 35d.

Furthermore, in the power factor correction ICs 35e to 35g, the delay circuit 52 delays the on signal Son1 for a predetermined period Tzcd determined based on the inductance L of the inductor 33 and the capacitance C of the parasitic capacitor 38, which resonates the inductor current IL2 together with the inductor 33.

As a result, in the power factor correction ICs 35e to 35g, resonance based on the inductance L and capacitance C allows the on-period Ton2 of the NMOS transistor 36 to be appropriately set relative to the period Tzcd during which the drain-source voltage Vds of the NMOS transistor 36 is at its minimum value. This makes it possible to both reduce the switching loss of the NMOS transistor 36 and improve the power factor of the AC-DC converter.

In addition, the power factor correction ICs 35e to 35g are equipped with a memory circuit 95 that records the period Tzcd corresponding to the inductance L and capacitance C.

This allows the on-period Ton2 of the NMOS transistor 36 to be appropriately set for the period Tzcd based on the inductance L and capacitance C stored in the memory circuit 95.

In addition, the power factor correction ICs 35b, 35c, 35e, and 35f are equipped with a detection circuit 63 that detects the period Toff based on the timing when the NMOS transistor 36 turns off and the timing when the inductor current IL2 becomes zero.

This allows the power factor correction ICs 35b, 35c, 35e, and 35f to detect the period Toff. Therefore, power factor correction can be achieved without using the voltage Vrdiv based on the rectified voltage Vr as the input to the correction circuits 64a and 64b.

Therefore, there is no need to provide a voltage divider circuit using resistors 43 and 44 to input voltage Vrdiv from AC-DC converter 10b to power factor correction ICs 35b, 35c, 35e, and 35f, reducing the load on the entire circuit. Furthermore, the RDIV terminal can be omitted from power factor correction ICs 35b, 35c, 35e, and 35f.

The correction circuit 64a also includes an arithmetic circuit 71 that divides the period Ton2 by the period Toff to calculate a ratio, a correction value output circuit 72 that multiplies the predetermined period Tzcd by the ratio to output a correction value ΔTon, and a second command value output circuit 73 that outputs a second command value Vc2 based on the first command value Vc1 and the correction value ΔTon.

This allows the correction circuit 64a to calculate the second command value Vc2 for setting the period Ton2 in the drive circuit 56 without using the voltages Vfb and Vr as inputs to the correction circuit 64a.

The correction circuit 64b also includes an estimation circuit 81 that calculates an estimated value Vres1 of the rectified voltage Vr based on the period Ton2, the period Toff, and the voltage Vfb; a calculation circuit 82 that calculates a ratio based on the estimated value Vres1 and the voltage Vfb; a correction value output circuit 83 that multiplies the predetermined period Tzcd by the ratio and outputs a correction value ΔVon; and a second command value output circuit 84 that outputs the second command value based on the first command value Vc1 and the correction value.

This allows the correction circuit 64b to calculate the second command value Vc2 for setting the period Ton2 in the drive circuit 56 without using the voltage Vr as an input to the correction circuit 64b.

In addition, power factor correction ICs 35c and 35g are equipped with a terminal RDIV to which a voltage Vrdiv corresponding to the rectified voltage Vr is applied, and the ratio is calculated based on voltage Vfb and voltage Vrdiv.

This allows the ratio based on the rectified voltage Vr and the output voltage Vout to be directly calculated based on the voltage Vfb and voltage Vrdiv.

The correction circuit 64c also includes an arithmetic circuit 91 that calculates a ratio based on the voltage Vrdiv applied to the terminal RDIV and the voltage Vfb, a correction value output circuit 92 that multiplies the ratio by a predetermined period Tzcd and outputs a correction value ΔTon, and a second command value output circuit 93 that outputs a second command value Vc2 based on the first command value Vc1 and the correction value ΔTon.

In this way, a calculation circuit 91 is shown that directly calculates a ratio based on the rectified voltage Vr and the output voltage Vout based on the voltage Vfb and the voltage Vrdiv, and a configuration is shown for specifically outputting the second command value Vc2 based on the calculation results of the calculation circuit 91.

In another aspect of the present invention, in power factor correction ICs 35b, 35f, 35h, and 35i, the on signal Son1 of NMOS transistor 36 is delayed based on the off period Toff of NMOS transistor 36, an estimated value of rectified voltage Vr in the AC-DC converter, and voltage Vfb.

This allows the drive circuit 56 to turn the NMOS transistor 36 on and off at the appropriate timing based on the period Toff, the estimated value of the rectified voltage Vr, and the voltage Vfb, thereby improving the power factor.

The rectified voltage estimation circuits 66a, 66b, and 66c also include a peak determination circuit 111a or 111b that determines the peak value Toffp of the period Toff based on the period Toff; an amplitude estimation circuit 112 that estimates the amplitude Vrp of the rectified voltage Vr based on the voltage Vfb, the peak value Toffp of the period Toff, and the period Ton2; and an output circuit 115 that outputs an estimated value Vres2 of the rectified voltage Vr based on the estimated amplitude Vrp.

This allows the rectified voltage estimation circuits 66a, 66b, and 66c to provide an estimate of the rectified voltage Vr without using the value of the period Toff when the rectified voltage Vr is in low phase. Therefore, the rectified voltage estimation circuits 66a, 66b, and 66c can more accurately estimate the rectified voltage Vr.

In addition, the rectified voltage estimation circuits 66a, 66b, and 66c include frequency estimation circuits 113a and 113b that estimate the frequency ω of the rectified voltage Vr. The peak determination circuits 111a and 111b determine the peak value Toffp of the period Toff each time the period Toff reaches its peak. The frequency estimation circuits 113a and 113b estimate the frequency ω of the rectified voltage Vr based on the determination results of the peak determination circuits 111a and 111b. The output circuit 115 outputs the rectified voltage Vr based on the estimated frequency ω.

This allows the frequency estimation circuits 113a and 113b to measure the period between the timings indicating the peak value Toffp and estimate the half-period Tin of the rectified voltage Vr. The output circuit 115 can output the waveform |sin(ω×t+θ)| of the rectified voltage Vr based on the period ω estimated by the frequency estimation circuits 113a and 113b.

In addition, the rectified voltage estimation circuits 66a, 66b, and 66c include a phase output circuit 114 that estimates the phase of the rectified voltage Vr based on the determination results of the peak determination circuits 111a and 111b and the estimated frequency ω, and the output circuit 115 outputs the estimated rectified voltage Vr based on the estimated phase.

As a result, the phase output circuit 114 can estimate the phase angle of the rectified voltage Vr at the peak value Toffp as 90 + 180m degrees, based on the time elapsed since the peak value Toffp was reached and the half-period Tin. Therefore, the waveform output circuit 121 can output the waveform |sin(ω×t+θ)| of the rectified voltage Vr based on the phase information output by the phase output circuit 114.

The peak determination circuit 111b outputs the peak value Toffpk if the period T2-T1 between the peak value Toffpk and the peak value Toffpk-1 immediately preceding the peak value Toffpk is within 20% of the half-cycle Tin of the rectified voltage Vr; if the period T2-T1 is not within 20% of the half-cycle Tin, it outputs the third period Toff, which is half-cycle Tin after the peak value Toffpk-1, as the new peak value.

As a result, if the period T2-T1 between peaks significantly deviates from the half-cycle Tin of the rectified voltage Vr, the rectified voltage estimation circuit 66b determines that the peak value Toffpk is an outlier due to erroneous detection caused by noise, etc. Therefore, the rectified voltage estimation circuit 66b can perform a peak value selection process that does not output outliers.

The rectified voltage estimation circuit 66c also includes a memory circuit 117 that records waveform data of the rectified voltage Vr with the amplitude Vrp normalized, and the output circuit 115 uses the waveform data to output the estimated rectified voltage Vr.

This allows the rectified voltage estimation circuit 66c to estimate the rectified voltage Vr without having to perform detailed estimation of the waveform of the rectified voltage Vr or the frequency or phase used to determine the waveform.

The correction circuit 64d also includes an arithmetic circuit 131 that calculates a ratio based on the estimated rectified voltage Vr and the voltage Vfb, a correction value output circuit 132 that multiplies the period Tzcd by the ratio and outputs a correction value ΔTon, and a second command value output circuit 133 that outputs a second command value Vc2 based on the first command value Vc1 and the correction value ΔTon.

This allows the correction circuit 64d to calculate the correction value ΔTon without using the value of the period Toff when the rectified voltage Vr is in the low phase. Therefore, even when the rectified voltage Vr is in the low phase, the period Ton2 during which the NMOS transistor 36 is turned on can be appropriately set.

In another aspect of the present invention, AC-DC converters 10b and 10c are provided that generate an output voltage Vout at a target level from an AC voltage Vac, and include an inductor 33 to which a rectified voltage Vr corresponding to the AC voltage Vac is applied, an NMOS transistor 36 that controls an inductor current IL2 flowing through the inductor 33, and power factor correction ICs 35b to 35g that control the switching of the NMOS transistor 36.

In this way, the on-period Ton2 of the NMOS transistor 36 can be properly corrected to compensate for the decrease in inductor current IL2 that occurs due to a delay in the on-signal Son1, thereby providing an AC-DC converter configuration with an IC that can improve the power factor.

In another aspect of the present invention, there are provided AC-DC converters 10b, 10c that generate an output voltage Vout at a target level from an AC voltage Vac, and that include power factor correction ICs 35b, 35f, 35h, and 35i. In the power factor correction ICs 35b, 35f, 35h, and 35i, the on signal Son1 of the NMOS transistor 36 is delayed based on the off period Toff of the NMOS transistor 36, an estimated value of the rectified voltage Vr in the AC-DC converter, and the voltage Vfb.

This allows the drive circuit 56 to turn the NMOS transistor 36 on and off at appropriate times based on the period Toff, the estimated value of the rectified voltage Vr, and the voltage Vfb, thereby providing an AC-DC converter equipped with a power factor correction IC that can improve the power factor.

The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that the technical scope of the present invention may include forms incorporating such modifications or improvements, and their equivalents, without departing from the spirit of the invention.

The order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," or the like, and it should be noted that processes can be performed in any order, unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that it is necessary to perform the processes in that order.

10a, 10b, 10c AC-DC converter 11 Load 20 AC power supply 21 Inductor 22 Capacitor 30 Full-wave rectifier circuit 31, 32 Capacitor 33 Inductor 34 Diodes 35a, 35b, 35c, 35d, 35e, 35f, 35g, 35h, 35i Power factor correction IC
36 NMOS transistor 37 body diode 38 parasitic capacitor 40 to 45 resistors 50, 53 ADC
51 ON signal output circuit 52 Delay circuit 54 Error amplifier circuit 55 First command value output circuit 56 Drive circuit 61 Current source 62 Delay period setting circuit 63 Detection circuits 64a, 64b, 64c, 64d Correction circuit 65 ADC
66, 66a, 66b, 66c Rectified voltage estimation circuit 71 Calculation circuits 72, 83, 92 Correction value output circuits 73, 84, 93 Second command value output circuit 81 Estimation circuit 82 Calculation circuit 91 Calculation circuit 95 Memory circuits 111a, 111b Peak determination circuit 112 Amplitude estimation circuits 113a, 113b Frequency estimation circuit 114 Phase output circuit 115 Output circuit 116 Memory circuit 117 Memory circuit 121 Waveform output circuit 122 Multiplication circuit 131 Calculation circuit 132 Correction value output circuit 133 Second command value output circuit

Claims (19)

An integrated circuit includes an inductor to which a rectified voltage corresponding to an AC voltage is applied, and a transistor that controls an inductor current flowing through the inductor, and controls switching of the transistor in a power supply circuit that generates an output voltage of a target level from the AC voltage,
a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage;
an on-signal output circuit that outputs an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off;
a delay circuit that delays the ON signal for a predetermined period of time;
a correction circuit that corrects the first command value and outputs the corrected value as a second command value for turning on the transistor for a second period longer than the first period;
a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value;
Equipped with
The correction circuit
correcting the first command value based on a third period from when the transistor is turned off until the inductor current reaches the predetermined value, a ratio based on the second period, and the predetermined period;
Integrated circuit. 10. The integrated circuit of claim 1,
a first terminal to which a second voltage corresponding to the predetermined period is applied;
a delay period setting circuit that sets the predetermined period in the delay circuit based on the second voltage;
Equipped with
Integrated circuit. 3. An integrated circuit according to claim 2,
a bias current source that supplies a predetermined current to the first terminal;
A resistor is connected to the first terminal.
Integrated circuit. 10. The integrated circuit of claim 1,
the delay circuit delays the on signal for the predetermined period determined based on the inductance of the inductor and the capacitance of a capacitor that resonates the inductor current together with the inductor;
Integrated circuit. 5. An integrated circuit according to claim 4,
a first storage circuit that records the predetermined period corresponding to the inductance and the capacitance;
Integrated circuit. 6. An integrated circuit according to any one of claims 1 to 5,
a detection circuit that detects the third period based on a first timing at which the transistor is turned off and a second timing at which the inductor current reaches the predetermined value;
Integrated circuit. 7. An integrated circuit according to claim 6,
The correction circuit
a first calculation circuit that calculates the ratio by dividing the second period by the third period;
a correction value output circuit that multiplies the predetermined period by the ratio and outputs a correction value;
a second command value output circuit that outputs the second command value based on the first command value and the correction value;
Including,
Integrated circuit. 7. An integrated circuit according to claim 6,
The correction circuit
an estimation circuit that calculates an estimate of the rectified voltage based on the second period, the third period, and the first voltage;
a second calculation circuit that calculates the ratio based on the estimated value and the first voltage;
a correction value output circuit that multiplies the predetermined period by the ratio and outputs a correction value;
a second command value output circuit that outputs the second command value based on the first command value and the correction value;
Including,
Integrated circuit. An integrated circuit includes an inductor to which a rectified voltage corresponding to an AC voltage is applied, and a transistor that controls an inductor current flowing through the inductor, and controls switching of the transistor in a power supply circuit that generates an output voltage of a target level from the AC voltage,
a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage;
an on-signal output circuit that outputs an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off;
a delay circuit that delays the ON signal for a predetermined period of time;
a correction circuit that corrects the first command value and outputs the corrected value as a second command value for turning on the transistor for a second period longer than the first period;
a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value;
a second estimation circuit that estimates the rectified voltage based on the first voltage, the second period, and a third period from when the transistor is turned off until the inductor current reaches the predetermined value;
Equipped with
The correction circuit
correcting the first command value based on the first voltage, the estimated rectified voltage, and the predetermined period;
Integrated circuit. 10. The integrated circuit of claim 9 ,
The second estimation circuit
a peak determination circuit that determines a peak value of the third period in a half cycle of the rectified voltage based on the third period;
an amplitude estimation circuit that estimates an amplitude of the rectified voltage based on the first voltage, a peak value in the third period, and the second period;
an output circuit that outputs the estimated rectified voltage based on the estimated amplitude;
Including,
Integrated circuit. 11. The integrated circuit of claim 10 ,
The second estimation circuit
a frequency estimation circuit for estimating a frequency of the rectified voltage;
the peak determination circuit determines a peak value of the third period every time the third period reaches a peak;
the frequency estimation circuit estimates the frequency of the rectified voltage based on the determination result of the peak determination circuit;
the output circuit outputs the estimated rectified voltage based on the estimated frequency.
Integrated circuit. 10. The integrated circuit of claim 1 ,
The second estimation circuit
a phase output circuit that estimates a phase of the rectified voltage based on a determination result of the peak determination circuit and the estimated frequency;
the output circuit outputs the estimated rectified voltage based on the estimated phase.
Integrated circuit. 13. An integrated circuit according to claim 11 or 12 ,
The peak determination circuit
When a period between a first peak value and a second peak value immediately preceding the first peak value is within a range of a predetermined percentage from a half cycle of the rectified voltage, the first peak value is output, and when the period is not within the range, the third period after the half cycle from the second peak value is output as a new peak value.
Integrated circuit. An integrated circuit according to any one of claims 10 to 13 ,
The second estimation circuit
a second memory circuit for recording waveform data of the rectified voltage whose amplitude has been normalized;
The output circuit
outputting the estimated rectified voltage using the waveform data;
Integrated circuit. An integrated circuit according to any one of claims 9 to 14 ,
The correction circuit
a third calculation circuit that calculates a ratio based on the estimated rectified voltage and the first voltage;
a correction value output circuit that multiplies the predetermined period by the ratio and outputs a correction value;
a second command value output circuit that outputs the second command value based on the first command value and the correction value;
Including,
Integrated circuit. A power supply circuit that generates an output voltage of a target level from an AC voltage,
an inductor to which a rectified voltage corresponding to the AC voltage is applied;
a transistor for controlling an inductor current flowing through the inductor;
an integrated circuit that controls the switching of the transistor;
Equipped with
The integrated circuit comprises:
a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage;
an on-signal output circuit that outputs an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off;
a delay circuit that delays the ON signal for a predetermined period of time;
a correction circuit that corrects the first command value and outputs the corrected value as a second command value for turning on the transistor for a second period longer than the first period;
a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value;
Including,
The correction circuit
correcting the first command value based on a third period from when the transistor is turned off until the inductor current reaches the predetermined value, a ratio based on the second period, and the predetermined period;
power circuit. A power supply circuit that generates an output voltage of a target level from an AC voltage,
an inductor to which a rectified voltage corresponding to the AC voltage is applied;
a transistor for controlling an inductor current flowing through the inductor;
an integrated circuit that controls the switching of the transistor;
Equipped with
The integrated circuit comprises:
a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage;
an on-signal output circuit that outputs an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off;
a delay circuit that delays the ON signal for a predetermined period of time;
a correction circuit that corrects the first command value and outputs the corrected value as a second command value for turning on the transistor for a second period longer than the first period;
a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value;
a second estimation circuit that estimates the rectified voltage based on the first voltage, a third period from when the transistor is turned off until the inductor current reaches the predetermined value, and the second period;
Including,
The correction circuit
correcting the first command value based on the first voltage, the estimated rectified voltage, and the predetermined period;
power circuit. An integrated circuit includes an inductor to which a rectified voltage corresponding to an AC voltage is applied, and a transistor that controls an inductor current flowing through the inductor, and controls switching of the transistor in a power supply circuit that generates an output voltage of a target level from the AC voltage,
a first command value output circuit that outputs a first command value for turning on the transistor for a first period based on a difference between a first voltage corresponding to the output voltage and a reference voltage;
an on-signal output circuit that outputs an on-signal for turning on the transistor when the inductor current becomes equal to or less than a predetermined value after the transistor is turned off;
a delay circuit that delays the ON signal for a predetermined period of time;
a correction circuit that corrects the first command value and outputs the corrected value as a second command value for turning on the transistor for a second period longer than the first period;
a drive circuit that turns on the transistor based on the delayed on signal and turns off the transistor based on the second command value;
a second terminal to which a third voltage corresponding to the rectified voltage is applied;
Equipped with
The correction circuit
correcting the first command value based on a ratio based on the first voltage and the third voltage and the predetermined period of time;
Integrated circuit. 20. The integrated circuit of claim 18 ,
The correction circuit
a third calculation circuit that calculates the ratio based on the third voltage applied to the second terminal and the first voltage;
a correction value output circuit that multiplies the predetermined period by the ratio and outputs a correction value;
a second command value output circuit that outputs the second command value based on the first command value and the correction value;
Including,
Integrated circuit.