JP7768965B2 - Power System - Google Patents

Description

This application is a continuation-in-part of U.S. Patent Application No. 16/760,762, filed April 30, 2020, which is a national stage application of International Application No. PCT/US2017/068301, filed December 22, 2017, both of which are incorporated herein by reference.

This disclosure relates generally to power supply technology, and more particularly to a system for monitoring and controlling the discharge of battery cells when connected to a power distribution bus.

This section is intended to introduce various aspects of the art that may be related to example embodiments of the present disclosure. This discussion is believed to help provide a framework to facilitate a better understanding of certain aspects of the present disclosure. Accordingly, it should be understood that this section should be read in this light, and not necessarily as admissions of prior art.

Modern information technology and telecommunications systems include power distribution buses that operate at a variety of power distribution bus voltages. For example, computer servers typically distribute 12 volts ("V") to internal subsystems such as memory, processors, storage, cooling fans, and I/O (such internal subsystems to which a power distribution bus provides supply voltage are referred to herein as "load circuits," or simply "loads"). Wired telecommunications systems typically use a 48V power distribution bus voltage level, while wireless telecommunications and cell site systems often use 24V as their internal power distribution bus voltage level. Despite the different power distribution bus voltage levels, all of the above systems share some common characteristics in that these power distribution buses can carry tens or hundreds of amperes ("A") of current under normal operation and generally have a requirement that the voltage on these buses be regulated to ensure that the maximum voltage excursion on the bus is limited to a fixed value above or below a desired nominal value. A regulated power distribution bus is subject to a specified voltage tolerance around its nominal value. For example, a 12V power distribution bus with a tolerance of +/-10% has an operating envelope ranging from a maximum level of 13.2V to a minimum level of 10.8V.

Within the past decade, battery systems optimized for delivering very high currents for short periods of time have been developed. Battery systems typically contain one or more battery cells (the terms "battery" and "cell" may be used interchangeably herein). Their compact size makes them attractive for some equipment types to replace traditional uninterruptible power supplies ("UPS"), which serve as short-term electrical backup for equipment in the event of an AC mains power outage. These high-power battery systems are unique in their ability to deliver very high discharge currents, but suffer from the drawback of only being able to accept charge currents slowly. This ratio of discharge current to charge current can be as high as 30:1 or even 40:1 with currently commercially available technology.

High-power battery systems used today for short-term backup applications typically use output regulators in the form of DC-DC converters capable of handling high energy (e.g., output DC-DC converters) to match the battery system's output voltage to the power distribution bus voltage and prevent reverse current flow from the power distribution bus to the battery, resulting in unsafe charging currents and representing a safety hazard. In many of today's systems, charging current is provided via a path separate from the discharge current and may be provided by a separate, low-power charging DC-DC converter. Therefore, an opportunity exists for cost reduction and electrical efficiency improvement if such high-power output DC-DC converters can be eliminated or replaced with a different approach having higher electrical efficiency and lower cost, allowing the battery system to be directly connected to the power distribution bus via this improved approach.

Today, conventional technology exists for directly connecting battery systems to electric buses, almost all of which utilizes a pair of high-side or low-side metal-oxide-semiconductor field-effect transistors ("MOSFETs") that function as switching elements (also referred to herein simply as "switches") for on/off control of charge and discharge currents. MOSFETs are commonly used in these applications because, by the nature of their manufacturing process, they contain a diode (i.e., a parasitic body diode) that allows current to flow in one direction through the MOSFET even when the MOSFET is switched off. While this body diode presents a problem in many applications, it is actually utilized as an advantage in embodiments of the present disclosure.

Many of today's battery systems utilize two switches arranged back-to-back, each containing either a parasitic body diode in parallel with the switch or an external diode across the switch. The switch with the forward-facing diode (pointing from the battery to the load) is considered the "charge" switch (when in the off state, it blocks any charging current), and the other switch is the "discharge" switch (when in the off state, it blocks any discharging current). This scheme works for low-power distribution buses where the following conditions are met: (1) the total current capacity of the bus (either available on the bus or consumed by loads coupled to the bus) does not exceed the safe charging or discharging current of the battery, (2) the distribution bus voltage is controllable so that it can be made high enough when necessary so that the battery receives a full charge after being discharged, and (3) the allowable operating voltage of the load circuit is between or includes the minimum battery terminal voltage when the battery is fully discharged (i.e., 0% state of charge) and the maximum battery terminal voltage when the battery is fully charged (i.e., 100% state of charge). However, this approach is impractical when the voltage tolerances required by the load circuits coupled to the power distribution bus require tight regulation such that the voltage supplied to the power distribution bus must remain below the battery's fully charged voltage, and cannot be used when the current normally available from the bus exceeds the battery's safe charging current level.

Low-power systems, such as those implemented for notebook and tablet computers and mobile phones, have industry standards for direct connection of single-cell or multi-cell battery systems to a power distribution bus. These devices use the aforementioned single-transistor switch “back-to-back” configuration for charge and discharge control. Figure 2 shows a “high-side” switch configuration in which switches _Q1 and _Q2 (e.g., MOSFETs) are positioned to connect to the high-voltage side (+) of the battery. Switches _Q1 and _Q2 are connected so that the battery can be charged and discharged depending on which of the two switches is switched on. A controller is coupled to each of the switches and controls which switch is switched on under which conditions and for which duration. In this manner, charge and discharge control by the controller is achieved. The controller may permit or disallow charging or discharging based on the battery’s state of health, charge level, instantaneous capacity, voltage, current, temperature, or any other parameter the designer can select. The combination of the switches, their parasitic body diodes, and the controller allows for controlled charging (prohibiting the flow of charge from the power distribution bus to the battery), controlled discharging (prohibiting the flow of charge from the battery to the power distribution bus), or complete electrical isolation of the battery terminals from the power distribution bus (prohibiting the flow of charge in either direction).

This dual-switch control scheme works for many battery applications where the allowable charge current, discharge current, and available bus current are close in magnitude, or where the allowable charge current is significantly higher than the available bus current. Laptop computer batteries have a typical design point where the charge rate is approximately equal to the discharge rate, e.g., approximately 1 C (i.e., 1 x the nominal battery capacity C). Cell phone batteries may be designed to have higher charge rates (e.g., up to 4 C), but typically have a very low discharge rate. This allows the phone to charge quickly while also having a long operating life on a single charge. At these low charge and discharge rates, the parasitic body diodes of the switches have sufficient thermal and power capabilities to pass the required charge and discharge currents with minimal temperature rise and power loss.

However, there are increasing examples of real-world systems with battery charge-discharge asymmetries where the allowable discharge rate far exceeds the allowable charge rate. For example, batteries performing electrical backup duty are typically designed for a 60-90 minute charge time and a fast discharge time that can completely deplete the battery in 60-90 seconds. This very large imbalance between the normal charge current and the normal discharge current (i.e., the large charge-discharge current asymmetry) makes the dual-switch control scheme of Figure 2 impractical. Specifically, the body diode found in the charge control switch _Q1 is completely inadequate to carry the discharge current seen when such a scheme is used, as its voltage drop and power loss would adversely affect system operation. Additionally, in the example of a tightly regulated +12V distribution bus with lithium-ion batteries as the energy storage device, the batteries selected for such an application should be as close as possible to +12V (e.g., three or four series-connected cells charged to 4.0V per cell). As those skilled in the art will appreciate, it is not possible to fully charge this battery from a +12V supply through an isolation diode with low forward voltage characteristics (as typically found in the parasitic body diode of a conventional MOSFET).

In addition to the isolation switch mentioned above, regulated systems are designed to convert battery voltage from one voltage level to another to control electrical output when safely connecting to a power bus. For example, a linear regulator can be used to provide a uniform voltage output at a specific value or set point. Referring to FIG. 3, a feedback circuit including an operational amplifier ("OPAMP") driving a series pass element (e.g., a transistor with a diode in parallel) is shown. In such a regulated system, the circuit of FIG. 3 essentially replaces the discharge control switch _Q2 of FIG. 2 and provides a regulated voltage output at the load up to a crossover point where a minimum voltage drop across the series pass element creates a voltage drop between the input to the linear regulator and its output (i.e., between the battery terminals and the load terminals) sufficient to reduce the voltage at the load terminals to within the load circuit's specified operating voltage threshold (e.g., minimum allowable operating voltage level).

Such linear regulators can work satisfactorily when implemented for low-power devices. However, there are many deficiencies that arise as power levels increase. First, the series pass element is operated in its linear mode, and the voltage difference between the input and output voltages is imposed on the series pass element, generating very high power dissipation and V*I-based heat at high currents. This generated heat must be transferred to the environment or otherwise removed from the device; otherwise, it concentrates within the series pass element package, causing even high-power transistors to quickly overheat and fail. Packages capable of handling the heat generated from this power dissipation require very large physical packages with direct-attached heat sinks and significant airflow to cool the device. Most high-power battery systems have physical space limitations and manufacturing constraints that prevent the use of this type of transistor packaging. Furthermore, it is difficult to find practical surface-mount transistors ("SMT") that can dissipate sufficient heat through their printed circuit board ("PCB") contacts.

Switching regulators are also used to convert battery voltages to fixed bus voltages, and they can be much more electrically efficient due to their operating mode. Generally, step-down or "buck" converters require a higher input voltage than their output voltage to operate and cannot generate an output voltage above that input voltage. A typical input-output voltage relationship for a buck converter is shown in Figure 4. This requires a series-connected battery stack with a higher series cell count to raise the input voltage to the converter to the required level necessary to achieve high efficiency and a manageable switching duty cycle. However, such a high cell count can increase cost, circuit complexity, total circuit packaging, and battery management system ("BMS") component count and complexity. Figure 5 shows an alternative implementation of a DC-DC converter as a "buck-boost" converter, which can generate a constant output voltage regardless of whether the input voltage is lower than, equal to, or higher than the constant output voltage, recognizing that if the input voltage drops too low, converter operating parameters such as input current may become too large to continue safe operation. For this reason, most buck-boost converters include an input undervoltage protection limit, or "UV shutdown," to prevent damage to the converter. While a buck-boost converter can accommodate fewer series cells than is achievable with a buck converter, the integrated circuit that forms the heart of a buck-boost converter's control circuitry is more difficult to find and generally more expensive than a buck converter's control integrated circuit ("IC"). A typical input/output voltage relationship for a buck-boost converter is shown in Figure 5. Regardless of which DC-DC topology—linear, switching buck, or switching buck-boost—is used in today's modern configurations, it's important to note that the DC-DC converter must be designed, both electrically and thermally, to handle the maximum output power of the battery system. For example, a battery system rated for 1500 watts of output power requires a DC-DC converter designed to handle the full 1500 watts the battery can deliver. Consequently, a large and expensive DC-DC converter must be coupled between the battery and the load circuit. This is illustrated in Figure 6, which shows the DC-DC converter placed between the battery (+) terminal and the output voltage terminal, _V. Because all power delivered from the battery to the output voltage terminal, _V, must be processed through the DC-DC converter, the DC-DC converter must be sized to safely handle the maximum power expected to be delivered.

U.S. Patent Application No. 2020/0350779

FIG. 1 is a circuit block diagram configured in accordance with an embodiment of the present disclosure. 1 is a system representing a prior art example of a charge/discharge control system for a battery coupled to a power source and a load. FIG. 1 illustrates a prior art implementation of a linear regulator DC-DC converter for regulating the output of a battery connected to a load. FIG. 2 illustrates input voltage versus output voltage characteristics of a step-down (buck) converter suitable for use in embodiments of the present disclosure. FIG. 2 illustrates input voltage versus output voltage characteristics of a step-up/step-down (buck-boost) converter suitable for use in embodiments of the present disclosure. FIG. 1 illustrates a prior art system for using a DC-DC converter in combination with a battery and a controller for providing a regulated output voltage to a load. FIG. 1 is a circuit block diagram of a system disclosed in U.S. Patent Application No. 2020/0350779. 1 is a plot of a family of voltage curves versus state of charge (“SOC”) at different possible load currents for an exemplary lithium-ion rechargeable battery in which four cells are connected in series, the cells being constructed of lithium manganese cobalt chemistry. FIG. 1 illustrates a non-limiting representation of control steps using a binary sequencing scheme that can be utilized in the system disclosed in U.S. Published Patent Application No. 2020/0350779. 1 is a plot of a family of voltage curves versus state of charge ("SOC") at different possible load currents for an exemplary lithium-ion rechargeable battery in which four cells are connected in series, the cells being constructed of lithium iron phosphate ("LFP") chemistry. FIG. 1 illustrates the output current limit characteristic of a DC-DC converter suitable for use in embodiments of the present disclosure. FIG. 10 illustrates a specified load voltage tolerance range and various control thresholds and set points for control of the system according to an embodiment of the present disclosure. FIG. 2 is a simplified block diagram of the system shown in FIG. 1 configured in accordance with an embodiment of the present disclosure. FIG. 2 is a block diagram of a non-limiting example of a control element used in embodiments of the present disclosure that implements a system state determination function, inputs signals to the control element, and outputs signals for the control element. FIG. 2 is a schematic diagram of a non-limiting example of an electronic circuit that implements a state determination function, according to an embodiment of the present disclosure. 1 is a truth table implemented in a non-limiting example of a state determination element used in an embodiment of the present disclosure showing output signal levels from a control element based on different states of input signals and defining which combinations of output signal levels will trigger a control action. 2 is a table demonstrating several non-limiting on/off control sequences that result in a gradual increase or decrease in the overall impedance of the FET/resistor pair network shown in FIG. 1. FIG. 1 is a flowchart diagram of a process configured in accordance with an embodiment of the present disclosure. 2 is a diagram illustrating a time domain analysis showing the instantaneous level of the voltage at the output node V _o of the system shown in FIG. 1, the slope (rising or falling) of the voltage at the output node V _o , and the resulting instantaneous state of the control signal for various exemplary situations that the system may experience during operation. 2 is a diagram illustrating a time domain analysis showing the instantaneous level of the voltage at the output node V _o of the system shown in FIG. 1, the slope (rising or falling) of the voltage at the output node V _o , and the resulting instantaneous state of the control signal for various exemplary situations that the system may experience during operation.

It will be understood that the specific embodiments described herein are shown by way of example and not as limitations on the embodiments of the present disclosure. The principal features of the present disclosure can be employed in various embodiments without departing from the scope of the present disclosure.

By convention, current in circuit diagrams and equations is referred to by the symbol i and is measured in units of amperes, or ("A").

As an alternative to linear or switching regulators, the system disclosed in U.S. Published Patent Application No. 2020/0350779 provides a set of individually controlled switches that connect a power source (e.g., a battery terminal voltage) to an output (e.g., a power distribution bus) to which a load circuit (see, e.g., FIG. 7) can be connected. When MOSFETs are utilized as switches, the MOSFETs can operate in a predetermined (e.g., programmed) manner to regulate the output voltage and current supply from the battery using the inherent forward voltage drop of the MOSFET's body diode and/or an external resistor (e.g., a resistive element) coupled in series with each MOSFET. Such a circuit can be configured to replace a battery discharge DC-DC converter, withstand high discharge currents, and/or operate more efficiently in many operating modes compared to linear or switching regulators operating at high power.

To understand how the parallel connection of discharge control switches can control the application of battery discharge voltage and provide equivalent output voltage regulation, the characteristic behavior of an example battery will now be described.

Rechargeable batteries, such as lithium-ion ("Li-ion")-based rechargeable batteries, can be constructed with different internal materials and specific chemical compositions that define each battery cell's operating voltage range, maximum discharge current, internal impedance, and specific capacity. Each of these parameters defines a family of discharge voltage versus discharge current curves (also called "V-I curves") that are unique to each type of cell.

A battery may be configured with a fixed chemical energy capacity determined by the finite weight or volume of active chemicals contained within each cell of the battery. Capacity is measured by discharge at a given current and time until a certain minimum voltage is achieved. Capacity is typically reported in milliampere-hours ("mAh") or ampere-hours ("Ah"). This capacity is represented herein by the letter "C," which corresponds to the continuous current available from a battery over one hour as the battery discharges from 100% state of charge ("SOC") (i.e., fully charged to the maximum allowable voltage) to 0% SOC (i.e., fully discharged to the minimum allowable voltage). For any given discharge current, the battery's terminal voltage drops according to its SOC. As the battery's chemical capacity is depleted, the SOC decreases from 100% to 0%.

Figure 8 shows a family of plots (i.e., V-I curves) of voltage curves versus SOC at different possible load currents for an exemplary battery of four series-connected lithium-ion rechargeable cells using nickel manganese cobalt ("NMC") chemistry. These curves define an exemplary operating envelope within which the battery voltage may operate for various conditions of battery current and SOC. More specifically, the plots in Figure 8 represent voltage curves versus SOC at different load currents where the battery has a capacity of 1 Ah during current demands of 10 A, 12 A, 15 A, and 20 A.

As can be easily seen, the terminal voltage of a battery at any given SOC shifts lower as current demand increases. The distance between the curves on the voltage scale increases as current demand increases is due to the internal resistance or impedance of the battery cell. The higher the internal impedance, the lower the battery terminal voltage for a given applied discharge current present at the battery output terminals. Therefore, the battery terminal voltage at a given SOC depends not only on the SOC but also on the discharge current demand, and lies within the operating envelope defined by the characteristic curve.

As can be seen from the diagram in FIG. 8, the output (discharge) voltage of a typical battery is not constant but rather varies with the discharge current present at the battery output terminals and SOC. Therefore, a typical battery itself does not have the inherent ability to regulate or maintain its discharge voltage within a specific voltage range over the time it takes for stored energy to be depleted from the battery or as the load current changes. However, as previously described herein, it is very common in power systems for any source supplying power to a power distribution bus to regulate the voltage supplied to the power distribution bus to ensure that maximum and minimum voltage excursions on the power distribution bus are limited to a desired nominal value, i.e., a specified value above or below a voltage tolerance range (referred to herein as a "specified load voltage tolerance") that can be tolerated by a load coupled to the power distribution bus to ensure specified (e.g., error-free) operation. This is one reason why voltage regulators or DC-DC converters, such as those described above, are implemented to maintain the output voltage supplied to the power distribution bus (e.g., by a battery or other power source) within such specified load voltage tolerance range.

Referring again to FIG. 8, for purposes of illustrating embodiments of the present disclosure, the operating envelope for a discharging battery to a particular load may be divided into several regions, in this example, Regions 1, 2, 3, and 4. The Region 1 area defines operating points on the battery terminal voltage for an SOC curve that is below the load's specified load voltage tolerance. The Region 2 area defines operating points on the battery terminal voltage for an SOC curve that is within the specified load voltage tolerance. The Region 3 area defines several operating points on the battery terminal voltage for an SOC curve that is above the specified load voltage tolerance. As described further herein, while operating within this Region 3 area, embodiments of the present disclosure are configured to provide finer control of the output voltage provided to the load by utilizing an N-FET/resistor pair network (e.g., see FIG. 9). According to an exemplary embodiment of the present disclosure, the upper boundary of the Region 3 area is less than about 5% above the upper boundary of the Region 2 area for the nominal value of the load voltage (e.g., 0.6 V for a 12 V nominal load voltage, 1.2 V for a 24 V nominal load voltage, etc.). The Region 4 area defines operating points on the battery terminal voltage for the SOC curve that are above the Region 3 area. The operating envelope of the exemplary battery described with respect to FIG. 10 is also divided into similar regions.

Figure 7 is a circuit block diagram of a system 700 disclosed in U.S. Patent Application Publication No. 2020/0350779. System 700 uses a battery system 706 configured to selectively couple the output terminals of a battery 708 to a power distribution bus 704 via a defined switching arrangement including a network of N (where N >= 2) parallel-connected discharge switches 710a-710d (e.g., MOSFETs), each coupled in series with a resistor 750a-750d to form a network of N FET/resistor pairs.

System 700 may be utilized with batteries having battery terminal voltages that extend beyond a specified load voltage tolerance (e.g., as required by load 705; see, e.g., the Region 2 area shown in the example of FIG. 8). As described herein, typical batteries have terminal voltages at some operating points outside of such narrowly specified load voltage tolerances required by many loads. Therefore, system 700 may be used to regulate the supply voltage to power distribution bus 704 substantially within this specified load voltage tolerance of 12V +/- 5%, as shown in the Region 2 area of FIG. 8, even though the voltage present at the terminals of battery 708 exceeds this Region 2 range. The voltage present at the terminals of battery 708 may be configured to be above the specified load voltage tolerance of power distribution bus 704 (e.g., see the Region 3 and Region 4 areas shown in the example of FIG. 8) under some SOC and battery current conditions, while the voltage supplied to load 705 is regulated to substantially match the specified load voltage tolerance of power distribution bus 704 under other SOC or battery current conditions, such as the Region 2 area.

Resistors 750a-750d may each be configured with a different resistance value, or may be configured so that the resistance value of each resistor in series 750a-750d is lower than the previous resistor in the series (e.g., resistor 750b has a lower resistance value than resistor 750a, resistor 750c has a lower resistance value than resistor 750b, etc.). The FET/resistor pairs may be connected in parallel between the battery terminals and the power distribution bus 704 via another switching element (e.g., MOSFET) 711 that prevents charging of the battery directly from the power distribution bus 704, and the N FETs 710a-710d and each of their paired resistors, as well as the FET 711, are independently controlled by the controller 702 via control lines 721a-721e. However, embodiments may be implemented with one or more of resistors 750a-750d having substantially equivalent resistance values.

The number N of parallel-connected discharge control FET/resistor pairs can range from 2 to any number that can be practically controlled by the controller 702. The number N of discharge control FET/resistor pairs can generally be determined by several factors, such as the minimum and maximum voltage available from the battery 708, the expected range of minimum and maximum output current, and the required minimum and maximum output voltage range (e.g., as determined by a specified load voltage tolerance (e.g., see area 2 shown in the example of Figure 8)).

The battery 708 may be coupled to the power distribution bus 704 by the controller 702 activating (e.g., switching on) one or more of the N FETs 710a-710d in a predetermined manner (e.g., sequentially, in a binary count sequence, or in any other sequence), beginning with the FET 710a, which may be paired with the highest resistance value resistor 750a. When the FET 710a is switched on, current begins to flow through the load 705, and the terminal voltage of the battery 708 begins to drop according to the battery impedance characteristic curve (see, e.g., Figures 8 and 10). If the current supplied to load 705 through the series combination of FET/resistor pair 710a/750a is sufficiently high, the voltage drop across the series combination of FET/resistor pair 710a/750a will increase until the voltage supplied to load 705 drops to a predetermined threshold, which may be set (e.g., within controller 702) according to a minimum regulation point specification (e.g., the lower limit of a specified load voltage tolerance) of load 705. When this threshold is reached and sensed by controller 702 via output voltage sensor 741, controller 702 may be configured to switch off FET/resistor pair 710a/750a and switch on the FET paired with resistor 750b, which may have the next highest resistance value in the series of resistors 750a-750d. Resistor 750b in series with FET 710b can be configured to have a significantly smaller resistance than that of resistor 750a, such that the voltage drop across the series combination of FET 710b and resistor 750b is lower than that across the series combination of FET 710a and resistor 750a. The effect of this is to raise the output voltage delivered to load 705 above the aforementioned threshold associated with the minimum regulation point specification of load 705 (e.g., the lower limit of a specified load voltage tolerance), thus keeping the output voltage delivered to load 705 above this minimum predetermined threshold. In this manner, the output voltage supplied to the load 705 can be maintained by the controller 702 within an application regulatory window (e.g., a specified load voltage tolerance range (e.g., see the region 2 area shown in the example of FIG. 8 )) under varying battery terminal voltages and load currents sensed by the controller 702 via the battery voltage sensor 742, the output voltage sensor 741, and the current sensor 707 by the controller 702 selectively activating the N FETs 710a-710d (e.g., in an upward binary count sequence or other suitable sequence) to increase the voltage supplied to the load 705 or selectively deactivating the N FETs 710a-710d (e.g., in a downward binary count sequence) to decrease the voltage supplied to the load 705, where FET 710a is associated with the least significant bit of the binary sequential counter and FET 710d (or higher) is associated with the most significant bit.

9, which shows the total voltage drop across the parallel-connected FET/resistor pairs in response to a binary count sequence for selective activation by controller 702 of N FETs 710a-710d. As can be seen, the voltage drop across the FET/resistor pair network can be controlled in N ^discrete steps (e.g., 16 when N=4) ranging from essentially 0 V to some desired maximum voltage (approximately 3.0 V in this example). Due to its placement within battery system 706 between the output terminal of battery 708 and the input terminal V _o of load 705, load 705 sees its input voltage as the terminal voltage of battery 708 minus the voltage drop across the FET/resistor pair network. By this technique, regulation of the voltage supplied to the load 705 (e.g., substantially within a specified load voltage tolerance) can be achieved and maintained by the controller 702 switching the N FETs 710a-710d on/off to regulate the impedance (i.e., and therefore the voltage drop) across the FET/resistor pair network.

Such a network of N parallel discharge switching elements (i.e., N FET/resistor pairs) can be configured (e.g., in response to instructions received from controller 702) to operate as a high-current digital-to-analog converter where the power supply voltage (i.e., from battery 708) is not constant over time (e.g., see FIG. 8) but varies with load current and SOC. In this configuration, information from voltage sensors 741, 742 and current sensor 707 can be utilized by controller 702 to compensate for variations in both the input and output voltages (i.e., battery 708 and load 705).

The resulting system 700 is thus configured as a network of N fixed impedance elements (i.e., N FETs 710a-710d and associated resistors 750a-750d), which can be switched in and out of the network by the controller 702 to compensate for changes in voltage on the input (i.e., battery 708) and output (i.e., load 705). By varying the resistance of the resistors 750a-750d, individual element impedances are defined. Each FET/resistor pair can be configured with a specific voltage drop at a given applied current. As a result, the system 700 can be configured to control a network of elements that defines a variable, controllable impedance between the battery 708 and the load 705. As the voltage on the load 705 increases, the network is adjusted by the controller 702 so that the total impedance increases and the voltage delivered to the load 705 decreases. As the voltage of the battery 708 drops, the network is reconfigured by the controller 702 so that the total impedance drops, and therefore the voltage across the network, thereby serving to maintain the voltage delivered to the load 705 within a desired range (e.g., substantially within a specified load voltage tolerance). The compensating voltage drop across the network, which is subtracted from the battery voltage, can then be controlled by the controller 702 using any number of different control techniques, such that the resulting voltage delivered to the load 705 is controlled by the sequencing of the various N FET/resistor pairs in the system 700 to provide high-resolution voltage matching whenever the battery operating point lies within (e.g., drifts for whatever reason) Region 1, 2, or 3 operating ranges (e.g., as shown in FIG. 8).

Because system 700 can only reduce the supplied battery voltage to some lower voltage required by load 705, there are some areas of the battery characteristic curve that are unusable, corresponding to the Region 1 area, for example, as shown in FIG. 8. Any energy contained in the Region 1 area cannot be used by system 700 and is essentially stalled. While the Region 1 area contains only a small portion of the total battery energy represented by this family of V-I curves, other battery chemistry types and configurations may have significantly more energy stalled in the unusable Region 1 area (see, for example, FIG. 10).

FIG. 1 shows a circuit block diagram of a system 100 configured in accordance with an embodiment of the present disclosure. System 100 may be configured to supply power to a load from a secondary power source via a power distribution bus when there is a failure of the primary power source. Although embodiments of the present disclosure are not limited to such a configuration, the primary power source may be a power supply unit coupled to an AC power source, and the secondary power source may be a battery.

In the non-limiting exemplary embodiment shown with respect to FIG. 1, the system 100 uses a battery system 106 configured to selectively couple the output terminals of the battery 108 to the power distribution bus 104 via a DC-DC converter 170 under the control of a controller 102, and a switching configuration including a network of N (where N≧1) parallel-connected discharge switches 110b-110d (e.g., MOSFETs), each coupled in series with a resistor 150b-150d to form a network of N FET/resistor pairs (also referred to herein as an "N-FET/resistor pair network").

Resistors 150b-150d may each be configured with a different resistance value, or may be configured so that the resistance value of each resistor in series 150b-150d is lower than the previous resistor in the series (e.g., resistor 150c has a lower resistance value than resistor 150b, resistor 150d has a lower resistance value than resistor 150c, etc.). However, embodiments may be implemented with one or more of resistors 150b-150d having substantially equivalent resistance values.

The N FET/resistor pairs may be connected in parallel between the positive terminal of the battery 108 and the power distribution bus 104 via another switching element (e.g., a MOSFET) 111, which may be implemented to prevent charging of the battery 108 directly from the power distribution bus 104, and may also be interposed, with each of the N FETs 110b-110d, as well as FET 111, being selectively and independently controlled by the controller 102 via control lines 121b-121e.

The number N of parallel-connected discharge control FET/resistor pairs can range from 1 to any number that can be practically controlled by the controller 102 and can generally be determined by one or more factors, such as the minimum and maximum voltage available from the battery 108, the expected range of minimum and maximum output current, and the required minimum and maximum output voltage range (e.g., as determined by a specified load voltage tolerance (e.g., see the Region 2 area shown in the example of FIG. 8)). Changes in the battery 108 terminal voltage and load current can be sensed by the controller 102 via the battery voltage sensor 142 and current sensor 107.

System 100 may be utilized with batteries having battery terminal voltages at useful operating points that extend beyond a specified load voltage tolerance (e.g., as required by load 105, as compared to the full range of battery operating points, including those outside of Region 2, e.g., those included in Regions 1, 3, and 4, see Region 2 area shown in the example of FIG. 8). As described herein, a typical battery or series-connected batteries will, in almost all cases, have terminal voltages at some operating points that fall outside the narrower, more tightly restricted specified load voltage tolerance required by most loads. Therefore, system 100 can be used to regulate the supplied battery voltage substantially within this specified load voltage tolerance. Battery 108 voltage may be configured to be above the specified load voltage tolerance of power distribution bus 104 (e.g., see Region 3 and Region 4 areas shown in the example of FIG. 8) under some SOC and battery current conditions, and to substantially match the specified load voltage tolerance of power distribution bus 104 (see Region 2 area shown in the example of FIG. 8) under other SOC or battery current conditions.

Operation of system 100 will be similar to that of system 700 having a DC-DC converter 170 implemented in accordance with the V _IN vs. V _OUT and output current limit characteristics (see, e.g., FIG. 11 ) of the type of DC-DC converter 170 implemented in system 100, and may be configured to be able to handle the supply of current to load 105 when load 105 is requesting low current (i.e., less than about 25% of the maximum current that may be required by load 105) and battery 108 is operating at a high state of charge (e.g., an SOC value greater than about 70%), e.g., corresponding to operation of system 100 in the Region 4 area as shown in FIG. 8 or FIG. 10 .

DC-DC converter 170 may be any of the types described herein (e.g., linear regulator, switching buck, switching buck-boost, etc.), including, but not limited to, those described in connection with FIGS. 4, 5, and 11. DC-DC converter 170 need not be configured (e.g., sized) to handle the battery's maximum output power as in prior art implementations; rather, in system 100, the balance of the output power is supplied by an N-FET/resistor pair network, as described further herein, so it may be configured to be able to handle approximately 25% to 30% of the battery's maximum output power. This provides an advantage of system 100 over such prior art implementations that use DC-DC converters, as the relative cost and size of a DC-DC converter are substantially higher than the relative cost and size of a FET/resistor pair network of similar power supply capability.

FIG. 4 shows the input-to-output voltage ( _VIN vs. _VOUT ) characteristics of a non-limiting example of a switching buck converter suitable for implementation as DC-DC converter 170 in system 100. When _VIN > _VOUT set point, the DC-DC converter operates as a normal buck converter, maintaining the output voltage _VOUT approximately equal to the _VOUT set point. However, if the input voltage _VIN drops so that it intersects the _VOUT set point, the output voltage _VOUT may essentially track the input voltage _VIN until it falls below the VOUT set point and reaches some threshold, shown as 11 V in this example. This is referred to as a "low dropout" characteristic, which is commonly found in linear regulator designs. _{The VOUT} set point, also referred to herein as the battery DC-DC converter set point (e.g., see FIG. 12), may be predetermined to be a voltage level at which DC-DC converter 170 is configured to begin supplying current to load 105 after a failure of PSU 101, as further described herein with respect to FIGS. 12 and 19.

FIG. 5 shows the input to output voltage (V _IN vs. V _OUT ) characteristics of a non-limiting example of a buck-boost converter, which is also suitable for implementation as DC-DC converter 170 in system 100, where the above-mentioned "low dropout" characteristic is not required and the DC-DC converter automatically switches from buck mode (V _IN >V _OUT set point) to boost mode when V _IN <V _OUT set point, thus maintaining the output voltage V _OUT equal to the V _OUT set point regardless of the input voltage V _IN until the UV shutdown input voltage is reached.

FIG. 11 illustrates the current-limit characteristic of the DC-DC converter implemented in system 100, with the x-axis representing time. The DC-DC converter is configured to maintain the DC-DC converter's output voltage VOUT constant for all DC-DC converter output currents _I0 below an output current value referred to as the current-limit transition point (where the DC-DC converter's output voltage changes from a constant _voltage to a constant current). When the DC-DC converter's output current _I0 (represented by the dashed line in FIG. 11) reaches the current-limit transition point ( _Ilimit(A) ), the output voltage _VOUT drops slightly, or is said to "droop." This represents the DC-DC converter's transition from "constant voltage" mode to "droop current-limit" mode, where the output voltage _VOUT is allowed to fall below the _VOUT set point for a narrow range of output current values between Ilimit _(A) and Ilimit _(A) plus a few percent. In other words, for any current value between 0 and _Ilimit(A) , the DC-DC converter's output voltage _VOUT is maintained at the _VOUT set point. Once I _limit(A) is reached, the output voltage V _OUT begins to droop, and this droop continues to accentuate as the output current continues to rise (the current slope at I _limit(A) appears flat, but is actually slightly positive).

During an event such as a hardware failure in the PSU 101 or an AC outage (generally referred to herein as a PSU 101 failure) that operates the system 100 such that the battery 108 discharges onto the power distribution bus 104, the voltage of the battery 108 drops as the discharge current increases (e.g., as shown in FIGS. 8 and 10 ), with a gradual increase in current as traced by different characteristic curves at lower voltages. This drop in the voltage of the battery 108 as the battery discharge current increases may be caused by the internal resistance or impedance of each battery cell. The amount of voltage drop of the battery 108 depends on the magnitude of the current supplied by the battery 108 to the load 105 and the internal impedance of each cell within the battery 108. The chemical composition of the cells of the battery 108 may be selected for their voltage, current capability, and impedance characteristics such that they can support the full power requirements of the power distribution bus 104 to which they are coupled, while maintaining a voltage drop small enough to keep the power distribution bus 104 within its voltage limits (e.g., substantially within a specified load voltage tolerance) during a discharge event.

According to embodiments of the present disclosure, system 100 may be configured such that at values of current supplied to load 105 that are below the current limit transition point of DC-DC converter 170 (see I _limit(A) shown in FIG. 11 ) and where the battery 108 is in a high state of charge, current may be supplied to load 105 by DC-DC converter 170 alone or in combination with some predetermined number of FET/resistor pairs in the N-FET/resistor pair network depending on the instantaneous operating point of the family of VI curves of battery 108.

Embodiments of the present disclosure will now be described with respect to a non-limiting example application and operation of system 100 in which controller 102 is configured to supply power to load 105 within a specified load voltage tolerance. Such specified load voltage tolerance is sometimes referred to herein as an application regulation window, which defines the voltage range that may be required by a load associated with a particular end application. Such specified load voltage tolerance may consist of a nominal, or desired, output voltage V _o and a +/- percentage range.

FIG. 12 shows a non-limiting example graphical representation of various set points and thresholds that may be implemented in system 100 based on a desired output voltage _V (e.g., 12V) and a specified load voltage tolerance (e.g., ±5%). Reference is made to the non-limiting example VI curve of FIG. 8 solely for purposes of illustrating embodiments of the present disclosure. The specified load voltage tolerance is shown, extending from a lower regulatory limit (12V-5%=11.4V in this example) to an upper regulatory limit (12V+5%=12.6V in this example). According to embodiments of the present disclosure, controller 102 may be configured to maintain the voltage supplied to load 105 between the upper and lower regulatory limits that define the specified load voltage tolerance. FIG. 12 also illustrates that several other thresholds and set points may be configured within the design of system 100, within the upper and lower regulatory limits. There may be a PSU output voltage set point for PSU 101, which may be predetermined during the design of system 100 (e.g., as a function of load dynamics, PSU control loop response, etc.), and in this example is selected to be 12.35V (as shown by solid line 2 in FIG. 12 ). The value of the PSU output voltage set point for PSU 101 may be selected as the normal operating output voltage supplied by PSU 101, and is selected to be within a specified load voltage tolerance. There may be a battery DC-DC converter set point for DC-DC converter 170, which is set lower than the PSU output voltage set point, and in this example is selected to be 12.0V (as shown by dashed line 3 in FIG. 12 ). There may be two control threshold set points: an upper control threshold ("UCT") set between the PSU output voltage set point and the battery DC-DC converter set point (selected at 12.3V in this example), and a lower control threshold ("LCT") set below the battery DC-DC converter set point and above the lower regulatory limit (LCT selected at 11.9V in this example). UCT and LCT values are further described with respect to Figures 14 and 15. The utilization of these thresholds and set points is further described herein.

The battery DC-DC converter setpoint may be selected to be within a specified load voltage tolerance, lower than the PSU output voltage setpoint, and higher than the LCT, and may be optimized by analyzing the dynamic characteristics of the system 100. The selection of the upper and lower regulatory limits (i.e., the specified load voltage tolerance) may be determined according to the specifications and requirements of the load 105. The value of the UCT may be selected at any appropriate value below the PSU output voltage setpoint so that monitoring a drop in the output voltage _V below the UCT indicates to the battery system 106 that there may be a failure of the PSU 101 or that the output voltage _V supplied by the battery system 106 to the load 105 may be increasing excessively, potentially outside the specified load voltage tolerance. The value of the LCT may be selected at any appropriate value below the battery DC-DC converter setpoint so that monitoring a drop in the output voltage _V below the LCT indicates to the battery system 106 that more current needs to be supplied from the battery 108 to the load 105 through the N-FET/resistor pair network. The system 100 designer's selection of UCT and LCT values that fall within a specified load voltage tolerance may depend on the particular characteristics of the battery 108 (e.g., terminal voltage, characteristic curves, etc.), the dynamic characteristics of the load 105 (e.g., dynamic load current magnitude and rise and fall times), and the effective capacitance of the system 100, shown as C _LOAD 160. This system capacitance C _LOAD 160 may represent the sum of the capacitances coupled to the output node V _o in the system 100 (e.g., any output capacitors present in the PSU 101 that are included to help stabilize the feedback control loop of the PSU 101, any output capacitors present at the output of the DC-DC converter 170 to improve transient response or help stabilize the control loop of the DC-DC converter 170, any capacitance associated with the load 105, and any other capacitance added by the designer of the battery system 106).

13 shows a simplified block diagram of system 100, which is presented to illustrate how monitoring of the voltage at output node V _o is utilized by controller 102 to adjust the amount of impedance inserted between battery 108 and load 105, according to embodiments of the present disclosure, as described further herein. Battery system 106 and PSU 101 are coupled to power distribution bus 104 at output node V _o . Also coupled to power distribution bus 104 at output node V _o are load 105 and system capacitance C _LOAD 160.

Well-known circuit theory dictates that the sum of any currents at any node in a system must be zero. Therefore, the sum of the currents present at node _V is:
i _Batt +i _PSU -i _Capacitance -i _Load =0
Solving for i _Capacitance gives:
(i _Batt +i _PSU )-i _Load =i _Capacitance
Considering the characteristic equation of a capacitor, it is as follows:
i _Capacitance =C*dV _Capacitance /dt
where dV _Capacitance /dt=dV _o /dt.

From the above equation, we can conclude that when (i _Batt +i _PSU ) equals i _Load , i _Capacitance is zero with respect to time, and dV _Capacitance /dt is also zero. Therefore, the voltage at the output node _Vo does not change. If (i _Batt +i _PSU )>i _Load , i _Capacitance is positive (i.e., the system capacitance C _LOAD 160 is charging), dV _Capacitance /dt is also positive, and the voltage at the output node Vo increases with respect to time. Correspondingly, if (i _Batt +i _PSU )<i _Load , i _Capacitance is negative (i.e., the system capacitance C _LOAD 160 is discharging into the load 105), dV _Capacitance /dt is also negative, and the voltage at the output node _Vo decreases with respect to time. These variables, the voltage across the system capacitance C _LOAD 160 (i.e., V _o ) and the current in the system capacitance C _LOAD 160 (C*dV _Capacitance /dt), represent a set of state variables of the system 100 and are utilized within the embodiments of the present disclosure described herein. Note that C*dV _Capacitance /dt can be positive or negative and has units of amperes (current), and dV _Capacitance /dt can be positive or negative and has units of volts/hour. Note also that dV _Capacitance /dt is equal to dV _o /dt and represents the same state variable.

FIG. 14 shows a block diagram of a non-limiting implementation for state determination system 141 (see FIG. 1), which may be configured to determine values representing state variables (i.e., V _o and dV _o /dt) of system 100. Threshold detector 1401 receives output voltage V _o as an input and compares V _o to the UCT and LCT limits (see FIG. 12). A truth table for the operation of threshold detector 1401 is shown in Table 16a of FIG. 16. When output voltage V _o is at a voltage level above the UCT, the signal Upper Control Threshold Exceeded ("UCTE") is set to logic level 1; when output voltage V _o falls below the UCT, UCTE is reset to logic level 0. When output voltage V _o is at a voltage level below the LCT, the signal Lower Control Threshold Exceeded ("LCTE") is set to logic level 1; when output voltage V _o exceeds the LCT, the LCTE signal is reset to logic level 0.

Differentiator 1402 receives output voltage V _o as an input, determines the sign of dV _o /dt, and generates a dV _o /dt Positive signal that is set to logic level 1 whenever dV _o /dt > 0 and a dV _{o /dt Negative signal that is set to logic level 1 whenever dV o /} dt > 0, thus providing the instantaneous sign of state variable dV _o /dt to controller 102. A truth table for the operation of differentiator 1402 is shown in Table 16b of FIG. 16. The UCTE, LCTE, dV _o /dt Negative, and dV _o /dt Positive signals (collectively also referred to herein as "state determination signals") are provided to controller 102 from state determination system 141 via signal line 180. Note that truth tables 16a and 16b include entries that are designated as not allowed or not possible. For example, the output voltage V _o cannot be above UCT and below LCT at the same time, so the conditions UTCE=1 and LTCE=1 cannot occur simultaneously.

The controller 102 is configured to receive a state determination signal from the state determination system 141 and perform operations according to the truth table set forth in Table 16c of FIG. 16, as further described with respect to the system and process 1800 of FIG. 18. FIG. 15 shows a schematic diagram of a non-limiting example of how the state determination system 141 can be implemented using an operational amplifier (OP1) and voltage comparators (CMP1-CMP4) to generate the truth table shown in Table 16c of FIG. 16, with the comparator reference values relating to the example provided with respect to FIG. 12.

Considering the non-limiting example of system 100 implemented with battery 108 as described with respect to Figure 8, when operating in the Region 4 area, the inclusion of DC-DC converter 170 provides higher electrical efficiency as well as more precise control over the exact input/output voltage differential over a wider range of currents, down to zero (0) battery discharge current, than was previously available with respect to system 700 of Figure 7. This is evident by inspecting Figure 9. As described herein, for any number N of FET/resistor pairs, there are ^N2 individual control steps available. Due to the decreasing resistance nature of resistors 710a-710d in system 700, the granularity of the control steps is not constant across the operating range; while operating in Region 3 (see FIG. 8), it can be seen that fine control is available (note in FIG. 9 that 70% of the available control steps are in the range of a V _BAT -V _o difference of 0.5V or less), but when operating in Region 4, where the V _BAT -V _o difference is in the range of 0.5V to 3.0V, only very coarse and imprecise control is available due to the small number of available control steps. Region 4 is an operating range with poor electrical efficiency due to the high VI losses in the resistive elements in this range. Region 4 is therefore an area where coarse control of the output voltage V _o is provided by incorporating DC-DC converter 170, which is specifically intended to have high efficiency in this area, thereby mitigating such efficiency issues. Thus, system 700 suffers from poor efficiency and control in the Region 4 area, while system 100 alleviates these problems by incorporating DC-DC converter 170, which significantly improves performance in the Region 4 area, while finer control of the output voltage V _o can be provided by controlling the total impedance of the N-FET/resistor pair network, as further described herein with respect to FIG. 18.

The choice of using a standard buck DC-DC converter or a buck-boost DC-DC converter may be determined by the requirements of the load 105 powered by the system 100, as well as the VI curve for the particular chemistry and configuration of the battery 108. As described herein with respect to FIG. 7, the system 700 can only supply current to the load 705 at voltages below the battery voltage. As a result, there is often unavailable energy in the battery 708. With reference to FIG. 8, the Region 1 area identifies battery operating points that are below the specified load voltage tolerance for the load. Whenever a battery operating point falls within the Region 1 area of the family of VI curves, battery energy is unavailable. Therefore, the resulting portion of the VI curve that falls within this Region 1 area is very small and exists only at very low states of charge where the SOC is near zero. For many end-user applications, this unavailable Region 1 energy can simply be ignored. However, compare the VI curves shown in FIG. 8 with the operation of different battery configurations as shown in FIG. 10, which represents the VI curves for a four-series cell configuration of iron phosphate battery cells operating at currents between 1 A and 60 A. It can be seen that the Region 4 area of operation for the iron phosphate battery system of FIG. 10 is significantly smaller in area than the nickel manganese cobalt system of FIG. 8 . Note that this may be suitable for a 12V system. However, note that the area of the curve present in the Region 1 area for the iron phosphate battery system of FIG. 10 is significantly larger than that for the nickel manganese cobalt system of FIG. 8 (e.g., up to approximately 40% SOC when operating at a maximum load of 60 A). This represents a significant amount of unusable energy contained in the Region 1 area, as discussed above, and may be unacceptable for certain applications desired to be powered by such a battery system. A potential solution is to replace the battery system 706 of FIG. 7 with the battery system 106 of FIG. 1 that implements a DC-DC converter design (e.g., a buck-boost DC-DC converter) with appropriate maximum power and current limit settings for the DC-DC converter 170, as this type of converter can boost battery voltages lower than those within the specified load voltage tolerance range to an output voltage that meets the specified load voltage tolerance range. It should be noted that care may be needed when using a buck-boost converter for DC-DC converter 170 to prevent power cycling from the output to the battery (input) when DC-DC converter 170 is boosting an output voltage above the voltage supplied by battery 108. To prevent this, the connection point of the output of DC-DC converter 170 may be moved to the drain side of transistor 111 (compared to FET/resistor pairs 110b-110d and 150b-150d being coupled to the source side of transistor 111). When operating in boost mode, transistor 111 is switched off, thus blocking any power cycling from the output of DC-DC converter 170 to battery 108. The result of operating DC-DC converter 170 in boost mode is that 100% of the output power supplied while battery 108 is discharging in Region 4 should be supplied through DC-DC converter 170, not through the N-FET/resistor pair network. This means that operation of system 100 in the Region 4 area should be at a power level below the power limit and current limit transition point (I _limit(A) ) of DC-DC converter 170. However, in applications where system 100 is utilized as a computer server, it is not uncommon to specifically allow this "power-down" operation from battery 108 at low SOC.

FIG. 17 shows some non-limiting examples of FET/resistor activation/deactivation sequences that may be implemented within the controller 102 depending on particular battery and load characteristics and requirements. Table 17a represents a binary counting sequence similar to that described with respect to FIG. 9 that may be implemented within the controller 102. FETs 110b, 110c, and 110d may be switched on in a binary count-up sequence, with FET 110b representing the least significant bit and FET 110d representing the most significant bit, and each subsequent binary digit representing a decreasing total impedance of the N-FET/resistor pair network. Thus, counting up one binary digit at a time will decrease the total impedance of the N-FET/resistor pair network, and counting down one digit at a time will increase the total impedance of the N-FET/resistor pair network. Table 17b shows a sequential sequence in which the FETs may be switched on and off, rather than in a binary counting mode, so that the first FET 110b is switched on, then FET 110c is switched on (without first switching FET 110b off), and finally FET 110d is switched on, to decrease the total impedance of the N-FET/resistor pair network. Similarly, to increase the impedance of the N-FET/resistor pair network, the controller 102 may be configured to switch off the FET in the most significant bit position, then the FET in the next most significant bit position, and so on, until all FETs are switched off. This sequential sequence results in fewer discrete impedance steps, but when starting from any given impedance value, the minimum or maximum impedance value is reached more quickly.

According to an embodiment of the present disclosure, the binary count sequence shown in Table 17a can be implemented in the controller 102 when the battery 108 is composed of NMC battery cells such as those shown in FIG. 8, where only about 20% of the area traced by the minimum current V-I curve and the maximum current V-I curve is within Region 2, with most of the area outside Region 2 located in Regions 3 and 4 above Region 2. According to an embodiment of the present disclosure, the sequential sequence shown in Table 17b can be implemented in the controller 102 when the battery 108 is composed of iron phosphate battery cells such as those shown in FIG. 10, where the area traced by the minimum current V-I curve and the maximum current V-I curve is within Region 2, with only about 30% in Regions 3 and 4 above Region 2.

An alternative binary/sequential or "hybrid" counting approach is shown in Table 17c, where the binary counting sequence and sequential sequence are combined, with FETs 110b and 110c operating in binary sequence and FET 110d being added in sequential sequence after FETs 110b and 110c reach their maximum binary values.

Embodiments of the present disclosure are further illustrated by the following examples, which are provided to illustrate the subject matter of the present disclosure and are not to be construed as limiting.

A non-limiting example implementation of system 100 will now be described. In this 12V example (V _o =12V), the upper regulation limit is 12.6V and the lower regulation limit is 11.4V, defining a specified load voltage tolerance range. The exemplary battery 108 is based on a four-series cell iron phosphate battery shown in FIG. 10, with a maximum load current of 60 amps and a minimum load current of 1 amp. The DC-DC converter 170 is configured as a suitable buck DC-DC converter (with characteristics as shown in FIG. 4), and the current limit transition point I _{limit (A)} , as shown in FIG. 11, is selected to be 15 amps, or 25% of the maximum current of the load 105. As shown in FIG. 12, the battery DC-DC converter set point is set to 12.0V, the PSU output voltage set point is set to 12.35V, the UCT is set to 12.3V, and the LCT is set to 11.9V. The controller 102 is configured to sequentially step up and step down the impedance of the N-FET/resistor pair network as shown in Table 17b of FIG. 17. Resistor 150b may be configured with the highest resistance value of all resistors 150b-150d. According to embodiments of the present disclosure, this resistance value for resistor 150b may be determined by the maximum value of the battery 180 voltage traced by the allowable VI curves for the minimum and maximum load current design points. In this example, this resistance value is identified by point A (13.4 V) shown in FIG. 10, and can be subtracted from the value of the battery DC-DC converter set point, which is 12.0 V, represented by point B shown in FIG. 10. The result is then divided by the current limit transition point of DC-DC converter 170 (I _limit(A) , i.e., 15 A) to provide the desired resistance value for resistor 150b. Using these values, the result is as follows:
Resistance value of element 150b = (13.4V - 12.0V) / 15A
Resistance of element 150b = 93 milliohms

Resistor 150c may be configured to have the next lowest resistance in the sequence, and may be configured to have a resistance equal to or slightly less than 1/10 the resistance of resistor 150b (e.g., 9 milliohms). Resistor 150d may be configured to have a resistance equal to or slightly less than 1/10 the resistance of resistor 150c (e.g., 0.9 milliohms). As a result, the total resistance of the N-FET/resistor pair network when all FETs are switched on is 0.8 milliohms. This provides a total voltage drop of 48 millivolts across the N-FET/resistor pair network at a maximum load of 60 A.

10, the iron phosphate cell characteristic VI curve lies largely within the Region 2 operating range of current values above the current limit transition point I _{limit (A)} of 15 A and below the maximum defined load current of 60 A, so system 100 may be configured with fewer parallel FET/resistor pairs, a sequential FET activation sequence, and a more aggressive reduction in resistance value per sequential pair, as previously described. If system 100 is configured with a battery 108 comprised of NMC cells such as those represented by FIG. 8, a relatively larger portion of the VI curve lies beyond the Region 2 operating range (i.e., the specified load voltage tolerance), as shown in FIG. 8, so system 100 may be configured with a larger number of parallel FET/resistor pairs, a binary count sequence, and a more gradual reduction in resistance value per sequential pair.

Referring again to FIG. 1, when operating properly (i.e., when AC input power is present and within specified values, and/or there are no hardware faults within the PSU 101), the PSU 101 is designed to have sufficient output current capacity to supply full load current to the load 105. If there is a failure of the AC input to the PSU 101 or if there is a hardware fault within the PSU 101, the PSU 101 will stop supplying current to the load 105, and the battery system 106 will discharge energy from the battery 108 to supply current to the load 105.

According to an embodiment of the present disclosure, the battery system 106 is configured to source current from the battery 108 between current paths provided by the DC- _DC converter 170 in combination with the N-FET/resistor pair network to maintain the voltage at the output node V o within a specified load voltage tolerance range bounded by upper and lower regulatory limits as shown in FIG. 12 . Depending on the current required to meet the demands of the load 105, the current can flow through any combination of elements of the DC-DC converter 170 and the N-FET/resistor pair network. The controller 102 can be configured to control the balancing of the output current from the discharging battery 108 between the DC-DC converter 170 and the N-FET/resistor pair network such that the voltage supplied to the load 105 is regulated between the upper and lower regulatory limits (i.e., within the specified load voltage tolerance range). The following description represents example transitions that may occur as part of the current balancing and voltage regulation process.

A non-limiting exemplary process for supplying current from the battery 108 to the load 105 by the battery system 106 according to an embodiment of the present disclosure will now be described with reference to the system and process 1800 of FIG. 18, which may be implemented for operation within the controller 102. In this example, the DC-DC converter 170 operates according to FIG. 4, the state determination system 141 is configured to operate according to the truth tables set forth in Tables 16a and 16b of FIG. 16, and the controller 102 is configured to operate according to the truth tables set forth in Table 16c of FIG. 16 and the FET sequence set forth in Table 17b of FIG. 17. The signal generated by the state determination system 141 according to the truth tables set forth in Tables 16a and 16b is received by the controller 102 via signal line 180.

19-20 illustrate time domain analyses illustrating an example operation of system 100 of the delivery of output voltages from battery 108 and PSU 101 to output node V _o and corresponding transitions in signals provided from state determination system 141 to controller 102. FIG. 19 illustrates an example time domain analysis for time interval t ₀ -t ₁₀ , and FIG. 20 illustrates an example time domain analysis for time interval t ₁₀ -t _21. The example operation of system and process 1800 is described with reference to the time instances in FIGS. 19 and 20 to describe what happens at the moment of each time instance and during the time intervals between each time instance. Note that FIGS. 19 and 20 are not drawn to scale, and some of the time intervals shown may be measured in microseconds, while other time intervals may be measured in seconds or minutes.

In process block 1801, PSU 101 is operating properly and may have been on for some previous period of time. In this example, the output voltage set point of PSU 101 is 12.35V and supplies full load current to load 105. Also, for some previous period of time, components of battery system 106 are initialized (represented by the dashed lines around process blocks 1802-1805). Controller 102 may be initialized in process block 1802 (e.g., upon receiving an AC_OK signal). In process block 1803, controller 102 switches off DC-DC converter 170 and all FETs 110b-101d via signal lines 171 and 121b-121d, respectively. In process block 1804, controller 102 may be configured to verify that the voltage present at output node V _o is equal to the PSU output voltage set point (e.g., a sensed level of output voltage V _o is provided to controller 102 via signal line 180 by a voltage sensor implemented within state determination system 141 in a manner similar to battery voltage sensor 142), and that the AC_OK signal on signal line 112 is present (e.g., a logic level 1 is received).

In process block 1805, DC-DC converter 170 is turned on via control signal 171, causing DC-DC converter 170 to regulate its output at its battery DC-DC converter set point (12.0 V in this example). However, because the voltage at output node _Vo is held at 12.35 V by PSU 101, no current flows from DC-DC converter 170 and all current to load 105 is supplied by PSU 101. At some point after DC-DC converter 170 has regulated its output, system and process 1800 proceed to process block 1806 and wait for an interrupt generated by a rising edge transition of either the UCTE or LCTE signal received by controller 102 from state determination system 141 via signal line 180. This wait condition represents a steady state condition and, in this example, is represented as the system state shown in FIG. 19 at time _t0 . As will be described further, the controller 102 may be configured to generate an interrupt upon receiving a rising edge (a transition from logic level 0 to logic level 1) of either the UCTE signal (e.g., see 1901 in FIG. 19) or the LCTE signal (e.g., see 1902 in FIGS. 19 and 20). This interrupt causes the system and process 1800 to transition from process block 1806 to process block 1807, where the state determination signal from the state determination system 141 is evaluated to determine whether any FET control action is required to adjust the impedance of the N-FET/resistor pair network either up or down, as will be described further herein.

This steady-state condition continues in process block 1806 during time interval _t0 to _t1 . Controller 102 maintains the switches of FETs 110b-110d switched off. All load current continues to be supplied by PSU 101, which is regulating the voltage supplied to output node _V0 at a point above the battery DC-DC converter set point of DC-DC converter 170. Because the voltage supplied to output node _V0 is higher than UCT, the UCTE signal is at logic level 1 (see Table 16a in FIG. 16), and because voltage _V0 does not change, state determination system 141 maintains the _dV0 /dt Positive and _dV0 /dt Negative signals at logic level 0 values (see Table 16b in FIG. 16). In process block 1806, no interrupt is generated because controller 102 is still waiting for a rising edge of either the UCTE or LCTE signal.

In this example, consider that at some subsequent time period, either an AC line fault (signaled to the controller 102 via the AC_OK signal 112) or a hardware failure of the PSU 101 occurs. This is shown in FIG. 19 as time _t1 . Eventually, the output voltage of the PSU 101 begins to drop from 12.35V. As the voltage _V drops, the C _LOAD 160 then discharges and supplies some of the current to the load 105, while the PSU 101 supplies the remainder of the current. When the voltage _V begins to drop at time _t1 , this is sensed by the state determination system 141, causing the dV _o /dt Negative signal to transition from logic level 0 to logic level 1 (see Table 16b in FIG. 16). Following time _t1 , the voltage V _o decreases sufficiently to fall below UCT, causing the state determination system 141 to transition the UCTE signal from logic level 1 to logic level 0. Process block 1806 is still waiting for an interrupt caused by either the UCTE signal or the LCTE signal transitioning from logic level 0 to logic level 1. The decrease in voltage _V continues during time interval _t1 to _t2 as more energy can be supplied from C _LOAD 160 to load 105.

At time _t2 , the voltage V _o drops until it reaches the battery DC-DC converter set point of DC-DC converter 170, which is set at 12.0 V. During time interval _t2 - _t3 , current is sourced from battery 108 through DC-DC converter 170, holding voltage V o constant as the current sourced by DC-DC converter 170 rises from zero current at time _t2 to a current limit transition point I _{limit (A)} at time _t3 . In response to this unchanged value of output voltage V _o during time interval _t2 - _t3 , the dV _o /dt Negative signal received by controller 102 _from state determination system 141 returns to a logic 0 value (see Table 16b of FIG. 16).

Upon reaching the current limit transition point I _{limit (A)} at time _t3 , DC-DC converter 170 enters its voltage "droop" mode (see FIG. 11), and output voltage V _o begins to decrease as C _LOAD 160 again begins to supply energy to load 105, which can be seen during time interval _t3 - _t4 in FIG. 19. The dV _o /dt Negative signal provided from state determination system 141 to controller 102 transitions to logic level 1 during this time interval. However, no interrupt is yet generated at process block 1806. Therefore, controller 102 keeps FETs 110b-110d switched off (corresponding to impedance sequence 0 set forth in Table 17b of FIG. 17) in accordance with the truth table of Table 16c of FIG. 16.

At time _t4 , the output voltage _V₀ falls below LCT, causing the state determination system 141 to transition the LCTE signal from logic level 0 to logic level 1 (shown as 1902 in FIG. ₁₉ at time t4), and an interrupt is generated by process block 1806. The system and process 1800 proceeds to process block 1807, where the levels of the state determination signals received from the state determination system 141 are read by the controller 102. According to the truth tables of Tables 16a and 16b of FIG. 16, the signal levels are UCTE=0, LCTE=1, _dV₀ /dt Positive=0, and _dV₀ /dt Negative=1. The system and process 1800 then proceeds to process block 1808, where it determines whether these signal levels correspond to either condition 2b or 3c set forth in the truth table of Table 16c of FIG. 16. In this example, at time _t4 , the level of the state-determining signal is determined to correspond to condition 3c in Table 16c, so system and process 1800 proceeds to process block 1810, where controller 102 determines that the impedance of the N-FET/resistor pair network needs to decrease. Because the N-FET/resistor pair network is currently in impedance sequence 0 (i.e., all FETs are switched off), the next step in Table 17b of FIG. 17, representing decreased impedance, is identified as impedance sequence 1. In process block 1810, controller 102 switches on FET 110b via control signal 121b to configure the N-FET/resistor pair network into the impedance sequence 1 configuration.

The time interval _t4 - _t5 represents the possible propagation delay along control line 121b of the switch ON signal sent to FET 110b. Such propagation delay may consist of the processing time of process block 1806 in processing the interrupt at time _t4 , the execution time of process blocks 1807, 1808, and 1810, the signal propagation time required to propagate the ON signal from controller 102 to FET 110b, and the switching time of FET 110b. Although this propagation time may be relatively short (e.g., on the order of microseconds), there may be a measurable time delay between time _t4 , when the need for an impedance change is first recognized, and time _t5 , when the impedance state of the N-FET/resistor pair network actually changes and the system state variables respond. To prevent overcompensation of the N-FET/resistor pair network, process block 1811 may optionally be included to insert a time delay (e.g., equal to the longest possible value of the propagation delay) before the system and process 1800 returns to process block 1807 and again resets the state of the state determination signal. Time _t5 represents the end of the propagation delay period, at which point it is known that the system state has responded to the control action taken at time _t4 (i.e., increasing voltage _V0 ). Thus, after time _t5 , the system and process 1800 returns to process block 1807.

At time _t5 , the optional propagation delay of process block 1811 is complete and FET 110b is now switched on. The current generated by battery 108, which previously flowed solely through DC-DC converter 170 to load 105, now has a second path to load 105, namely through FET 110b and resistor 150b. As a result, the current in DC-DC converter 170 falls below the current limit transition point as current is diverted from DC-DC converter 170 and the output voltage of DC-DC converter 170, and therefore the output voltage V _o , rises back towards its 12.0V set point.

Following time _t5 , in process block 1807, controller 102 again reads the state determination signal and passes control to process block 1808. As illustrated by the example shown in FIG. 19, during time interval _t5 - _t6 , voltage V _o is below LCT, but voltage V _o is rising, and the state determination signal received from state determination system 141 causes controller 102 to determine in process block 1808 that the N-FET/resistor pair network is operating in accordance with condition 3b (see Table 16c of FIG. 16), which corresponds to the "neither" path out of process block 1808. In process block 1812, signals UCTE and LCTE are each evaluated by controller 102 for a logic level 1. Because the LCTE signal remains at logic level 1, the system and process 1800 continuously loop from process block 1812 to process block 1807 to process block 1808 to process block 1812 back to process block 1812 until the rising output voltage _V exceeds the LCT threshold (shown to occur at time _t6 ), resulting in the LCTE signal transitioning from logic level 1 to logic level 0.

At time _t6 , the output voltage V _o continues to rise as the output current from DC-DC converter 170 continues to increase. When process block 1812 is first invoked after the LCTE signal transitions to logic level 0, the system and process 1800 exit process block 1812 and return to process block 1806 to re-engage the wait for an interrupt triggered by the rising edge of either the UCTE or LCTE signal.

Referring again to FIG. 19, during a first portion of the time interval _t6 - _t7 , the output voltage _V0 continues to increase toward the battery DC-DC converter set point of 12.0 V as the output current ramps up within the DC-DC converter 170. Eventually, a current-limit transition point is reached, shown approximately halfway between times _t6 and _t7 . At this point, the DC-DC converter 170 again enters "droop" mode, and the output voltage _V0 begins to decrease (see FIG. 11). This reversal of _dV0 /dt is indicated by the change in the signal levels of _dV0 /dt Positive and _dV0 /dt Negative, which occurs halfway between times _t6 and _t7 . Because there are no rising edges in either the UCTE or LCTE signals during the time interval _t6 - _t7 , no interrupt is generated, and the system and process 1800 remain at process block 1806.

At time _t7 , the output voltage _V₀ falls beyond LCT, generating a rising edge on the LCTE signal (shown as 1902 in FIG. 19 at time _t7 ) and an interrupt, and system and process 1800 proceeds from process block 1806 to process block 1807, where the controller 102 reads the state determination signal received from the state determination system 141. System and process 1800 then proceeds to process block 1808, where it evaluates the state determination signal and indicates that the combination of UCTE=0, LCTE=1, _dV₀ /dt Positive=0, and _dV₀ /dt Negative=1 corresponds to condition 3c in Table 16c. As a result, system and process 1800 then proceeds to process block 1810, where it is determined that the next step in the impedance sequence corresponding to condition 3c is impedance sequence 2 because the N-FET/resistor pair network is configured in impedance sequence 1 according to the truth table in Table 17b. To accomplish this, controller 102 keeps FET 110b switched on and switches FET 110c on via control signal 121c, then exits process block 1810 and proceeds to process block 1811. During time interval _t7 - _t8 , the system and process 1800 may remain in process block 1811 waiting for FET 110c to switch on.

At time _t8 , when FET 110c is switched on, the current generated by the battery 108 now has a conductive path through the DC-DC converter 170, the FET 110b/resistor 150b pair, and the FET 110c/resistor 150c pair. The addition of the conductive path through the FET 110c/resistor 150c pair, along with the much lower impedance of this new conductive path, diverts more current from the DC-DC converter 170, reducing its current to a level below I _{limit (A).} Thus, the output voltage V _o begins to increase again as the DC-DC converter 170, now operating at a reduced current, attempts to regulate its output at its battery DC-DC converter set point (12.0 V in this example). The system and process 1800 then proceeds to process block 1807, whereby the controller 102 reads the state determination signal. In process block 1808, the controller 102 evaluates the levels of the state-determining signals, which are determined to be UCTE=0, LCTE=1, _dVo /dt Positive=1, and _dVo /dt Negative=0. This combination of state-determining signal levels corresponds to condition 3b listed in Table 16c, and the required impedance action is "none." The system and process 1800 then proceed to process block 1812, and because the voltage _Vo is less than the LCT, LCTE=1, and the system and process 1800 loop from process block 1812 to process block 1807, process block 1808, and then process block 1812, remaining in this loop until the voltage _Vo increases above the LCT.

19, time _t9 indicates that the output voltage V _o rises and exceeds LCT, causing the LCTE signal to be reset to logic level 0 (see Table 16a). Following the transition of the LCTE signal to logic level 0, the system and process 1800 proceeds to process block 1806 on the next pass through process block 1812. The system and process 1800 remain in process block 1806 until the next interrupt caused by the rising edge of either the UCTE or LCTE signal.

19, the time interval including _t8 to _t10 represents a steady-state condition where the current to the load 105 is maintained at a constant level and the battery 108 is slowly discharging. The controller 102 maintains the N-FET/resistor pair network in the Impedance Condition 2 configuration.

In this example, time _t10 indicates the occurrence of a discontinuity in the trajectory of the output voltage Vo, where _dVo /dt suddenly increases from a relatively small positive value to a relatively large positive value. A condition that can cause this type of discontinuity is a sudden decrease in current to the load 105, resulting in a positive current to _CLOAD 160 and a corresponding change (increase) in _dVo /dt.

Referring to FIG. 20, during time interval t ₁₀ -t ₁₁ , the value of the output voltage V _o is increasing and the system and process 1800 is waiting for an interrupt at process block 1806 .

Time _t11 illustrates a situation in which the output voltage V _o rises above UCT, causing a rising edge of the UCTE signal (shown as 1901 in FIG. 20 at time _t11 ), generating an interrupt at process block 1806. The system and process 1800 then proceeds to process block 1807, where the state determination signals received from the state determination system 141 are received by the controller 102. At process block 1808, the controller 102 evaluates the received signals generated by the state determination system 141 (see Tables 16a and 16b in FIG. 16) in this situation as follows: UCTE=1, LCTE=0, dV _o /dt Positive=1, and dV _o /dt Negative=0. According to Table 16c, the controller 102 determines that the signal combination is Condition 2b. Accordingly, system and process 1800 proceeds to process block 1809, where controller 102 determines that the impedance of the N-FET/resistor pair network needs to increase. Because the N-FET/resistor pair network is currently configured in impedance sequence 2 (i.e., FET 110b is switched on, FET 110c is switched on, and FET 110d is switched off), controller 102 determines from Table 17b that increasing the impedance will result in the N-FET/resistor pair network being configured in impedance sequence 1. Therefore, controller 102 switches FET 110c off via control line 121c, configuring the N-FET/resistor pair network into the impedance sequence 1 configuration. System and process 1800 then proceeds to process block 1811, where it enters an optional wait state equal to the maximum propagation delay, as previously described herein.

Referring again to FIG. 20, time _t12 illustrates the effect of increasing impedance, changing the sign of _dVo /dt and inverting the logic levels of the _dVo /dt Positive and _dVo /dt Negative signals. System and process 1800 proceeds to process block 1807, where the levels of the state determination signals received from state determination system 141 are received and read by controller 102. In process block 1808, controller 102 evaluates the received signals generated by state determination system 141 (see Tables 16a and 16b of FIG. 16) in this situation as follows: UCTE=1, LCTE=0, _dVo /dt Positive=0, and _dVo /dt Negative=1. According to Table 16c, controller 102 determines that the signal combination is condition 2c. Process block 1808 completes via the "neither" path, and system and process 1800 proceeds to process block 1812. Because the UCTE signal remains at logic level 1, the system and process 1800 then loops through process blocks 1807, 1808, and back to process block 1812 until the output voltage V _o falls below UCT (shown in FIG. 20 at time _t13 ), causing the UCTE signal to transition from logic level 1 to logic level 0 (see Table 16a). The next time process block 1812 is processed, neither the UCTE nor the LCTE signal is at logic level 1, so the system and process 1800 exits process block 1812 and proceeds to process block 1806, where it again waits for an interrupt.

Time _t14 illustrates a situation where the output voltage V _o falls below LCT, resulting in the LCTE signal transitioning from logic level 0 to logic level 1 (shown as 1902 in FIG. ₂₀ at time t14) and generating an interrupt at process block 1806. The system and process 1800 then proceeds to process block 1807, where the levels of the state determination signals received from the state determination system 141 are received and read by the controller 102. At process block 1808, the controller 102 evaluates the received signals generated by the state determination system 141 (see Tables 16a and 16b in FIG. 16) in this situation as follows: UCTE=0, LCTE=1, dV _o /dt Positive=0, and dV _o /dt Negative=1. According to Table 16c, the controller 102 determines that the signal combination is Condition 3c. System and process 1800 then proceeds to process block 1810, where it is determined that because the N-FET/resistor pair network is configured in impedance sequence 1 according to the truth table of Table 17b, the next step in the impedance sequence corresponding to condition 3c is impedance sequence 2. To accomplish this, controller 102 keeps FET 110b switched on and switches FET 110c on via control signal 121c, then exits process block 1810 and proceeds to process block 1811. In process block 1811, an optional appropriate propagation delay time may occur.

At process block 1807, controller 102 reads the state determination signal received from state determination system 141 shortly after time _t15 . At process block 1808, controller 102 evaluates the received signal generated by state determination system 141 (see Tables 16a and 16b of FIG. 16) for this situation and determines that the state determination signal remains in the configuration that it had at time _t14 , where UCTE=0, LCTE=1, _dVo /dt Positive=0, and _dVo /dt Negative=1. According to Table 16c, controller 102 determines that the signal combination remains for condition 3c. The system and process 1800 then proceed to process block 1810, where it is determined that because the N-FET/resistor pair network is configured in impedance sequence 2, the next step in the impedance sequence corresponding to condition 3c is impedance sequence 3. To accomplish this, controller 102 keeps FETs 110b and 110c switched on, and controller 102 switches FET 110d on via control signal 121d. According to this non-limiting example, the N-FET/resistor pair network is now in its lowest impedance state. System and process 1800 then exits process block 1810 and proceeds to process block 1811, where it can optionally wait one or more propagation delay time intervals until time _t16 .

After time _t16 , the system and process 1800 proceeds from process block 1811 to process block 1807, where the state determination signals generated by the state determination system 141 are received by the controller 102. In process block 1808, the controller 102 evaluates the received signals and determines the state determination signals as follows: UCTE=0, LCTE=1, _dVo /dt Positive=1, and _dVo /dt Negative=0. According to Table 16c, the controller 102 determines that the signal combination is condition 3b. The system and process 1800 takes no impedance action and exits process block 1808 via the path marked "neither" to process block 1812, where the LCTE signal is evaluated and determined to be a logic level 1. The system and process 1800 then continuously loops through process blocks 1807, 1808, and back to process block 1812 until the output voltage _V exceeds LCT, as shown at time _t17 . At this point, the LCTE and UCTE signals are both logic level 0, and the next pass through process block 1812 will cause the system and process 1800 to exit to process block 1806 where it will wait for the next interrupt.

Time _t18 represents a change in _dVo /dt that may be due to an event such as an increase in load current. Because the output voltage _Vo is within the range set by the UCT and LCT, no interrupt is generated at process block 1806, and the system and process 1800 remain at process block 1806. Time _t19 represents another event that may occur during operation of the system 100 when the current delivered to the load 105 decreases. Because the output voltage _Vo is still within the range set by the UCT and LCT, no interrupt is generated at process block 1806. The system and process 1800 remain at process block 1806 waiting for an interrupt.

Time _t20 represents when the output voltage V _o rises above UCT, causing a rising edge of the UCTE signal (shown as 1901 in FIG. ₂₀ at time t20), resulting in the generation of an interrupt at process block 1806. The system and process 1800 then proceeds to process block 1807, where the levels of the state determination signals received from the state determination system 141 are received and read by the controller 102. At process block 1808, the controller 102 evaluates the received signals generated by the state determination system 141 (see Tables 16a and 16b in FIG. 16) in this situation as follows: UCTE=1, LCTE=0, dV _o /dt Positive=1, and dV _o /dt Negative=0. According to Table 16c, the controller 102 determines that the signal combination is condition 2b. Process block 1808 is exited via path 2b, and process block 1809 is executed. In process block 1809, controller 102 determines that the impedance of the N-FET/resistor pair network needs to increase, and because the N-FET/resistor pair network is currently configured according to impedance sequence 3, it determines that the next step in table 17b of FIG. 17, representing the increased impedance, is impedance sequence 2. As a result, controller 102 switches off FET 110d via control line 121d to configure the N-FET/resistor pair network according to impedance sequence 2. System and process 1800 then proceed to process block 1811 and enter an optional wait state equal to the maximum propagation delay (represented as the time interval _t20 to _t21 ), as previously described herein.

The battery system 106 may continue discharging the battery 108 while regulating the output voltage V _o according to system and process 1800 until the battery 108's energy is depleted and the battery system 106 shuts off, or until AC power is restored and the PSU 101 returns to operation. According to embodiments of the present disclosure, in such a situation, the controller 102 may be configured to incrementally increase the impedance of the N-FET/resistor pair network (e.g., stepwise according to Table 17b of FIG. 17 ) until all FETs are switched off. At this point, the DC-DC converter 170 may be switched off. Additionally, at some point, charge may be restored to the battery 108 via the charger 103. In a situation where the battery 108 is depleted of energy (such as when the terminal voltage of the battery 108, as sensed via the voltage sensor 147, drops to a level equal to the voltage at the boundary between Region 2 and Region 1 in FIG. 10), the controller 102 may be configured to turn off the battery system, for example, by switching off all of the FETs in the N-FET/resistor pair network and switching off the DC-DC converter 170.

As described with respect to the exemplary operation of FIG. 18 , the N-FET/resistor pair network can be operated according to several terminal configurations. In one configuration, all FET/resistor pairs in the N-FET/resistor pair network are switched off, resulting in no current flowing through the N-FET/resistor pair network. For example, this may occur during the initial state of system 100, when no current is being supplied from battery 108 to load 105 through the N-FET/resistor pair network. In this case, current from battery 108 is supplied solely through DC-DC converter 170, which regulates output voltage V _o to be within the range between UCT and LCT until the current supplied to load 105 increases and reaches a current limit transition point I _{limit (A)} , at which point the output voltage of DC-DC converter 170 droops. When the output voltage of DC-DC converter 170 falls below the LCT, controller 102 decreases the impedance of the N-FET/resistor pair network, and all of the FET/resistor pairs in the N-FET/resistor pair network are switched off so that the N-FET/resistor pair network has a full range of impedance reduction actions available to controller 102 (see, for example, Tables 17a, 17b, and 17c of FIG. 17 ). If controller 102 needs to increase the impedance of the N-FET/resistor pair network (e.g., in response to a decrease in required load current), and the UCTE has been triggered enough times to switch all of the FET/resistor pairs off, the current to load 105 has dropped sufficiently so that DC-DC converter 170 can again regulate the output voltage V _o without any additional conduction path provided for the current through the N-FET/resistor pair network, so that the remaining current to load 105 can be supplied by DC-DC converter 170.

In another terminal configuration, a situation may arise in which all of the FET/resistor pairs in the N-FET/resistor pair network are switched on and the controller is unable to further reduce the impedance of the N-FET/resistor pair network (e.g., according to any one of the impedance sequences set forth in Tables 17a, 17b, and 17c of FIG. 17). For example, this may occur under conditions of high load current and/or low battery state-of-charge, such as when the operating point of the battery 108 on the VI curve is at the lower end of Region 2 (see, e.g., FIGS. 8 and 10). In such a situation, when using a linear regulator or buck converter as DC-DC converter 170 and discharging battery 108 causes its operating point to approach the boundary between the Region 2 and Region 1 areas, controller 102 may need to reduce the current supplied to load 105 or shut down system 100 to prevent output voltage _V from falling below a lower regulatory limit (see, e.g., FIG. 12). When a buck-boost converter is used as DC-DC converter 170, there may be an additional option if the current supplied to load 105 is reduced to a value below the current limit transition point. If this occurs, operation of system 100 can continue discharging battery 108 via DC-DC converter 170 until the operating point of battery 108 reaches the bottom boundary of Region 1, which represents the minimum allowable battery voltage. Another situation in which this may occur is a short circuit in load 105 or other overload that exceeds the design point of system 100, and therefore the battery operating point is at a current level outside the allowable characteristic VI curve of battery 108. If this situation occurs, system 100 may be configured to protect itself, for example, by terminating all current paths between battery 108 and load 105 (e.g., by switching off all FET/resistor pairs in the N-FET/resistor pair network). DC-DC converter 170 may also be switched off via its control line 171, although this is not strictly necessary since DC-DC converter 170 can be protected by its current limiting characteristic.

As a result of the foregoing, it can be readily appreciated that system 100 can be configured to maintain the output voltage provided from battery 108 to load 105 within a desired voltage range when battery 108 is discharging, including maintaining such output voltage within a required operating voltage range (e.g., substantially within a specified load voltage tolerance), such that system 100 can be implemented as a voltage regulator (e.g., for use as a battery backup unit or DC UPS).

Although embodiments of the present disclosure are disclosed herein as utilizing a battery as a power source (e.g., for battery backup), embodiments of the present disclosure may be configured to utilize any suitable type of power source. Correspondingly, system 100 is suitable for use with any type of power source (instead of a battery) that has an unregulated output voltage (e.g., the output voltage of such a power source varies outside of a specified load voltage tolerance for a particular power distribution bus and its associated load).

As will be appreciated by those skilled in the art, aspects of the present disclosure (e.g., system and process 1800) may be embodied as a system, method, and/or program product. Accordingly, aspects of the present disclosure (e.g., system and process 1800), as well as the threshold detection and differentiator blocks illustrated in FIG. 14, may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be generally referred to herein as a "circuit," "circuitry," "module," or "system." Furthermore, aspects of the present disclosure may take the form of a program product embodied in one or more computer-readable storage media having computer-readable program code embodied thereon (although any combination of one or more computer-readable media may be utilized; the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium).

It should also be noted that each of the circuit block diagrams and/or functional blocks illustrated in the diagrams of FIGS. 1 and 18, and combinations of the circuit block diagrams and/or functional blocks illustrated in the diagrams of FIGS. 14 and 15, can be implemented by a dedicated hardware-based system that performs the specified functions or acts, or a combination of dedicated hardware and computer instructions. For example, a module (e.g., controller 102) can be implemented as a hardware circuit including custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, controllers, or other discrete components. A module (e.g., controller 102) can also be implemented in a programmable hardware device such as a field programmable gate array, programmable array logic, or programmable logic device.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. As used in this application, including the claims, the terms "a" and "an" mean "one or more."

As used herein, the term "about" is used to provide flexibility for the endpoints of numerical ranges by providing that a given value may be "slightly above" or "slightly below" the endpoint.

As used herein, the term "substantially" refers to the complete or nearly complete extent or degree of an action, characteristic, quality, state, structure, item, or result. For example, a "substantially" sealed object means that the object is completely sealed or nearly completely sealed. The exact acceptable degree of deviation from absolute perfection may, in some cases, depend on the particular situation. Generally speaking, however, the proximity of perfection results in an overall result similar to that which would result if absolute and complete perfection were achieved. The use of "substantially" is equally applicable when used in a negative sense to refer to the complete or nearly complete absence of an action, characteristic, quality, state, structure, item, or result.

As used herein, the term "and/or" and the "/" character between two words, when used in the context of a list of entities, refer to the entities present either singly or in combination. Thus, for example, the phrase "A, B, C, and/or D" includes A, B, C, and D individually, but also any and all combinations and subcombinations of A, B, C, and D.

As used herein, the terms "electrically coupled" or "coupled," when used to describe a path in an electric or electronic circuit, refer to components that have a conduction path for electrical energy (i.e., current) in at least one direction between the components. Current does not have to flow along the conduction path for components to be coupled or electrically coupled. Components may be directly coupled with a conduction path that includes only low-impedance wires, etc., or may be indirectly coupled with semiconductors or higher impedance components that allow electrical energy to flow along the conduction path.

100 systems
102 Controller
103 Charger
104 Power Distribution Bus
105 Load
106 Battery System
108 Battery
110b to 110d FET/Resistor Pairs
111 Transistor
141 State Determination System
147 Voltage Sensor
150b~150d resistor
160 C _LOAD
170 DC-DC converter
180 signal line
700 System
702 Controller
704 Power Distribution Bus
705 Load
706 Battery System
707 Current Sensor
708 Battery
710a to 710d Discharge switch
711 Switching element
721a to 721e control lines
741 Voltage Sensor
742 Voltage Sensor
750a~750d resistor
1401 Threshold Detector
1402 Differentiator

Claims (18)

1. A method for regulating power supplied to a power distribution bus, comprising:
monitoring an output voltage provided to the power distribution bus, the output voltage resulting from a supply of current to the power distribution bus by a first power source;
when the monitored output voltage decreases to a level equal to a voltage regulation set point of a DC-DC converter, supplying current from a second power source to the power distribution bus via the DC-DC converter, the DC-DC converter being coupled in parallel with a network of N FET/resistor pairs, where N≧1, between the second power source and the power distribution bus. The method of claim 1, further comprising: when the monitored output voltage falls below a first predetermined threshold, sourcing current from the second power supply to the power distribution bus through the network of N FET/resistor pairs. The method of claim 2, wherein the N FETs in the network of N FET/resistor pairs are switched off when the current is being supplied by the DC-DC converter before the monitored output voltage decreases below the first predetermined threshold, such that no current is supplied from the second power source to the power distribution bus during a first time period before the monitored output voltage decreases below the first predetermined threshold. The method of claim 2, wherein the current supplied from the second power source to the power distribution bus is supplied to be shared by the DC-DC converter and the network of N FET/resistor pairs during a second time period after the monitored output voltage decreases below the first predetermined threshold. The method of claim 1, wherein the second power source is a discharged battery. The method of claim 5, wherein the decrease in the monitored output voltage is due to a failure of the first power source. The method of claim 4, wherein when the monitored output voltage falls below a first predetermined threshold, the step of supplying current from the second power source to the power distribution bus through the network of N FET/resistor pairs includes the step of switching on one or more of the N FETs in the network of N FET/resistor pairs. 1. A method for regulating a delivery of current from a power source to a load over a power distribution bus, comprising:
monitoring a voltage supply to the power distribution bus;
maintaining the voltage within a specified load voltage tolerance by controlling how much current is provided from the power source to the power distribution bus through each of a first conductive path and a second conductive path coupled in parallel between the power source and the power distribution bus, wherein the first conductive path includes a DC-DC converter and the second conductive path includes a network of N FET/resistor pairs coupled in parallel between the power source and the power distribution bus, each of the N FET/resistor pairs including a FET coupled in series with a resistor. The method of claim 8, wherein maintaining the voltage within the specified load voltage tolerance includes modifying the total impedance of the network of N FET/resistor pairs by selectively switching each of the N FETs on and off according to a predetermined sequence. The method of claim 9, wherein the N resistors each have a different resistance value. modifying the total impedance of the network of N FET/resistor pairs;
decreasing the total impedance when the voltage is below a first predetermined threshold and the voltage is decreasing over time;
increasing the total impedance when the voltage is greater than a second predetermined threshold and the voltage is increasing over time, the first predetermined threshold and the second predetermined threshold being within the specified load voltage tolerance range;
10. The method of claim 9, comprising: 1. A power system for supplying power to a load over a power distribution bus, comprising:
Power supply and
a network of N transistors (where N>1) coupled between an output terminal of the power supply and the power distribution bus, each of the N transistors coupled in series with a resistor;
a DC-DC converter coupled in parallel with the network of N transistors between the output terminal of the power supply and the power distribution bus;
a controller configured to selectively and independently activate/deactivate the DC-DC converter and the network of N transistors to enable the power supply to power the load via the power distribution bus at an output voltage level adjusted responsive to activation/deactivation of the DC-DC converter and the network of N transistors. The system of claim 12, wherein the power source is a battery including one or more series-connected cells. The system of claim 12, wherein the controller is configured to regulate the voltage drop across the network by activating/deactivating a specific number of the N parallel-connected transistor/resistor pairs according to a predetermined sequence. The system of claim 14, wherein the output voltage level is adjusted to be within a specified load voltage tolerance range. a differentiator configured to determine whether the output voltage level is increasing or decreasing over time;
16. The system of claim 15, further comprising: a state determination system including: a threshold detector configured to determine when the output voltage level is greater than a first predetermined threshold and less than a second predetermined threshold, wherein the controller is configured to regulate the output voltage level within the specified load voltage tolerance range by selectively and independently activating/deactivating a certain number of the N parallel-connected transistor/resistor pairs according to the predetermined sequence. The controller:
circuitry configured to reduce a total impedance of the network when the output voltage level is below the second predetermined threshold and the output voltage level is decreasing over time;
and circuitry configured to increase the total impedance when the output voltage level is greater than the first predetermined threshold and the output voltage level is increasing over time. The system of claim 12, wherein the DC-DC converter coupled in parallel with the network of N transistors is configured to handle no more than approximately 30% of the maximum output power of the power supply.