JP7769746B2 - Semiconductor Devices - Google Patents

Description

The present invention relates to a SiC semiconductor device.

Various proposals have been made to prevent problems from occurring when testing the characteristics of semiconductor devices. For example, Patent Document 1 proposes measures to prevent discharge in the atmosphere during electrical characteristic testing. Specifically, Patent Document 1 discloses a method for manufacturing a semiconductor device, which includes the steps of forming a base region and an emitter region in a semiconductor wafer, patterning the base electrode and emitter electrode, and then depositing and patterning a polyimide film on the surface to cover the dicing region and other areas excluding electrode bonding portions.

Japanese Unexamined Patent Publication No. 60-50937 Japanese Unexamined Patent Publication No. 54-45570 JP 2011-243837 A Japanese Patent Application Laid-Open No. 2001-176876 Republished Patent No. WO2009/101668

Now, high-temperature, high-humidity, high-voltage testing is beginning to be adopted as a method of testing semiconductor devices. In this test, semiconductor devices are exposed to conditions of, for example, 85°C, 85% RH, and an applied voltage of 960 V for 1,000 consecutive hours (approximately 40 days). Conventionally, measures have been taken to withstand the above temperature, humidity, and voltage conditions individually, but no measures have yet been proposed that can withstand all three conditions.

The object of the present invention is to provide a SiC semiconductor device that can prevent discharge during electrical characteristic tests conducted on wafers and can withstand high-temperature, high-humidity, high-voltage tests.

A semiconductor device according to one aspect of the present invention comprises a first conductivity type SiC layer having an active region on its surface where multiple transistor elements are formed and an outer peripheral region that is the periphery of the active region; electrodes selectively formed on the SiC layer and electrically connected to the transistor elements; and an insulator formed on the SiC layer so as to extend toward a dicing region at an end of the SiC layer, the insulator including an insulating film formed below the electrode and a surface insulating film covering the insulating film and a portion of the electrode, the surface insulating film being formed so as to reach the dicing region, the surface insulating film having a first region formed to overlap the insulating film, and a second region formed outside the first region where the surface insulating film contacts the SiC layer and extends toward the end of the SiC layer.

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is an enlarged view of the area surrounded by the dashed line II in FIG. FIG. 3 is an enlarged view of the area surrounded by the two-dot chain line III in FIG. FIG. 4 is a cross-sectional view of the semiconductor device taken along line IV-IV in FIG. FIG. 5 is an enlarged view of the area surrounded by the two-dot chain line V in FIG. FIG. 6 is a cross-sectional view of the semiconductor device taken along line VI-VI in FIG. FIG. 7A is a cross-sectional view for explaining a process related to cutting the wafer. FIG. 7B is a cross-sectional view showing the state of the wafer after cutting. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention. FIG. 12 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention. FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention. FIG. 14 is a schematic cross-sectional view of a semiconductor device according to an eighth embodiment of the present invention.

The following describes in detail an embodiment of the present invention with reference to the accompanying drawings.

Figure 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present invention. Note that, for clarity, in Figure 1, some elements that are not exposed on the outermost surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

Semiconductor device 1 is a semiconductor device that uses SiC and is formed, for example, in the shape of a square chip when viewed from a plane normal to its outermost surface (hereinafter simply referred to as "plan view").

The semiconductor device 1 has an active region 2 and a peripheral region 3 surrounding the active region 2. In this embodiment, the active region 2 is formed in an inner region of the semiconductor device 1 and has a generally rectangular shape in plan view, but its shape is not particularly limited.

In the active region 2, a gate metal 44, a source metal 43 as an example of an electrode of the present invention, and gate fingers 5 are formed. A passivation film 40 is formed on the outermost surface of the semiconductor device 1 to cover these. Openings 41 and 42 are formed in the passivation film 40, exposing a portion of the gate metal 44 and a portion of the source metal 43 as gate pad 4 and source pad 6, respectively. Meanwhile, the gate fingers 5 are entirely covered by the passivation film 40. Note that in Figure 1, the gate fingers 5 are shown with solid lines and hatched for clarity.

The gate metal 44, gate finger 5, and source metal 43 are made of metal wiring such as Al (aluminum), AlCu (aluminum-copper alloy), or Cu (copper). Preferably, as described in the description of Figure 6, they have a layered structure represented by Ti/TiN/Al-Cu.

By constructing the gate fingers 5 using metal wiring with lower resistance than polysilicon, gate current can be supplied in a short time even to transistor cells 18 (see Figure 2) located relatively far from the gate metal 44. Furthermore, Al has good workability (is easy to process), simplifying the process of forming these wiring. On the other hand, AlCu can improve the power cycle resistance and humidity resistance of the semiconductor device 1 compared to when Al is used, and can also improve the bonding strength of the bonding wire to the gate pad 4. The use of Cu has the advantage of lower resistivity than Al and AlCu.

Gate metal 44 is selectively formed in part of the periphery of active region 2 (near the boundary with outer peripheral region 3). Gate fingers 5 extend from the position where gate pad 4 is formed, in two directions: along the periphery of active region 2 and toward the inside of active region 2. As a result, cell regions 7 and 45 are formed in the active region 2 in the area partitioned by multiple gate fingers 5 extending in different directions on either side of gate metal 44, and in the area outside the gate fingers 5.

More specifically, in this embodiment, the gate metal 44 is formed in a rectangular shape in plan view and is selectively disposed in the center of one side 8 of the active region 2. The sides of the active region 2 other than the side 8 (the side on which the gate metal 44 is disposed) are the side 9 opposite the side 8, and sides 10 and 11 continuing from both ends of these sides 8 and 9, respectively.

The gate finger 5 includes a pad periphery 12 that surrounds the gate metal 44 at a distance, and a first finger 13 and a second finger 14 that extend from the pad periphery 12 in a direction along the side 8 of the active area 2 and a direction perpendicular to the side 8, respectively.

The pad peripheral portion 12 is formed in a rectangular ring shape in plan view along the periphery of the gate metal 44.

A pair of first fingers 13 are formed along side 8 in the direction toward side 10 and the opposite side 11 relative to the pad periphery 12.

The second finger 14 includes a linear main portion 15 that crosses the active area 2 in a direction perpendicular to the first finger 13 up to the side 9, and multiple branch portions 16 that are integrally connected to the main portion 15 and extend from the connection point along the first finger 13. In this embodiment, the branch portions 16 are connected to two points, the tip and midway of the main portion 15, to form a total of two pairs of branch portions 16, but this number is not particularly limited.

In this way, cell regions 7 and 45 are defined in the active region 2 by the first finger 13 and second finger 14 (main portion 15 and branch portion 16). In this embodiment, a total of four inner cell regions 7 are formed, one at each corner of the intersection formed by the main portion 15 of the second finger 14 and the central branch portion 16. In addition, an annular outer cell region 45 is formed along the periphery of the active region 2 between the periphery of the active region 2 and the gate finger 5.

The source metal 43 is formed to cover almost the entire inner cell region 7 and outer cell region 45. A total of four openings 42 are formed in the passivation film 40 so that one source pad 6 is placed in each inner cell region 7.

In addition, a recess 17 corresponding to the shape of the gate metal 44 is formed in the source metal 43. The gate metal 44 is set back toward the inside of the active region 2 relative to the first finger 14, and the recess 17 is a depression formed to avoid this gate metal 44.

Figure 2 is an enlarged view of the area surrounded by dashed line II in Figure 1. That is, it is an enlarged view of the gate pad 4 of the semiconductor device 1 and the area surrounding it. Note that, for clarity, in Figure 2, some elements that are not exposed on the outermost surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

As shown in Figure 2, a plurality of transistor cells 18 are arranged in the inner cell region 7 and outer cell region 45 defined by the gate fingers 5 (pad periphery 12, first finger 13, and second finger 14).

In this embodiment, the multiple transistor cells 18 are arranged in a matrix in plan view in each of the inner cell region 7 and the outer cell region 45. Near the gate finger 5, the multiple transistor cells 18 are aligned to match the shape of the gate finger 5. For example, the multiple transistor cells 18 are aligned in a curved manner to match the shape of the corners of the pad peripheral portion 12, and are aligned in a straight line to match the shape of the main portion 15 of the linear second finger 14. The source metal 43 is formed to cover the multiple transistor cells 18.

For clarity, Figure 2 shows only a portion of the multiple transistor cells 18 covered with source metal 43. Furthermore, the arrangement of the multiple transistor cells 18 is not limited to a matrix, and may be, for example, a stripe or staggered pattern. Furthermore, the planar shape of each transistor cell 18 is not limited to a square, and may be, for example, a circle, a triangle, a hexagon, etc.

Gate electrodes 19 are formed between adjacent transistor cells 18. In the inner cell region 7 and outer cell region 45, the gate electrodes 19 are arranged between each of the matrix-arranged transistor cells 18, forming a lattice pattern in plan view as a whole. Meanwhile, these gate electrodes 19 are formed not only in the inner cell region 7 and outer cell region 45, but also in the region where the gate fingers 5 are arranged, with the lower portions of the gate fingers 5 making contact with the gate fingers 5.

In this embodiment, a portion of the gate electrode 19 is formed in the region below the first finger 13 and the second finger 14 and faces the first finger 13 and the second finger 14 as a contact portion. For clarity, in FIG. 2, the portion of the gate electrode 19 formed in this region below is represented by a hatched area. As a result, the gate electrodes 19 of adjacent inner cell regions 7 are continuous via the gate electrode 19 that crosses the second finger 14 below. This continuous form of the gate electrode 19 is also the same between the inner cell region 7 and the outer cell region 45 adjacent to the gate metal 44. In other words, the gate electrodes 19 in these regions are continuous via the gate electrode 19 that crosses the first finger 13 below.

The first finger 13 and the second finger 14 are each connected to a gate electrode 19 located in the region below them by a gate contact 20. The gate contact 20 is formed linearly along the longitudinal direction of each of the first finger 13 and the second finger 14 in the center of the finger, spaced apart from each side edge.

In addition, in this embodiment, multiple built-in resistors 21 are arranged below the gate metal 44. It is preferable to arrange the multiple built-in resistors 21 at positions approximately equidistant from each other from the center of gravity of the planar shape of the gate metal 44, thereby providing symmetry in the arrangement of the multiple built-in resistors 21. In this embodiment, the multiple built-in resistors 21 are arranged one at each corner of the gate metal 44, which is equidistant from the center of gravity G of the gate metal 44, which has a rectangular shape in plan view. This provides symmetry to the four built-in resistors 21.

Various such symmetrical patterns are possible. For example, two built-in resistors 21 may be arranged one at each of two diagonally opposite corners of the gate metal 44, or they may be arranged one on each of two opposite sides of the gate metal 44, facing each other. Furthermore, for example, if the gate metal 44 is circular in plan view, two built-in resistors 21 may be arranged one at each end of the diameter of the gate metal 44, or if the gate metal 44 is triangular in plan view, three built-in resistors 21 may be arranged one at each of the three corners of the gate metal 44.

Each built-in resistor 21 is formed across the annular gap region 26 between the gate metal 44 and the gate finger 5 (pad peripheral region 12), spanning both. This means that the built-in resistor 21 faces the gate metal 44 and the gate finger 5, respectively. The gate metal 44 and the gate finger 5 (pad peripheral region 12) are each connected to the built-in resistor 21 located in the region below them by a pad-side contact 22 and a cell-side contact 23.

In this embodiment, the four built-in resistors 21 extend from below the peripheral edge 24 of each of the two opposing sides of the gate metal 44 in an outward direction perpendicular to those sides to below the pad peripheral portion 12. Each built-in resistor 21 is formed in a rectangular shape in a plan view and has a size of, for example, 200 μm square or less (200 μm × 200 μm or less). In practice, if the size of each built-in resistor 21 is 200 μm square or less, the area of the region on the SiC epitaxial layer 28 (see Figure 4) sacrificed for the built-in resistor 21 can be reduced, thereby saving space.

The pad-side contacts 22 and cell-side contacts 23 are formed in parallel, straight lines along the edges of the gate metal 44 and pad peripheral portion 12, respectively.

The built-in resistor 21 is placed below the peripheral portion 24 of the gate metal 44, avoiding the center portion. Furthermore, the area above the area where the built-in resistor 21 is placed is covered with a passivation film 40. This ensures that the gate pad 4, which serves as a wire area surrounded by the built-in resistor 21, is located in the center of the gate metal 44. The gate pad 4 is the area to which the bonding wire is connected.

That is, in this embodiment, each corner of the gate metal 44 where the built-in resistor 21 is located is selectively covered with the passivation film 40, and the remaining portion of the gate metal 44 is exposed through the opening 41. As a result, a gate pad 4 that is rectangular in plan view and has each corner recessed inward is exposed on the outermost surface of the semiconductor device 1. In this way, by covering the area above the area where the built-in resistor 21 is located with the passivation film 40, it is possible to prevent the bonding wire from being erroneously bonded to the portion of the gate metal 44 that overlaps with the built-in resistor 21 when bonding the bonding wire. As a result, it is possible to prevent the built-in resistor 21 from being damaged or destroyed by impacts such as ultrasound when bonding the bonding wire.

Figure 3 is an enlarged view of the area surrounded by the two-dot chain line III in Figure 2. Figure 4 is a cross-sectional view of the semiconductor device 1 taken along the cutting line IV-IV in Figure 3. Note that, for clarity, the scale of each component in Figures 3 and 4 may differ from that in Figures 1 and 2, and the scale of each component may also differ between Figures 3 and 4. Also, for clarity, in Figures 3 and 4, some elements that are not exposed on the outermost surface of the semiconductor device 1 in an actual plan view are shown with solid lines.

Next, the detailed configuration of the built-in resistor 21 and its surrounding area will be described along with the cross-sectional structure of the semiconductor device 1.

The semiconductor device 1 includes a SiC substrate 27 and a SiC epitaxial layer 28. The SiC epitaxial layer 28 is stacked on the SiC substrate 27, and this stacked structure is shown as an example of a SiC layer in the present invention.

The SiC substrate 27 and the SiC epitaxial layer 28 are n ⁺ -type and n ^- -type SiC, respectively. The impurity concentration of the ^{n +} -type SiC substrate 27 is, for example, 1×10 ¹⁷ cm ^-3 to 1×10 ²¹ cm ^-3 . On the other hand, the impurity concentration of the n ^- -type SiC epitaxial layer 28 is, for example, 1×10 ¹⁴ cm ^-3 to 1×10 ¹⁶ cm ^-3 . Examples of n-type impurities that can be used include N (nitrogen), P (phosphorus), and As (arsenic) (the same applies hereinafter).

The thickness of the SiC substrate 27 is, for example, 50 μm to 1000 μm, and the thickness of the SiC epitaxial layer 28 is, for example, 5 μm or more (specifically, 5 μm to 100 μm).

In the inner cell region 7, a plurality of transistor cells 18 are formed on the surface portion of the SiC epitaxial layer 28. The plurality of transistor cells 18 include a p ^- type body region 29, an n ⁺ type source region 30 selectively formed in an inner region spaced apart from the periphery of the p ^- type body region 29, and a p ⁺ type body contact region 31 selectively formed in an inner region spaced apart from the periphery of the n ⁺ type source region 30. The n ^- type portion of the SiC epitaxial layer 28 serves as a common drain region for the plurality of transistor cells 18.

3, in a plan view, except for the transistor cells 18 along the pad peripheral portion 12 (gate fingers 5), an n ⁺ type source region 30 is formed so as to surround the p ⁺ type body contact region 31, and further, a ^p- type body region 29 is formed so as to surround the n ⁺ type source region 30. In the ^p- type body region 29, the annular region surrounding the n ⁺ type source region 30 is a channel region 32 in which a channel is formed when the semiconductor device 1 is turned on.

On the other hand, in the transistor cells 18 along the pad peripheral portion 12 (gate fingers 5), the p ^- type body regions 29 and p ⁺ type body contact regions 31 are electrically connected to the p ^- type regions 34 and p ⁺ type regions 33, respectively, which will be described later.

The impurity concentration of the p ^- type body region 29 is, for example, 1×10 ¹⁴ cm ^-3 to 1×10 ¹⁹ cm ^-3 , the impurity concentration of the n ⁺ type source region 30 is, for example, 1×10 ¹⁷ cm ^-3 to 1×10 ²¹ cm ^-3 , and the impurity concentration of the p ⁺ type body contact region 31 is, for example, 1×10 ¹⁹ cm ^-3 to 1×10 ²¹ cm ^-3 .

To form these regions 29-31, for example, a p ^- type body region 29 is formed by ion implantation into the surface portion of the SiC epitaxial layer 28. Then, an n-type impurity and a p-type impurity are ion-implanted sequentially into the surface portion of the p ^- type body region 29 to form an n ⁺ type source region 30 and a p ⁺ type body contact region 31. This forms a transistor cell 18 made up of the regions 29-31. For example, B (boron), Al (aluminum), or the like can be used as the p-type impurity (the same applies hereinafter).

In the active region 2, in a region other than the inner cell region 7 and the outer cell region 45, specifically, in the region below the gate metal 44, the gate finger 5, and the gap region 26, a p ^- type region 34 is formed in the surface portion of the SiC epitaxial layer 28. A p ⁺ type region 33 is formed in the surface portion of the p ^- type region 34.

The p ⁺ -type region 33 is formed over substantially the entire region below the gate metal 44, etc., so that the p ⁻ -type portion of the p ⁻ -type region 34 is selectively exposed at the SiC surface in a region of the SiC epitaxial layer 28 facing the built-in resistor 21, and the p ⁺ -type portion of the p + -type region 33 is selectively exposed at the SiC surface in other regions. That is, the gate metal 44 and the gate finger 5 face the p ⁻ -type portion in the region where the built-in resistor 21 is disposed, but face the p ⁺ -type portion in most other regions. The p ⁺ -type region 33 and the p ⁻ -type region 34 are each formed to extend below the source metal 43, and are integrally connected to the p ⁺ -type body contact region 31 and the p ⁻ -type body region 29 below the source metal 43 (in this embodiment, the portion outside the source pad 6). 3, the p ⁺ body contact region 31 and p ⁺ region 33 of the transistor cell 18 along the pad peripheral portion 12 (gate finger 5) are represented by hatched regions. In practice, the p ⁺ body contact region 31 is fixed to ground potential together with the source metal 43, thereby stabilizing the p ⁺ region 33 at 0 V. Therefore, as in this embodiment, it is preferable to have most of the gate metal 44 and the gate finger 5 facing the p ⁺ region 33.

The p ⁺ -type region 33 and the p ⁻ -type region 34 are formed in the same process as the p ⁺ -type body contact region 31 and the p ⁻ -type body region 29, respectively, and have the same impurity concentration and depth.

A gate insulating film 35 is formed on the surface of the SiC epitaxial layer 28. The gate insulating film 35 is made of an insulating material such as silicon oxide and has a thickness of, for example, 0.001 μm to 1 μm. The gate insulating film 35 is a common insulating film that insulates the gate electrode 19 and the built-in resistor 21 from the SiC epitaxial layer 28.

Gate electrode 19 and built-in resistor 21 are formed on gate insulating film 35. Gate electrode 19 is formed to face channel region 32 of each transistor cell 18 with gate insulating film 35 interposed therebetween. Meanwhile, built-in resistor 21 is formed to face exposed p ⁻ -type portion of p ⁻ -type region 34 with gate insulating film 35 interposed therebetween.

The gate electrode 19 and the built-in resistor 21 are both made of p-type polysilicon and may be formed in the same process. In this embodiment, the gate electrode 19 and the built-in resistor 21 contain B (boron) as a p-type impurity. B (boron)-containing polysilicon has a higher resistivity than phosphorus (P)-containing polysilicon, which is commonly used in Si semiconductor devices. Therefore, boron-containing polysilicon (built-in resistor 21) requires a smaller area than phosphorus-containing polysilicon to achieve the same resistance value. This allows the built-in resistor 21 to occupy a smaller area on the SiC epitaxial layer 28, thereby enabling more efficient use of space.

The concentration of p-type impurities contained in the polysilicon can be adjusted appropriately to match the design resistance values of the gate electrode 19 and the built-in resistor 21. In this embodiment, this concentration is set so that the sheet resistance of the built-in resistor 21 is 10 Ω/□ or higher. In practice, if the sheet resistance of the built-in resistor 21 is 10 Ω/□ or higher, the overall resistance of the built-in resistor 21 can be made greater than the resistance variation among multiple semiconductor devices 1 without increasing the area of the built-in resistor 21. For example, if the resistance variation is 0.1 Ω to 20 Ω, the resistance of the built-in resistor 21 can be set to 2 Ω to 40 Ω with a small area. As a result, the area of the region on the SiC epitaxial layer 28 sacrificed for the built-in resistor 21 can be reduced, minimizing the impact on the layout of other elements. In this case, the combined resistance of the gate electrode 19 and the built-in resistor 21 is preferably 4 Ω to 50 Ω.

Furthermore, it is preferable that the thickness of the gate electrode 19 and the built-in resistor 21 be 2 μm or less. By making the thickness of the built-in resistor 21 2 μm or less, it is possible to easily make the resistance value of the entire built-in resistor 21 larger than the variation in resistance value between multiple semiconductor devices 1. Conversely, if the built-in resistor 21 is too thick, its resistance value will be too low, which is not preferable.

An insulating film 47 is further formed on the SiC epitaxial layer 28. The insulating film 47 is made of an insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN) and has a thickness of, for example, 1 μm to 5 μm. In particular, it is preferable to use a BPSG (Boron Phosphorus Silicon Glass) film having a thickness of 1 μm or more.

The insulating film 47 includes an interlayer film 36 formed to cover the gate electrode 19 and built-in resistor 21. The interlayer film 36 is formed to extend into a region (first region) on the gate insulating film 35 where the gate electrode 19 and built-in resistor 21 are not located. This increases the distance (insulating film thickness T) between the SiC epitaxial layer 28 and the gate metal 44 in the region where the built-in resistor 21 is not located, thereby reducing the capacitance between them.

The pad-side contact 22 and the cell-side contact 23 are formed to penetrate this interlayer film 36. The pad-side contact 22 and the cell-side contact 23 are metal vias formed integrally with the gate metal 44 and the gate finger 5 (pad peripheral portion 12), respectively.

Furthermore, a source contact 46 is formed penetrating the interlayer film 36 to make contact from the source metal 43 to the n ⁺ -type source region 30 and the p ⁺ -type body contact region 31. The source contact 46 is made of a metal via formed integrally with the source metal 43.

Gate metal 44, gate fingers 5, and source metal 43 are formed on the interlayer film 36 at intervals from one another.

A passivation film 40 is formed on the interlayer film 36 to cover the gate metal 44, gate fingers 5, and source metal 43. Openings 41 and 42 are formed in the passivation film 40, exposing portions of the gate metal 44 and source metal 43.

As described above, according to the semiconductor device 1, as shown in Figures 3 and 4, a polysilicon resistor (built-in resistor 21) is interposed between the gate metal 44 and the gate finger 5 (pad peripheral portion 12). In other words, the built-in resistor 21 is interposed midway along the current path leading from the outside to the multiple transistor cells 18.

By adjusting the resistance value of this built-in resistor 21, the resistance value of the built-in resistor 21 can be made dominant over the total resistance value (gate resistance) of the gate electrode 19 and the built-in resistor 21. Therefore, even when multiple semiconductor devices 1 with varying gate electrode 19 resistance values are connected in parallel for use, by making the resistance value of the built-in resistor 21 larger than the variation, it is possible to limit the flow of current into semiconductor devices 1 with relatively low gate electrode 19 resistance values. As a result, noise generation during use can be reduced.

Furthermore, the polysilicon that makes up the built-in resistor 21 is a material whose resistance value can be easily controlled by implanting impurities, and its processing is also established using conventional semiconductor manufacturing technology. Therefore, the introduction of the built-in resistor 21 can avoid complicating the structure of the semiconductor device 1 itself and the module that includes it.

As with the gate electrode 19, variations in size and thickness of the built-in resistor 21 may occur due to variations in processing accuracy (etching dimensions, etc.) when manufacturing the semiconductor device 1, but the processing dimensions are smaller than those of the gate electrode 19. Therefore, variations in the built-in resistor 21 rarely cause noise generation.

In addition, because the built-in resistor 21 is connected to the gate metal 44 below the gate metal 44, the flow of gate current can be restricted at the entrance of the current path leading from the outside to multiple transistor cells 18. This makes it possible to prevent inrush current from flowing only to specific transistor cells 18.

For example, consider the case in Figure 2 where the built-in resistor 21 is formed midway through the first finger 13 or the second finger 14 of the gate finger 5 as a detour for these fingers 13, 14. In this case, on the side closer to the gate metal 44 than the built-in resistor 21, an inrush current may flow from the fingers 13, 14 to the gate electrode 19 via the gate contact 20 before reaching the built-in resistor 21. In contrast, if the gate current can be limited at the entrance of the current path, as in this embodiment, it is possible to reduce variations in switching speed among multiple transistor cells 18.

Furthermore, as shown in Figure 2, the built-in resistors 21 are arranged symmetrically. This feature also reduces variations in switching speed among multiple transistor cells 18.

3 and 4, in SiC epitaxial layer 28, the region facing built-in resistor 21 is p ^- type region 34 having an impurity concentration of 1×10 ¹⁹ cm ⁻³ or less. This effectively suppresses dielectric breakdown of gate insulating film 35. Furthermore, since p ^- type regions are less likely to accumulate carriers than n-type regions, it is also possible to reduce the capacitance between built-in resistor 21 and p ^- type region 34, which face each other across gate insulating film 35.

Furthermore, as shown in Figures 3 and 4, the gate metal 44 and the built-in resistor 21 are connected by a pad-side contact 22 made of a metal via. Therefore, the resistance value contributed by the built-in resistor 21 in the current path extending from the outside to the multiple transistor cells 18 can be easily adjusted by processing the position of the pad-side contact 22 along the surface of the SiC epitaxial layer 28 or by processing the via diameter.

For example, as with pad-side contact 37 shown by dashed lines in FIG. 4 , simply by being closer to the pad peripheral area 12 than pad-side contact 22, the distance from the contact position for built-in resistor 21 to pad peripheral area 12 can be easily shortened from _D1 to _D2 . This reduces the resistance of built-in resistor 21. Conversely, by being farther away from pad peripheral area 12, the resistance of built-in resistor 21 can be increased. Also, as with pad-side contact 38 shown by dashed lines in FIG. 3 , the resistance of the current path toward built-in resistor 21 can be increased simply by making the via diameter smaller than that of pad-side contact 22. Conversely, by increasing the via diameter, the resistance of the path can be reduced.

Furthermore, these processes only require the use of a mask that matches the distance and via diameter design when forming the pad-side contacts 22 (vias), preventing the manufacturing process from becoming complicated.

Figure 5 is an enlarged view of the area surrounded by the two-dot chain line V in Figure 2. Figure 6 is a cross-sectional view of the semiconductor device taken along the cutting line VI-VI in Figure 5. Note that, for clarity, the scale of each component in Figures 5 and 6 may differ from that in Figures 1 to 4, and the scale of each component may also differ between Figures 5 and 6. Also, for clarity, in Figures 5 and 6, some elements that are not exposed on the outermost surface of the semiconductor device 1 in an actual plan view are shown with solid lines.

Next, the detailed configuration of the peripheral portion of the active region 2 and the outer peripheral region 3 of the semiconductor device 1 will be described along with the cross-sectional structure of the semiconductor device 1.

As mentioned above, in the outer cell region 45 formed on the periphery of the active region 2, multiple transistor cells 18 are arranged in a matrix in plan view. The configuration of each transistor cell 18 is similar to the configuration described in Figures 3 and 4.

Outside the outer cell region 45, a p ^- type region 51 is formed in the surface portion of the SiC epitaxial layer 28. A p ⁺ type region 52 is formed in the surface portion of the p ^- type region 51. The p ^- type region 51 is formed linearly along the periphery of the active region 2 and is integrated with the p ^- type body regions 29 of the (outermost) plurality of transistor cells 18. Note that while FIG. 5 shows only the portion of the p ^- type region 51 adjacent to the outer cell region 45, in reality, the p ^{-type region 51 may surround the cell regions (the inner cell region 7 and the outer cell region 45) along the entire periphery of the active region 2. The p+} type region 52 is formed linearly extending in the longitudinal direction in an inner region of the p ^- type region 51 (a region spaced from the periphery of the p ^- type region 51). The p ⁻ -type region 51 and the p ⁺ -type region 52 are formed in the same process as the p ⁻ -type body region 29 and the p ⁺ -type body contact region 31, respectively, and have the same impurity concentration and depth.

A plurality of guard rings 53, which are an example of a termination structure of the present invention, are further formed on the periphery of the active region 2 so as to surround the cell regions (the inner cell region 7 and the outer cell region 45). The plurality of guard rings 53 are arranged in a guard ring region of a predetermined width (G) from the outermost region (in this embodiment, the p ^- type region 51) of the SiC epitaxial layer 28 that is at the same potential as the source metal 43. In this embodiment, the predetermined width (G) is 5 μm to 100 μm (e.g., 28 μm). When the guard rings 53 are formed in the same process as the p ^- type body region 29, the impurity concentration and depth are also the same. When formed in a separate process, the impurity concentration is, for example, 1×10 ¹⁴ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ and the depth is 0.1 μm to 2 μm.

On the other hand, in peripheral region 3, p ^- type region 55 is formed in the surface portion of SiC epitaxial layer 28, and p ⁺ type region 56 is formed in the surface portion of p ^- type region 55. Like p ^- type region 51 and p ⁺ type region 52, p ^- type region 55 and p ⁺ type region 56 are regions formed in the same process as p ^- type body region 29 and p ⁺ type body contact region 31 (they have the same impurity concentration and depth). However, p ^- type region 55 and p ⁺ type region 56 form a stacked structure because p ⁺ type region 56 is formed over the entire surface portion of p ^- type region 55.

The p ⁻ -type region 55 and the p ⁺ -type region 56 in the peripheral region 3 are formed in a dicing region 54 set at the end of the SiC epitaxial layer 28. As shown in FIGS. 7A and 7B , the dicing region 54 is a region of a predetermined width that includes a dicing line 58 set at the boundary between adjacent semiconductor devices 1 in the wafer 57. Each semiconductor device 1 is separated by cutting the wafer 57 along the dicing line 58. At this time, it is necessary to provide a margin of a predetermined width in consideration of misalignment of the dicing saw, and this margin portion remains as the dicing region 54 after separation.

The p ⁻ -type region 55 and the p ⁺ -type region 56 (p-type regions) are arranged in the dicing region 54 so as to be exposed at an end surface 59 of the SiC epitaxial layer 28. In this embodiment, the width (F) of the p ⁻ -type region 55 and the p ⁺ -type region 56 based on the exposed surface (end surface 59) is 5 μm to 100 μm (e.g., 20 μm). This width (F) may be set, for example, in a range equal to or greater than the difference between the width (D) of the dicing region 54 and twice the width (E) of the depletion layer 60 extending from the guard ring 53. In designing the width (F), the width (D) of the dicing region 54 can be the distance from the end surface 59 of the SiC epitaxial layer 28 to the edge of the passivation film 40 (e.g., 13 μm). Meanwhile, the width (E) of the depletion layer 60 can be calculated using the following formula (1):

(where ε _s is the dielectric constant of SiC, V _bi is the built-in potential of the pn junction between the p-type guard ring 53 and the n-type SiC epitaxial layer 28, q is the absolute value of the charge, and N _B is the donor concentration of the n-type SiC epitaxial layer 28.)
In addition to the interlayer film 36, the insulating film 47 further includes an under-metal insulating film 61 and an end insulating film 62, which are examples of the under-electrode insulating film of the present invention. A contact hole 63 exposing the p ⁺ type region 52 is formed in the insulating film 47, and the inner portion of the contact hole 63 is the interlayer film 36, which is formed on the gate insulating film 35. On the other hand, the outer portion adjacent to the interlayer film 36 across the contact hole 63 is the under-metal insulating film 61.

The source metal 43 is connected to the p ⁺ -type region 52 via a contact hole 63. The source metal 43 also has an overlap portion 64 that extends laterally outward to overlap the under-metal insulating film 61. The overlap portion 64 faces the guard ring 53 across the under-metal insulating film 61. In this embodiment, the overlap portion 64 is provided so as to partially cover the region where the guard ring 53 is formed (a guard ring region having a width (G)), and its end is located inside the outer end of the guard ring region. The overlap portion 64 may cover the entire guard ring region, but the position of its end is determined so that the distance (B) in FIG. 6 is 40 μm or more (e.g., 45 μm to 180 μm). The distance (B) is the lateral length between the source metal 43 and the SiC epitaxial layer 28 on the under-metal insulating film 61. In this embodiment, the distance (B) is the length from the edge of the overlap portion 64 to the edge of the under-metal insulating film 61. The distance (B) may be twice or more the width (E) of the depletion layer 60 .

As mentioned above, the source metal 43 preferably has a layered structure represented by Ti/TiN/Al-Cu. For example, in this embodiment, the source metal 43 includes a Ti/TiN film 65 (barrier film) and an Al-Cu film 66, which are layered in this order from the SiC epitaxial layer 28 side. Note that the Ti/TiN film 65 and the Al-Cu film 66 are not shown in Figure 4.

An n-type region 67 (first conductivity type region) is formed outside the under-metal insulating film 61, exposing the SiC surface of the SiC epitaxial layer 28 over a distance (A). The n-type region 67 is a portion of the SiC epitaxial layer 28 exposed through an opening 68 formed outside the under-metal insulating film 61 (in this embodiment, between the under-metal insulating film 61 and the edge insulating film 62). As shown in FIG. 5, the opening 68 is formed linearly, for example, along the boundary between the active region 2 and the peripheral region 3. The distance (A) of the n-type region 67 is 40 μm or more (e.g., 45 μm to 180 μm), but the sum of the distance (A) and the distance (B) is preferably 180 μm or less. By keeping the sum of the distances (A) and (B) 180 μm or less, the chip size of the semiconductor device 1 can be kept reasonable.

The edge insulating film 62 is formed so as to cover the dicing region 54 of the SiC epitaxial layer 28. Specifically, the edge insulating film 62 extends laterally from the edge surface 59 of the SiC epitaxial layer 28, beyond the dicing region 54, and into a region further inward. In this embodiment, the width (H) of the edge insulating film 62 based on the edge surface 59 is 10 μm to 105 μm (for example, 22 μm). As a result, the p ⁻ -type region 55 and the p ⁺ -type region 56 (p-type regions) are covered with the edge insulating film 62.

The passivation film 40, together with the insulating film 47, is an example of an insulator according to the present invention and is made of an organic insulator. Examples of organic insulators that can be used include polyimide-based materials, polybenzoxazole-based materials, and acrylic-based materials. In other words, in this embodiment, the passivation film 40 is configured as an organic passivation film. The thickness of the passivation film 40 is, for example, 0.2 μm to 20 μm.

The passivation film 40 is formed to cover the insulating film 47. In this embodiment, the passivation film 40 is formed over almost the entire SiC epitaxial layer 28, except that it does not cover the end of the SiC epitaxial layer 28 (in other words, the passivation film 40 defines the dicing region 54). Therefore, the passivation film 40 contacts the n-type region 67 of the SiC epitaxial layer 28 over a distance (A) of 40 μm or more in the opening 68 of the insulating film 47.

The passivation film 40 does not cover the end of the SiC epitaxial layer 28, but has an overlapping portion 69 that overlaps a portion of the end insulating film 62. This overlapping portion 69 prevents the SiC surface of the SiC epitaxial layer 28 from being exposed to the outside. In this embodiment, the overlap width (C) between the overlapping portion 69 and the end insulating film 62 is 5 μm or more (for example, 9 μm). In this embodiment, the overlapping portion 69 is formed inward and spaced apart from the p-type regions (p ⁻ -type region 55 and p ⁺ -type region 56) in a plan view. As a result, the overlapping portion 69 faces the n-type portion of the SiC epitaxial layer 28 across the end insulating film 62, but does not face the p-type region.

As described above, with the semiconductor device 1, as shown in Figures 5 and 6, the distance (A) is 40 μm or greater, ensuring sufficient contact area between the organic passivation film 40 and the SiC epitaxial layer 28 (n-type region 67). This improves adhesion of the organic passivation film 40 to the SiC epitaxial layer 28. Furthermore, because the distance (B) is 40 μm or greater or greater than twice the width (E) of the depletion layer 60, the device can withstand high-temperature, high-humidity, high-voltage testing (e.g., 1,000 hours of continuous testing under conditions of 85°C, 85% RH, and 960 V). Setting the distances (A) and (B) within the above ranges is a completely new finding for SiC semiconductor devices. Because the lateral expansion of the depletion layer 60 in SiC is smaller than that in Si, it was previously unnecessary to increase the distances (A) and (B) to increase the chip size. This is because the depletion layer 60 is unlikely to reach the chip end surface 59 even without increasing the chip size, and increasing the chip size could result in an increase in on-resistance per chip area. Based on this background, the inventors of the present application discovered that by deliberately setting distance (A) and distance (B) to 40 μm or greater, it is possible to improve resistance to high-temperature, high-humidity, high-voltage testing.

Furthermore, in this embodiment, p-type regions (p ⁻ -type region 55 and p ⁺ -type region 56) are formed in SiC epitaxial layer 28, and these p-type regions are further covered with edge insulating film 62. Therefore, when testing the electrical characteristics of semiconductor device 1 in the state of wafer 57 before dicing as shown in FIG. 7A , it is possible to reduce the burden of voltage Va applied to the atmosphere between dicing region 54 and source metal 43 (portion exposed from opening 42).

In the test, for example, the source metal 43 of one semiconductor device 1 is set to 0 V, and the backside of the wafer 57 is set to 1000 V or more (e.g., 1700 V). This applies a maximum applied voltage (BV) that generates a potential difference of 1000 V or more between the source metal 43 and the wafer 57, and the breakdown voltage of each MOSFET is measured. At this time, the n-type portion of the wafer 57, including a portion of the dicing region 54 (portions other than the p ⁻ -type region 55 and the p ⁺ -type region 56), is fixed to a potential of 1000 V or more, resulting in a potential difference of 1000 V or more between the dicing region 54 and the source metal 43. Even in such a case, according to this embodiment, p-type regions (p ⁻ -type region 55 and p ⁺ -type region 56) are formed along the dicing region 54, and the dicing region 54 is further covered with an edge insulating film 62. Therefore, the maximum applied voltage (BV) of 1000 V or more applied between the dicing region 54 and the source metal 43 can be mitigated in two stages: the end insulating film 62 and the p-type region (p ⁻ -type region 55 and p ⁺ -type region 56). This reduces the burden of the voltage Va applied to the atmosphere between the dicing region 54 and the source metal 43. As a result, a semiconductor device 1 with a breakdown voltage value (BV) of 1000 V or more can be realized.

Furthermore, by making the thickness of the under-metal insulating film 61 1 μm or more, it is possible to prevent dielectric breakdown even when a voltage of 1000 V or more is applied to the under-metal insulating film 61. Furthermore, if the insulating film 47 is BPSG, the under-metal insulating film 61 and the end insulating film 62 can be easily planarized by reflow, and the corners of the insulating films 61 and 62 can be rounded (smoothed). As a result, the adhesion of the passivation film 40 to the insulating films 61 and 62 can be improved.

In addition, since the dicing region 54 is not covered with the passivation film 40, the semiconductor device 1 in the form of wafer 57b can be easily divided (diced).

Figures 8 to 14 are schematic cross-sectional views of semiconductor devices according to second to eighth embodiments of the present invention, respectively. In Figures 8 to 14, elements corresponding to those in Figure 6 above are denoted by the same reference numerals.

Next, we will explain another embodiment of the present invention, focusing on the differences from the semiconductor device 1 of the first embodiment.

8, the overlap portion 69 of the passivation film 40 is formed so as to selectively cover the p-type region (p ⁻ -type region 55 and p ⁺ -type region 56) via the end insulating film 62. As a result, the overlap portion 69 has an overlapping portion with the p-type region.

In the semiconductor device 73 of Figure 9, the edge insulating film 62 is not formed; instead, the passivation film 40 covers the SiC epitaxial layer 28 up to the edge surface 59. In this case, the dicing region 54 can be set to an appropriate width (D) from the edge surface 59. Furthermore, the distance (A) can be defined as the length from the edge of the under-metal insulating film 61 to the edge surface 59 of the SiC epitaxial layer 28.

10 has the same configuration as the semiconductor device 73 of FIG. 9 except that p ⁻ -type region 55 and p ⁺ -type region 56 (p-type region) are formed in dicing region 54. In this case, distance (A) may be defined as the length from the edge of under-metal insulating film 61 to the p-type region. In other words, distance (A) may be 40 μm or more with respect to the section where passivation film 40 contacts the n-type portion of SiC epitaxial layer 28.

11 , at least two openings 68 are formed in the insulating film 47 outside the under-metal insulating film 61. In this embodiment, an opening 68 is formed between the under-metal insulating film 61 and the outer insulating film 79, and between the outer insulating film 79 and the end face 59 of the SiC epitaxial layer 28. In each opening 68, the passivation film 40 contacts the n-type region 67 of the SiC epitaxial layer 28 over a distance (A ₁ ) and a distance (A ₂ ). In this case, the total distance of the section where the passivation film 40 contacts the n-type region 67, including the distances (A ₁ ) and (A ₂ ) of the contact sections in each of the multiple n-type regions 67, may be 40 μm or more.

12 has the same configuration as the semiconductor device 73 of FIG. 9 except that a recess 80 is selectively formed in the n-type region 67. In the recess 80, the passivation film 40 contacts the n-type region 67 on the inner surface (bottom and both side surfaces) of the recess 80. In this case, the total distance of the section where the passivation film 40 contacts the n-type region 67 may be 40 μm or more, including the contact distance (A ₅ ) in the region other than the recess 80 and the distances (A ₃ ) and (A ₄ ) of the contact sections on the bottom and both side surfaces of the recess 80.

In the semiconductor device 77 of Figure 13, the transistor cells 18 are composed of MOSFET cells with a trench gate structure. In this case, the gate electrodes 19 are embedded in gate trenches 39 formed between each of the multiple transistor cells 18, with the gate insulating film 35 interposed between them.

In the semiconductor device 78 of Figure 14, a Schottky barrier diode 81 is formed in the active region 2. In other words, instead of the source metal 43, a Schottky metal 82 is provided that forms a Schottky junction with the SiC epitaxial layer 28.

As described above, the semiconductor devices 72 to 78 of the second to eighth embodiments all have three characteristics: (1) the distance (A) is 40 μm or more; (2) the distance (B) is 40 μm or more or is at least twice the width (E) of the depletion layer 60; and (3) the ends of the SiC epitaxial layer 28 are covered with an insulator (end insulating film 62 or passivation film 40). Therefore, like the first embodiment, the second to eighth embodiments can provide SiC semiconductor devices that can prevent discharge during electrical characteristic tests performed in wafer form and can withstand high-temperature, high-humidity, high-voltage tests.

The above describes an embodiment of the present invention, but the present invention can also be implemented in other forms.

For example, the transistor cell 18 may be an IGBT cell having a planar gate structure or a trench gate structure. In this case, a p ⁺ type SiC substrate 27 may be used instead of the n ⁺ type SiC substrate 27 in Figures 4 and 13. In addition, various semiconductor element structures may be formed in the active region 2.

Furthermore, surface electrodes such as the source metal 43 and Schottky metal 82 do not need to be made of metal, but may be semiconductor electrodes such as polysilicon.

Furthermore, the built-in resistor 21 does not need to be embedded in the interlayer film 36 below the gate metal 44; for example, polysilicon wiring connecting the gate metal 44 and the gate finger 5 may be formed as a built-in resistor on the surface of the interlayer film 36.

In addition, instead of polysilicon, the material for the built-in resistor 21 may be a material having a resistance value equal to or greater than that of the gate metal 44 and gate finger 5 (for example, metal wiring such as Al (aluminum), AlCu (aluminum-copper alloy), or Cu (copper)). Even if the built-in resistor 21 is metal, the distance between the gate metal 44 and the gate finger 5 can be increased, thereby increasing the total resistance value of the gate electrode 19 and the built-in resistor 21.

Furthermore, the built-in resistor 21 does not need to be formed below the gate metal 44; it may be formed, for example, below the gate finger 5.

Furthermore, the built-in resistor 21 may be linear and extend along part of the peripheral edge 24 of the gate metal 44, or may be annular and extend along the entire periphery of the peripheral edge 24 of the gate metal 44.

Furthermore, a configuration in which the conductivity types of the semiconductor portions of the semiconductor device 1 described above are reversed may be adopted. For example, in the semiconductor device 1, the p-type portions may be n-type, and the n-type portions may be p-type.

In addition, various design modifications may be made within the scope of the claims.

Furthermore, the following features can be extracted from the above-mentioned embodiment.

A semiconductor device (item 1) comprising: a SiC layer of a first conductivity type; an electrode selectively formed on the SiC layer; and an insulator formed on the SiC layer and reaching a dicing area set at the edge of the SiC layer, the insulator including an under-electrode insulating film arranged to extend from below the electrode toward the dicing area and an organic insulating layer arranged to cover the under-electrode insulating film, the distance (A) of the section where the organic insulating layer contacts the SiC layer being 40 μm or more, and the lateral distance (B) from the edge of the electrode on the under-electrode insulating film to the portion where the organic insulating layer contacts the SiC layer being 40 μm or more.

With this configuration, the dicing area is covered with an insulator, which reduces the burden of the voltage applied to the atmosphere between the dicing area and the electrodes when testing the electrical characteristics of semiconductor devices in wafer form. In other words, the voltage applied between the dicing area and the electrodes can be shared between the atmosphere and the insulator, preventing discharge in the atmosphere.

Furthermore, because distance (A) is 40 μm or greater, sufficient contact area between the organic insulating layer and the SiC layer can be ensured, improving the adhesion of the organic insulating layer to the SiC layer. Furthermore, because distance (B) is 40 μm or greater, the device can withstand high-temperature, high-humidity, high-voltage testing. Setting distances (A) and (B) within the above ranges is a completely new finding for SiC semiconductor devices. Because the lateral expansion of the depletion layer in SiC is smaller than in Si, it was previously unnecessary to increase distances (A) and (B) and increase the chip size. This is because the depletion layer is unlikely to reach the chip edge even without increasing the chip size, and increasing the chip size could result in an increase in on-resistance per chip area. Based on this background, the inventors of the present application discovered that by intentionally setting distances (A) and (B) to 40 μm or greater, the device can withstand high-temperature, high-humidity, high-voltage testing.

If the semiconductor device further includes a second conductivity type region formed in the dicing region, the distance (A) may be 40 μm or more in the section where the organic insulating layer contacts the first conductivity type region of the SiC layer (Item 2).

With this configuration, the voltage applied between the dicing region and the electrode can be distributed to the second conductivity type region as well. This makes it possible to more effectively prevent discharge in the atmosphere.

The organic insulating layer may be formed to cover the dicing region and may be in contact with the second conductivity type region in the dicing region (item 3).

When the organic insulating layer does not cover the dicing area and the insulator further includes an edge insulating film made of the same film layer as the under-electrode insulating film, covering the dicing area and partially overlapping the organic insulating layer, the overlap width (C) between the organic insulating layer and the edge insulating film may be 5 μm or more (Item 4).

With this configuration, the dicing area is not covered with an organic insulating layer, making it easy to separate (diced) the semiconductor device in wafer form. Even in this case, the dicing area is covered with an edge insulating film that forms an insulator, so the above-mentioned discharge prevention effect can be fully achieved.

When the insulator is made of the same layer as the under-electrode insulating film and further includes an edge insulating film covering the dicing region, the organic insulating layer overlaps the edge insulating film so as to selectively cover the second conductivity type region via the edge insulating film, and the overlap width (C) between the organic insulating layer and the edge insulating film may be 5 μm or more (Item 5).

The edge insulating film may have the same thickness as the under-electrode insulating film (item 6).

This configuration simplifies the manufacturing process, as the end insulating film can be fabricated in the same process as the under-electrode insulating film.

The distance (A) may be 45 μm to 180 μm (item 7), and the distance (B) may be 45 μm to 180 μm (item 8). The sum of the distances (A) and (B) may be 180 μm or less (item 9).

By keeping distance (A) and distance (B) within the above ranges, the chip size of the semiconductor device can be kept at a reasonable size. Also, since atmospheric discharge is likely to occur when distance (A) and distance (B) are within the above ranges, it is useful to cover the dicing area with an insulator.

The breakdown voltage (BV) of the semiconductor device may be 1000 V or more (Item 10).

When the breakdown voltage (BV) is 1000V or higher, atmospheric discharge is likely to occur, so it is helpful to cover the dicing area with an insulator.

The SiC layer may have a first conductivity type impurity concentration of 1×10 ¹⁶ cm ⁻³ or less, and a thickness of 5 μm or more (Item 11).

If the semiconductor device further includes a second conductivity type termination structure consisting of an impurity region formed in the SiC layer outward from the electrode, the width (F) of the second conductivity type region may be equal to or greater than the difference between the width (D) of the dicing region and twice the width (E) of the depletion layer extending from the termination structure (Item 12).

The electrode may have a layered structure represented by Ti/TiN/Al-Cu (Item 13).

By using Al-Cu, resistance to humidity can be further improved.

The under-electrode insulating film may be made of a SiO ₂ film having a thickness of 1 μm or more (Item 14). In this case, the SiO ₂ film may contain phosphorus (P) or boron (B) (Items 15 and 16).

If an _SiO2 film with a thickness of 1 μm or more is used, dielectric breakdown can be prevented even when a voltage of 1000 V or more is applied to the insulating film under the electrode. Furthermore, if phosphorus (P) or boron (B) is included, the insulating film under the electrode can be easily flattened by reflow. Furthermore, the corners of the insulating film under the electrode can be rounded.

The under-electrode insulating film may be made of a SiN film having a thickness of 1 μm or more (Item 17).

If a SiN film with a thickness of 1 μm or more is used, dielectric breakdown can be prevented even when a voltage of 1000 V or more is applied to the insulating film under the electrode.

The organic insulating layer may be made of a polyimide-based material, a polybenzoxazole-based material, an acrylic-based material, or the like (items 18, 19, and 20).

A MOSFET may be formed on the SiC layer as a semiconductor device structure, and the electrode may include a source electrode electrically connected to the source of the MOSFET (item 21). In this case, the MOSFET may have a planar gate structure (item 22) or a trench gate structure (item 23).

Furthermore, a Schottky barrier diode may be formed in the SiC layer as a semiconductor element structure, and the electrode may include a Schottky electrode that forms part of the Schottky barrier diode (Item 24).

Furthermore, an IGBT may be formed as a semiconductor element structure on the SiC layer, and the electrode may include a source electrode electrically connected to the source of the IGBT (item 25).

If the organic insulating layer is in contact with the SiC layer in multiple regions, the distance (A) may be 40 μm or more in total across the contact sections in each of the multiple regions (Item 26).

If the semiconductor device further includes a recess selectively formed in the SiC layer and filled with the organic insulating layer, the distance (A) may be 40 μm or more in total, including the contact area of the organic insulating layer on the inner surface of the recess (Item 27).

A semiconductor device extracted from the above-described embodiment includes a first conductivity type SiC layer, an electrode selectively formed on the SiC layer, an insulator formed on the SiC layer and reaching a dicing region set at an end of the SiC layer, and a second conductivity type termination structure consisting of an impurity region formed in the SiC layer outward from the electrode, wherein the insulator includes an under-electrode insulating film arranged to extend from below the electrode toward the dicing region and an organic insulating layer arranged to cover the under-electrode insulating film, wherein the distance (A) of the section where the organic insulating layer contacts the SiC layer is 40 μm or more, and the lateral distance (B) from the end of the electrode on the under-electrode insulating film to the portion where the organic insulating layer contacts the SiC layer may be two times or more the width (E) of a depletion layer extending from the termination structure (Item 28).

With this configuration, the dicing area is covered with an insulator, so when testing the electrical characteristics of semiconductor devices in wafer form, the applied voltage can be alleviated by the insulator. This reduces the burden of the voltage applied to the atmosphere between the dicing area and the electrode. In other words, the voltage applied between the dicing area and the electrode can be shared between the atmosphere and the insulator, preventing discharge in the atmosphere.

Furthermore, since the distance (A) is 40 μm or more and the distance (B) is at least twice the width (E) of the depletion layer extending from the termination structure, it can also withstand high-temperature, high-humidity, high-voltage tests.

1 semiconductor device 2 active region 18 transistor cell 19 gate electrode 27 SiC substrate 28 SiC epitaxial layer 29 p ^- type body region 30 n ⁺ type source region 31 p ⁺ type body contact region 32 channel region 35 gate insulating film 36 interlayer film 39 gate trench 40 passivation film 43 source metal 44 gate metal 47 insulating film 51 p ^- type region 52 p ⁺ type region 53 guard ring 54 dicing region 55 p ^- type region 56 p ⁺ type region 57 wafer 58 dicing line 59 end surface 60 depletion layer 61 under-metal insulating film 62 end insulating film 63 contact hole 64 overlapping portion 65 Ti/TiN film 66 Al-Cu film 67 n-type region 68 opening 69 overlapping portion 72 semiconductor device 73 semiconductor device 74 semiconductor device 75 semiconductor device 76 semiconductor device 77 semiconductor device 78 semiconductor device 79 semiconductor device 80 recess 81 Schottky barrier diode 82 Schottky metal

Claims (20)

an active region having a plurality of transistor elements formed on a surface thereof;
an outer peripheral region that is a peripheral portion of the active region;
a first conductivity type SiC layer having a chip end face in the outer peripheral region and a recess formed on the surface;
a first pad electrode and a second pad electrode selectively formed on the SiC layer and electrically connected to first electrodes and second electrodes of the plurality of transistor elements, respectively;
a first insulating film formed on the SiC layer side in the active region so as to at least partially overlap the first pad electrode;
a second insulating film formed on the SiC layer side so as to overlap at least a portion of the first pad electrode and extending partway through the outer periphery region toward the chip end face;
a surface insulating film covering at least a portion of the first pad electrode, the first insulating film, and the second insulating film;
a termination structure having an impurity region of a second conductivity type formed outside the first pad electrode of the SiC layer,
the recess is formed in a first conductivity type impurity region of the SiC layer, the first conductivity type impurity region being spaced apart from the second conductivity type impurity region;
the surface insulating film covers an end portion of the second insulating film in the peripheral region, and contacts the SiC layer at a bottom surface and a side surface of the recess that is closer to the chip end face than the termination structure and does not have the second conductivity type impurity region. the SiC layer is formed in a quadrangular shape in plan view, with the chip end surface having four sides;
The semiconductor device according to claim 1 , wherein the second pad electrode is disposed at the center of one of the four sides. a gate finger electrically connected to the second pad electrode and dividing a central portion of the first pad electrode;
3. The semiconductor device according to claim 1, wherein the gate finger is electrically connected to the second pad electrode via a built-in resistor made of polysilicon. The semiconductor device according to any one of claims 1 to 3, wherein the plurality of transistor elements include a plurality of transistor cells arranged in a matrix in a planar view. The semiconductor device according to claim 3, wherein the gate finger extends from the second pad electrode across a central portion of the first pad electrode from the side on which the second pad electrode is disposed to the opposite side. a first contact portion is a portion of the surface insulating film that is in contact with the SiC layer on a bottom surface and a side surface of the recess;
6. The semiconductor device according to claim 1, wherein a thickness of the surface insulating film in a region directly above the recess in a thickness direction of the SiC layer is thicker than a thickness of the first contact portion. a dicing region is formed at an end of the SiC layer;
7. The semiconductor device according to claim 1, wherein the SiC layer includes a second conductivity type region formed in the first conductivity type region of the dicing region. The semiconductor device described in claim 7, wherein the width (F) of the second conductivity type region is equal to or greater than the difference between the width (D) of the dicing region and twice the width (E) of the depletion layer extending from the termination structure. The semiconductor device described in any one of claims 1 to 8, wherein the breakdown voltage is 1000 V or more. the SiC layer has a first conductivity type impurity concentration of 1×10 ¹⁶ cm ⁻³ or less;
10. The semiconductor device according to claim 1, wherein the SiC layer has a thickness of 5 μm or more. The semiconductor device described in any one of claims 1 to 10, wherein the first pad electrode has a layered structure represented by Ti/TiN/Al-Cu. 12. The semiconductor device according to claim 1, wherein the second insulating film is made of a SiO ₂ film having a thickness of 1 μm or more. The semiconductor device according to any one of claims 1 to 11, wherein the second insulating film is a SiN film having a thickness of 1 μm or more. The semiconductor device described in any one of claims 1 to 13, wherein the surface insulating film includes an organic insulating layer made of a polyimide-based material. A MOSFET is formed as the transistor element,
15. The semiconductor device according to claim 1, wherein the first pad electrode includes a source electrode electrically connected to a source through which an on-current of the MOSFET flows. The semiconductor device of claim 15, wherein the MOSFET has a planar gate structure. an IGBT is formed as the transistor element,
15. The semiconductor device according to claim 1, wherein the first pad electrode includes an emitter electrode electrically connected to an emitter through which an on-current of the IGBT flows. the transistor element has a first region of a second conductivity type formed in a surface portion of the SiC layer, and a second region of the second conductivity type formed in a surface portion of the first region and having a higher impurity concentration than the first region;
a contact hole exposing the second region of the transistor element is formed between the first insulating film and the second insulating film;
18. The semiconductor device according to claim 1, wherein the first pad electrode and the second region of the transistor element are electrically connected via the contact hole. The semiconductor device described in any one of claims 1 to 18, wherein the surface insulating film has a flat upper surface near the chip end surface of the SiC layer. 20. The semiconductor device according to claim 1, wherein the surface insulating film is in contact with the first conductivity type impurity region of the SiC layer exposed over the entire bottom and side surfaces of the recess.