JP7770901B2 - Semiconductor device manufacturing method - Google Patents

Description

Embodiments of the present invention relate to semiconductor manufacturing equipment and semiconductor device manufacturing methods.

As semiconductor devices become increasingly miniaturized, high-precision processing is required when processing layers using dry etching. For example, when manufacturing three-dimensional semiconductor memories, it is desirable to form memory holes with high aspect ratios with high processing precision.

JP 2012-199535 A Japanese Patent Application Laid-Open No. 2001-102435

In one embodiment of the present invention, the objective is to process a workpiece layer with high precision when dry etching it.

In a manufacturing method of a semiconductor manufacturing apparatus according to an embodiment, a substrate having a workpiece layer is placed on a holder provided in a chamber and having a recess provided on a surface thereof, a first hole provided in the recess, and a second hole provided in the recess; a first valve provided in a first gas passage connected to the first hole and a second valve provided in a second gas passage connected to the second hole are opened to supply a first gas that comes into contact with the substrate between the holder and the substrate via the first gas passage and the second gas passage; a pressure of the first gas is controlled to a first pressure; and a first etching process is performed to etch the workpiece layer using a reactive ion etching method; a first etching process, a second etching process, ...

1 is a schematic cross-sectional view of a semiconductor device manufactured by a semiconductor device manufacturing method according to a first embodiment; FIG. 2 is a schematic diagram of an example of a reactive ion etching apparatus used in the method for manufacturing the semiconductor device according to the first embodiment. 3A to 3C are explanatory diagrams of a method for manufacturing the semiconductor device according to the first embodiment. 5A to 5C are schematic views showing a method for manufacturing the semiconductor device according to the first embodiment; 5A to 5C are schematic views showing a method for manufacturing the semiconductor device according to the first embodiment; 5A to 5C are schematic views showing a method for manufacturing the semiconductor device according to the first embodiment; 5A to 5C are schematic views showing a method for manufacturing the semiconductor device according to the first embodiment; 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a second embodiment. 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a third embodiment. 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fourth embodiment. 10A to 10C are explanatory diagrams of a method for manufacturing a semiconductor device according to a fifth embodiment. 10A to 10C are schematic views showing a method for manufacturing a semiconductor device according to a fifth embodiment. 10A to 10C are schematic views showing a method for manufacturing a semiconductor device according to a fifth embodiment. 10A to 10C are schematic views showing a method for manufacturing a semiconductor device according to a fifth embodiment. 10A to 10C are schematic views showing a method for manufacturing a semiconductor device according to a fifth embodiment. FIG. 10 is a schematic diagram of a semiconductor manufacturing apparatus according to a sixth embodiment. FIG. 10 is a schematic diagram of a main part of a semiconductor manufacturing apparatus according to a sixth embodiment. FIG. 13 is an explanatory diagram of the operation of the semiconductor manufacturing apparatus according to the sixth embodiment. FIG. 1 is a schematic diagram of a main part of a semiconductor manufacturing apparatus according to a comparative example. FIG. 13 is a schematic diagram of a main part of a semiconductor manufacturing apparatus according to a seventh embodiment. FIG. 13 is a schematic diagram of a main part of a semiconductor manufacturing apparatus according to a modified example of the seventh embodiment. FIG. 13 is a schematic diagram of a main part of a semiconductor manufacturing apparatus according to an eighth embodiment. FIG. 13 is a schematic diagram of a main part of a semiconductor manufacturing apparatus according to a ninth embodiment.

Embodiments of the present invention will be described below with reference to the drawings. In the following description, identical or similar components will be designated by the same reference numerals, and descriptions of components that have already been described may be omitted as appropriate.

In addition, the terms "upper" and "lower" may be used in this specification for convenience. "Upper" and "lower" are terms that indicate relative positional relationships within a drawing, for example. The terms "upper" and "lower" do not necessarily define a positional relationship with respect to gravity.

Qualitative and quantitative analysis of the chemical composition of the components constituting the semiconductor device described herein can be performed using, for example, secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX). Furthermore, measurements of the thickness of the components constituting the semiconductor device, the distance between components, and so forth can be performed using, for example, a transmission electron microscope (TEM) or a scanning electron microscope (SEM).

The manufacturing method of the semiconductor device according to the embodiment will be described below with reference to the drawings.

(First embodiment)
A method for manufacturing a semiconductor device according to a first embodiment includes the steps of: placing a substrate having a workpiece layer on a holder provided in a chamber; supplying a first gas between the holder and the substrate, the first gas being in contact with the substrate; controlling the pressure of the first gas to a first pressure; performing a first etching process to etch the workpiece layer using a reactive ion etching method after controlling the pressure of the first gas to the first pressure; controlling the pressure of the first gas to a second pressure lower than the first pressure after controlling the pressure of the first gas to the second pressure; performing a first reaction product removal process to remove reaction products on the workpiece layer; controlling the pressure of the first gas to a third pressure higher than the second pressure after controlling the pressure of the first gas to the third pressure; and performing a second etching process to etch the workpiece layer using a reactive ion etching method after controlling the pressure of the first gas to the third pressure.

In addition, the semiconductor device manufacturing method of the first embodiment includes placing a substrate having a workpiece layer on a holder provided in a chamber, supplying a first gas in contact with the substrate between the holder and the substrate, controlling the pressure of the first gas to a first pressure, and performing a first etching process to etch the workpiece layer using a reactive ion etching method in a first state where the substrate temperature is 60°C or less after controlling the pressure of the first gas to the first pressure, controlling the pressure of the first gas to a second pressure lower than the first pressure after controlling the pressure of the first gas to the second pressure, achieving a second state where the substrate temperature is 100°C or higher, controlling the pressure of the first gas to a third pressure higher than the second pressure after controlling the pressure of the first gas to the third pressure, and performing a second etching process to etch the workpiece layer using a reactive ion etching method in a third state where the substrate temperature is 60°C or less.

Figure 1 is a schematic cross-sectional view of a semiconductor device manufactured by the semiconductor device manufacturing method of the first embodiment. The semiconductor device manufactured by the semiconductor device manufacturing method of the first embodiment is a non-volatile memory 100 in which memory cells are arranged three-dimensionally. Figure 1 is a cross-sectional view of the memory cell array of non-volatile memory 100.

Nonvolatile memory 100 includes a silicon substrate 10, a channel layer 11, multiple interlayer insulating layers 12, a gate insulating layer 13, multiple word lines WL, and multiple bit lines BL. Nonvolatile memory 100 includes multiple memory cells MC arranged three-dimensionally. The area surrounded by the dotted line in Figure 1 corresponds to one memory cell MC.

The channel layer 11 extends in the normal direction to the surface of the silicon substrate 10. The channel layer 11 is electrically connected to the silicon substrate 10. The channel layer 11 functions as a channel region of the transistor of the memory cell MC. The channel layer 11 is a semiconductor. The channel layer 11 is, for example, polycrystalline silicon.

The word lines WL are stacked in the normal direction to the surface of the silicon substrate 10. The word lines WL function as gate electrodes of the transistors in the memory cells MC. The word lines WL are, for example, plate-shaped conductors. The word lines WL are, for example, made of tungsten (W). The channel layer 11 passes through multiple word lines WL.

Interlayer insulating layer 12 is provided between word lines WL. Interlayer insulating layer 12 electrically separates word lines WL from each other.

The bit line BL extends in a direction parallel to the surface of the silicon substrate 10. The bit line BL is electrically connected to the channel layer 11.

The gate insulating layer 13 is provided between the channel layer 11 and the word line WL. The gate insulating layer 13 includes, for example, a tunnel insulating film, a charge storage film, and a block insulating film, all of which are not shown. The tunnel insulating film is, for example, a silicon oxide film. The charge storage film is, for example, a silicon nitride film. The block insulating film is, for example, an aluminum oxide film.

Memory cells MC store data using charges stored in the charge storage film of the gate insulating layer 13. The threshold voltage of the transistor in the memory cell MC changes depending on the amount of charge stored in the charge storage film. Data stored in the memory cell MC is read by monitoring the current flowing between the word line WL and bit line BL, which changes depending on the transistor's threshold voltage.

Figure 2 is a schematic diagram of an example of a reactive ion etching apparatus used in the semiconductor device manufacturing method of the first embodiment. The reactive ion etching apparatus (RIE apparatus) in Figure 2 is a dual-frequency capacitively coupled plasma apparatus (CCP apparatus).

The RIE apparatus includes, for example, a chamber 20, a holder 22, a first high-frequency power supply 24, a second high-frequency power supply 26, a process gas supply pipe 30, a shower plate 32, a process gas exhaust pipe 34, an exhaust device 36, a refrigerant unit 38, a refrigerant supply pipe 40, a refrigerant exhaust pipe 42, a heat transfer gas supply unit 44, a first heat transfer gas supply pipe 46, a heat transfer gas exhaust pipe 48, a first main valve 50, a second main valve 52, and a control circuit 54.

The holder 22 is provided in the chamber 20. The holder 22 holds, for example, a semiconductor wafer W.

The holder 22 has a support portion 22a, an electrostatic chuck 22b, and an outer ring 22c.

The support portion 22a functions as a lower electrode. High-frequency power is applied to the support portion 22a. The support portion 22a is made of, for example, metal.

A refrigerant flow path 22ax is provided inside the support portion 22a. The refrigerant flow path 22ax is an air gap. A refrigerant for cooling the support portion 22a is supplied to the refrigerant flow path 22ax. The refrigerant is, for example, a fluorine-based inert liquid.

The electrostatic chuck 22b is provided on the support portion 22a. The electrostatic chuck 22b has the function of attracting and fixing the semiconductor wafer W. The electrostatic chuck 22b is formed, for example, from a dielectric material with an electrode inside. The dielectric material is, for example, ceramics.

A thermal conduction gas region 76 is formed on the upper surface of the electrostatic chuck 22b. A thermal conduction gas for cooling the semiconductor wafer W is supplied between the electrostatic chuck 22b and the semiconductor wafer W. By fixing the semiconductor wafer W to the electrostatic chuck 22b, the thermal conduction gas region 76 becomes an enclosed space.

Thermal conduction gases include, for example, helium (He), hydrogen (H), nitrogen (N), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe). Thermal conduction gases include, for example, helium gas, hydrogen gas, nitrogen gas, neon gas, argon gas, krypton gas, or xenon gas.

The outer ring 22c is provided on the support portion 22a. The outer ring 22c is provided around the electrostatic chuck 22b. The outer ring 22c has the function of supporting the outer periphery of the semiconductor wafer W. The upper surface of the outer ring 22c is made of, for example, silicon.

The first high-frequency power supply 24 has the function of applying first high-frequency power to the interior of the chamber 20. The first high-frequency power supply 24 applies high-frequency power between the support portion 22a of the holder 22 and the shower plate 32. Plasma is generated in the chamber 20 by the first high-frequency power applied to the chamber 20 using the first high-frequency power supply 24.

The first high-frequency power applied by the first high-frequency power supply 24 is, for example, 50 W or more and 20,000 W or less. The first frequency applied by the first high-frequency power supply 24 is, for example, 20 MHz or more and 200 MHz or less.

The second high-frequency power supply 26 has the function of applying a second high-frequency power to the interior of the chamber 20. The second high-frequency power supply 26 applies the second high-frequency power to the support portion 22a of the holder 22. By applying the second high-frequency power to the holder 22, the energy of the ions colliding with the semiconductor wafer W is controlled.

The second high-frequency power applied to the holder 22 is, for example, 50 W or more and 20,000 W or less. The second frequency applied to the holder 22 is lower than the first frequency applied to the chamber 20 by the first high-frequency power supply 24. The second frequency applied to the holder 22 is, for example, 0.1 MHz or more and 20 MHz or less.

The process gas supply pipe 30 is installed at the top of the chamber 20. Etching gas is supplied from the process gas supply pipe 30 to the shower plate 32.

The shower plate 32 is provided in the chamber 20. The shower plate 32 is provided above the holder 22.

Etching gas is supplied to the shower plate 32 from the process gas supply pipe 30. The etching gas is supplied into the chamber 20 from multiple gas supply ports provided in the shower plate 32.

The shower plate 32 also functions as the upper electrode for the first high-frequency power.

The process gas exhaust pipe 34 is installed at the bottom of the chamber 20. Etching gas and reaction products not consumed in the etching reaction are exhausted from the process gas exhaust pipe 34 to the outside of the chamber 20.

The exhaust device 36 is connected to the process gas exhaust pipe 34 and the heat transfer gas exhaust pipe 48. The exhaust device 36 is, for example, a vacuum pump.

The refrigerant unit 38 is connected to the refrigerant supply pipe 40. The refrigerant supply pipe 40 is connected to the refrigerant flow path 22ax. The refrigerant flow path 22ax is connected to the refrigerant discharge pipe 42. The refrigerant unit 38 circulates the refrigerant through the refrigerant supply pipe 40, the refrigerant flow path 22ax, and the refrigerant discharge pipe 42.

The heat transfer gas supply unit 44 is connected to a first heat transfer gas supply pipe 46. The first heat transfer gas supply pipe 46 is connected to the heat transfer gas region 76. A first main valve 50 is provided on the first heat transfer gas supply pipe 46. The heat transfer gas supply unit 44 supplies heat transfer gas to the heat transfer gas region 76.

The first main valve 50 is, for example, a flow control valve. By controlling the first main valve 50, it is possible to control the pressure of the thermal conduction gas in the thermal conduction gas region 76. The first main valve 50 can also be used to cut off the supply of thermal conduction gas to the thermal conduction gas region 76.

The thermal conduction gas region 76 is connected to the thermal conduction gas exhaust pipe 48. The thermal conduction gas exhaust pipe 48 is connected to the exhaust device 36. The thermal conduction gas in the thermal conduction gas region 76 is exhausted using the thermal conduction gas exhaust pipe 48.

A second main valve 52 is provided on the thermal conduction gas exhaust pipe 48. The second main valve 52 is used to control the exhaust of the thermal conduction gas.

The control circuit 54 has the function of controlling the operation of the first high-frequency power supply 24, the second high-frequency power supply 26, the exhaust device 36, the refrigerant unit 38, the heat transfer gas supply unit 44, the first main valve 50, and the second main valve 52.

The semiconductor wafer W placed on the holder 22 is anisotropically etched using plasma generated between the shower plate 32 and the holder 22 in the chamber 20.

Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

Figure 3 is an explanatory diagram of the method for manufacturing the semiconductor device of the first embodiment. Figures 4, 5, 6, and 7 are schematic diagrams showing the method for manufacturing the semiconductor device of the first embodiment. Figures 4, 5, 6, and 7 correspond to the portion including one channel layer 11 in Figure 1.

First, a stack 60 is formed on a silicon substrate 10 (Figure 4(a)). The silicon substrate 10 is a semiconductor wafer. The stack 60 is an insulating layer. The silicon substrate 10 is an example of a substrate. The stack 60 is an example of a layer to be processed. The silicon substrate 10 is an example of the semiconductor wafer W in Figure 2.

The stacked body 60 includes a structure in which silicon oxide films 60a and silicon nitride films 60b are alternately stacked. The silicon oxide films 60a and silicon nitride films 60b are formed by, for example, a chemical vapor deposition (CVD) method.

A portion of the silicon oxide film 60a will eventually become the interlayer insulating layer 12.

Next, a carbon layer 62 having a hole pattern 62a is formed on the laminate 60 (FIG. 4(b)). The carbon layer 62 is a mask layer. The carbon layer 62 is formed by, for example, sputtering. The hole pattern 62a is formed by, for example, lithography and RIE.

The mask layer may be, for example, a resist layer, an insulating layer, or a metal layer.

Next, the silicon substrate 10 is loaded into the chamber 20 of the RIE device. The silicon substrate 10 is placed on a holder 22 provided in the chamber 20. The silicon substrate 10 is an example of a substrate.

Memory holes MH are formed in the chamber 20 of the RIE apparatus using reactive ion etching with the carbon layer 62 as a mask (Figures 4(c) to 5(d)). The etching of the memory holes MH is performed while periodically changing the pressure of the thermally conductive gas that cools the silicon substrate 10. The memory holes MH are an example of recesses.

Figure 3 shows the relationship between the thermal conduction gas pressure, total high frequency power, wafer temperature, and etching time when forming the memory hole MH.

At time t1, thermal conduction gas is supplied to the thermal conduction gas region 76 between the holder 22 and the silicon substrate 10. The thermal conduction gas is, for example, helium gas. The helium gas contacts the back surface of the silicon substrate 10. The helium gas is an example of a first gas.

At time t1, the pressure of the helium gas is controlled to a first pressure P1. The pressure of the helium gas is controlled, for example, by flow control using the first main valve 50. The pressure of the helium gas is controlled to the first pressure P1 by adjusting the opening of the first main valve 50.

The first pressure P1 is, for example, 133 Pa (1 Torr) or more and 13,332 Pa (100 Torr) or less.

Furthermore, at time t1, high-frequency power is applied inside the chamber 20. For example, a first high-frequency power is applied between the support portion 22a of the holder 22 and the shower plate 32 using the first high-frequency power supply 24. For example, a second high-frequency power is applied to the support portion 22a of the holder 22 using the second high-frequency power supply 26. The sum of the first high-frequency power and the second high-frequency power is referred to as the total high-frequency power.

Also, at time t1, etching gas is supplied into the chamber 20. The etching gas is supplied from the process gas supply pipe 30 through the shower plate 32 into the chamber 20.

The etching gas includes, for example, carbon (C) and fluorine (F). The etching gas includes, for example, CxHyFz (x is an integer of 1 or more, y is an integer of 0 or more, and z is an integer of 1 _or more ₎ . The etching gas includes, for example, _C4F6 , _C4F8 , _{and CH2F2} .

The etching gas may include, for example, oxygen gas. The etching gas may include, for example, hydrogen bromide gas (HBr).

Furthermore, at time t1, a coolant is supplied to the coolant flow path 22ax. The coolant is, for example, a fluorine-based inert liquid. By supplying the coolant to the coolant flow path 22ax, the temperature of the support portion 22a of the holder 22 and the electrostatic chuck 22b decreases. The temperature of the support portion 22a of the holder 22 and the electrostatic chuck 22b is, for example, -196°C or higher and 60°C or lower.

After the helium gas pressure is controlled to the first pressure P1, a first etching process is performed using reactive ion etching to etch the stack 60 (Figure 4(c)). Between time t1 and time t2, the first etching process to etch the stack 60 is performed. During the first etching process, the memory hole MH does not penetrate the stack 60.

During the first etching process, the temperature of the silicon substrate 10 is, for example, -150°C or higher and 60°C or lower. During the first etching process, a first state is achieved in which the temperature of the silicon substrate 10 is, for example, -150°C or higher and 60°C or lower.

During the first etching process, reaction products 63 are formed on the stack 60. During the first etching process, reaction products 63 are formed on the bottom and side surfaces of the memory hole MH. The reaction products 63 formed during the first etching process are an example of first reaction products.

The reaction product 63 includes, for example, silicon (Si), nitrogen (N), and fluorine ( _F ). The reaction product 63 includes, for example, ammonium silicofluoride. The reaction product 63 includes, for example, ( _NH4 ) _2SiF6 .

After the first etching process, at time t2, the helium gas pressure is controlled to a second pressure P2. After the first etching process, at time t2, the helium gas pressure is changed from the first pressure P1 to a second pressure P2. The second pressure P2 is lower than the first pressure P1.

The pressure of the helium gas is controlled, for example, by flow rate control using the first main valve 50. For example, closing the first main valve 50 blocks the flow of helium gas into the thermal conduction gas region 76. For example, closing the first main valve 50 causes the second pressure P2 to approach vacuum.

The second pressure P2 is, for example, 0 Pa or more and 13.3 Pa (0.1 Torr) or less. The second pressure P2 is, for example, 1/100 or less of the first pressure P1.

After controlling the helium gas pressure to the second pressure P2, a first reaction product removal is performed to remove the reaction product 63 on the stack 60 (FIG. 4(d)). Between time t2 and time t3, the reaction product 63 on the stack 60 is removed. The first reaction product removal removes the reaction product 63 on the bottom and side surfaces of the memory hole MH.

When the first reaction product is removed, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. When the first reaction product is removed, a second state is achieved in which the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower.

At time t2, after the helium gas pressure is controlled from the first pressure P1 to the second pressure P2, the temperature of the silicon substrate 10 rises, and a second state is achieved in which the temperature of the silicon substrate 10 is 100°C or higher. The reduction in the helium gas pressure suppresses the propagation of heat within the helium gas. Heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas is suppressed, and the temperature of the silicon substrate 10 rises.

For example, the higher the temperature, the more accelerated the decomposition reaction of the reaction product 63, facilitating its removal from the memory hole MH. For example, the decomposition reaction of the reaction product 63 is accelerated when the temperature of the silicon substrate 10 reaches 100°C or higher. In particular, when the reaction product 63 is ammonium fluorosilica, the decomposition reaction is accelerated when the temperature of the silicon substrate 10 reaches 100°C or higher.

Note that, for example, the supply of etching gas into chamber 20 continues during the removal of the first reaction product.

After the first reaction product is removed, at time t3, the pressure of the helium gas is controlled to a third pressure P3. After the first reaction product is removed, at time t3, the pressure of the helium gas is changed from the second pressure P2 to a third pressure P3. After the second state is achieved, the pressure of the helium gas is controlled to the third pressure P3.

The third pressure P3 is higher than the second pressure P2. The pressure of the helium gas is controlled, for example, by flow rate control using the first main valve 50. For example, opening the first main valve 50 starts the flow of helium gas into the thermal conduction gas region 76. The pressure of the helium gas is controlled to the third pressure P3 by adjusting the opening of the first main valve 50.

The third pressure P3 is, for example, equal to or greater than 133 Pa (1 Torr) and equal to or less than 13,332 Pa (100 Torr). The third pressure P3 is, for example, equal to the first pressure P1.

After the helium gas pressure is controlled to the third pressure P3, a second etching process is performed to etch the stack 60 using reactive ion etching (Figure 5(a)). During the second etching process, the supply of etching gas into the chamber 20 continues.

Between time t3 and time t4, a second etching process is performed to etch the stack 60. During the second etching process, the bottom surface of the memory hole MH is etched. During the second etching process, the memory hole MH becomes deeper. During the second etching process, the memory hole MH does not penetrate the stack 60.

Increasing the pressure of the helium gas from the second pressure P2 to the third pressure P3 promotes the transfer of heat within the helium gas. This promotes heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas, lowering the temperature of the silicon substrate 10.

During the second etching process, the temperature of the silicon substrate 10 is, for example, -150°C or higher and 60°C or lower. During the second etching process, a third state is achieved, in which the temperature of the silicon substrate 10 is, for example, -150°C or higher and 60°C or lower.

During the second etching process, reaction products 63 are formed on the stack 60. During the second etching process, reaction products 63 are formed on the bottom and side surfaces of the memory hole MH. The reaction products 63 formed during the second etching process are an example of second reaction products.

After the second etching process, at time t4, the helium gas pressure is controlled to fourth pressure P4. After the second etching process, at time t4, the helium gas pressure is changed from third pressure P3 to fourth pressure P4. Fourth pressure P4 is lower than third pressure P3. Fourth pressure P4 is equal to second pressure P2, for example.

The fourth pressure P4 is, for example, 0 Pa or more and 13.3 Pa (0.1 Torr) or less. The fourth pressure P4 is, for example, 1/100 or less of the third pressure P3.

After controlling the helium gas pressure to fourth pressure P4, a second reaction product removal is performed to remove the reaction product 63 on the stack 60 (FIG. 5(b)). Between time t4 and time t5, the reaction product 63 on the stack 60 is removed. The second reaction product removal removes the reaction product 63 on the bottom and side surfaces of the memory hole MH.

When the second reaction product is removed, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. When the second reaction product is removed, a fourth state is realized in which the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower.

At time t4, the pressure of the helium gas is changed from the third pressure P3 to the fourth pressure P4, and the temperature of the silicon substrate 10 rises, achieving a fourth state in which the temperature of the silicon substrate 10 is between 100°C and 300°C.

Note that, for example, the supply of etching gas into chamber 20 continues during the removal of the second reaction product.

After the second reaction product is removed, at time t5, the pressure of the helium gas is controlled to fifth pressure P5. After the second reaction product is removed, at time t5, the pressure of the helium gas is changed from fourth pressure P4 to fifth pressure P5. After the fourth state is achieved, the pressure of the helium gas is controlled to fifth pressure P5.

The fifth pressure P5 is higher than the fourth pressure P4. The fifth pressure P5 is, for example, equal to or greater than 133 Pa (1 Torr) and equal to or less than 13,332 Pa (100 Torr). The fifth pressure P5 is, for example, equal to the first pressure P1 and the third pressure P3.

After the helium gas pressure is controlled to a fifth pressure P5, a third etching process is performed to etch the stack 60 using reactive ion etching (Figure 5(c)). During the fifth etching process, the supply of etching gas into the chamber 20 continues.

Between time t5 and time t6, a third etching process is performed to etch the stack 60. During the third etching process, the bottom surface of the memory hole MH is etched. During the third etching process, the memory hole MH becomes deeper. During the third etching process, the memory hole MH penetrates the stack 60 and reaches the silicon substrate 10. The aspect ratio of the memory hole MH that penetrates the stack 60 is, for example, 30 or more.

As the pressure of the helium gas increases from the fourth pressure P4 to the fifth pressure P5, the temperature of the silicon substrate 10 decreases.

During the third etching process, the temperature of the silicon substrate 10 is, for example, -150°C or higher and 60°C or lower. During the third etching process, a fifth state is achieved, in which the temperature of the silicon substrate 10 is, for example, -150°C or higher and 60°C or lower.

During the third etching process, reaction products 63 are formed on the stack 60. During the third etching process, reaction products 63 are formed on the bottom and side surfaces of the memory hole MH.

After the third etching process, at time t6, the pressure of the helium gas is controlled to a sixth pressure P6. After the third etching process, at time t6, the pressure of the helium gas is changed from the fifth pressure P5 to the sixth pressure P6. The sixth pressure P6 is lower than the fifth pressure P5. The sixth pressure P6 is equal to, for example, the second pressure P2 and the fourth pressure P4.

The sixth pressure P6 is, for example, 0 Pa or more and 13.3 Pa (0.1 Torr) or less. The sixth pressure P6 is, for example, 1/100 or less of the fifth pressure P5.

After controlling the helium gas pressure to a sixth pressure P6, a third reaction product removal is performed to remove the reaction product 63 on the stack 60 (FIG. 5(d)). After time t6, the reaction product 63 on the stack 60 is removed. The third reaction product removal removes the reaction product 63 on the bottom and side surfaces of the memory hole MH.

When the third reaction product is removed, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. When the third reaction product is removed, a sixth state is realized in which the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower.

At time t6, the pressure of the helium gas is changed from fifth pressure P5 to sixth pressure P6, and the temperature of the silicon substrate 10 rises, achieving a sixth state in which the temperature of the silicon substrate 10 is 100°C or higher.

Note that, for example, the supply of etching gas into chamber 20 continues during the removal of the third reaction product.

After the third reaction product is removed, at time t7, the application of high-frequency power to the interior of chamber 20 is stopped. Also at time t7, the supply of etching gas into chamber 20 is cut off.

At time t7, etching of memory hole MH is completed.

After removing the third reaction product, the pressure of the helium gas may be increased to a pressure higher than the sixth pressure P6, and the etching of the memory hole MH may be completed with the temperature of the silicon substrate 10 kept low.

As shown in FIG. 3, the time during which the helium gas pressure is controlled to the first pressure P1 when etching the memory hole MH is td1. The time during which the helium gas pressure is controlled to the second pressure P2 when etching the memory hole MH is td2. The time during which the helium gas pressure is controlled to the third pressure P3 when etching the memory hole MH is td3. The time during which the helium gas pressure is controlled to the fourth pressure P4 when etching the memory hole MH is td4. The time during which the helium gas pressure is controlled to the fifth pressure P5 when etching the memory hole MH is td5.

For example, time td1, time td3, and time td5 are equal. Also, for example, time td2 and time td4 are equal.

Also, for example, time td1 and time td2 are equal. Also, for example, time td3 and time td4 are equal.

Also, for example, time td2 is shorter than time td1. Also, for example, time td4 is shorter than time td3.

Also, for example, time td2 is longer than time td1. Also, for example, time td4 is longer than time td3.

When the time during which the pressure of the helium gas is controlled to the second pressure P2 is td2 (sec), the temperature of the holder 22 during the first etching process is T (°C), the ratio of the surface area of the silicon substrate 10 to the sum of the area of the silicon substrate 10 and the area of the inner wall of the chamber 20 is k, the high-frequency power applied to the inside of the chamber 20 while the pressure of the helium gas is controlled to the second pressure P2 is Pw (W), the mass of the silicon substrate 10 is m (kg), and the specific heat capacity of the silicon substrate 10 is c (J/(kg·°C)), for example, the following inequality (1) is established.
td2≧(100-T)/{(k×Pw)/(m×c)}...(1)

The temperature T of the holder 22 is the set temperature of the electrostatic chuck 22b. During etching of the memory hole MH, the set temperature of the electrostatic chuck 22b is maintained at a constant temperature. The temperature of the electrostatic chuck 22b is measured, for example, by a thermometer not shown in FIG. 2.

The ratio k is expressed by the following formula.
k = surface area of silicon substrate / (surface area of silicon substrate + inner wall area of chamber)

Furthermore, the high-frequency power Pw is the total high-frequency power, which is the sum of the first high-frequency power and the second high-frequency power.

Similarly, for the time td4 during which the pressure of the helium gas is controlled to the fourth pressure P4, for example, the following inequality (2) holds.
td4≧(100-T)/{(k×Pw)/(m×c)}...(2)

After etching of the memory holes MH is completed, the silicon substrate 10 is removed from the chamber 20 of the RIE apparatus.

Next, the carbon layer 62 is removed (Figure 6(a)). The carbon layer 62 is removed, for example, by ashing using oxygen plasma.

Next, a laminated insulating layer 66 is formed in the memory hole MH (FIG. 6(b)). The laminated insulating layer 66 has a laminated structure of, for example, a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The laminated insulating layer 66 will eventually become the gate insulating layer 13.

Next, a polycrystalline silicon layer 68 is formed in the memory hole MH (Figure 6(c)). The polycrystalline silicon layer 68 will eventually become the channel layer 11.

Next, the silicon nitride film 60b is selectively removed (Figure 7(a)).

Next, a first tungsten layer 70 is formed in the area where the silicon nitride film 60b has been removed (Figure 7(b)). The first tungsten layer 70 will eventually become the word line WL.

Next, a second tungsten layer 69 is formed on the polycrystalline silicon layer 68 (Figure 7(c)). The second tungsten layer 69 will eventually become the bit line BL.

The non-volatile memory 100 shown in Figure 1 is manufactured using the above manufacturing method.

Next, we will explain the functions and effects of the semiconductor device manufacturing method of the first embodiment.

In a nonvolatile memory 100 in which memory cells are arranged three-dimensionally, in order to increase the memory capacity, for example, the diameter of the memory holes is reduced and the number of stacked word lines WL is increased. Reducing the diameter of the memory holes and increasing the number of stacked word lines WL requires the formation of memory holes with a high aspect ratio (depth of memory hole/diameter of memory hole).

When the aspect ratio of the memory hole becomes high, the problem arises that the memory hole cannot be processed into the desired shape. In other words, there is a problem that the processing accuracy of the memory hole shape decreases.

For example, the cross-sectional shape perpendicular to the depth direction of the memory hole may be distorted from the desired shape. Furthermore, for example, etching in the depth direction of the memory hole may not proceed vertically, resulting in a curved shape in the depth direction of the memory hole.

One of the causes of the aforementioned decrease in processing accuracy of the memory hole shape is thought to be the reaction products that form on the bottom and side surfaces of the memory hole during etching. In other words, the reaction products that form on the bottom and side surfaces of the memory hole inhibit etching, which is thought to decrease the processing accuracy of the memory hole shape.

For example, the etching rate of memory holes increases as the temperature of the substrate having the layer to be processed decreases. From the viewpoint of improving the throughput of etching memory holes, it is desirable to lower the temperature of the substrate having the layer to be processed. From the viewpoint of improving the throughput of etching memory holes, the temperature of the substrate having the layer to be processed is preferably 60°C or less, more preferably 20°C or less, and even more preferably 0°C or less.

On the other hand, if the decomposition temperature of the reaction products formed during etching of the memory hole is high, the reaction products will be less likely to decompose as the substrate temperature drops. Therefore, as the substrate temperature drops, etching may be further hindered by the reaction products. This further hindering of etching may further reduce the processing accuracy of the memory hole shape.

In the semiconductor device manufacturing method of the first embodiment, when forming the memory hole MH, the temperature of the silicon substrate 10 having the stacked body 60, which is the layer to be processed, is changed. In other words, a low temperature state of the silicon substrate 10 and a high temperature state of the silicon substrate 10 are alternately repeated.

The first, third, and fifth states correspond to low-temperature states. The second, fourth, and sixth states correspond to high-temperature states.

When the silicon substrate 10 is in a low temperature state, the etching rate of the memory hole MH increases, and etching of the stack 60 mainly progresses. On the other hand, when the silicon substrate 10 is in a high temperature state, the decomposition reaction of the reaction product 63 formed on the bottom and side surfaces of the memory hole MH is accelerated, and decomposition of the reaction product 63 mainly progresses.

When the silicon substrate 10 transitions from a high-temperature state to a low-temperature state, the reaction products 63 are removed, making it less likely that etching will be hindered by the reaction products 63. This improves the processing accuracy of the memory hole shape.

In the semiconductor device manufacturing method of the first embodiment, the memory holes MH are formed by alternately exposing the silicon substrate 10 to low temperatures and high temperatures, thereby improving the processing accuracy of the memory hole shape. Furthermore, the throughput of etching the memory holes MH is improved.

In the semiconductor device manufacturing method of the first embodiment, the silicon substrate 10 is transitioned between a high-temperature state and a low-temperature state by changing the pressure of the thermally conductive gas. The thermally conductive gas is, for example, helium gas.

By changing the pressure of the thermal conduction gas, the heat transfer between the silicon substrate 10 and the holder 22 is changed. Increasing the pressure of the thermal conduction gas accelerates the heat transfer, while decreasing the pressure of the thermal conduction gas suppresses the heat transfer. For example, by decreasing the pressure of the thermal conduction gas, the silicon substrate 10 can be transitioned from a low-temperature state to a high-temperature state. Also, by increasing the pressure of the thermal conduction gas, the silicon substrate 10 can be transitioned from a high-temperature state to a low-temperature state.

In the semiconductor device manufacturing method of the first embodiment, the temperature of the silicon substrate 10 is changed simply by changing the pressure of the thermally conductive gas used to cool the silicon substrate 10. Therefore, it is not necessary to add a new structure to the RIE apparatus to change the temperature of the silicon substrate 10. This makes it easy to improve the processing accuracy of the memory hole shape.

During etching of the laminate 60, the surface of the silicon substrate 10 is exposed to high-energy plasma formed by the application of high-frequency power. The temperature of the silicon substrate 10 rises due to heat input from the high-energy plasma. Meanwhile, the temperature of the silicon substrate 10 decreases due to heat output toward the holder 22, which is cooled by the supply of a coolant. The temperature of the silicon substrate 10 is determined by the balance between the heat input from the plasma and the heat output toward the holder 22.

When the time during which the pressure of the helium gas is controlled to a low pressure is td (sec), the temperature of the holder 22 before the helium gas pressure starts to be controlled to a low pressure is T (°C), the ratio of the surface area of the silicon substrate 10 to the sum of the surface area of the silicon substrate 10 and the inner wall area of the chamber 20 is k, the high-frequency power applied to the inside of the chamber 20 while the pressure of the helium gas is controlled to a low pressure is Pw (W), the mass of the silicon substrate 10 is m (kg), and the specific heat capacity of the silicon substrate 10 is c (J/(kg°C)), it is preferable that the following inequality (3) is established.
td≧(100-T)/{(k×Pw)/(m×c)}...(3)

The temperature T of the holder 22 is the set temperature of the electrostatic chuck 22b. The set temperature of the electrostatic chuck 22b is maintained at a constant temperature during etching of the memory hole MH. The temperature of the electrostatic chuck 22b is measured, for example, by a thermometer not shown in FIG. 2. The temperature T of the holder 22 may also be the temperature of the electrostatic chuck 22b measured by the thermometer when control is switched from high pressure to low pressure, for example.

The ratio k is expressed by the following formula.
k = surface area of silicon substrate / (surface area of silicon substrate + inner wall area of chamber)

Furthermore, the high-frequency power Pw is the total high-frequency power, which is the sum of the first high-frequency power and the second high-frequency power.

When the time td satisfies the above inequality (3), it becomes possible to raise the temperature of the silicon substrate 10 to 100°C or higher during the time td. Raising the temperature of the silicon substrate 10 to 100°C or higher promotes the decomposition of the reaction product 63.

Therefore, it is preferable that the following inequality (1) be satisfied for the time td2 during which the pressure of the helium gas is controlled to the second pressure P2.
td2≧(100-T)/{(k×Pw)/(m×c)}...(1)

Similarly, for the time td4 during which the pressure of the helium gas is controlled to the fourth pressure P4, it is preferable that the following inequality (2) be established.
td4≧(100-T)/{(k×Pw)/(m×c)}...(2)

From the viewpoint of promoting the decomposition reaction of the reaction product 63 on the silicon substrate 10, it is preferable that the temperature of the silicon substrate 10 is high. Therefore, it is preferable that the time during which the helium gas pressure is controlled to a low pressure is long. Therefore, the time td2 during which the helium gas pressure is controlled to the second pressure P2 is preferably longer than 10 seconds, and more preferably longer than 15 seconds. Furthermore, the time td4 during which the helium gas pressure is controlled to the fourth pressure P4 is preferably longer than 10 seconds, and more preferably longer than 15 seconds.

From the perspective of improving the throughput of memory hole etching, it is preferable that the time during the high-temperature state, during which reaction product generation and removal primarily progress, is shorter than the time during the low-temperature state, during which etching primarily progresses. Therefore, it is preferable that the time during which the helium gas pressure is controlled to low pressure is shorter than the time during which the helium gas pressure is controlled to high pressure. Therefore, it is preferable that time td2 is shorter than times td1, td3, and td5. It is preferable that time td4 is shorter than times td1, td3, and td5. It is preferable that time td6 is shorter than times td1, td3, and td5.

From the perspective of increasing the rate of temperature change of the silicon substrate 10, it is preferable that the thermally conductive gas be helium gas or hydrogen gas, which have high thermal conductivity.

(Modification)
The modified example of the method for manufacturing a semiconductor device of the first embodiment differs from the method for manufacturing a semiconductor device of the first embodiment in that the temperature of the substrate is measured and the pressure of the first gas is controlled to a third pressure based on the measured temperature of the substrate.

In the modified semiconductor device manufacturing method, the RIE apparatus used to etch the memory holes MH is equipped with a thermometer (not shown in FIG. 2) that measures the temperature of the silicon substrate 10. The thermometer measures the temperature of the silicon substrate 10 directly or indirectly.

The thermometer is, for example, a thermometer using a phosphor that directly measures the temperature of the silicon substrate 10, or a thermocouple. The thermometer is, for example, a thermometer using a phosphor that directly measures the temperature of the outer ring 22c, or a thermocouple. The temperature of the silicon substrate 10 can be indirectly derived from the temperature of the outer ring 22c.

In the modified semiconductor device manufacturing method, the helium gas pressure is controlled based on the substrate temperature measured by a thermometer. Control of the helium gas pressure based on the temperature of the silicon substrate 10 is performed, for example, using a control circuit 54.

For example, the temperature of the silicon substrate 10 is measured while the helium gas pressure is controlled to the second pressure P2. For example, when the temperature of the silicon substrate 10 reaches a predetermined temperature, the helium gas pressure is switched from the second pressure P2 to a third pressure P3 that is higher than the second pressure P2. The predetermined temperature is, for example, 120°C. The helium gas pressure is controlled to the third pressure P3 based on the temperature of the silicon substrate 10.

By switching the helium gas pressure from the second pressure P2 to the third pressure P3 based on the temperature of the silicon substrate 10, it is possible to reliably prevent the temperature of the silicon substrate 10 from becoming too high, for example.

Furthermore, for example, the temperature of the silicon substrate 10 is measured while the helium gas pressure is controlled to the third pressure P3. For example, after the temperature of the silicon substrate 10 has dropped to a predetermined temperature, and a predetermined time has elapsed, the helium gas pressure is switched from the third pressure P3 to a fourth pressure P4 that is lower than the third pressure P3. The predetermined temperature is, for example, 20°C. The predetermined time is, for example, 10 seconds. The helium gas pressure is controlled to the fourth pressure P4 based on the temperature of the silicon substrate 10.

By switching the helium gas pressure from the third pressure P3 to the fourth pressure P4 based on the temperature of the silicon substrate 10, it is possible to precisely control, for example, the amount of etching of the stack 60.

As described above, the semiconductor device manufacturing method of the first embodiment and its variations enable highly accurate processing when processing a processing layer by dry etching.

Second Embodiment
The semiconductor device manufacturing method of the second embodiment differs from the manufacturing method of the first embodiment in that the control of the change in the pressure of the first gas is synchronized with the control of the change in the high-frequency power applied inside the chamber. Furthermore, in the semiconductor device manufacturing method of the second embodiment, the high-frequency power applied inside the chamber during the first reaction product removal is set higher than the high-frequency power applied inside the chamber during the first etching process. Hereinafter, some of the content overlapping with the first embodiment may be omitted.

Figure 8 is an explanatory diagram of the manufacturing method of the semiconductor device of the second embodiment. Figure 8 shows the relationship between the thermal conduction gas pressure, total high-frequency power, wafer temperature, and etching time when forming the memory hole MH.

At time t1, thermal conduction gas is supplied to the thermal conduction gas region 76 between the holder 22 and the silicon substrate 10. The thermal conduction gas is, for example, helium gas.

At time t1, the pressure of the helium gas is controlled to a first pressure P1. At time t1, a first power Pw1 is applied to the interior of the chamber 20.

Also, at time t1, etching gas is supplied into the chamber 20. Also, at time t1, coolant is supplied to the coolant flow path 22ax.

After the pressure of the helium gas is controlled to the first pressure P1, a first etching process is performed using reactive ion etching to etch the stack 60. During the first etching process, the temperature of the silicon substrate 10 is, for example, -150°C or higher and 60°C or lower. During the first etching process, a first state is achieved in which the temperature of the silicon substrate 10 is, for example, -150°C or higher and 60°C or lower. During the first etching process, a reaction product 63 is formed on the stack 60.

After the first etching process, at time t2, the helium gas pressure is controlled to a second pressure P2. After the first etching process, at time t2, the helium gas pressure is changed from the first pressure P1 to a second pressure P2. The second pressure P2 is lower than the first pressure P1.

Furthermore, at time t2, a second power Pw2 is applied to the interior of the chamber 20. At time t2, the high-frequency power applied to the interior of the chamber 20 is changed from the first power Pw1 to the second power Pw2. The second power Pw2 is higher than the first power Pw1.

The helium gas pressure is controlled to a second pressure P2, and after the second power Pw2 is applied, a first reaction product removal is performed to remove the reaction product 63 on the stack 60.

When the first reaction product is removed, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. When the first reaction product is removed, a second state is achieved in which the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower.

After the first reaction product is removed, at time t3, the pressure of the helium gas is controlled to a third pressure P3. After the first reaction product is removed, at time t3, the pressure of the helium gas is changed from the second pressure P2 to a third pressure P3. The third pressure P3 is higher than the second pressure P2.

Furthermore, at time t3, a third power Pw3 is applied to the interior of the chamber 20. At time t3, the high-frequency power applied to the interior of the chamber 20 is changed from the second power Pw2 to the third power Pw3. The third power Pw3 is lower than the second power Pw2.

The helium gas pressure is controlled to a third pressure P3, and after a third power Pw3 is applied, a second etching process is performed to etch the stack 60 using reactive ion etching.

Between time t3 and time t4, a second etching process is performed to etch the stack 60.

By increasing the pressure of the helium gas from the second pressure P2 to the third pressure P3, the temperature of the silicon substrate 10 decreases. During the second etching process, a third state is achieved in which the temperature of the silicon substrate 10 is between -150°C and 60°C. During the second etching process, a reaction product 63 is formed on the stack 60.

After the second etching process, at time t4, the helium gas pressure is controlled to fourth pressure P4. After the second etching process, at time t4, the helium gas pressure is changed from third pressure P3 to fourth pressure P4. The fourth pressure P4 is lower than the third pressure P3.

Furthermore, at time t4, a fourth power Pw4 is applied to the interior of the chamber 20. At time t4, the high-frequency power applied to the interior of the chamber 20 is changed from the third power Pw3 to the fourth power Pw4. The fourth power Pw4 is higher than the third power Pw3.

The helium gas pressure is controlled to a fourth pressure P4, and after a fourth power Pw4 is applied, a second reaction product removal is performed to remove the reaction product 63 on the stack 60.

When the second reaction product is removed, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. When the second reaction product is removed, a fourth state is realized in which the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower.

After the second reaction product is removed, at time t5, the pressure of the helium gas is controlled to a fifth pressure P5. After the first reaction product is removed, at time t5, the pressure of the helium gas is changed from the fourth pressure P4 to a fifth pressure P5. The fifth pressure P5 is higher than the fourth pressure P4.

Furthermore, at time t5, a fifth power Pw5 is applied to the interior of the chamber 20. At time t5, the high-frequency power applied to the interior of the chamber 20 is changed from the fourth power Pw4 to the fifth power Pw5. The fifth power Pw5 is lower than the fourth power Pw4.

The helium gas pressure is controlled to a fifth pressure P5, and a fifth power Pw5 is applied. After that, a third etching process is performed to etch the stack 60 using reactive ion etching.

Between time t5 and time t6, a third etching process is performed to etch the stack 60.

By increasing the pressure of the helium gas from the fourth pressure P4 to the fifth pressure P5, the temperature of the silicon substrate 10 decreases. During the third etching process, for example, a fifth state is achieved in which the temperature of the silicon substrate 10 is between -150°C and 60°C. During the third etching process, a reaction product 63 is formed on the stack 60.

After the third etching process, at time t6, the helium gas pressure is controlled to sixth pressure P6. After the third etching process, at time t6, the helium gas pressure is changed from fifth pressure P5 to sixth pressure P6. Sixth pressure P6 is lower than fifth pressure P5.

Furthermore, at time t6, a sixth power Pw6 is applied to the interior of the chamber 20. At time t6, the high-frequency power applied to the interior of the chamber 20 is changed from the fifth power Pw5 to the sixth power Pw6. The sixth power Pw6 is higher than the fifth power Pw5.

The helium gas pressure is controlled to a sixth pressure P6, and after a sixth power Pw6 is applied, a third reaction product removal is performed to remove the reaction product 63 on the stack 60.

When the third reaction product is removed, the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower. When the third reaction product is removed, a sixth state is realized in which the temperature of the silicon substrate 10 is, for example, 100°C or higher and 300°C or lower.

After the third reaction product is removed, at time t7, the application of high-frequency power to the interior of chamber 20 is stopped. Also at time t7, the supply of etching gas into chamber 20 is cut off.

At time t7, etching of memory hole MH is completed.

Next, we will explain the operation and effects of the semiconductor device manufacturing method of the second embodiment.

In the semiconductor device manufacturing method of the second embodiment, control of the change in the pressure of the conductive gas is synchronized with control of the change in the high-frequency power applied inside the chamber. The high-frequency power is increased in synchronization with a decrease in the pressure of the conductive gas. The high-frequency power is also decreased in synchronization with an increase in the pressure of the conductive gas.

Specifically, for example, as described above, after the first etching process, at time t2, the helium gas pressure is reduced from the first pressure P1 to the second pressure P2, and simultaneously the high-frequency power applied to the interior of the chamber 20 is increased from the first power Pw1 to the second power Pw2. Furthermore, at time t3, the helium gas pressure is increased from the second pressure P2 to the third pressure P3, and simultaneously the high-frequency power applied to the interior of the chamber 20 is reduced from the second power Pw2 to the third power Pw3.

In removing the first reaction product after the first etching process, a high temperature of the silicon substrate 10 is desirable to improve the removal efficiency of the reaction product 63. Furthermore, from the perspective of improving the throughput of etching the memory holes MH, it is desirable for the temperature of the silicon substrate 10 to increase quickly.

Furthermore, from the viewpoint of improving the throughput of etching the memory holes MH, it is preferable that the temperature of the silicon substrate 10 decreases quickly after the first reaction product is removed.

At time t2, the high-frequency power is increased from the first power Pw1 to the second power Pw2, increasing the heat input from the plasma to the silicon substrate 10. Therefore, it is possible to increase the temperature of the silicon substrate 10 during the removal of the first reaction product. It is also possible to increase the rate at which the temperature of the silicon substrate 10 rises.

Furthermore, at time t3, the high-frequency power is reduced from the second power Pw2 to the third power Pw3, thereby reducing the heat input from the plasma to the silicon substrate 10. Therefore, the rate at which the temperature of the silicon substrate 10 decreases after the first reaction product is removed can be prevented from slowing down.

Note that the change in the conductive gas pressure and the change in the high-frequency power do not necessarily have to occur simultaneously. For example, the change in the high-frequency power may occur a predetermined time earlier than the change in the conductive gas pressure, or the change in the high-frequency power may occur a predetermined time later than the change in the conductive gas pressure.

As described above, the semiconductor device manufacturing method of the second embodiment enables highly accurate processing when processing the processing layer by dry etching.

(Third embodiment)
The semiconductor device manufacturing method of the third embodiment differs from the manufacturing method of the first embodiment in that the control of the change in the pressure of the first gas is synchronized with the control of the change in the high-frequency power applied inside the chamber. The semiconductor device manufacturing method of the third embodiment also differs from the semiconductor device manufacturing method of the second embodiment in that the high-frequency power applied inside the chamber during the first reaction product removal is set lower than the high-frequency power applied inside the chamber during the first etching process. Hereinafter, some of the content overlapping with the first or second embodiment may be omitted.

Figure 9 is an explanatory diagram of the manufacturing method of the semiconductor device of the third embodiment. Figure 9 shows the relationship between the thermal conduction gas pressure, total high-frequency power, wafer temperature, and etching time when forming the memory hole MH.

As shown in FIG. 9, at time t2, a second power Pw2 is applied to the interior of the chamber 20. At time t2, the high-frequency power applied to the interior of the chamber 20 is changed from the first power Pw1 to the second power Pw2. The second power Pw2 is lower than the first power Pw1.

Furthermore, at time t3, a third power Pw3 is applied to the interior of the chamber 20. At time t3, the high-frequency power applied to the interior of the chamber 20 is changed from the second power Pw2 to the third power Pw3. The third power Pw3 is higher than the second power Pw2.

Furthermore, at time t4, a fourth power Pw4 is applied to the interior of the chamber 20. At time t4, the high-frequency power applied to the interior of the chamber 20 is changed from the third power Pw3 to the fourth power Pw4. The fourth power Pw4 is lower than the third power Pw3.

Furthermore, at time t5, a fifth power Pw5 is applied to the interior of the chamber 20. At time t5, the high-frequency power applied to the interior of the chamber 20 is changed from the fourth power Pw4 to the fifth power Pw5. The fifth power Pw5 is higher than the fourth power Pw4.

Furthermore, at time t6, a sixth power Pw6 is applied to the interior of the chamber 20. At time t6, the high-frequency power applied to the interior of the chamber 20 is changed from the fifth power Pw5 to the sixth power Pw6. The sixth power Pw6 is lower than the fifth power Pw5.

Also, at time t7, the application of high-frequency power to the interior of chamber 20 is stopped. Also, at time t7, the supply of etching gas into chamber 20 is cut off.

At time t7, etching of memory hole MH is completed.

Note that the change in the conductive gas pressure and the change in the high-frequency power do not necessarily have to occur simultaneously. For example, the change in the high-frequency power may occur a predetermined time earlier than the change in the conductive gas pressure, or the change in the high-frequency power may occur a predetermined time later than the change in the conductive gas pressure.

Next, we will explain the operation and effects of the semiconductor device manufacturing method of the third embodiment.

In the semiconductor device manufacturing method of the third embodiment, control of the change in the pressure of the conductive gas is synchronized with control of the change in the high-frequency power applied inside the chamber. The high-frequency power is decreased in synchronization with a decrease in the pressure of the conductive gas. The high-frequency power is increased in synchronization with an increase in the pressure of the conductive gas.

Specifically, for example, as described above, after the first etching process, at time t2, the helium gas pressure is reduced from the first pressure P1 to the second pressure P2, and simultaneously the high-frequency power applied to the interior of the chamber 20 is reduced from the first power Pw1 to the second power Pw2. Furthermore, at time t3, the helium gas pressure is increased from the second pressure P2 to the third pressure P3, and simultaneously the high-frequency power applied to the interior of the chamber 20 is increased from the second power Pw2 to the third power Pw3.

During the first reaction product removal after the first etching process, the helium gas pressure is reduced from the first pressure P1 to the second pressure P2, and the pressure in the thermal conduction gas region 76 decreases. When the pressure in the thermal conduction gas region 76 decreases, discharges become more likely to occur within the thermal conduction gas region 76. If discharges occur within the thermal conduction gas region 76, there is a risk that, for example, the silicon substrate 10 or the electrostatic chuck 22b may be damaged.

In the semiconductor device manufacturing method of the third embodiment, for example, at time t2, the high-frequency power is reduced from the first power Pw1 to the second power Pw2, thereby suppressing discharge within the thermal conduction gas region 76. Therefore, damage to the silicon substrate 10 and the electrostatic chuck 22b due to discharge can be suppressed.

As described above, the semiconductor device manufacturing method of the third embodiment enables highly accurate processing when processing the processing layer by dry etching.

(Fourth embodiment)
The semiconductor device manufacturing method of the fourth embodiment differs from the manufacturing method of the first embodiment in that, after controlling the pressure of the first gas to the second pressure, a third gas having a lower thermal conductivity than the first gas is supplied between the holder and the substrate so as to be in contact with the substrate, instead of the first gas, and after removing the first reaction product, the first gas is supplied between the holder and the substrate so as to be in contact with the substrate, instead of the third gas, and the pressure of the first gas is controlled to the third pressure higher than the second pressure. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

Figure 10 is an explanatory diagram of the manufacturing method of the semiconductor device of the fourth embodiment. Figure 10 shows the relationship between the thermal conduction gas pressure, total high-frequency power, wafer temperature, and etching time when forming the memory hole MH.

At time t1, thermal conduction gas is supplied to the thermal conduction gas region 76 between the holder 22 and the silicon substrate 10. The thermal conduction gas is, for example, helium gas. Helium gas is an example of a first gas.

At time t1, the pressure of the helium gas is controlled to a first pressure P1. At time t1, a first power Pw1 is applied to the interior of the chamber 20.

Also, at time t1, etching gas is supplied into the chamber 20. The etching gas is an example of a second gas. Also, at time t1, a coolant is supplied to the coolant flow path 22ax.

After the pressure of the helium gas is controlled to the first pressure P1, a first etching process is performed using reactive ion etching to etch the stack 60.

After the first etching process, at time t2, the helium gas pressure is controlled to a second pressure P2. After the first etching process, at time t2, the helium gas pressure is changed from the first pressure P1 to a second pressure P2. The second pressure P2 is lower than the first pressure P1.

After the helium gas pressure is controlled to the second pressure P2, argon gas is supplied to the thermal conduction gas region 76 between the holder 22 and the silicon substrate 10 at time ta, replacing the helium gas. The argon gas contacts the backside of the silicon substrate 10. Argon gas is an example of a third gas. The thermal conductivity of argon gas is lower than that of helium gas.

The supply of helium gas is switched to argon gas, for example, by the control circuit 54 controlling the thermal conduction gas supply unit 44.

The pressure of the argon gas is controlled to, for example, pressure Pa. Pressure Pa is higher than second pressure P2. Pressure Pa is equal to, for example, first pressure P1.

In Figure 10, the pressure of helium gas is shown by a solid line, and the pressure of argon gas is shown by a dotted line.

After controlling the helium gas pressure to the second pressure P2, a first reaction product removal is performed to remove the reaction product 63 on the stack 60.

After the first reaction product is removed, at time t3, helium gas is supplied to the thermal conduction gas region 76 between the holder 22 and the silicon substrate 10, replacing the argon gas. The helium gas contacts the backside of the silicon substrate 10. The pressure of the helium gas is controlled to a third pressure P3. The third pressure P3 is higher than the second pressure P2.

After controlling the helium gas pressure to a third pressure P3, a second etching process is performed using reactive ion etching to etch the stack 60.

Between time t3 and time t4, a second etching process is performed to etch the stack 60.

After the second etching process, at time t4, the helium gas pressure is controlled to fourth pressure P4. After the second etching process, at time t4, the helium gas pressure is changed from third pressure P3 to fourth pressure P4. The fourth pressure P4 is lower than the third pressure P3.

After the helium gas pressure is controlled to the fourth pressure P4, at time tb, argon gas is supplied to the thermal conduction gas region 76 between the holder 22 and the silicon substrate 10, replacing the helium gas.

The pressure of the argon gas is controlled to, for example, pressure Pb. Pressure Pb is higher than the fourth pressure P4. Pressure Pb is equal to, for example, the third pressure P3.

After controlling the helium gas pressure to the fourth pressure P4, a second reaction product removal is performed to remove the reaction product 63 on the stack 60.

After the second reaction product is removed, at time t5, helium gas is supplied to the thermal conduction gas region 76 between the holder 22 and the silicon substrate 10, replacing the argon gas. The helium gas contacts the backside of the silicon substrate 10. The pressure of the helium gas is controlled to a fifth pressure P5. The fifth pressure P5 is higher than the fourth pressure P4.

After controlling the helium gas pressure to a fifth pressure P5, a third etching process is performed using reactive ion etching to etch the stack 60.

Between time t5 and time t6, a third etching process is performed to etch the stack 60.

After the third etching process, at time t6, the helium gas pressure is controlled to sixth pressure P6. After the third etching process, at time t6, the helium gas pressure is changed from fifth pressure P5 to sixth pressure P6. Sixth pressure P6 is lower than fifth pressure P5.

After controlling the helium gas pressure to the sixth pressure P6, a third reaction product removal is performed to remove the reaction product 63 on the stack 60.

After the third reaction product is removed, at time t7, the application of high-frequency power to the interior of chamber 20 is stopped. Also at time t7, the supply of etching gas into chamber 20 is cut off.

At time t7, etching of memory hole MH is completed.

Next, we will explain the operation and effects of the semiconductor device manufacturing method of the fourth embodiment.

In the semiconductor device manufacturing method of the fourth embodiment, for example, at time ta, argon gas, which has a lower thermal conductivity than helium gas, is supplied into the thermal conduction gas region 76. Because the thermal conductivity of argon gas is lower than that of helium gas, the rate of change in temperature of the silicon substrate 10 is slower than in the case of helium gas.

As a result, for example, it becomes possible to stably maintain the silicon substrate 10 at a temperature of 100°C or higher. It also becomes easier to extend the time during which the silicon substrate 10 is maintained at a temperature of 100°C or higher. This makes it possible to facilitate the removal of reaction products.

In addition, hydrogen gas can be used as the first gas instead of helium gas. Furthermore, as a third gas with a lower thermal conductivity than the first gas, nitrogen gas, neon gas, krypton gas, or xenon gas can be used instead of argon gas, for example.

Furthermore, pressure Pa may be different from the first pressure P1. Further, pressure Pb may be different from the third pressure P3. Further, pressure Pc may be different from the fifth pressure P5.

As described above, the semiconductor device manufacturing method of the fourth embodiment enables highly accurate processing when processing the processing layer by dry etching.

Fifth Embodiment
A method for manufacturing a semiconductor device according to a fifth embodiment includes the steps of: placing a substrate having a workpiece layer on a holder provided in a chamber; supplying a first gas between the holder and the substrate, the first gas being in contact with the substrate; controlling the pressure of the first gas to a first pressure; performing a first etching process to form a recess in the workpiece layer by reactive ion etching using the first process gas; after the first etching process, controlling the pressure of the first gas to a second pressure lower than the first pressure; and performing a first process to supply hydrogen radicals to the recess using a second process gas containing hydrogen while the substrate temperature is between 200° C. and 350° C.; after the first process, controlling the pressure of the first gas to a third pressure higher than the second pressure; and performing a second etching process to etch the bottom of the recess by reactive ion etching using the third process gas.

The semiconductor device manufactured by the semiconductor device manufacturing method of the fifth embodiment is similar to the semiconductor device manufactured by the semiconductor device manufacturing method of the first embodiment. The semiconductor device manufactured by the semiconductor device manufacturing method of the fifth embodiment is a nonvolatile memory 100 in which memory cells are arranged three-dimensionally. Figure 1 is a cross-sectional view of the memory cell array of nonvolatile memory 100. In the following description of nonvolatile memory 100, some of the content that overlaps with the first embodiment will be omitted.

The reactive ion etching apparatus used in the semiconductor device manufacturing method of the fifth embodiment is similar to the reactive ion etching apparatus used in the semiconductor device manufacturing method of the first embodiment. Figure 2 is a schematic diagram of an example of a reactive ion etching apparatus used in the semiconductor device manufacturing method of the fifth embodiment. The reactive ion etching apparatus (RIE apparatus) in Figure 2 is a dual-frequency capacitively coupled plasma apparatus (CCP apparatus). In the following description of the RIE apparatus, some of the content that overlaps with the first embodiment will be omitted.

Next, an example of a method for manufacturing a semiconductor device according to the fifth embodiment will be described.

Figure 11 is an explanatory diagram of a method for manufacturing a semiconductor device according to the fifth embodiment. Figures 12, 13, 14, and 15 are schematic diagrams showing the method for manufacturing a semiconductor device according to the fifth embodiment. Figures 12, 13, 14, and 15 correspond to a portion including one channel layer 11 in Figure 1.

First, a stack 60 is formed on a silicon substrate 10 (Figure 12(a)). The silicon substrate 10 is a semiconductor wafer. The stack 60 is an insulating layer. The silicon substrate 10 is an example of a substrate. The stack 60 is an example of a layer to be processed. The silicon substrate 10 is an example of the semiconductor wafer W in Figure 2.

The stacked body 60 includes a structure in which silicon oxide films 60a and silicon nitride films 60b are alternately stacked. The silicon oxide films 60a and silicon nitride films 60b are formed, for example, by a chemical vapor deposition (CVD) method. The silicon oxide film 60a is an example of a first layer. The silicon nitride film 60b is an example of a second layer.

A portion of the silicon oxide film 60a will eventually become the interlayer insulating layer 12.

Next, a carbon layer 62 having a hole pattern 62a is formed on the laminate 60 (Figure 12(b)). The carbon layer 62 is an example of a mask layer. The carbon layer 62 is formed by, for example, sputtering. The hole pattern 62a is formed by, for example, lithography and RIE.

The mask layer may be, for example, a resist layer, an insulating layer, or a metal layer.

Next, the silicon substrate 10 is loaded into the chamber 20 of the RIE device. The silicon substrate 10 is placed on a holder 22 provided in the chamber 20. The silicon substrate 10 is an example of a substrate.

Memory holes MH are formed in the chamber 20 of the RIE apparatus using reactive ion etching with the carbon layer 62 as a mask (Figures 12(c) to 14(a)). The etching of the memory holes MH is performed while periodically changing the pressure of the thermally conductive gas that cools the silicon substrate 10. The memory holes MH are an example of recesses.

Figure 11 shows the relationship between the thermal conduction gas pressure, total high frequency power, wafer temperature, and etching time when forming the memory hole MH. Figure 11 also shows the timing at which hydrogen plasma is supplied to the silicon substrate 10.

At time t1, thermal conduction gas is supplied to the thermal conduction gas region 76 between the holder 22 and the silicon substrate 10. The thermal conduction gas is, for example, helium gas. The helium gas contacts the back surface of the silicon substrate 10. The helium gas is an example of a first gas.

At time t1, the pressure of the helium gas is controlled to a first pressure P1. The pressure of the helium gas is controlled, for example, by flow control using the first main valve 50. The pressure of the helium gas is controlled to the first pressure P1 by adjusting the opening of the first main valve 50.

The first pressure P1 is, for example, 133 Pa (1 Torr) or more and 13,332 Pa (100 Torr) or less.

Furthermore, at time t1, high-frequency power is applied to the interior of the chamber 20. For example, a first high-frequency power is applied between the support portion 22a of the holder 22 and the shower plate 32 using the first high-frequency power supply 24. For example, a second high-frequency power is applied to the support portion 22a of the holder 22 using the second high-frequency power supply 26. The sum of the first high-frequency power and the second high-frequency power is referred to as the total high-frequency power. At time t1, a first power Pw1 is applied to the interior of the chamber 20.

Also, at time t1, a first etching gas is supplied into the chamber 20. The first etching gas is an example of a first process gas. The etching gas is supplied into the chamber 20 from the process gas supply pipe 30 through the shower plate 32.

The first etching gas contains, for example, carbon (C) and fluorine (F).

Furthermore, at time t1, a coolant is supplied to the coolant flow path 22ax. The coolant is, for example, a fluorine-based inert liquid. By supplying the coolant to the coolant flow path 22ax, the temperature of the support portion 22a of the holder 22 and the electrostatic chuck 22b decreases. The temperature of the support portion 22a of the holder 22 and the electrostatic chuck 22b is, for example, -150°C or higher and 20°C or lower.

After the helium gas pressure is controlled to the first pressure P1, a first etching process is performed using reactive ion etching to etch the stack 60 (Figure 12(c)). Between time t1 and time t2, the first etching process to etch the stack 60 is performed. During the first etching process, the memory hole MH does not penetrate the stack 60.

During the first etching process, the temperature of the silicon substrate 10 is, for example, -150°C or higher and 20°C or lower. During the first etching process, a first state is achieved in which the temperature of the silicon substrate 10 is, for example, -150°C or higher and 20°C or lower.

During the first etching process, a first protective film 64a is formed on the surface of the memory hole MH. The first protective film 64a is formed, for example, on the sidewall of the memory hole MH. The first protective film 64a is formed simultaneously with the formation of the memory hole MH. The first protective film 64a is an example of a first film.

The first protective film 64a is a reaction product derived from the first etching gas. The first protective film 64a contains, for example, carbon (C) and fluorine (F). The first protective film 64a is, for example, a fluorocarbon film.

After the first etching process, at time t2, the helium gas pressure is controlled to a second pressure P2. After the first etching process, at time t2, the helium gas pressure is changed from the first pressure P1 to a second pressure P2. The second pressure P2 is lower than the first pressure P1.

The pressure of the helium gas is controlled, for example, by flow rate control using the first main valve 50. For example, closing the first main valve 50 blocks the flow of helium gas into the thermal conduction gas region 76. For example, closing the first main valve 50 causes the second pressure P2 to approach vacuum.

The second pressure P2 is, for example, 0 Pa or more and 13.3 Pa (0.1 Torr) or less. The second pressure P2 is, for example, 1/100 or less of the first pressure P1.

After the first etching process, for example, at time t3, a second power Pw2 is applied to the interior of the chamber 20. At time t3, the high-frequency power applied to the interior of the chamber 20 is changed from the first power Pw1 to the second power Pw2. The second power Pw2 is lower than the first power Pw1.

The helium gas pressure is controlled to a second pressure P2, and the high-frequency power applied to the interior of the chamber 20 is changed to a second power Pw2, after which a first modification process is performed (Figure 12(d)). In the first modification process, hydrogen radicals are supplied to the memory holes MH in the chamber 20. The first modification process is an example of a first process.

During the first modifying process, for example, at time t3, a first modifying gas is supplied into the chamber 20. The first modifying gas is a gas containing hydrogen (H). The first modifying gas contains, for example, hydrogen gas. The first modifying gas is an example of a second process gas.

During the first modification process, the gas supplied to the interior of the chamber 20 is switched from the first etching gas to the first modifying gas. For example, at time t3, the gas supplied to the interior of the chamber 20 is switched from the first etching gas to the first modifying gas.

During the first modification process, high-frequency power is applied to the hydrogen gas to generate plasma containing hydrogen radicals.

Plasma containing hydrogen radicals is supplied to the surface of the silicon substrate 10. The hydrogen radicals are supplied into the memory holes MH. The surface of the first protective film 64a is exposed to the hydrogen radicals.

The first modification process is performed when the temperature of the silicon substrate 10 is between 200°C and 350°C. During the first modification process, a second state is achieved in which the temperature of the silicon substrate 10 is between 200°C and 350°C.

At time t2, after the helium gas pressure is controlled from the first pressure P1 to the second pressure P2, the temperature of the silicon substrate 10 rises, and a second state is achieved in which the temperature of the silicon substrate 10 is 200°C or higher. The reduction in the helium gas pressure suppresses the propagation of heat within the helium gas. Heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas is suppressed, and the temperature of the silicon substrate 10 rises.

During the first modification process, the first protective film 64a is modified into a first modified protective film 65a. The chemical composition of the first modified protective film 65a is different from that of the first protective film 64a, for example.

During the first modification process, the first protective film 64a is, for example, reduced. During the first modification process, for example, the fluorine concentration of the first protective film 64a is reduced.

During the first modification process, for example, no film is formed on the first protective film 64a. After the first modification process, for example, the inner diameter of the memory hole MH does not decrease. After the first modification process, for example, the volume of the cavity of the memory hole MH does not decrease.

After the first reforming process, at time t4, the pressure of the helium gas is controlled to the third pressure P3. After the first reforming process, at time t4, the pressure of the helium gas is changed from the second pressure P2 to the third pressure P3. After the second state is achieved, the pressure of the helium gas is controlled to the third pressure P3.

The third pressure P3 is higher than the second pressure P2. The pressure of the helium gas is controlled, for example, by flow rate control using the first main valve 50. For example, opening the first main valve 50 starts the flow of helium gas into the thermal conduction gas region 76. The pressure of the helium gas is controlled to the third pressure P3 by adjusting the opening of the first main valve 50.

The third pressure P3 is, for example, equal to or greater than 133 Pa (1 Torr) and equal to or less than 13,332 Pa (100 Torr). The third pressure P3 is, for example, equal to the first pressure P1.

After the first modification process, for example, at time t4, a third power Pw3 is applied to the interior of the chamber 20. At time t4, the high-frequency power applied to the interior of the chamber 20 is changed from the second power Pw2 to the third power Pw3. The third power Pw3 is higher than the second power Pw2.

Furthermore, at time t4, a second etching gas is supplied into the chamber 20. The second etching gas is an example of a third process gas. The second etching gas is supplied into the chamber 20 from the process gas supply pipe 30 through the shower plate 32. For example, at time t4, the gas supplied into the chamber 20 is switched from the first modifying gas to the second etching gas.

The second etching gas contains, for example, carbon (C) and fluorine (F).

The pressure of the helium gas is controlled to a third pressure P3, the high frequency power applied inside the chamber 20 is changed to a third power Pw3, and a second etching gas is supplied inside the chamber 20, and then a second etching process is performed to etch the stack 60 using a reactive ion etching method (Figure 13(a)).
A second etching process is performed using the carbon layer 62 as a mask.

The second etching process etches at least the bottom surface of the memory hole MH. The second etching process is performed between time t4 and time t5. During the second etching process, the memory hole MH does not penetrate the stack 60.

Increasing the pressure of the helium gas from the second pressure P2 to the third pressure P3 promotes the transfer of heat within the helium gas. This promotes heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas, lowering the temperature of the silicon substrate 10.

During the second etching process, the temperature of the silicon substrate 10 is, for example, -150°C or higher and 20°C or lower. During the second etching process, a third state is achieved, in which the temperature of the silicon substrate 10 is, for example, -150°C or higher and 20°C or lower.

During the second etching process, a second protective film 64b is formed on the surface of the memory hole MH. The second protective film 64b is formed, for example, on the sidewall of the memory hole MH in the portion that has been deepened by the second etching process. The second protective film 64b is an example of a second film.

The second protective film 64b is a reaction product derived from the second etching gas. The second protective film 64b contains, for example, carbon (C) and fluorine (F). The second protective film 64b is, for example, a fluorocarbon film.

After the second etching process, at time t5, the helium gas pressure is controlled to fourth pressure P4. After the second etching process, at time t5, the helium gas pressure is changed from third pressure P3 to fourth pressure P4. The fourth pressure P4 is lower than the third pressure P3.

The pressure of the helium gas is controlled, for example, by flow rate control using the first main valve 50. For example, closing the first main valve 50 blocks the flow of helium gas into the thermal conduction gas region 76. For example, closing the first main valve 50 causes the fourth pressure P4 to approach vacuum.

The fourth pressure P4 is, for example, 0 Pa or more and 13.3 Pa (0.1 Torr) or less. The fourth pressure P4 is, for example, 1/100 or less of the third pressure P3.

After the second etching process, for example, at time t6, a fourth power Pw4 is applied to the interior of the chamber 20. At time t6, the high-frequency power applied to the interior of the chamber 20 is changed from the third power Pw3 to the fourth power Pw4. The fourth power Pw4 is lower than the third power Pw3.

The helium gas pressure is controlled to a third pressure P3, and the high-frequency power applied to the interior of the chamber 20 is changed to a fourth power Pw4, after which a second modification process is performed (Figure 13(b)). In the second modification process, hydrogen radicals are supplied to the memory holes MH in the chamber 20. The second modification process is an example of a second process.

During the second modifying process, for example, at time t6, a second modifying gas is supplied into the chamber 20. The second modifying gas is a gas containing hydrogen (H). The second modifying gas contains, for example, hydrogen gas. The second modifying gas is an example of a fourth process gas.

During the second modification process, the gas supplied to the interior of the chamber 20 is switched from the second etching gas to the second modifying gas. For example, at time t6, the gas supplied to the interior of the chamber 20 is switched from the second etching gas to the second modifying gas.

During the second modification process, high-frequency power is applied to the hydrogen gas to generate plasma containing hydrogen radicals.

Plasma containing hydrogen radicals is supplied to the surface of the silicon substrate 10. The hydrogen radicals are supplied into the memory holes MH. The surface of the second protective film 64b is exposed to the hydrogen radicals.

The second modification process is performed when the temperature of the silicon substrate 10 is between 200°C and 350°C. During the second modification process, a fourth state is achieved in which the temperature of the silicon substrate 10 is between 200°C and 350°C.

At time t5, after the helium gas pressure is controlled from the third pressure P3 to the fourth pressure P4, the temperature of the silicon substrate 10 rises, and a fourth state is achieved in which the temperature of the silicon substrate 10 is 200°C or higher. The reduction in the helium gas pressure suppresses the propagation of heat within the helium gas. Heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas is suppressed, and the temperature of the silicon substrate 10 rises.

During the second modification process, the second protective film 64b is modified into a second modified protective film 65b. The chemical composition of the second modified protective film 65b is different from that of the second protective film 64b, for example.

During the second modification process, the second protective film 64b is, for example, reduced. During the second modification process, the fluorine concentration of the second protective film 64b is reduced, for example.

During the second modification process, for example, no film is formed on the second protective film 64b. After the second modification process, for example, the inner diameter of the memory hole MH does not decrease. After the second modification process, for example, the volume of the cavity of the memory hole MH does not decrease.

After the second reforming process, at time t7, the pressure of the helium gas is controlled to the fifth pressure P5. After the second reforming process, at time t7, the pressure of the helium gas is changed from the fourth pressure P4 to the fifth pressure P5. After the fourth state is achieved, the pressure of the helium gas is controlled to the fifth pressure P5.

The fifth pressure P5 is higher than the fourth pressure P4. The pressure of the helium gas is controlled, for example, by flow rate control using the first main valve 50. For example, opening the first main valve 50 starts the flow of helium gas into the thermal conduction gas region 76. The pressure of the helium gas is controlled to the fifth pressure P5 by adjusting the opening of the first main valve 50.

The fifth pressure P5 is, for example, equal to or greater than 133 Pa (1 Torr) and equal to or less than 13,332 Pa (100 Torr). The fifth pressure P5 is, for example, equal to the first pressure P1.

After the second modification process, for example, at time t7, a fifth power Pw5 is applied to the interior of the chamber 20. At time t7, the high-frequency power applied to the interior of the chamber 20 is changed from the fourth power Pw4 to a fifth power Pw5. The fifth power Pw5 is higher than the fourth power Pw4.

Furthermore, at time t7, a third etching gas is supplied into the chamber 20. The third etching gas is an example of a fifth process gas. The third etching gas is supplied into the chamber 20 from the process gas supply pipe 30 through the shower plate 32. For example, at time t7, the gas supplied into the chamber 20 is switched from the second modifying gas to the third etching gas.

The third etching gas contains, for example, carbon (C) and fluorine (F).

The helium gas pressure is controlled to a fifth pressure P5, the high-frequency power applied to the interior of the chamber 20 is changed to a fifth power Pw5, and a third etching gas is supplied to the interior of the chamber 20. After that, a third etching process is performed using reactive ion etching to etch the laminate 60 (Figure 13(c)). The third etching process is performed using the carbon layer 62 as a mask.

The third etching process etches at least the bottom surface of the memory hole MH. The third etching process is performed between time t7 and time t8. During the third etching process, the memory hole MH does not penetrate the stack 60.

Increasing the pressure of the helium gas from the fourth pressure P4 to the fifth pressure P5 promotes the transfer of heat within the helium gas. This promotes heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas, lowering the temperature of the silicon substrate 10.

During the third etching process, the temperature of the silicon substrate 10 is, for example, -150°C or higher and 20°C or lower. During the third etching process, a fifth state is achieved, in which the temperature of the silicon substrate 10 is, for example, -150°C or higher and 20°C or lower.

During the third etching process, a third protective film 64c is formed on the surface of the memory hole MH. The third protective film 64c is formed, for example, on the sidewall of the memory hole MH in the portion that has been deepened by the third etching process. The third protective film 64c is an example of a third film.

The third protective film 64c is a reaction product derived from the third etching gas. The third protective film 64c contains, for example, carbon (C) and fluorine (F). The third protective film 64c is, for example, a fluorocarbon film.

After the third etching process, at time t8, the helium gas pressure is controlled to sixth pressure P6. After the third etching process, at time t8, the helium gas pressure is changed from fifth pressure P5 to sixth pressure P6. Sixth pressure P6 is lower than fifth pressure P5.

The pressure of the helium gas is controlled, for example, by flow rate control using the first main valve 50. For example, closing the first main valve 50 blocks the flow of helium gas into the thermal conduction gas region 76. For example, closing the first main valve 50 causes the sixth pressure P6 to approach vacuum.

The sixth pressure P6 is, for example, 0 Pa or more and 13.3 Pa (0.1 Torr) or less. The sixth pressure P6 is, for example, 1/100 or less of the fifth pressure P5.

After the third etching process, for example, at time t9, a sixth power Pw6 is applied to the interior of the chamber 20. At time t9, the high-frequency power applied to the interior of the chamber 20 is changed from the fifth power Pw5 to the sixth power Pw6. The sixth power Pw6 is lower than the fifth power Pw5.

The helium gas pressure is controlled to a sixth pressure P6, and the high-frequency power applied to the interior of the chamber 20 is changed to a sixth power Pw6, after which a third modification process is performed (Figure 13(d)). In the third modification process, hydrogen radicals are supplied to the memory holes MH in the chamber 20. The third modification process is an example of a third process.

During the third reforming process, for example, at time t9, a third reforming gas is supplied into the chamber 20. The third reforming gas is a gas containing hydrogen (H). The third reforming gas contains, for example, hydrogen gas.

During the third modification process, the gas supplied to the interior of the chamber 20 is switched from the third etching gas to the third modifying gas. For example, at time t9, the gas supplied to the interior of the chamber 20 is switched from the third etching gas to the third modifying gas.

During the third modification process, high-frequency power is applied to the hydrogen gas to generate plasma containing hydrogen radicals.

Plasma containing hydrogen radicals is supplied to the surface of the silicon substrate 10. The hydrogen radicals are supplied into the memory holes MH. The surface of the third protective film 64c is exposed to the hydrogen radicals.

The third modification process is performed when the temperature of the silicon substrate 10 is between 200°C and 350°C. During the third modification process, a sixth state is achieved in which the temperature of the silicon substrate 10 is between 200°C and 350°C.

At time t8, after the helium gas pressure is controlled from fifth pressure P5 to sixth pressure P6, the temperature of the silicon substrate 10 rises, and a sixth state is achieved in which the temperature of the silicon substrate 10 is 200°C or higher. The reduction in helium gas pressure suppresses the propagation of heat within the helium gas. Heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas is suppressed, and the temperature of the silicon substrate 10 rises.

During the third modification process, the third protective film 64c is modified into a third modified protective film 65c. The chemical composition of the third modified protective film 65c is different from that of the third protective film 64c, for example.

During the third modification process, the third protective film 64c is, for example, reduced. During the third modification process, for example, the fluorine concentration of the third protective film 64c is reduced.

During the third modification process, for example, no film is formed on the third protective film 64c. After the third modification process, for example, the inner diameter of the memory hole MH does not decrease. After the third modification process, for example, the volume of the cavity of the memory hole MH does not decrease.

After the third reforming process, at time t10, the pressure of the helium gas is controlled to the seventh pressure P7. After the third reforming process, at time t10, the pressure of the helium gas is changed from the sixth pressure P6 to the seventh pressure P7. After the sixth state is achieved, the pressure of the helium gas is controlled to the seventh pressure P7.

The seventh pressure P7 is higher than the sixth pressure P6. The pressure of the helium gas is controlled, for example, by flow rate control using the first main valve 50. For example, opening the first main valve 50 starts the flow of helium gas into the thermal conduction gas region 76. The pressure of the helium gas is controlled to the seventh pressure P7 by adjusting the opening of the first main valve 50.

The seventh pressure P7 is, for example, equal to or greater than 133 Pa (1 Torr) and equal to or less than 13,332 Pa (100 Torr). The seventh pressure P7 is, for example, equal to the first pressure P1.

After the third modification process, for example, at time t10, a seventh power Pw7 is applied to the interior of the chamber 20. At time t10, the high-frequency power applied to the interior of the chamber 20 is changed from the sixth power Pw6 to the seventh power Pw7. The seventh power Pw7 is higher than the sixth power Pw6.

Furthermore, at time t10, a fourth etching gas is supplied into the chamber 20. The fourth etching gas is supplied into the chamber 20 from the process gas supply pipe 30 through the shower plate 32. For example, at time t10, the gas supplied into the chamber 20 is switched from the third modifying gas to the fourth etching gas.

The fourth etching gas contains, for example, carbon (C) and fluorine (F).

The helium gas pressure is controlled to a seventh pressure P7, the high-frequency power applied to the interior of the chamber 20 is changed to a seventh power Pw7, and a fourth etching gas is supplied to the interior of the chamber 20. Then, a fourth etching process is performed using reactive ion etching to etch the laminate 60 (Figure 14(a)). The fourth etching process is performed using the carbon layer 62 as a mask.

The fourth etching process etches at least the bottom surface of the memory hole MH. The fourth etching process is performed between time t10 and time t11. During the fourth etching process, the memory hole MH penetrates the stack 60.

Increasing the pressure of the helium gas from the sixth pressure P6 to the seventh pressure P7 promotes the transfer of heat within the helium gas. This promotes heat dissipation from the silicon substrate 10 to the holder 22 via the helium gas, lowering the temperature of the silicon substrate 10.

During the fourth etching process, the temperature of the silicon substrate 10 is, for example, -150°C or higher and 20°C or lower. During the fourth etching process, a seventh state is achieved, in which the temperature of the silicon substrate 10 is, for example, -150°C or higher and 20°C or lower.

During the fourth etching process, a fourth protective film 64d is formed on the surface of the memory hole MH. The fourth protective film 64d is formed, for example, on the sidewall of the memory hole MH in the portion that has been deepened by the fourth etching process.

The fourth protective film 64d is a reaction product derived from the fourth etching gas. The fourth protective film 64d contains, for example, carbon (C) and fluorine (F). The fourth protective film 64d is, for example, a fluorocarbon film.

After the fourth etching process, at time t11, the application of high-frequency power to the interior of chamber 20 is stopped. Also, at time t11, the supply of etching gas for the fourth etching process into chamber 20 is cut off.

At time t11, etching of memory hole MH is completed.

The aspect ratio of the memory hole MH that penetrates the stack 60 is, for example, 30 or more.

After the fourth etching process, the silicon substrate 10 is removed from the chamber 20 of the RIE apparatus.

The first etching gas, second etching gas, third etching gas, and fourth etching gas contain, for example, carbon (C) and fluorine (F). The first etching gas, second etching gas, third etching gas, and fourth etching gas contain, for example, oxygen (O). The first etching gas, second etching gas, third etching gas, and fourth etching gas contain, for example, hydrogen (H).

The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas include, for example, CxHyFz (x is an integer of 1 or more, y is an integer of 0 or more, and z is an integer of 1 or more). The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas include, for _example , _C4F6 , _{C4F8 , and CH2F2} .

The first etching gas, second etching gas, third etching gas, and fourth etching gas contain, for example, oxygen gas.

The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas are, for example, mixed gases of C ₄ F ₆ , C ₄ F ₈ , CH ₂ F ₂ , and oxygen gas.

The first etching gas, second etching gas, third etching gas, and fourth etching gas may, for example, be the same gas. Also, for example, at least one of the first etching gas, second etching gas, third etching gas, and fourth etching gas may be different from the other gases.

The first, second, and third reforming gases contain hydrogen (H). The first, second, and third reforming gases contain, for example, hydrogen gas.

Next, the carbon layer 62, the first modified protective film 65a, the second modified protective film 65b, the third modified protective film 65c, and the fourth protective film 64d are removed (Figure 14(b)). The carbon layer 62, the first modified protective film 65a, the second modified protective film 65b, the third modified protective film 65c, and the fourth protective film 64d are removed by, for example, an ashing process using oxygen plasma.

Next, a laminated insulating layer 66 is formed in the memory hole MH (Figure 14(c)). The laminated insulating layer 66 has a laminated structure of, for example, a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The laminated insulating layer 66 will eventually become the gate insulating layer 13.

Next, a polycrystalline silicon layer 68 is formed in the memory hole MH (Figure 14(d)). The polycrystalline silicon layer 68 will eventually become the channel layer 11.

Next, the silicon nitride film 60b is selectively removed (Figure 15(a)).

Next, a first tungsten layer 70 is formed in the area where the silicon nitride film 60b has been removed (Figure 15(b)). The first tungsten layer 70 will eventually become the word line WL.

Next, a second tungsten layer 69 is formed on the polycrystalline silicon layer 68 (Figure 15(c)). The second tungsten layer 69 will eventually become the bit line BL.

The non-volatile memory 100 shown in Figure 1 is manufactured using the above manufacturing method.

Next, we will explain the operation and effects of the semiconductor device manufacturing method of the fifth embodiment.

Hereinafter, for convenience of explanation, the first etching process, second etching process, third etching process, and fourth etching process may be collectively referred to simply as etching process. The first modification process, second modification process, and third modification process may be collectively referred to simply as modification process. The first protective film 64a, second protective film 64b, and third protective film 64c may be collectively referred to simply as protective film 64. The first modified protective film 65a, second modified protective film 65b, and third modified protective film 65c may be collectively referred to simply as modified protective film 65.

In non-volatile memories with memory cells arranged three-dimensionally, increasing the memory capacity requires, for example, reducing the diameter of the memory holes and increasing the number of stacked word lines WL. Reducing the diameter of the memory holes and increasing the number of stacked word lines WL requires forming memory holes with a high aspect ratio (depth of memory hole / diameter of memory hole).

When the aspect ratio of a memory hole becomes high, the problem of the memory hole becoming bowed arises. The bowed shape of a memory hole occurs when the hole diameter widens during the etching process that forms the memory hole.

When etching a memory hole, substances derived from the plasma-converted etching gas adhere to the sidewalls, forming a protective film on the sidewalls. The formation of a protective film on the sidewalls of the memory hole prevents the sidewalls from being etched and prevents the hole diameter from widening.

The reason why the hole diameter widens during etching of the memory hole is thought to be that the protective film formed on the sidewall of the memory hole during etching reacts with the material exposed on the sidewall of the memory hole, causing the etching of the sidewall of the memory hole to progress. The reaction between the protective film and the material exposed on the sidewall is caused, for example, by the kinetic energy of ions incident on the protective film during etching. As the etching of the sidewall of the memory hole progresses, the diameter of the memory hole widens.

The sidewalls of the memory hole are formed of a material containing silicon (Si), such as silicon oxide or silicon nitride. The protective film formed on the sidewalls of the memory hole is, for example, a fluorocarbon film containing carbon and fluorine.

For example, silicon contained in the material forming the sidewall reacts with fluorine contained in the protective film to form silicon fluoride. As silicon fluoride is formed and released as a gas, etching of the sidewall of the memory hole progresses. As etching of the sidewall of the memory hole progresses, the diameter of the memory hole widens.

In the semiconductor device manufacturing method of the fifth embodiment, when etching the memory hole MH, the protective film 64 formed on the sidewall is modified to form a modified protective film 65. By modifying the protective film 64 into the modified protective film 65, reaction between the modified protective film 65 and the material forming the sidewall of the memory hole MH is suppressed.

Specifically, for example, the protective film 64 is reduced to form the modified protective film 65. Specifically, for example, the fluorine concentration of the protective film 64 is reduced to form the modified protective film 65.

Specifically, for example, hydrogen radicals are supplied to the surface of the protective film 64, causing the hydrogen radicals to react with fluorine in the protective film 64, generating hydrogen fluoride. The generated hydrogen fluoride is released as a gas, and a modified protective film 65 is formed that has a lower fluorine concentration than the protective film 64.

Because the fluorine concentration of the modified protective film 65 is reduced, reaction between the modified protective film 65 and the material forming the sidewall of the memory hole MH is suppressed. Therefore, etching of the sidewall of the memory hole MH is suppressed, and the expansion of the hole diameter of the memory hole MH is suppressed.

Furthermore, by reducing the fluorine concentration in the modified protective film 65, the proportion of carbon-carbon bonds (C-C bonds), which have higher bond energy than carbon-fluorine bonds (C-F bonds), increases in the modified protective film 65. Therefore, the etching resistance of the protective film during memory hole MH formation also increases.

Therefore, according to the semiconductor device manufacturing method of the fifth embodiment, etching of the sidewalls of the memory holes MH is suppressed, and the memory holes are prevented from becoming bowed.

When modifying the protective film 64 through a modification process, it may be difficult to modify the protective film 64 at the bottom of a deep trench with a large aspect ratio. If the protective film 64 at the bottom of the trench is not sufficiently modified, the bottom of the trench will have a bowing shape.

In the semiconductor device manufacturing method of the fifth embodiment, hydrogen radicals are used during the modification process. Hydrogen radicals are less likely to be deactivated than, for example, hydrogen ions. For this reason, it is believed that hydrogen radicals can easily reach the bottom of deep trenches with large aspect ratios without being deactivated.

To modify the protective film 64 using hydrogen radicals, it is necessary to provide energy to cause the hydrogen radicals to react with the fluorine in the protective film 64. In the semiconductor device manufacturing method of the fifth embodiment, the temperature of the silicon substrate 10 is increased. In the semiconductor device manufacturing method of the fifth embodiment, thermal energy is used as the energy to cause the hydrogen radicals to react with the fluorine in the protective film 64.

As a result of research by the inventors, it was found that a temperature of 200°C or higher is required to cause hydrogen radicals to react with fluorine in the fluorocarbon film and extract the fluorine from the fluorocarbon film. It was also found that a fluorocarbon film in contact with a silicon oxide film reacts at temperatures above 350°C, causing etching of the silicon oxide film. It was also found that decomposition of the fluorocarbon film becomes apparent at temperatures above 300°C.

In the semiconductor device manufacturing method of the fifth embodiment, the temperature of the silicon substrate 10 on which the stacked body 60 is formed is controlled to 200°C or higher. This allows the reaction between hydrogen radicals and fluorine in the protective film 64 to proceed, thereby modifying the protective film 64.

Furthermore, in the semiconductor device manufacturing method of the fifth embodiment, the temperature of the silicon substrate 10 on which the stacked body 60 is formed is controlled to 350°C or less. This suppresses reaction between the material of the sidewall of the memory hole MH and the protective film 64, and prevents etching of the material of the sidewall. This suppresses the expansion of the hole diameter of the memory hole MH, and prevents the memory hole MH from becoming bowed.

From the viewpoint of promoting the modification of the protective film 64, the temperature of the silicon substrate 10 during the modification process is preferably 225°C or higher, and more preferably 250°C or higher. Furthermore, from the viewpoint of suppressing etching of the sidewall material and suppressing decomposition of the protective film 64, the temperature of the silicon substrate 10 during the modification process is preferably 325°C or lower, and more preferably 300°C or lower. Note that by controlling the temperature of the silicon substrate within this range, it is also possible to remove the reaction product 63 of the first embodiment.

In the semiconductor device manufacturing method of the fifth embodiment, from the viewpoint of improving the etching rate of the stacked body 60 and improving the throughput of the etching process, it is preferable that the temperature of the silicon substrate 10 on which the stacked body 60 is formed is low. In the semiconductor device manufacturing method of the fifth embodiment, the temperature of the silicon substrate 10 during the etching process is preferably, for example, 20°C or less, and more preferably 0°C or less. The temperature of the silicon substrate 10 during the modification process is preferably higher than the temperature of the silicon substrate 10 during the etching process.

In the semiconductor device manufacturing method of the fifth embodiment, when forming the memory hole MH, the temperature of the silicon substrate 10 having the stacked body 60, which is the layer to be processed, is changed. That is, a low-temperature state of the silicon substrate 10 and a high-temperature state of the silicon substrate 10 are alternately repeated.

The first, third, and fifth states correspond to low-temperature states. The second, fourth, and sixth states correspond to high-temperature states.

The memory holes MH are etched when the silicon substrate 10 is at a low temperature. On the other hand, the protective film 64 is modified when the silicon substrate 10 is at a high temperature.

In the semiconductor device manufacturing method of the fifth embodiment, the memory holes MH are formed in the same RIE apparatus by alternately exposing the silicon substrate 10 to low temperatures and high temperatures, thereby improving the processing accuracy of the memory hole shape. Furthermore, the throughput of etching the memory holes MH is improved.

In the semiconductor device manufacturing method of the fifth embodiment, the silicon substrate 10 is transitioned between a high-temperature state and a low-temperature state by changing the pressure of the thermally conductive gas. The thermally conductive gas is, for example, helium gas.

By changing the pressure of the thermal conduction gas, the heat transfer between the silicon substrate 10 and the holder 22 is changed. Increasing the pressure of the thermal conduction gas accelerates the heat transfer, while decreasing the pressure of the thermal conduction gas suppresses the heat transfer. For example, by decreasing the pressure of the thermal conduction gas, the silicon substrate 10 can be transitioned from a low-temperature state to a high-temperature state. Also, by increasing the pressure of the thermal conduction gas, the silicon substrate 10 can be transitioned from a high-temperature state to a low-temperature state.

In the semiconductor device manufacturing method of the fifth embodiment, the temperature of the silicon substrate 10 is changed by changing the pressure of the thermally conductive gas used to cool the silicon substrate 10. Therefore, it is not necessary to add a new structure to the RIE apparatus to change the temperature of the silicon substrate 10. This makes it possible to easily improve the processing accuracy of the shape of the memory hole.

In the semiconductor device manufacturing method of the fifth embodiment, from the viewpoint of preventing ions in the plasma from colliding with the carbon layer 62 and etching the carbon layer 62 during the modification process, it is preferable that the high-frequency power applied to the silicon substrate 10 during the modification process be lower than the high-frequency power applied to the silicon substrate 10 during the etching process.

As described above, the semiconductor device manufacturing method of the fifth embodiment can prevent the memory hole from becoming bowed, and can form the memory hole with high processing accuracy.

Sixth Embodiment
A semiconductor manufacturing apparatus of a sixth embodiment includes a chamber, a holder provided in the chamber and capable of adsorbing a substrate, the holder including a recess on its surface, a first hole provided in the recess, and a second hole provided in the recess, a first gas passage connected to the first hole, a second gas passage connected to the second hole, a first valve provided in the first gas passage, a second valve provided in the second gas passage, a first gas supply pipe for supplying a first gas to the recess, and a gas exhaust pipe for exhausting gas from the recess, wherein the first gas passage and the second gas passage are connected to the first gas supply pipe, or the first gas passage and the second gas passage are connected to the gas exhaust pipe.

The semiconductor manufacturing apparatus of the sixth embodiment is used, for example, to implement the semiconductor device manufacturing methods of the first to fifth embodiments.

A sixth embodiment of a semiconductor device manufacturing method includes placing a substrate having a workpiece layer on a holder provided in a chamber and having a recess on the surface, a first hole in the recess, and a second hole in the recess; opening a first valve provided in a first gas passage connected to the first hole and a second valve provided in a second gas passage connected to the second hole to supply a first gas that contacts the substrate between the holder and the substrate via the first gas passage and the second gas passage; controlling the pressure of the first gas to a first pressure; and A semiconductor device manufacturing method includes: performing a first etching process to etch a workpiece layer using an etching method; closing the first and second valves during or after the first etching process; opening the first and second valves after closing the first and second valves; exhausting a first gas from between the holder and the substrate via the first and second gas passages; controlling the pressure of the first gas to a second pressure lower than the first pressure; and removing a reaction product from the workpiece layer. Then, either the first or second valve is opened first when supplying the first gas, or either the first or second valve is opened first when exhausting the first gas. The semiconductor device manufacturing method of the sixth embodiment differs from the semiconductor device manufacturing method of the first embodiment in that the semiconductor manufacturing apparatus of the sixth embodiment is used. Hereinafter, some of the content overlapping with the semiconductor device manufacturing method of the first embodiment may be omitted.

Figure 16 is a schematic diagram of a semiconductor manufacturing apparatus according to a sixth embodiment. The semiconductor manufacturing apparatus according to the sixth embodiment is a reactive ion etching apparatus (RIE apparatus). The reactive ion etching apparatus according to the sixth embodiment is a dual-frequency capacitively coupled plasma apparatus (CCP apparatus).

The RIE apparatus includes, for example, a chamber 20, a holder 22, a first high-frequency power supply 24, a second high-frequency power supply 26, a process gas supply pipe 30, a shower plate 32, a process gas exhaust pipe 34, an exhaust device 36, a refrigerant unit 38, a refrigerant supply pipe 40, a refrigerant exhaust pipe 42, a heat transfer gas supply unit 44, a first heat transfer gas supply pipe 46, a heat transfer gas exhaust pipe 48, a first main valve 50, a second main valve 52, a control circuit 54, a heat transfer gas passage 56, and a heat transfer gas valve 58.

The thermal conduction gas passages 56 include a first thermal conduction gas passage 56a, a second thermal conduction gas passage 56b, a third thermal conduction gas passage 56c, a fourth thermal conduction gas passage 56d, and a fifth thermal conduction gas passage 56e. The thermal conduction gas valves 58 include a first thermal conduction gas valve 58a, a second thermal conduction gas valve 58b, a third thermal conduction gas valve 58c, a fourth thermal conduction gas valve 58d, and a fifth thermal conduction gas valve 58e.

The first heat conduction gas supply pipe 46 is an example of a first gas supply pipe. The heat conduction gas exhaust pipe 48 is an example of a gas exhaust pipe. The first heat conduction gas passage 56a is an example of a first gas passage. The second heat conduction gas passage 56b is an example of a second gas passage. The third heat conduction gas passage 56c is an example of a third gas passage. The fourth heat conduction gas passage 56d is an example of a fourth gas passage. The fifth heat conduction gas passage 56e is an example of a fifth gas passage.

The first thermal conduction gas valve 58a is an example of a first valve. The second thermal conduction gas valve 58b is an example of a second valve. The third thermal conduction gas valve 58c is an example of a third valve. The fourth thermal conduction gas valve 58d is an example of a fourth valve. The fifth thermal conduction gas valve 58e is an example of a fifth valve.

Figure 17 is a schematic diagram of the main parts of a semiconductor manufacturing apparatus according to the sixth embodiment. Figure 17(a) is a top view of the holder 22. Figure 17(a) is a top view of the electrostatic chuck 22b. Figure 17(b) is a diagram showing the relationship between the electrostatic chuck 22b, the thermal conduction gas passage 56, the thermal conduction gas valve 58, the first thermal conduction gas supply pipe 46, the thermal conduction gas exhaust pipe 48, the first main valve 50, and the second main valve 52. Figure 17(b) is a diagram including the AA' cross section of Figure 17(a).

The holder 22 is provided in the chamber 20. For example, a semiconductor wafer W is placed on the holder 22. The holder 22 is capable of adsorbing the semiconductor wafer W. The semiconductor wafer W is an example of a substrate.

The holder 22 has a support portion 22a, an electrostatic chuck 22b, and an outer ring 22c.

The support portion 22a functions as a lower electrode. High-frequency power is applied to the support portion 22a. The support portion 22a is made of, for example, metal.

A refrigerant flow path 22ax is provided inside the support portion 22a. The refrigerant flow path 22ax is an air gap. A refrigerant for cooling the support portion 22a is supplied to the refrigerant flow path 22ax. The refrigerant is, for example, a fluorine-based inert liquid.

The electrostatic chuck 22b includes a substrate support portion 71, a recess 72, and thermal conduction gas holes 74. The thermal conduction gas holes 74 include a first thermal conduction gas hole 74a, a second thermal conduction gas hole 74b, a third thermal conduction gas hole 74c, a fourth thermal conduction gas hole 74d, and a fifth thermal conduction gas hole 74e. The first thermal conduction gas hole 74a is an example of a first hole. The second thermal conduction gas hole 74b is an example of a second hole. The third thermal conduction gas hole 74c is an example of a third hole. The fourth thermal conduction gas hole 74d is an example of a fourth hole. The fifth thermal conduction gas hole 74e is an example of a fifth hole.

The electrostatic chuck 22b is provided on the support portion 22a. The electrostatic chuck 22b has the function of attracting and fixing the semiconductor wafer W. The electrostatic chuck 22b is formed, for example, from a dielectric material with an electrode inside. The dielectric material is, for example, ceramics.

A substrate support portion 71 is provided on the surface of the electrostatic chuck 22b. The substrate support portion 71 has, for example, an annular portion provided on the outer periphery of the electrostatic chuck 22b and multiple protrusions provided on the inside of the annular portion. When a semiconductor wafer W is placed on the holder 22, the back surface of the semiconductor wafer W contacts the substrate support portion 71.

A recess 72 is provided on the surface of the electrostatic chuck 22b. When a semiconductor wafer W is placed on the holder 22, a thermally conductive gas region 76 is formed on the upper surface of the electrostatic chuck 22b, surrounded by the back surface of the semiconductor wafer W and the recess 72.

A plurality of thermal conduction gas holes 74 are provided on the surface of the electrostatic chuck 22b. The thermal conduction gas holes 74 are provided in the recess 72. Thermal conduction gas for cooling the semiconductor wafer W is supplied to the thermal conduction gas region 76 through the thermal conduction gas holes 74.

The multiple thermal conduction gas holes 74 are, for example, provided at equal intervals on the surface of the electrostatic chuck 22b. The distance between two adjacent thermal conduction gas holes 74 is, for example, 10 cm or more and 20 cm or less.

Thermal conduction gases include, for example, helium (He), hydrogen (H), nitrogen (N), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe). Thermal conduction gases include, for example, helium gas, hydrogen gas, nitrogen gas, neon gas, argon gas, krypton gas, or xenon gas.

The outer ring 22c is provided on the support portion 22a. The outer ring 22c is provided around the electrostatic chuck 22b. The outer ring 22c has the function of supporting the outer periphery of the semiconductor wafer W. The upper surface of the outer ring 22c is made of, for example, silicon.

The first high-frequency power supply 24 has the function of applying first high-frequency power to the interior of the chamber 20. The first high-frequency power supply 24 applies high-frequency power between the support portion 22a of the holder 22 and the shower plate 32. Plasma is generated in the chamber 20 by the first high-frequency power applied to the chamber 20 using the first high-frequency power supply 24.

The first high-frequency power applied by the first high-frequency power supply 24 is, for example, 50 W or more and 20,000 W or less. The first frequency applied by the first high-frequency power supply 24 is, for example, 20 MHz or more and 200 MHz or less.

The second high-frequency power supply 26 has the function of applying a second high-frequency power to the interior of the chamber 20. The second high-frequency power supply 26 applies the second high-frequency power to the support portion 22a of the holder 22. By applying the second high-frequency power to the holder 22, the energy of the ions colliding with the semiconductor wafer W is controlled.

The second high-frequency power applied to the holder 22 is, for example, 50 W or more and 20,000 W or less. The second frequency applied to the holder 22 is lower than the first frequency applied to the chamber 20 by the first high-frequency power supply 24. The second frequency applied to the holder 22 is, for example, 0.1 MHz or more and 20 MHz or less.

The process gas supply pipe 30 is provided at the top of the chamber 20. Process gas is supplied from the process gas supply pipe 30 to the shower plate 32. For example, etching gas or modifying gas is supplied from the process gas supply pipe 30 to the shower plate 32.

The shower plate 32 is provided in the chamber 20. The shower plate 32 is provided above the holder 22.

Process gas is supplied to the shower plate 32 from the process gas supply pipe 30. The process gas is supplied into the chamber 20 from multiple gas supply ports provided in the shower plate 32.

The shower plate 32 also functions as the upper electrode for the first high-frequency power.

The process gas exhaust pipe 34 is provided at the bottom of the chamber 20. For example, etching gas and reaction products not consumed in the etching reaction are exhausted from the process gas exhaust pipe 34 to the outside of the chamber 20.

The exhaust device 36 is connected to the process gas exhaust pipe 34 and the heat transfer gas exhaust pipe 48. The exhaust device 36 is, for example, a vacuum pump.

The refrigerant unit 38 is connected to the refrigerant supply pipe 40. The refrigerant supply pipe 40 is connected to the refrigerant flow path 22ax. The refrigerant flow path 22ax is connected to the refrigerant discharge pipe 42. The refrigerant unit 38 circulates the refrigerant through the refrigerant supply pipe 40, the refrigerant flow path 22ax, and the refrigerant discharge pipe 42.

The thermal conduction gas supply unit 44 is connected to a first thermal conduction gas supply pipe 46. The thermal conduction gas supply unit 44 is, for example, a gas cylinder that stores thermal conduction gas. The thermal conduction gas is supplied from the thermal conduction gas supply unit 44 to the first thermal conduction gas supply pipe 46. The thermal conduction gas is an example of a first gas.

The first heat conduction gas supply pipe 46 is connected to the recess 72. The first heat conduction gas supply pipe 46 is connected to the heat conduction gas passage 56. Heat conduction gas is supplied from the first heat conduction gas supply pipe 46 to the heat conduction gas passage 56.

The first main valve 50 is provided on the first heat transfer gas supply pipe 46. The first main valve 50 is, for example, a flow control valve. The first main valve 50 is used to control the supply of heat transfer gas to the heat transfer gas passage 56. The first main valve 50 can also be used to cut off the supply of heat transfer gas to the heat transfer gas passage 56.

The exhaust device 36 is connected to the chamber 20 and the thermal conduction gas exhaust pipe 48. The thermal conduction gas is exhausted outside the RIE apparatus through the thermal conduction gas exhaust pipe 48.

The thermal conduction gas exhaust pipe 48 is connected to the recess 72. The thermal conduction gas exhaust pipe 48 is connected to the thermal conduction gas passage 56. The thermal conduction gas is exhausted outside the RIE apparatus through the thermal conduction gas passage 56.

The second main valve 52 is provided on the thermal conduction gas exhaust pipe 48. The second main valve 52 is used to control the exhaust of thermal conduction gas from the thermal conduction gas passage 56.

The heat conduction gas passages 56 are connected to the heat conduction gas holes 74. For example, the first heat conduction gas passage 56a is connected to the first heat conduction gas hole 74a. For example, the second heat conduction gas passage 56b is connected to the second heat conduction gas hole 74b. For example, the third heat conduction gas passage 56c is connected to the third heat conduction gas hole 74c. For example, the fourth heat conduction gas passage 56d is connected to the fourth heat conduction gas hole 74d. For example, the fifth heat conduction gas passage 56e is connected to the fifth heat conduction gas hole 74e.

Thermal conduction gas is supplied to the thermal conduction gas region 76 from the thermal conduction gas passage 56 through the thermal conduction gas holes 74. Furthermore, thermal conduction gas is discharged from the thermal conduction gas region 76 to the thermal conduction gas passage 56 through the thermal conduction gas holes 74.

At least a portion of the thermal conduction gas passage 56 is provided within the holder 22.

The heat conduction gas passage 56 is connected to the first heat conduction gas supply pipe 46. For example, the first heat conduction gas passage 56a, the second heat conduction gas passage 56b, the third heat conduction gas passage 56c, the fourth heat conduction gas passage 56d, and the fifth heat conduction gas passage 56e are connected to the first heat conduction gas supply pipe 46.

The thermal conduction gas passages 56 are also connected to the thermal conduction gas exhaust pipe 48. For example, the first thermal conduction gas passage 56a, the second thermal conduction gas passage 56b, the third thermal conduction gas passage 56c, the fourth thermal conduction gas passage 56d, and the fifth thermal conduction gas passage 56e are connected to the thermal conduction gas exhaust pipe 48.

The heat transfer gas valves 58 are provided in the heat transfer gas passages 56. For example, the first heat transfer gas valve 58a is provided in the first heat transfer gas passage 56a. For example, the second heat transfer gas valve 58b is provided in the second heat transfer gas passage 56b. For example, the third heat transfer gas valve 58c is provided in the third heat transfer gas passage 56c. For example, the fourth heat transfer gas valve 58d is provided in the fourth heat transfer gas passage 56d. For example, the fifth heat transfer gas valve 58e is provided in the fifth heat transfer gas passage 56e. For example, heat transfer gas valves 58 are also provided in heat transfer gas passages 56 other than the first to fifth heat transfer gas passages 56a to 56e.

It is also possible to configure multiple heat conduction gas passages 56 in common and provide one heat conduction gas valve 58. That is, it is also possible to configure one heat conduction gas valve 58 for multiple heat conduction gas holes 74. For example, it is also possible to configure one heat conduction gas valve 58 for multiple heat conduction gas holes 74 arranged in a ring shape on the surface of the electrostatic chuck 22b. It is also possible to configure one heat conduction gas valve 58 for multiple heat conduction gas holes 74 arranged in a fan shape on the surface of the electrostatic chuck 22b.

The thermal conduction gas valve 58 makes it possible to control, for example, the flow rate of thermal conduction gas supplied from the thermal conduction gas passage 56 to the thermal conduction gas region 76 for each thermal conduction gas passage 56. Also, the thermal conduction gas valve 58 makes it possible to control, for example, the flow rate of thermal conduction gas discharged from the thermal conduction gas region 76 to the thermal conduction gas passage 56 for each thermal conduction gas passage 56.

The thermal conduction gas valve 58 is, for example, a flow control valve or a pressure control valve.

The thermal conduction gas valve 58 is provided, for example, in the holder 22. The thermal conduction gas valve 58 is provided, for example, in the support portion 22a.

The control circuit 54 has the function of controlling the operation of the first high-frequency power supply 24, the second high-frequency power supply 26, the exhaust device 36, the refrigerant unit 38, the heat transfer gas supply unit 44, the first main valve 50, the second main valve 52, and the heat transfer gas valve 58.

The control circuit 54, for example, controls the opening and closing of the thermal conduction gas valve 58. The control circuit 54, for example, independently controls the opening and closing of multiple thermal conduction gas valves 58. The control circuit 54, for example, independently controls the opening and closing of the first thermal conduction gas valve 58a and the second thermal conduction gas valve 58b.

The control circuit 54 also controls, for example, the opening degree of the thermal conduction gas valve 58. The control circuit 54, for example, independently controls the opening degrees of the multiple thermal conduction gas valves 58. The control circuit 54, for example, independently controls the opening degree of the first thermal conduction gas valve 58a and the opening degree of the second thermal conduction gas valve 58b.

The control circuit 54 is composed of, for example, hardware and software. The control circuit 54 includes, for example, an electronic circuit.

The semiconductor wafer W placed on the holder 22 is anisotropically etched using plasma generated between the shower plate 32 and the holder 22 in the chamber 20.

Next, a method for manufacturing a semiconductor device according to the sixth embodiment using the semiconductor manufacturing apparatus according to the sixth embodiment will be described. Below, an example will be described in which etching of the stack 60 is performed using the RIE apparatus according to the sixth embodiment in a manner similar to the method for manufacturing a semiconductor device according to the first embodiment. Below, the description will be made with reference to Figure 4 of the first embodiment.

Figure 18 is an explanatory diagram of the operation of the semiconductor manufacturing apparatus of the sixth embodiment. Figure 18 is a diagram showing an example of the control sequence of the first main valve 50, the second main valve 52, and the thermal conduction gas valve 58 when changing the temperature of the semiconductor wafer W.

For example, when performing the first etching process as shown in FIG. 4(c), as shown in FIG. 18(a), the first main valve 50 and the thermal conduction gas valve 58 are opened, and helium gas is supplied from the first thermal conduction gas supply pipe 46 to the thermal conduction gas region 76. For example, the pressure of the helium gas in the thermal conduction gas region 76 is controlled to a first pressure P1.

The silicon substrate 10 is in a low temperature state. When the silicon substrate 10 is in a low temperature state, the etching rate of the memory hole MH increases, and etching of the stack 60 mainly progresses.

Next, during or after the first etching process, as shown in FIG. 18(b), the first main valve 50 and the thermal conduction gas valve 58 are closed. Then, by opening the second main valve 52, the helium gas in the thermal conduction gas passage 56 between the thermal conduction gas valve 58 and the thermal conduction gas exhaust pipe 48 is exhausted from the thermal conduction gas exhaust pipe 48 connected to the thermal conduction gas passage 56. The thermal conduction gas passage 56 downstream of the thermal conduction gas valve 58 is placed in a vacuum state.

Next, when removing the first reaction product shown in FIG. 4(d), the pressure of the helium gas in the thermal conduction gas region 76 is changed from the first pressure P1 to the second pressure P2. The second pressure P2 is lower than the first pressure P1.

First, as shown in Figure 18(c), the fourth thermal conduction gas valve 58d and the fifth thermal conduction gas valve 58e are opened first. The thermal conduction gas passage 56 downstream of the thermal conduction gas valve 58 is already in a vacuum state, which promotes a reduction in pressure in the thermal conduction gas region 76.

Next, as shown in Figure 18(d), the first thermal conduction gas valve 58a, the second thermal conduction gas valve 58b, and the third thermal conduction gas valve 58c are opened.

As the pressure in the thermal conduction gas region 76 decreases, the silicon substrate 10 reaches a high temperature. When the silicon substrate 10 is in a high temperature state, the decomposition reaction of the reaction product 63 formed on the bottom and side surfaces of the memory hole MH is accelerated, and the decomposition of the reaction product 63 mainly progresses.

Next, when performing the second etching and second reaction product removal, the operations shown in Figures 18(a) to 18(d) are repeated. By repeating the operations shown in Figures 18(a) to 18(d), the pressure of the conduction gas in the thermal conduction gas region 76 is changed, allowing the silicon substrate 10 to alternate between a low-temperature state and a high-temperature state.

Next, we will explain the operation and effects of the semiconductor manufacturing apparatus of the sixth embodiment.

Figure 19 is a schematic diagram of the main parts of a semiconductor manufacturing apparatus of a comparative example. Figure 19(a) is a top view of the holder 22. Figure 19(a) is a top view of the electrostatic chuck 22b. Figure 19(b) is a diagram showing the relationship between the electrostatic chuck 22b, the thermal conduction gas passage 56, the thermal conduction gas valve 58, the first thermal conduction gas supply pipe 46, the thermal conduction gas exhaust pipe 48, the first main valve 50, and the second main valve 52. Figure 19(b) is a view including the B-B' cross section of Figure 19(a). Figure 19 corresponds to Figure 17 of the sixth embodiment.

The RIE apparatus of the comparative example differs from the RIE apparatus of the sixth embodiment in that it is provided with one heat conduction gas passage 56, one heat conduction gas valve 58, and one heat conduction gas hole 74 for supplying heat conduction gas, and one heat conduction gas passage 56, one heat conduction gas valve 58, and one heat conduction gas hole 74 for discharging heat conduction gas.

Specifically, the RIE apparatus of the comparative example has a thermal conduction gas passage 56x, a thermal conduction gas valve 58x, and a thermal conduction gas hole 74x for supplying thermal conduction gas. The RIE apparatus of the comparative example has a thermal conduction gas passage 56y, a thermal conduction gas valve 58y, and a thermal conduction gas hole 74y for exhausting thermal conduction gas.

In the case of the comparative example RIE apparatus, when the pressure of the conductive gas in the thermal conductive gas region 76 is changed to alternate between a low temperature state and a high temperature state of the semiconductor wafer W, there is a problem in that the temperature of the semiconductor wafer W varies greatly across its surface. If the temperature variation of the semiconductor wafer W increases across its surface, variations will increase, for example, during etching processing and removal of reaction products, reducing the processing accuracy when processing the workpiece layer by dry etching.

One possible reason for the in-plane temperature variation of the semiconductor wafer W is the large positional dependency of the pressure change of the conduction gas in the thermal conduction gas region 76.

For example, when the semiconductor wafer W is transitioned from a high-temperature state to a low-temperature state, i.e., when the pressure of the conductive gas in the thermal conduction gas region 76 is increased, if the supply of thermal conduction gas to the outer periphery of the electrostatic chuck 22b is delayed, the temperature of the outer periphery of the semiconductor wafer W will be difficult to decrease. Conversely, if the supply of thermal conduction gas to the inner periphery of the electrostatic chuck 22b is delayed, the temperature of the inner periphery of the semiconductor wafer W will be difficult to decrease.

Furthermore, for example, when the semiconductor wafer W is transitioned from a low-temperature state to a high-temperature state, i.e., when the pressure of the conductive gas in the thermal conduction gas region 76 is reduced, if the discharge of the thermal conduction gas from the outer periphery of the electrostatic chuck 22b is delayed, the temperature of the outer periphery of the semiconductor wafer W will be difficult to increase. Conversely, if the discharge of the thermal conduction gas from the inner periphery of the electrostatic chuck 22b is delayed, the temperature of the inner periphery of the semiconductor wafer W will be difficult to increase.

The RIE apparatus of the sixth embodiment is provided with multiple thermal conduction gas passages 56 and multiple thermal conduction gas holes 74 for supplying thermal conduction gas. Therefore, the supply of thermal conduction gas to the thermal conduction gas region 76 is accelerated compared to the comparative example. Therefore, when the semiconductor wafer W is transitioned from a high-temperature state to a low-temperature state, in-plane temperature variations of the semiconductor wafer W are suppressed.

Furthermore, the RIE apparatus of the sixth embodiment is provided with multiple thermal conduction gas passages 56 and multiple thermal conduction gas holes 74 for discharging the thermal conduction gas. Therefore, the discharge of the thermal conduction gas from the thermal conduction gas region 76 is facilitated compared to the comparative example. Therefore, when the semiconductor wafer W is transitioned from a low-temperature state to a high-temperature state, the temperature variation across the semiconductor wafer W is suppressed.

Furthermore, in the RIE apparatus of the sixth embodiment, a thermal conduction gas valve 58 is provided in each of the multiple thermal conduction gas passages 56. The opening and closing or opening degree of the thermal conduction gas valves 58 can be independently controlled.

As a result, for example, it is possible to adjust the supply of thermal conduction gas to the thermal conduction gas region 76 for each position in the thermal conduction gas region 76. For example, it is possible to promote the supply of thermal conduction gas to regions where the temperature of the semiconductor wafer W is difficult to decrease. Therefore, when the semiconductor wafer W is transitioned from a high-temperature state to a low-temperature state, it is possible to further suppress in-plane temperature variations of the semiconductor wafer W.

Furthermore, for example, it is possible to adjust the discharge of thermal conduction gas from the thermal conduction gas region 76 for each position in the thermal conduction gas region 76. For example, it is possible to promote the discharge of thermal conduction gas from regions where the temperature of the semiconductor wafer W is less likely to rise. Therefore, when the semiconductor wafer W is transitioned from a low-temperature state to a high-temperature state, it is possible to further suppress in-plane temperature variations of the semiconductor wafer W.

Figure 18 shows an example of the control sequence of the first main valve 50, the second main valve 52, and the thermal conduction gas valve 58, for example, when the silicon substrate 10 is transitioned from a low-temperature state to a high-temperature state and the temperature of the outer periphery of the silicon substrate 10 is difficult to increase. As shown in Figure 18(c), by opening the fourth thermal conduction gas valve 58d and the fifth thermal conduction gas valve 58e first, the discharge of thermal conduction gas from the thermal conduction gas region 76 corresponding to the outer periphery of the silicon substrate 10 is promoted. This makes it easier for the temperature of the outer periphery of the silicon substrate 10 to increase. This makes it possible to suppress in-plane temperature variations in the silicon substrate 10 when the silicon substrate 10 is transitioned from a low-temperature state to a high-temperature state.

Note that while the fourth thermal conduction gas valve 58d and the fifth thermal conduction gas valve 58e are shown opened first in FIG. 18(c), the valves that are opened first are not limited to this. For example, the first thermal conduction gas valve 58a may be opened before the second thermal conduction gas valve 58b. Also, for example, the second thermal conduction gas valve 58b may be opened before the first thermal conduction gas valve 58a.

For example, when transitioning the silicon substrate 10 from a high-temperature state to a low-temperature state, i.e., when opening the first main valve 50 and the heat conduction gas valve 58 and supplying helium gas from the first heat conduction gas supply pipe 46 to the heat conduction gas region 76, it is possible to open some of the heat conduction gas valves 58 first. For example, the first heat conduction gas valve 58a is opened before the second heat conduction gas valve 58b. This allows the temperature of the silicon substrate 10 above the first heat conduction gas hole 74a to be lowered more quickly than the temperature of the silicon substrate 10 above the second heat conduction gas hole 74b. Also, for example, the second heat conduction gas valve 58b is opened before the first heat conduction gas valve 58a. This allows the temperature of the silicon substrate 10 above the second heat conduction gas hole 74b to be lowered more quickly than the temperature of the silicon substrate 10 above the first heat conduction gas hole 74a.

As described above, the semiconductor device manufacturing apparatus and semiconductor device manufacturing method of the sixth embodiment enable highly accurate processing when processing a processing layer by dry etching.

Seventh Embodiment
The semiconductor manufacturing apparatus of the seventh embodiment differs from the semiconductor manufacturing apparatus of the sixth embodiment in that the first gas passage and the second gas passage are connected to a gas exhaust pipe, and the first gas passage and the second gas passage are not connected to a first gas supply pipe. Hereinafter, some of the description overlapping with the sixth embodiment may be omitted.

Figure 20 is a schematic diagram of the main components of a semiconductor manufacturing apparatus according to the seventh embodiment. Figure 20 corresponds to Figure 17(b) of the sixth embodiment.

One of the heat transfer gas passages 56 is connected to the first heat transfer gas supply pipe 46. The fourth heat transfer gas passage 56d is connected to the first heat transfer gas supply pipe 46.

In addition, a portion of the heat transfer gas passage 56 is connected to the heat transfer gas exhaust pipe 48. The first heat transfer gas passage 56a, the second heat transfer gas passage 56b, the third heat transfer gas passage 56c, and the fifth heat transfer gas passage 56e are connected to the heat transfer gas exhaust pipe 48.

The RIE apparatus of the seventh embodiment, for example, makes it possible to adjust the discharge of thermal conduction gas from the thermal conduction gas region 76 for each position in the thermal conduction gas region 76. For example, it becomes possible to promote the discharge of thermal conduction gas from regions where the temperature of the semiconductor wafer W is less likely to rise. Therefore, when the semiconductor wafer W is transitioned from a low-temperature state to a high-temperature state, it is possible to suppress in-plane temperature variations of the semiconductor wafer W.

(Modification)
Fig. 21 is a schematic diagram of a main part of a semiconductor manufacturing apparatus according to a modification of the seventh embodiment. Fig. 21 is a diagram corresponding to Fig. 20 of the seventh embodiment. The semiconductor manufacturing apparatus according to the seventh embodiment differs from the semiconductor manufacturing apparatus according to the seventh embodiment in that the first gas passage and the second gas passage are not connected to a gas exhaust pipe, but are connected to a first gas supply pipe.

Some of the heat conduction gas passages 56 are connected to the first heat conduction gas supply pipe 46. The first heat conduction gas passage 56a, the second heat conduction gas passage 56b, the third heat conduction gas passage 56c, and the fourth heat conduction gas passage 56d are connected to the first heat conduction gas supply pipe 46.

In addition, one of the thermal conduction gas passages 56 is connected to the thermal conduction gas exhaust pipe 48. The fifth thermal conduction gas passage 56e is connected to the thermal conduction gas exhaust pipe 48.

The RIE apparatus of the modified example of the seventh embodiment, for example, makes it possible to adjust the supply of thermal conduction gas to the thermal conduction gas region 76 for each position in the thermal conduction gas region 76. For example, it becomes possible to promote the supply of thermal conduction gas to regions of the semiconductor wafer W where the temperature is difficult to decrease. Therefore, when the semiconductor wafer W is transitioned from a high-temperature state to a low-temperature state, it is possible to suppress in-plane temperature variations of the semiconductor wafer W.

As described above, the semiconductor device manufacturing apparatus of the seventh embodiment and its modified examples enables highly accurate processing when processing a processing layer by dry etching.

Eighth Embodiment
The semiconductor manufacturing apparatus of the eighth embodiment differs from the semiconductor manufacturing apparatus of the sixth embodiment in that the first gas passage, the second gas passage, and the third gas passage are connected to the first gas supply pipe but not to the gas exhaust pipe, and the fourth gas passage and the fifth gas passage are not connected to the first gas supply pipe but to the gas exhaust pipe. Hereinafter, some description of the content that overlaps with the sixth embodiment may be omitted.

Figure 22 is a schematic diagram of the main components of a semiconductor manufacturing apparatus according to the eighth embodiment. Figure 22 corresponds to Figure 17(b) of the sixth embodiment.

Some of the heat conduction gas passages 56 are connected to the first heat conduction gas supply pipe 46. The first heat conduction gas passage 56a, the second heat conduction gas passage 56b, and the third heat conduction gas passage 56c are connected to the first heat conduction gas supply pipe 46.

In addition, a portion of the thermal conduction gas passage 56 is connected to the thermal conduction gas exhaust pipe 48. The fourth thermal conduction gas passage 56d and the fifth thermal conduction gas passage 56e are connected to the thermal conduction gas exhaust pipe 48.

The RIE apparatus of the eighth embodiment, for example, makes it possible to adjust the discharge of thermal conduction gas from the thermal conduction gas region 76 for each position in the thermal conduction gas region 76. For example, it becomes possible to promote the discharge of thermal conduction gas from regions where the temperature of the semiconductor wafer W is less likely to rise. Therefore, when the semiconductor wafer W is transitioned from a low-temperature state to a high-temperature state, it is possible to suppress in-plane temperature variations of the semiconductor wafer W.

Furthermore, for example, it is possible to adjust the supply of thermal conduction gas to the thermal conduction gas region 76 for each position in the thermal conduction gas region 76. For example, it is possible to promote the supply of thermal conduction gas to regions where the temperature of the semiconductor wafer W is difficult to decrease. Therefore, when the semiconductor wafer W is transitioned from a high-temperature state to a low-temperature state, it is possible to suppress in-plane temperature variations of the semiconductor wafer W.

As described above, the eighth embodiment and the semiconductor device manufacturing apparatus enable highly accurate processing when processing a processing layer by dry etching.

Ninth Embodiment
The semiconductor manufacturing apparatus of the ninth embodiment differs from the semiconductor manufacturing apparatus of the sixth embodiment in that it further includes a second gas supply pipe for supplying a second gas different from the first gas to the recess, and the first gas passage and the second gas passage are connected to the first gas supply pipe and the second gas supply pipe. Hereinafter, some description of the content that overlaps with the sixth embodiment may be omitted.

Figure 23 is a schematic diagram of the main components of a semiconductor manufacturing apparatus according to the ninth embodiment. Figure 23 corresponds to Figure 17(b) of the sixth embodiment.

The RIE apparatus of the ninth embodiment is equipped with a second thermal conduction gas supply pipe 47 and a third main valve 53.

The second heat conduction gas supply pipe 47 is connected to the recess 72. The second heat conduction gas supply pipe 47 is connected to the heat conduction gas passage 56. Heat conduction gas is supplied from the second heat conduction gas supply pipe 47 to the heat conduction gas passage 56.

A thermal conduction gas different from the thermal conduction gas supplied from the first thermal conduction gas supply pipe 46 is supplied from the second thermal conduction gas supply pipe 47. The thermal conduction gas supplied from the second thermal conduction gas supply pipe 47 is an example of a second gas.

The thermal conduction gas supplied from the second thermal conduction gas supply pipe 47 has, for example, a lower thermal conductivity than the thermal conduction gas supplied from the first thermal conduction gas supply pipe 46.

For example, the thermal conduction gas supplied from the first thermal conduction gas supply pipe 46 is helium gas, and the thermal conduction gas supplied from the second thermal conduction gas supply pipe 47 is argon gas or nitrogen gas.

The third main valve 53 is provided on the second heat transfer gas supply pipe 47. The third main valve 53 is, for example, a flow control valve. The third main valve 53 is used to control the supply of heat transfer gas to the heat transfer gas passage 56. The third main valve 53 can also be used to cut off the supply of heat transfer gas to the heat transfer gas passage 56.

The RIE apparatus of the ninth embodiment is used, for example, to implement the semiconductor device manufacturing method of the fourth embodiment, which uses two types of thermally conductive gases.

As described above, the ninth embodiment and semiconductor device manufacturing apparatus enable highly accurate processing when processing a processing layer by dry etching.

In the first to fourth embodiments, an example was described in which etching was performed three times, with the reaction products being removed after each etching. However, the number of etchings is not limited to three. The number of etchings can be any number of times, as long as it is two or more.

In the fifth embodiment, an example was described in which etching was performed four times. However, the number of times etching is not limited to four. The number of times etching can be any number of times, as long as it is two or more.

In the first to fifth embodiments, the semiconductor device is described as a non-volatile memory, but the semiconductor device is not limited to a non-volatile memory.

In the first to fifth embodiments, the processing layer includes a structure in which silicon oxide films and silicon nitride films are alternately stacked, but the processing layer is not particularly limited. For example, the processing layer may include a structure in which insulating films other than silicon oxide films and silicon nitride films are alternately stacked. Furthermore, for example, the processing layer may include a structure in which insulating films and semiconductor films are alternately stacked. Furthermore, for example, the processing layer may include a structure in which insulating films and metal films are alternately stacked. Furthermore, the processing layer may be composed of a single film.

In the first to fifth embodiments, an example has been described in which memory holes MH are formed in the work layer by etching, but the pattern formed in the work layer is not limited to a hole pattern. The pattern formed in the work layer may be, for example, a groove pattern. It is also possible to adopt a form in which the entire work layer is etched.

In the first to fifth embodiments, the reactive ion etching apparatus (RIE apparatus) has been described as a dual-frequency capacitively coupled plasma apparatus (CCP apparatus). However, the type of RIE apparatus is not particularly limited.

In the first to fourth embodiments, an etching gas is supplied into the chamber 20 even when removing reaction products. However, for example, hydrogen gas, nitrogen gas, argon gas, or the like may be supplied into the chamber 20 instead of the etching gas when removing reaction products.

Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in a variety of other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as set forth in the claims.

(Appendix 1)
placing a substrate having a layer to be processed on a holder provided in the chamber;
supplying a first gas between the holder and the substrate, the first gas being in contact with the substrate;
controlling the pressure of the first gas to a first pressure;
performing a first etching process on the workpiece layer by reactive ion etching using a first process gas to form a recess;
After the first etching process, the pressure of the first gas is controlled to a second pressure lower than the first pressure;
performing a first process of supplying hydrogen radicals to the recessed portion using a second process gas containing hydrogen while the temperature of the substrate is in a state of 200° C. or higher and 350° C. or lower;
After the first treatment, the pressure of the first gas is controlled to a third pressure higher than the second pressure;
A method for manufacturing a semiconductor device includes performing a second etching process to etch the bottom surface of the recess by reactive ion etching using a third process gas.

(Appendix 2)
2. The method for manufacturing a semiconductor device according to claim 1, wherein the first etching process, the first process, and the second etching process are performed in the same chamber.

(Appendix 3)
2. The method for manufacturing a semiconductor device according to claim 1, wherein the first process gas contains carbon and fluorine.

(Appendix 4)
2. The method for manufacturing a semiconductor device according to claim 1, wherein a first film is formed on the surface of the recess by reactive ion etching using the first process gas.

(Appendix 5)
5. The method for manufacturing a semiconductor device according to claim 4, wherein the first film contains carbon and fluorine.

(Appendix 6)
5. The method for manufacturing a semiconductor device according to claim 4, wherein the first film is reduced in the first treatment.

(Appendix 7)
5. The method for manufacturing a semiconductor device according to claim 4, wherein the first treatment reduces the fluorine concentration of the first film.

(Appendix 8)
2. The method for manufacturing a semiconductor device according to claim 1, wherein the second process gas contains hydrogen gas.

(Appendix 9)
2. The method for manufacturing a semiconductor device according to claim 1, further comprising forming a mask layer having a pattern on the processing layer before performing the first etching process, and forming the recess using the mask layer as a mask.

(Appendix 10)
10. The method for manufacturing a semiconductor device according to claim 9, wherein the mask layer contains carbon.

(Appendix 11)
2. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature of the substrate during the first etching process is 20° C. or less.

(Appendix 12)
2. The method for manufacturing a semiconductor device according to claim 1, wherein a high frequency power applied to the substrate during the first processing is lower than a high frequency power applied to the substrate during the first etching processing.

(Appendix 13)
2. The method for manufacturing a semiconductor device according to claim 1, wherein the processing layer contains silicon.

(Appendix 14)
2. The method for manufacturing a semiconductor device according to claim 1, wherein the processing layer includes a structure in which first layers and second layers different from the first layers are alternately stacked.

(Appendix 15)
15. The method for manufacturing a semiconductor device according to claim 14, wherein the first layer is a silicon oxide film and the second layer is a silicon nitride film.

(Appendix 16)
After the second etching process, the pressure of the first gas is controlled to a fourth pressure lower than the third pressure;
performing a second process of supplying hydrogen radicals to the recessed portion using a fourth process gas containing hydrogen while the temperature of the substrate is in a state of 200° C. or higher and 350° C. or lower;
After the second treatment, the pressure of the first gas is controlled to a fifth pressure higher than the fourth pressure;
2. The method for manufacturing a semiconductor device according to claim 1, further comprising: performing a third etching process to etch the bottom surface of the recess by reactive ion etching using a fifth process gas.

(Appendix 17)
placing a substrate having a layer to be processed on a holder provided in the chamber;
supplying a first gas between the holder and the substrate, the first gas being in contact with the substrate;
controlling the pressure of the first gas to a first pressure;
performing a first etching process of etching the workpiece layer using a reactive ion etching method;
After the first etching process, the pressure of the first gas is controlled to a second pressure lower than the first pressure;
performing a first reaction product removal step of removing a reaction product on the processed layer;
After removing the first reaction product, controlling the pressure of the first gas to a third pressure higher than the second pressure;
A method for manufacturing a semiconductor device includes a second etching process for etching the processed layer using a reactive ion etching method.

(Appendix 18)
18. The method for manufacturing a semiconductor device according to claim 17, wherein a second gas containing carbon (C) and fluorine (F) is supplied into the chamber during the first etching process and the second etching process.

(Appendix 19)
19. The method for manufacturing a semiconductor device according to claim 18, wherein the second gas is supplied into the chamber when the first reaction product is removed.

(Appendix 20)
18. The method for manufacturing a semiconductor device according to claim 17, wherein the processing layer contains silicon (Si) and nitrogen (N).

(Appendix 21)
18. The method for manufacturing a semiconductor device according to claim 17, wherein the processing layer includes a structure in which silicon oxide films and silicon nitride films are alternately stacked.

(Appendix 22)
18. The method for manufacturing a semiconductor device according to claim 17, wherein the following inequality holds when the time during which the pressure of the first gas is controlled to the second pressure is td (sec), the temperature of the holder during the first etching process is T (°C), the ratio of the area of the substrate to the sum of the area of the substrate and the area of the inner wall of the chamber is k, the high-frequency power applied to the inside of the chamber is Pw (W), the mass of the substrate is m (kg), and the specific heat capacity of the substrate is c (J/(kg°C)).
td≧(100-T)/{(k×Pw)/(m×c)}

(Appendix 23)
18. The method for manufacturing a semiconductor device according to claim 17, wherein the pressure of the first gas is controlled to the second pressure for a time period longer than 10 seconds.

(Appendix 24)
18. The method for manufacturing a semiconductor device according to claim 17, wherein control of the change in pressure of the first gas is synchronized with control of the change in high frequency power applied to the interior of the chamber.

(Appendix 25)
25. The method for manufacturing a semiconductor device according to claim 24, wherein a high frequency power applied to the inside of the chamber during the first reaction product removal is higher than a high frequency power applied to the inside of the chamber during the first etching process.

(Appendix 26)
25. The method for manufacturing a semiconductor device according to claim 24, wherein a high frequency power applied to the inside of the chamber during the first reaction product removal is lower than a high frequency power applied to the inside of the chamber during the first etching process.

(Appendix 27)
forming a recess in the workpiece layer during the first etching process;
18. The method for manufacturing a semiconductor device according to claim 17, wherein the bottom surface of the recess is etched during the second etching process.

(Appendix 28)
18. The method for manufacturing a semiconductor device according to claim 17, wherein the first gas contains helium (He), hydrogen (H), nitrogen (N), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe).

(Appendix 29)
After controlling the pressure of the first gas to the second pressure, a third gas having a lower thermal conductivity than the first gas is supplied between the holder and the substrate so as to be in contact with the substrate, in place of the first gas;
After the first reaction product is removed, the first gas is supplied in place of the third gas between the holder and the substrate so as to be in contact with the substrate;
18. The method for manufacturing a semiconductor device according to claim 17, wherein the pressure of the first gas is controlled to a third pressure higher than the second pressure.

(Appendix 30)
18. The method for manufacturing a semiconductor device according to claim 17, wherein the second pressure is 1/100 or less of the first pressure.

(Appendix 31)
the temperature of the substrate during the first etching process is 60° C. or less;
18. The method for manufacturing a semiconductor device according to claim 17, wherein the temperature of the substrate during the removal of the first reaction product is 100° C. or higher.

(Appendix 32)
After the second etching process, the pressure of the first gas is controlled to a fourth pressure lower than the third pressure;
performing a second reaction product removal step of removing the reaction product on the processed layer;
After removing the second reaction product, controlling the pressure of the first gas to a fifth pressure higher than the fourth pressure;
18. The method for manufacturing a semiconductor device according to claim 17, further comprising the step of performing a third etching process of etching the processing layer using a reactive ion etching method.

(Appendix 33)
18. The method for manufacturing a semiconductor device according to claim 17, further comprising measuring a temperature of the substrate, and controlling the pressure of the first gas to the third pressure based on the measured temperature of the substrate.

(Appendix 34)
placing a substrate having a layer to be processed on a holder provided in the chamber;
supplying a first gas between the holder and the substrate, the first gas being in contact with the substrate;
controlling the pressure of the first gas to a first pressure;
performing a first etching process in which the workpiece layer is etched using a reactive ion etching method in a first state in which the temperature of the substrate is 60° C. or less;
After the first etching process, the pressure of the first gas is controlled to a second pressure lower than the first pressure;
A second state is realized in which the temperature of the substrate is 100° C. or higher;
After realizing the second state, controlling the pressure of the first gas to a third pressure higher than the second pressure;
A method for manufacturing a semiconductor device, comprising: performing a second etching process in which the processed layer is etched using a reactive ion etching method in a third state in which the temperature of the substrate is 60° C. or less.

(Appendix 35)
35. The method for manufacturing a semiconductor device according to claim 34, wherein the following inequality holds when the time during which the pressure of the first gas is controlled to the second pressure is td (sec), the temperature of the holder during the first etching process is T (°C), the ratio of the area of the substrate to the sum of the area of the substrate and the area of the inner wall of the chamber is k, the high-frequency power applied to the inside of the chamber is Pw (W), the mass of the substrate is m (kg), and the specific heat capacity of the substrate is c (J/(kg°C)).
td≧(100-T)/{(k×Pw)/(m×c)}

(Appendix 36)
35. The method for manufacturing a semiconductor device according to claim 34, wherein control of the change in pressure of the first gas is synchronized with control of the change in high frequency power applied to the interior of the chamber.

10 Silicon substrate (substrate)
20 Chamber 22 Holder 22b Electrostatic chuck 46 First heat transfer gas supply pipe (first gas supply pipe)
47 Second heat transfer gas supply pipe (second gas supply pipe)
48 Heat conduction gas exhaust piping (gas exhaust piping)
50 First main valve 52 Second main valve 54 Control circuit 56a First heat transfer gas passage (first gas passage)
56b Second heat transfer gas passage (second gas passage)
56c Third heat transfer gas passage (third gas passage)
58a First thermal transfer gas valve (first valve)
58b Second thermal transfer gas valve (second valve)
58c Third heat transfer gas valve (third valve)
60 Laminate (processed layer)
60a: silicon oxide film (first layer)
60b Silicon nitride film (second layer)
62 Carbon layer (mask layer)
64a First protective film (first film)
72 Recess 74a First heat conduction gas hole (first hole)
74b Second heat conduction gas hole (second hole)
74c Third heat conduction gas hole (third hole)
100 Nonvolatile memory (semiconductor device)
MH Memory hole (recess)

Claims (13)

a holder is provided in the chamber, the holder having a recess provided on a surface thereof, a first hole provided in the recess, and a second hole provided in the recess; and a substrate having a workpiece layer is placed on the holder;
a first valve provided in a first gas passage connected to the first hole and a second valve provided in a second gas passage connected to the second hole are opened to supply a first gas that will come into contact with the substrate between the holder and the substrate through the first gas passage and the second gas passage;
controlling the pressure of the first gas to a first pressure;
performing a first etching process of etching the workpiece layer using a reactive ion etching method;
closing the first valve and the second valve during or after the first etching process;
After closing the first valve and the second valve, the first valve and the second valve are opened to exhaust the first gas from between the holder and the substrate through the first gas passage and the second gas passage;
controlling the pressure of the first gas to a second pressure lower than the first pressure;
A method for manufacturing a semiconductor device, comprising: performing a first reaction product removal step of removing a reaction product on the processed layer;
When supplying the first gas, either the first valve or the second valve is opened first, or
A method for manufacturing a semiconductor device, wherein when the first gas is discharged, either the first valve or the second valve is opened first. 2. The method for manufacturing a semiconductor device according to claim 1 , wherein when supplying said first gas, either said first valve or said second valve is opened first . 2. The method for manufacturing a semiconductor device according to claim 1 , wherein when exhausting said first gas, either said first valve or said second valve is opened first . 2. The method for manufacturing a semiconductor device according to claim 1, wherein, after closing the first valve and the second valve and before opening the first valve and the second valve, the first gas in the first gas passage between the first valve and the gas exhaust pipe and the first gas in the second gas passage between the second valve and the gas exhaust pipe are exhausted from a gas exhaust pipe connected to the first gas passage and the second gas passage. After removing the first reaction product, controlling the pressure of the first gas to a third pressure higher than the second pressure;
2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of performing a second etching process for etching the processing layer using a reactive ion etching method. 6. The method for manufacturing a semiconductor device according to claim 5, wherein a second gas containing carbon (C) and fluorine (F) is supplied into said chamber during said first etching process and said second etching process. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the second gas is supplied into the chamber when the first reaction product is removed. 2. The method for manufacturing a semiconductor device according to claim 1, wherein control of the change in pressure of said first gas is synchronized with control of the change in high frequency power applied to the interior of said chamber. forming a recess in the workpiece layer during the first etching process;
6. The method for manufacturing a semiconductor device according to claim 5, wherein the bottom surface of the recess in the processed layer is etched during the second etching process. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first gas includes helium (He), hydrogen (H), nitrogen (N), neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe). After controlling the pressure of the first gas to the second pressure, a third gas having a lower thermal conductivity than the first gas is supplied between the holder and the substrate so as to be in contact with the substrate, in place of the first gas;
After the first reaction product is removed, the first gas is supplied in place of the third gas between the holder and the substrate so as to be in contact with the substrate;
2. The method for manufacturing a semiconductor device according to claim 1, wherein the pressure of said first gas is controlled to a third pressure higher than said second pressure. the temperature of the substrate during the first etching process is 60° C. or less;
2. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature of said substrate during said first reaction product removal is 100[deg.] C. or higher. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the following inequality holds when the time during which the pressure of the first gas is controlled to the second pressure is td (sec), the temperature of the holder during the first etching process is T (°C), the ratio of the area of the substrate to the sum of the area of the substrate and the area of the inner wall of the chamber is k, the high-frequency power applied to the inside of the chamber is Pw (W), the mass of the substrate is m (kg), and the specific heat capacity of the substrate is c (J/(kg °C)).
td≧(100-T)/{(k×Pw)/(m×c)}