JP7777412B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device and a manufacturing method thereof.

Patent Document 1 discloses a semiconductor device including a drift layer, a trench, a p-type region, and an anode electrode. The trench is formed in the surface of the drift layer. The p-type region is formed in the drift layer so as to cover the bottom wall and sidewall of the trench. The anode electrode covers the drift layer.

US Patent Application Publication No. 2013/105820

One embodiment provides a semiconductor device and a manufacturing method thereof that can improve electrical characteristics.

One embodiment provides a semiconductor device including: a chip having a main surface; a semiconductor region of a first conductivity type formed in the chip so as to be exposed from the main surface; a trench formed in the main surface and having sidewalls and a bottom wall; an impurity region of a second conductivity type formed in the semiconductor region only in a region along the bottom wall of the trench; and a main surface electrode covering the main surface and forming a Schottky junction with the semiconductor region.

One embodiment provides a method for manufacturing a semiconductor device, including the steps of: preparing a wafer having a main surface on which a semiconductor region of a first conductivity type is exposed; forming a trench having sidewalls and a bottom wall in the main surface by removing unnecessary portions of the wafer from the main surface side; forming an impurity region of a second conductivity type in the semiconductor region along only the bottom wall of the trench by introducing a second conductivity type impurity only into the bottom wall of the trench; and forming a main surface electrode on the main surface that forms a Schottky junction with the semiconductor region.

The above and other objects, features, and advantages will become apparent from the embodiments described below with reference to the accompanying drawings.

FIG. 1 is a perspective view showing a semiconductor device according to the first embodiment. FIG. 2 is a plan view showing the semiconductor device shown in FIG. FIG. 3 is a plan view showing an example of the layout of the first main surface of the chip shown in FIG. FIG. 4 is a cross-sectional view taken along line IV-IV shown in FIG. FIG. 5 is a cross-sectional view taken along line V-V shown in FIG. FIG. 6 is an enlarged view of region VI shown in FIG. FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. FIG. 8 is a graph showing the sufficiency of the target value of the reverse current IR and the target value of the forward voltage VF based on the relationship between the first value a and the second value b. FIG. 9 is a graph showing the sufficiency of the target value of the reverse current IR and the target value of the forward voltage VF based on the relationship between the third value c and the fourth value d. FIG. 10A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. FIG. 10B is a cross-sectional view showing a step subsequent to the step shown in FIG. 10A. FIG. 10C is a cross-sectional view showing a step subsequent to the step shown in FIG. 10B. FIG. 10D is a cross-sectional view showing a step subsequent to the step shown in FIG. 10C. FIG. 10E is a cross-sectional view showing a step subsequent to the step shown in FIG. 10D. FIG. 10F is a cross-sectional view showing a step subsequent to the step shown in FIG. 10E. FIG. 10G is a cross-sectional view showing a step subsequent to the step shown in FIG. 10F. FIG. 10H is a cross-sectional view showing a step subsequent to the step shown in FIG. 10G. FIG. 10I is a cross-sectional view showing a step subsequent to the step shown in FIG. 10H. FIG. 10J is a cross-sectional view showing a step subsequent to the step shown in FIG. 10I. FIG. 11 is a perspective view showing the inside of a package in which the semiconductor device shown in FIG. 1 is mounted. FIG. 12 is a perspective view showing a semiconductor device according to the second embodiment. FIG. 13 is a plan view showing the semiconductor device shown in FIG. FIG. 14 is a plan view showing an example of the layout of the first main surface of the chip shown in FIG. FIG. 15 is a plan view showing an example of the layout of first polarity electrodes and second polarity electrodes. 16 is a cross-sectional view taken along line XVI-XVI shown in FIG. 13. FIG. FIG. 17 is a plan view showing an example of the layout of outer trenches according to a modified example. FIG. 18 is a plan view showing an example of the layout of trenches according to the first modification. FIG. 19 is a plan view showing an example of the layout of trenches according to the second modification.

Embodiments will now be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams, are not strictly illustrative, and are not necessarily drawn to scale. Corresponding structures between the accompanying drawings are designated by the same reference numerals, and duplicate descriptions have been omitted or simplified. For structures whose descriptions have been omitted or simplified, the descriptions given before the omission or simplification apply.

Figure 1 is a perspective view showing a semiconductor device 1A according to the first embodiment. Figure 2 is a plan view showing the semiconductor device 1A shown in Figure 1. Figure 3 is a plan view showing an example layout of the first main surface 3 of the chip 2 shown in Figure 1. Figure 4 is a cross-sectional view taken along line IV-IV shown in Figure 3. Figure 5 is a cross-sectional view taken along line V-V shown in Figure 3. Figure 6 is an enlarged view of region VI shown in Figure 3. Figure 7 is a cross-sectional view taken along line VII-VII shown in Figure 6.

Referring to Figures 1 to 7, semiconductor device 1A is a semiconductor rectifying device equipped with an SBD (Schottky Barrier Diode). Semiconductor device 1A includes a hexahedral (specifically, rectangular) chip 2. Chip 2 is made of single crystal silicon (Si) or a single crystal wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a bandgap higher than that of Si. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and diamond (C). In this embodiment, chip 2 is made of a Si chip.

The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view"). The first main surface 3 is a device-forming surface. The second main surface 4 is a non-device-forming surface. The second main surface 4 may be a ground surface having grinding marks.

The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X. The lengths of the first to fourth side surfaces 5A to 5D may be 0.5 mm or more and 2 mm or less.

The semiconductor device 1A includes an n-type (first conductivity type) first semiconductor region 6 formed in a surface layer portion on the first main surface 3 side of the chip 2. The first semiconductor region 6 is formed in a layer shape extending along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In other words, the first semiconductor region 6 forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 may have an n-type impurity concentration of 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less. The first semiconductor region 6 may have a thickness of 2 μm or more and 20 μm or less. In this embodiment, the first semiconductor region 6 is formed by an n-type epitaxial layer (Si epitaxial layer).

The semiconductor device 1A includes an n-type second semiconductor region 7 formed in the surface layer on the second main surface 4 side of the chip 2. The second semiconductor region 7 is formed in a layer extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In other words, the second semiconductor region 7 forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. The second semiconductor region 7 is electrically connected to the first semiconductor region 6 inside the chip 2.

The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6. The second semiconductor region 7 may have an n-type impurity concentration of 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less. The second semiconductor region 7 has a thickness greater than that of the first semiconductor region 6. The thickness of the second semiconductor region 7 may be 50 μm or more and 800 μm or less. In this embodiment, the second semiconductor region 7 is formed of an n-type semiconductor substrate (Si substrate).

The semiconductor device 1A includes an active region 8 defined on the first main surface 3. The active region 8 is a region in which an SBD is formed. The active region 8 is defined in an inner portion of the first main surface 3 (the center portion in this embodiment) and spaced apart from the periphery of the first main surface 3 in a plan view. In this embodiment, the active region 8 is defined in a rectangular shape having four sides extending along the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) in a plan view.

The semiconductor device 1A includes an outer region 9 defined on the first main surface 3. The outer region 9 is a region in which no SBD is formed. The outer region 9 is defined on the periphery of the first main surface 3. In this embodiment, the outer region 9 extends in a band shape along the periphery of the first main surface 3 in a plan view and is defined in the shape of a ring (specifically, a rectangular ring) surrounding the active region 8.

The semiconductor device 1A includes at least one trench 10 (in this embodiment, multiple trenches 10) formed in the first main surface 3 in the active region 8. The number of trenches 10 is arbitrary and is adjusted according to the planar area of the first main surface 3 (active region 8). The multiple trenches 10 are arranged at intervals in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y. In other words, the multiple trenches 10 are arranged in a stripe shape extending in the second direction Y in a plan view. Each of the multiple trenches 10 has one end on one side (the first side surface 5A side) and the other end on the other side (the second side surface 5B side) in the second direction Y.

The multiple trenches 10 are formed at intervals from the bottom of the first semiconductor region 6 (second semiconductor region 7) toward the first major surface 3 in a cross-sectional view, and each have sidewalls and bottom walls defined within the first semiconductor region 6. The multiple trenches 10 may each be formed in a tapered shape with an opening width that gradually decreases toward the bottom wall in a cross-sectional view. The multiple trenches 10 may each be formed in a vertical shape with an approximately constant opening width in a cross-sectional view. The corners of the bottom walls of the multiple trenches 10 are preferably curved. The opening corners of the multiple trenches 10 are also preferably curved.

Referring to Figures 6 and 7, the multiple trenches 10 are formed in a cross-sectional view at intervals of a first value a in the first direction X. The first value a may be 0.4 μm or more and 1.4 μm or less. The multiple trenches 10 each have a width in the first direction X of a second value b (b≦a) that is less than the first value a. The second value b may be 0.4 μm or more and 1.2 μm or less. Preferred numerical values for the first value a and the second value b will be described below.

The multiple trenches 10 each have a predetermined depth D. The depth D may be 0.2 μm or greater and 0.4 μm or less. The depth D is preferably 0.25 μm or greater and 0.35 μm or less. The multiple trenches 10 may each have an aspect ratio b/D of 1 or greater and 5 or less. The aspect ratio b/D is defined by the ratio of the second value b to the depth D. The aspect ratio b/D preferably exceeds 1. In other words, the multiple trenches 10 are preferably formed in a horizontally elongated shape extending along the first main surface 3 in a cross-sectional view perpendicular to the extension direction (stripe direction).

The semiconductor device 1A includes at least one outer trench 11 (in this embodiment, multiple outer trenches 11) formed on the first main surface 3 so as to define the active region 8 in the outer region 9. The multiple outer trenches 11 sandwich the group of multiple trenches 10 on both sides in the first direction X. The multiple outer trenches 11 are spaced apart from the group of multiple trenches 10 in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y.

In other words, the multiple outer trenches 11 are arranged in a stripe pattern extending in the second direction Y together with the multiple trenches 10 in a plan view. Each of the multiple outer trenches 11 has a length in the second direction Y that is approximately equal to that of the multiple trenches 10. In this configuration, the multiple outer trenches 11 can be considered to form the outermost trenches 10 of the multiple trenches 10. Each of the multiple outer trenches 11 has one end on one side (the first side surface 5A side) and the other end on the other side (the second side surface 5B side) in the second direction Y.

The multiple outer trenches 11 are formed at intervals from the bottom of the first semiconductor region 6 (second semiconductor region 7) toward the first major surface 3 in a cross-sectional view, and each has an inner wall, outer wall, and bottom wall defined within the first semiconductor region 6. The inner wall of the outer trench 11 is located on the active region 8 side. The outer wall of the outer trench 11 is located on the outer region 9 side. The bottom wall of the outer trench 11 connects the inner wall and outer wall.

The multiple outer trenches 11 may each be formed in a tapered shape with an opening width that gradually decreases toward the bottom wall in a cross-sectional view. The multiple outer trenches 11 may each be formed in a vertical shape with an approximately constant opening width in a cross-sectional view. The corners of the bottom walls of the multiple outer trenches 11 are preferably formed in a curved shape. Also, the corners of the openings of the multiple outer trenches 11 are preferably formed in a curved shape.

Referring to Figures 6 and 7, the outer trenches 11, like the trenches 10, are formed in a cross-sectional view at intervals of a first value a from adjacent trenches 10 in the first direction X. Also, like the trenches 10, the outer trenches 11 each have a width of a second value b (b≦a) that is less than the first value a. Like the trenches 10, the outer trenches 11 each have a predetermined depth D. In other words, the outer trenches 11 each have an aspect ratio b/D.

The semiconductor device 1A includes a plurality of p-type (second conductivity type) impurity regions 12 formed in the first semiconductor region 6 in regions along the bottom walls of the plurality of trenches 10. The plurality of impurity regions 12 may have a p-type impurity concentration of 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less. The plurality of impurity regions 12 are arranged at intervals in the first direction X in plan view, following the layout of the plurality of trenches 10, and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of impurity regions 12 are arranged in a strip shape extending in the second direction Y in plan view. Each of the plurality of impurity regions 12 extends in a strip shape across the entire area between one end and the other end of the corresponding trench 10 in the second direction Y.

The multiple impurity regions 12 are each formed only on the bottom wall of the corresponding trench 10, and not on the sidewall of that trench 10. As a result, the multiple impurity regions 12 are formed so that the first semiconductor region 6 is exposed from the entire sidewall of the corresponding trench 10. Specifically, the multiple impurity regions 12 are each formed at intervals inward from the sidewall of the corresponding trench 10, so that the first semiconductor region 6 is exposed from at least the corners of the bottom wall of the corresponding trench 10.

In this embodiment, the multiple impurity regions 12 are formed so as to expose the first semiconductor region 6 from the bottom wall corners and bottom wall peripheries of the corresponding trenches 10. In a cross-sectional view, the multiple impurity regions 12 are formed at intervals from the bottom of the first semiconductor region 6 (second semiconductor region 7) toward the first major surface 3. As a result, the multiple impurity regions 12 form pn junctions with the first semiconductor region 6.

The form in which the first semiconductor region 6 is exposed from the wall surface of the trench 10 includes a form in which the first semiconductor region 6 is not converted into a p-type semiconductor region by the p-type impurities introduced to form the impurity region 12. Therefore, the form in which the first semiconductor region 6 is exposed from the sidewall, bottom corners, and bottom periphery of the trench 10 includes a form in which an extremely small amount (extremely low concentration) of p-type impurities has diffused into at least one of the sidewall, bottom corners, and bottom periphery of the trench 10. In other words, the first semiconductor region 6 may include an n-type impurity region and a p-type impurity region having a p-type impurity concentration lower than the n-type impurity concentration of the n-type impurity region in a portion along at least one of the sidewall, bottom corners, and bottom periphery of the trench 10.

Referring to FIG. 7, each of the multiple impurity regions 12 has a concentration gradient in which the p-type impurity concentration gradually decreases from the inner portion toward the periphery. Specifically, each of the multiple impurity regions 12 includes a high-concentration region 13 on the inner side and a low-concentration region 14 on the periphery. In FIG. 7, the high-concentration region 13 is indicated by a dashed line. The high-concentration region 13 is exposed from the center of the bottom wall of the trench 10. The low-concentration region 14 is exposed from the periphery of the bottom wall of the trench 10 at a distance from the sidewall of the trench 10.

The multiple impurity regions 12 are formed in regions along the bottom walls of the multiple trenches 10, spaced apart in the first direction X in a cross-sectional view at intervals of a third value c (a≦c) that is equal to or greater than the first value a. The third value c may be 0.4 μm or greater and 1.6 μm or less. The first difference value c−a between the third value c and the first value a is preferably 0 μm or greater and 0.6 μm or less. The first difference value c−a is preferably 0.2 μm or greater.

The multiple impurity regions 12 each have a width in the first direction X of a fourth value d (b≦d) that is less than or equal to the second value b. The fourth value d may be 0.35 μm or greater and 1.2 μm or less. The second difference value b−d between the second value b and the fourth value d is preferably 0 μm or greater and 0.6 μm or less. The second difference value b−d is preferably 0.2 μm or greater. The second difference value b−d is approximately equal to the first difference value c−a.

The semiconductor device 1A includes outer impurity regions 15 formed in the first semiconductor region 6 so as to define the active region 8 in the outer region 9. The plurality of outer impurity regions 15 may have a p-type impurity concentration of 1×10 ¹⁶ cm ⁻³ or more and 1×10 ¹⁸ cm ⁻³ or less. The outer impurity region 15 preferably has a p-type impurity concentration substantially equal to that of the plurality of impurity regions 12. The outer impurity region 15 is formed in a ring shape surrounding the active region 8 (the plurality of trenches 10 and the plurality of outer trenches 11) in a plan view.

Specifically, the outer impurity region 15 includes a plurality of first outer impurity regions 16 and a plurality of second outer impurity regions 17. The plurality of first outer impurity regions 16 are each formed in a band shape extending along the corresponding outer trench 11 in a plan view. The plurality of first outer impurity regions 16 extend in a band shape across the entire area between one end and the other end of the corresponding outer trench 11 in the second direction Y.

The multiple first outer impurity regions 16 are each formed in a region along the outer wall and bottom wall of the corresponding outer trench 11 so as to expose the entire inner wall of the outer trench 11. Specifically, the multiple first outer impurity regions 16 are each formed at intervals from the inner wall of the outer trench 11 toward the outer region 9 so as to expose the first semiconductor region 6 from the inner wall corners of the inner wall and bottom wall of the corresponding outer trench 11.

In this embodiment, the multiple first outer impurity regions 16 expose the first semiconductor region 6 from the inner wall corners and bottom wall periphery of the bottom wall of the corresponding outer trench 11. The multiple first outer impurity regions 16 extend from the outer walls of the corresponding outer trenches 11 toward the periphery of the first major surface 3 and are exposed from the first major surface 3. The multiple first outer impurity regions 16 are formed at intervals inward from the periphery of the first major surface 3. The multiple first outer impurity regions 16 are formed at intervals from the bottom of the first semiconductor region 6 (second semiconductor region 7) toward the first major surface 3 in a cross-sectional view. As a result, the multiple first outer impurity regions 16 form pn junctions with the first semiconductor region 6.

The multiple first outer impurity regions 16 are each formed in a region along the bottom wall of the corresponding outer trench 11, spaced apart from the adjacent impurity region 12 in a cross-sectional view by a third value c (a≦c) that is equal to or greater than the first value a. The multiple first outer impurity regions 16 each have a width in the first direction X that is a fifth value e (d<e) that exceeds the fourth value d of the impurity region 12. The fifth value e exceeds the second value b of the trench 10 (b<e). The fifth value e may be 5 μm or greater and 25 μm or less.

The multiple second outer impurity regions 17 are formed in the first semiconductor region 6 in the regions between the multiple first outer impurity regions 16, sandwiching the group of multiple trenches 10 from both sides in the second direction Y. The multiple second outer impurity regions 17 are each formed in a strip shape extending in the first direction X.

Specifically, one second outer impurity region 17 extends in a band-like manner in the first direction X so as to connect one ends of the multiple first outer impurity regions 16 together, and covers one ends of the multiple trenches 10 and one ends of the multiple outer trenches 11. The other second outer impurity region 17 extends in a band-like manner in the first direction X so as to connect the other ends of the multiple first outer impurity regions 16 together, and covers the other ends of the multiple trenches 10 and the other ends of the multiple outer trenches 11.

The multiple second outer impurity regions 17 cover the sidewalls and bottom walls of the multiple trenches 10 at both ends of the multiple trenches 10 and are connected to the multiple impurity regions 12. The multiple second outer impurity regions 17 cover the inner walls, outer walls, and bottom walls of the multiple outer trenches 11 at both ends of the multiple outer trenches 11 and are connected to the multiple first outer impurity regions 16. The multiple second outer impurity regions 17, together with the multiple first outer impurity regions 16, form a single annular outer impurity region 15.

The multiple second outer impurity regions 17 are formed at intervals from the bottom of the first semiconductor region 6 (second semiconductor region 7) toward the first major surface 3 in a cross-sectional view. This allows the outer impurity region 15 to form a pn junction with the first semiconductor region 6. Like the first outer impurity region 16, the multiple second outer impurity regions 17 each have a width of a fifth value e (d<e) that exceeds the fourth value d of the impurity region 12 in a cross-sectional view.

The semiconductor device 1A includes an insulating film 20 that selectively covers the first main surface 3. The insulating film 20 has wall portions 22 that define contact openings 21 that expose the first main surface 3 on the active region 8 side, and covers the first main surface 3 on the outer region 9 side. The wall portions 22 are formed at intervals from the multiple trenches 10 and multiple outer trenches 11 toward the periphery of the first main surface 3 so as to expose at least a portion of the outer impurity region 15.

In this embodiment, the wall portion 22 is located directly above the outer impurity region 15. The wall portion 22 exposes a portion of the outer impurity region 15 (a plurality of second outer impurity regions 17) between the wall portion 22 and the sidewalls of the plurality of trenches 10, and exposes a portion of the outer impurity region 15 (a plurality of first outer impurity regions 16) between the wall portion 22 and the outer walls of the plurality of outer trenches 11. As a result, the contact opening 21 covers a portion (outer edge) of the outer impurity region 15, and exposes the entire areas of the plurality of trenches 10, the entire areas of the plurality of outer trenches 11, and a portion (inner edge) of the outer impurity region 15.

In this embodiment, the insulating film 20 has a layered structure including a first insulating film 23 and a second insulating film 24 stacked in this order from the first main surface 3 side. The insulating film 20 does not necessarily have to have a layered structure including the first insulating film 23 and the second insulating film 24. The insulating film 20 may have, for example, a single-layer structure consisting of either the first insulating film 23 or the second insulating film 24.

The first insulating film 23 is preferably made of an insulating film 20 having a relatively high density. The first insulating film 23 may include a silicon oxide film. The first insulating film 23 preferably includes an oxide film made of an oxide of the chip 2. The first insulating film 23 may have a thickness of 10 nm or more and 1000 nm or less. The first insulating film 23 preferably has a thickness of 50 nm or more and 500 nm or less.

The second insulating film 24 is preferably made of an insulating film 20 having a lower density than the first insulating film 23. The second insulating film 24 may also include a silicon oxide film having properties different from those of the first insulating film 23. The second insulating film 24 may include at least one of a PSG (phosphorus silicate glass) film, a BPSG (boron and phosphorus silicate glass) film, a USG (undoped silicate glass) film, and a TEOS (tetraethyl orthosilicate) film. In this embodiment, the second insulating film 24 is made of a PSG film. The second insulating film 24 is thicker than the first insulating film 23. The second insulating film 24 may have a thickness of 100 nm or more and 1500 nm or less. The second insulating film 24 is preferably made of a PSG film.

The semiconductor device 1A includes a first polarity electrode 25 (first principal surface electrode) formed on the first principal surface 3. The first polarity electrode 25 is an anode electrode (Schottky electrode) of the SBD. The first polarity electrode 25 covers the first principal surface 3 in the active region 8 and forms a Schottky junction with the first semiconductor region 6. The first polarity electrode 25 extends from the first principal surface 3 into multiple trenches 10.

The first polarity electrode 25 is electrically connected to the impurity region 12 at the bottom wall of each trench 10 and forms a Schottky junction with the first semiconductor region 6 at the side wall of each trench 10. In this embodiment, the first polarity electrode 25 includes a portion that forms a Schottky junction with the first semiconductor region 6 at the bottom wall of each trench 10.

Specifically, the first polarity electrode 25 forms a Schottky junction with the first semiconductor region 6 at the bottom wall corners and bottom wall periphery of each trench 10. In other words, even if the first semiconductor region 6 contains a trace amount of p-type impurities in a portion along at least one of the sidewall, bottom wall corners, and bottom wall periphery of each trench 10, the first polarity electrode 25 forms a Schottky junction with the first semiconductor region 6 at the sidewall, bottom wall corners, and bottom wall periphery of each trench 10.

The first polarity electrode 25 is electrically connected to the outer impurity region 15 at both ends of each trench 10. The first polarity electrode 25 further extends from the first major surface 3 into the multiple outer trenches 11. The first polarity electrode 25 is electrically connected to the outer impurity region 15 at the outer wall and bottom wall of each outer trench 11, and forms a Schottky junction with the first semiconductor region 6 at the inner wall of each outer trench 11. In this embodiment, the first polarity electrode 25 includes a portion that forms a Schottky junction with the first semiconductor region 6 at the bottom wall of each outer trench 11. Specifically, the first polarity electrode 25 forms a Schottky junction with the first semiconductor region 6 at the inner corners and peripheral edge of the bottom wall of each outer trench 11.

The first polarity electrode 25 includes an extension 26 that extends from above the first major surface 3, via the wall 22, onto the insulating film 20. The extension 26 faces the outer impurity region 15 across the insulating film 20. The extension 26 may extend to a region outside the outer impurity region 15 in plan view. The extension 26 is formed at a distance from the periphery of the first major surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8.

In this embodiment, the first polarity electrode 25 has a layered structure including a first electrode film 27, a second electrode film 28, and a third electrode film 29, which are layered in this order from the chip 2 side. The first electrode film 27 is formed in the form of a film along the first main surface 3, the wall surfaces of the multiple trenches 10, the wall surfaces of the multiple outer trenches 11, and the outer surface of the insulating film 20. The first electrode film 27 defines a recess space within each trench 10 and defines a recess space within each outer trench 11.

The first electrode film 27 is made of a Schottky barrier electrode film. The first electrode film 27 may contain at least one metal species selected from the group consisting of magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt), and gold (Au).

The electrode material of the first electrode film 27 is arbitrary as long as a Schottky junction is formed. The first electrode film 27 may be made of an alloy film containing at least one of the above metal species. In this embodiment, the first electrode film 27 has a single-layer structure made of a Ti film. The first electrode film 27 may have a thickness of 10 nm or more and 100 nm or less. It is preferable that the first electrode film 27 have a thickness of 50 nm or more and 500 nm or less.

The second electrode film 28 is formed in the form of a film along the first electrode film 27. The second electrode film 28 covers the wall surface of each trench 10, sandwiching the first electrode film 27 between them within each trench 10, and covers the wall surface of each outer trench 11, sandwiching the first electrode film 27 between them within each outer trench 11. The second electrode film 28 defines a recess space within each trench 10, and defines a recess space within each outer trench 11.

The second electrode film 28 is made of a barrier film. In this embodiment, the second electrode film 28 is made of a TiN film. The second electrode film 28 is thicker than the first electrode film 27. The second electrode film 28 may have a thickness of 10 nm or more and 1000 nm or less. The second electrode film 28 may have a thickness of 50 nm or more and 750 nm or less.

The third electrode film 29 is formed in the form of a film along the second electrode film 28. The third electrode film 29 backfills the multiple recess spaces defined by the second electrode film 28 in each trench 10 and each outer trench 11. The third electrode film 29 covers the wall surfaces of each trench 10, sandwiching the first electrode film 27 and the second electrode film 28 within each trench 10, and covers the wall surfaces of each outer trench 11, sandwiching the first electrode film 27 and the second electrode film 28 within each outer trench 11.

The third electrode film 29 is made of a Cu-based metal film or an Al-based metal film. The third electrode film 29 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the third electrode film 29 is made of an AlCu alloy film. The third electrode film 29 is thicker than the second electrode film 28. The third electrode film 29 may have a thickness of 0.5 μm or more and 10 μm or less. The thickness of the third electrode film 29 is preferably 3 μm or more and 5 μm or less.

In this way, an SBD structure 30 (Schottky junction) is formed in the active region 8, having the first polarity electrode 25 as the anode and the first semiconductor region 6 (second semiconductor region 7) as the cathode.

The semiconductor device 1A includes a silicide layer 31 formed at the connection portion of the chip 2 with the first polarity electrode 25. Specifically, the silicide layer 31 is formed at the connection portion of the chip 2 and the first electrode film 27. That is, in this embodiment, the silicide layer 31 includes Ti silicide. The silicide layer 31 is formed in the form of a film along the first main surface 3, the wall surfaces of the multiple trenches 10, and the wall surfaces of the multiple outer trenches 11.

The semiconductor device 1A includes an upper insulating film 35 that covers the peripheral edge of the first polarity electrode 25. In this embodiment, the upper insulating film 35 has a single-layer structure made of an inorganic insulating film. The upper insulating film 35 is preferably made of an insulator different from the insulating film 20. The upper insulating film 35 preferably includes at least one of a silicon nitride film and a silicon oxynitride film. In this embodiment, the upper insulating film 35 has a single-layer structure made of a silicon nitride film.

The upper insulating film 35 is formed in a film shape along the insulating film 20 and the first polarity electrode 25, and has a pad opening 36 that exposes the center of the first polarity electrode 25. In this embodiment, the pad opening 36 is formed in a rectangular shape with four sides parallel to the periphery of the first main surface 3. The upper insulating film 35 is preferably thicker than the insulating film 20. The upper insulating film 35 is preferably thinner than the first polarity electrode 25. The upper insulating film 35 may have a thickness of 0.5 μm or more and 5 μm or less. The thickness of the upper insulating film 35 is preferably 1 μm or more and 3 μm or less.

The upper insulating film 35 may have a layered structure including an organic insulating film layered on the inorganic insulating film. In this case, the organic insulating film may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. The thickness of the organic insulating film may be 1 μm or more and 20 μm or less.

The semiconductor device 1A includes a second polarity electrode 37 (second main surface electrode) that covers the second main surface 4 of the chip 2. The second polarity electrode 37 is the cathode electrode of the SBD. In other words, the semiconductor device 1A includes a vertical type SBD. The second polarity electrode 37 covers the entire second main surface 4 and forms ohmic contact with the second main surface 4 (second semiconductor region 7).

In this embodiment, the second polarity electrode 37 has a layered structure including a Ti film 37a, a Ni film 37b, and an Ag film 37c, layered in this order from the second main surface 4 side. The Ti film 37a may have a thickness of 10 nm or more and 500 nm or less. The Ni film 37b may have a thickness of 100 nm or more and 500 nm or less. The Ag film 37c is thicker than the Ni film 37b. The Ag film 37c may have a thickness of 500 nm or more and 1500 nm or less.

As described above, the semiconductor device 1A includes a chip 2, a first semiconductor region 6, a trench 10, an impurity region 12, and a first polarity electrode 25 (main surface electrode). The chip 2 has a first main surface 3. The first semiconductor region 6 is formed within the chip 2 so as to be exposed from the first main surface 3. The trench 10 is formed in the first main surface 3 and has sidewalls and a bottom wall. The impurity region 12 is formed within the first semiconductor region 6 in a region along the bottom wall of the trench 10 so as to expose the entire sidewall of the trench 10. The first polarity electrode 25 covers the first main surface 3 and forms a Schottky junction with the first semiconductor region 6.

This structure makes it possible to provide a semiconductor device 1A with improved electrical characteristics. Specifically, by adjusting the layout of the trenches 10 and the layout of the impurity regions 12, it is possible to provide a semiconductor device 1A with improved forward voltage VF and reverse current IR characteristics, which are examples of electrical characteristics. As an example, the forward voltage VF and reverse current IR characteristics are adjusted by adjusting the first value a, second value b, third value c, and fourth value d, as shown in Figures 8 and 9.

Figure 8 is a graph showing the sufficiency of the target value of reverse current IR and the target value of forward voltage VF based on the relationship between first value a and second value b (see Figures 6 and 7). The target value of reverse current IR is defined by the reverse current IR generated at the Schottky junction when a reverse voltage VR of 3 V is applied to the Schottky junction in a temperature environment of 125°C. The target value of reverse current IR is 10 mA or less. The target value of forward voltage VF is defined by the forward voltage VF generated at the Schottky junction when a forward current IF of 7.5 mA is applied to the Schottky junction in a temperature environment of -40°C. The target value of forward voltage VF is 300 mV or less.

Figure 8 shows multiple black plot points and multiple white plot points. The multiple black plot points indicate conditions where the target value for reverse current IR was met, but the target value for forward voltage VF was not met. The multiple white plot points indicate conditions where both the target value for reverse current IR and the target value for forward voltage VF were met.

Referring to Figure 8, the forward voltage VF characteristics and reverse current IR characteristics tend to improve as the first value a increases and the second value b decreases. Furthermore, the forward voltage VF characteristics and reverse current IR characteristics tend to improve as the first value a decreases and the second value b increases.

The first value a is preferably 0.4 μm or greater. The second value b is preferably 0.6 μm or greater. When these conditions are met, at least the target value of reverse current IR can be met. It is particularly preferable that the first value a be 0.6 μm or greater. In this case, by adjusting the second value b, both the target value of reverse current IR and the target value of forward voltage VF can be met. The first value a may be 1.4 μm or less. The first value a may be 1.2 μm or less. The second value b may be 1.2 μm or less. The second value b may be 1.0 μm or less.

It is preferable that the first value a and the second value b satisfy the relationship "a > -b + 1.4." In this case, it is preferable that the second value b falls within the range of 0.6 μm or greater and 1.0 μm (0.6≦b≦1.0). When these conditions are met, the likelihood of meeting both the target value of reverse current IR and the target value of forward voltage VF can be increased. In this case, it is particularly preferable that the first value a and the second value b satisfy the relationship "a ≧ -b + 1.6." When this condition is met, it is possible to meet both the target value of reverse current IR and the target value of forward voltage VF.

The first value a and the second value b may satisfy the relationship "a≦-b+1.8". In other words, the first value a and the second value b may satisfy both the relationship "a>-b+1.4" and the relationship "a≦-b+1.8". It is preferable that the first value a and the second value b satisfy both the relationship "a≧-b+1.6" and the relationship "a≦-b+1.8".

Figure 9 is a graph showing the sufficiency of the target value of reverse current IR and the target value of forward voltage VF based on the relationship between the third value c and the fourth value d (see Figures 6 and 7). As mentioned above, the target value of forward voltage VF is 300 mV or less. As mentioned above, the target value of reverse current IR is 10 mA or less.

Figure 9 shows multiple black plot points and multiple white plot points. The multiple black plot points indicate conditions where the target value for reverse current IR was met, but the target value for forward voltage VF was not met. The multiple white plot points indicate conditions where both the target value for reverse current IR and the target value for forward voltage VF were met.

Referring to Figure 9, the larger the third value c and the larger the fourth value d, the more the forward voltage VF characteristics and reverse current IR characteristics tend to improve. The third value c is preferably 0.6 μm or greater. Furthermore, the fourth value d is preferably 0.35 μm or greater. If these conditions are met, at least the target value for reverse current IR can be met. It is particularly preferable that the third value c be 1.2 μm or greater.

When this condition is met, both the target value of reverse current IR and the target value of forward voltage VF can be met. The third value c may be 1.6 μm or less. The third value c may be 1.4 μm or less. The fourth value d may be 0.6 μm or less. The fourth value d may be 0.5 μm or less.

Examples of preferred numerical ranges for the first to third values a, b, and c extracted from the graphs of Figures 8 and 9 are shown below. The first value a is preferably 0.6 μm or greater and 1.2 μm or less. The second value b is preferably 0.6 μm or greater and 1.0 μm or less. The third value c is preferably 1.2 μm or greater and 1.4 μm or less. The fourth value d is preferably 0.35 μm or greater and 0.5 μm or less.

Under these conditions, the reverse current IR and forward voltage VF characteristics can be appropriately improved. As an example, when a reverse voltage VR of 3 V is applied to the Schottky junction in a temperature environment of 125°C, a reverse current IR of 10 mA or less can be achieved. Furthermore, when a forward current IF of 7.5 mA is applied to the Schottky junction in a temperature environment of -40°C, a forward voltage VF of 300 mV or less can be achieved.

In these cases, it is preferable that the first value a and the second value b satisfy the relationship "a > -b + 1.4." In this case, it is preferable that the second value b be in the range of 0.6 μm or greater and 1.0 μm (0.6≦b≦1.0). It is particularly preferable that the first value a and the second value b satisfy the relationship "a ≧ -b + 1.6." These conditions allow for more appropriate improvements in the reverse current IR and forward voltage VF characteristics.

Figures 10A to 10J are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1A shown in Figure 1. Figures 10A to 10J are cross-sectional views of the region corresponding to Figure 7. Referring to Figure 10A, a disk-shaped wafer 40 is prepared. The wafer 40 has a wafer main surface 41. The wafer 40 includes a first semiconductor region 6 and a second semiconductor region 7. In this form, the second semiconductor region 7 is made of an n-type base wafer that forms the main body of the wafer 40.

In this embodiment, the first semiconductor region 6 is composed of an n-type epitaxial layer deposited on the second semiconductor region 7 (base wafer) by epitaxial growth, and is exposed from the wafer main surface 41. Next, a hard mask 42 is formed to cover the wafer main surface 41 in a film-like manner. The hard mask 42 may be formed by oxidation (for example, thermal oxidation) or CVD (Chemical Vapor Deposition).

Next, referring to FIG. 10B, a first resist mask 43 having a predetermined pattern is formed on the hard mask 42. The first resist mask 43 exposes the regions where the trenches 10 and outer trenches 11 will be formed, and covers the remaining regions. Next, unnecessary portions of the hard mask 42 are removed by etching through the first resist mask 43. The etching method may be wet etching and/or dry etching. This forms multiple openings in the hard mask 42 that expose the regions where the trenches 10 and outer trenches 11 will be formed. The first resist mask 43 is then removed.

Next, referring to FIG. 10C , unnecessary portions of the wafer 40 are removed from the wafer main surface 41 side by etching via the hard mask 42. The etching method may be wet etching and/or dry etching. The unnecessary portions of the wafer 40 are removed up to the middle of the depth direction of the first semiconductor region 6. As a result, a plurality of trenches 10 exposing the first semiconductor region 6 and a plurality of outer trenches 11 exposing the first semiconductor region 6 are formed in the wafer main surface 41.

Next, referring to FIG. 10D, a first insulating film 23 is formed on the wafer main surface 41. The first insulating film 23 may be formed by an oxidation process (e.g., a thermal oxidation process). The first insulating film 23 is formed in the form of a film along the wafer main surface 41, the wall surfaces of the multiple trenches 10, and the wall surfaces of the multiple outer trenches 11.

Next, referring to FIG. 10E, a second resist mask 44 (shielding mask) having a predetermined pattern is formed on the first insulating film 23. The second resist mask 44 exposes the regions where the multiple impurity regions 12 will be formed and the regions where the outer impurity regions 15 (first outer impurity regions 16 and second outer impurity regions 17) will be formed, and covers the remaining regions. Specifically, the second resist mask 44 covers the sidewalls of the multiple trenches 10 and exposes the bottom walls of the multiple trenches 10. It is preferable that the second resist mask 44 cover the corners and peripheral edges of the bottom walls of the multiple trenches 10.

The second resist mask 44 also covers the inner walls of the outer trenches 11, exposing the outer walls and bottom walls of the outer trenches 11 along with a portion of the wafer main surface 41. It is preferable that the second resist mask 44 covers the inner corners and periphery of the bottom walls of the outer trenches 11. The second resist mask 44 exposes the side walls and bottom walls of the trenches 10 at both ends of the trenches 10. The second resist mask 44 also exposes the inner walls, outer walls, and bottom walls of the outer trenches 11 at both ends of the trenches 11.

Next, p-type impurities (such as boron, an example of a trivalent element) are introduced into the first semiconductor region 6 by ion implantation via the second resist mask 44. In this embodiment, the p-type impurities are introduced into the first semiconductor region 6 via the first insulating film 23. This forms a plurality of first impurity diffusion starting points 45 that form the bases of the plurality of impurity regions 12, and a second impurity diffusion starting point 46 that forms the bases of the outer impurity regions 15 (first outer impurity region 16 and second outer impurity region 17). The second resist mask 44 is then removed.

Next, referring to FIG. 10F, a heat treatment (drive-in treatment) is performed on the wafer 40 to diffuse p-type impurities into the first semiconductor region 6 from the first impurity diffusion starting points 45 and the second impurity diffusion starting points 46. This process includes heating the wafer 40 under heating conditions (i.e., heating temperature and heating time) that prevent the multiple impurity regions 12 from reaching the sidewalls of the multiple trenches 10. The heating conditions include conditions that prevent the outer impurity region 15 from reaching the inner wall of the outer trench 11. This results in the formation of multiple impurity regions 12 having a predetermined layout and outer impurity region 15 having a predetermined layout (see also FIGS. 6 to 9).

Next, referring to FIG. 10G, a second insulating film 24 is formed on the first insulating film 23. The second insulating film 24 may be formed by a CVD method. The second insulating film 24 fills the multiple trenches 10 and the multiple outer trenches 11 and covers the entire wafer main surface 41. This forms an insulating film 20 including the first insulating film 23 and the second insulating film 24. Before the step of forming the second insulating film 24, a step of thickening the first insulating film 23 by an oxidation treatment (e.g., a thermal oxidation treatment) may be performed.

Next, referring to FIG. 10H, a third resist mask 47 having a predetermined pattern is formed on the insulating film 20. The third resist mask 47 exposes the regions where the contact openings 21 are to be formed and covers the remaining regions. Next, unnecessary portions of the insulating film 20 are removed by etching through the third resist mask 47. The etching method may be wet etching and/or dry etching. As a result, the contact openings 21 are formed in the insulating film 20. The third resist mask 47 is then removed.

Next, referring to FIG. 10I, a first electrode film 27 is formed on the wafer main surface 41. In this embodiment, the first electrode film 27 is made of a Ti film. The first electrode film 27 may be formed by sputtering or vapor deposition. Next, a heat treatment method (e.g., RTA (Rapid Thermal Annealing)) is performed on the wafer 40 to form a silicide layer 31 at the connection portion between the wafer 40 and the first electrode film 27.

Next, referring to FIG. 10J, the second electrode film 28 is formed on the first electrode film 27. In this embodiment, the second electrode film 28 is made of a TiN film. The second electrode film 28 may be formed by sputtering or vapor deposition. Next, the third electrode film 29 is formed on the second electrode film 28. In this embodiment, the third electrode film 29 is made of an AlCu film. The third electrode film 29 may be formed by sputtering or vapor deposition. Next, unnecessary portions of the first to third electrode films 27 to 29 are removed to form the first polarity electrode 25. Thereafter, the upper insulating film 35 and the second polarity electrode 37 are formed, and the wafer 40 is cut. The semiconductor device 1A is manufactured through the processes described above.

Figure 11 is a transparent perspective view of the interior of a package 50 equipped with the semiconductor device 1A shown in Figure 1. Referring to Figure 11, the package 50 includes a package body 51, pads 52, a first terminal 53, a second terminal 54, the semiconductor device 1A, a conductive bonding material 55, and at least one conductor 56 (one in this embodiment).

The package body 51 contains molded resin and is molded into a roughly hexahedral shape (roughly rectangular parallelepiped shape). The package body 51 has a first surface 57 on one side, a second surface 58 on the other side, and first to fourth side walls 59A to 59D connecting the first surface 57 and the second surface 58.

The first surface 57 and the second surface 58 are formed into a rectangular shape in a plan view. The first side wall 59A and the second side wall 59B extend in one direction (the first direction X in this embodiment) and face each other in an intersecting direction (the second direction Y in this embodiment) that intersects (specifically, is perpendicular to) the one direction. The first side wall 59A and the second side wall 59B form the short sides of the package body 51. The third side wall 59C and the fourth side wall 59D extend in the intersecting direction (the second direction Y) and face each other in one direction (the first direction X). The third side wall 59C and the fourth side wall 59D form the long sides of the package body 51.

The pad portion 52 is made of a metal plate-shaped member. The pad portion 52 is formed in a rectangular shape when viewed from above. In this embodiment, the pad portion 52 is disposed within the package body 51 so as to be exposed from the second surface 58.

The first terminal 53 is made of a metal plate-shaped member. The first terminal 53 is an anode terminal. The first terminal 53 extends from inside the package body 51 through the first side wall 59A and is pulled out to the outside of the package body 51. The first terminal 53 has a first inner end 60 inside the package body 51 and a first outer end 61 outside the package body 51. The first inner end 60 is formed at a distance from the pad 52. The first terminal 53 has multiple (a pair in this embodiment) recesses 62 recessed in the first direction X in a pair of side wall portions of the first inner end 60 extending along the second direction Y. The multiple recesses 62 engage with the package body 51 (i.e., the molded resin) within the package body 51.

The second terminal 54 is made of a metal plate-shaped member. The second terminal 54 is a cathode terminal. The second terminal 54 extends from inside the package body 51 through the second side wall 59B to the outside of the package body 51. The second terminal 54 has a second inner end 63 inside the package body 51 and a second outer end 64 outside the package body 51. In this embodiment, the second inner end 63 is connected to the pad 52. Specifically, the second inner end 63 is formed integrally with the pad 52.

The semiconductor device 1A is disposed within the package body 51 on the pad portion 52 with the second polarity electrode 37 facing the pad portion 52. In other words, the second polarity electrode 37 is electrically connected to the second terminal portion 54 via the pad portion 52. A conductive bonding material 55 is interposed between the second polarity electrode 37 and the pad portion 52, mechanically and electrically bonding the second polarity electrode 37 and the pad portion 52. The conductive bonding material 55 may be solder or a metal paste.

The conductor 56 is connected to the first polarity electrode 25 of the semiconductor device 1A and the first inner end 60 of the first terminal 53 within the package body 51. In other words, the first polarity electrode 25 is electrically connected to the first terminal 53 via the conductor 56. In this embodiment, the conductor 56 is made of a bonding wire. The conductor 56 may include at least one of an Au wire, a Cu wire, an Ag wire, and an Al wire. Instead of a bonding wire, the conductor 56 may be made of a metal clip (a metal plate-shaped member).

Figure 12 is a perspective view showing a semiconductor device 1B according to the second embodiment. Figure 13 is a plan view showing the semiconductor device 1B shown in Figure 12. Figure 14 is a plan view showing an example layout of the first main surface 3 of the chip 2 shown in Figure 12. Figure 15 is a plan view showing an example layout of the first polarity electrodes 25 and the second polarity electrodes 37. Figure 16 is a cross-sectional view taken along line XVI-XVI shown in Figure 13.

Referring to Figures 12 to 16, semiconductor device 1B, like semiconductor device 1A, includes a chip 2, a first semiconductor region 6, and a second semiconductor region 7. Description of the first semiconductor region 6 and the second semiconductor region 7 is omitted. Chip 2 has a first main surface 3, a second main surface 4, and first to fourth side surfaces 5A to 5D. In this embodiment, the first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view. The first side surface 5A and the second side surface 5B form the long sides of chip 2. The third side surface 5C and the fourth side surface 5D form the short sides of chip 2.

The length of the first side surface 5A and the second side surface 5B may be 0.2 mm or more and 4 mm or less. The length of the third side surface 5C and the fourth side surface 5D may be 0.1 mm or more and 2 mm or less. Depending on the size of the chip 2 (the length of the first to fourth sides 5A to 5D), the semiconductor device 1B is referred to as a 1608 (1.6 mm x 0.8 mm) chip, a 1006 (1.0 mm x 0.6 mm) chip, a 0603 (0.6 mm x 0.3 mm) chip, a 0402 (0.4 mm x 0.2 mm) chip, a 03015 (0.3 mm x 0.15 mm) chip, or the like. In other words, the semiconductor device 1B is a chip component consisting of a wafer-level chip-size package whose package size is the same as the size of the chip 2 cut from the wafer 40.

Similar to semiconductor device 1A, semiconductor device 1B includes an active region 8 defined on the first main surface 3. In this embodiment, the active region 8 includes a first active region 8A and a second active region 8B. The first active region 8A is defined in an area on the third side surface 5C of the first main surface 3, spaced from the periphery of the first main surface 3. In this embodiment, the first active region 8A is defined in a quadrilateral shape (specifically, a rectangular shape extending in the second direction Y) with four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

The second active region 8B is set in the inner portion (specifically, the center portion) of the first main surface 3, spaced from the periphery of the first main surface 3, and faces the first active region 8A in the first direction X. In this embodiment, the second active region 8B is set in a rectangular shape with four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. The second active region 8B has a length in the second direction Y that is shorter than the length of the first active region 8A.

Similar to semiconductor device 1A, semiconductor device 1B includes an outer region 9 defined on the first main surface 3. The outer region 9 is defined on the periphery of the first main surface 3. In this embodiment, the outer region 9 extends along the periphery of the first main surface 3 in a plan view and is defined in an annular shape surrounding the first active region 8A and the second active region 8B.

The semiconductor device 1B includes an n-type diode region 70 formed in the surface layer portion of the first main surface 3 in the first active region 8A. In this embodiment, the diode region 70 is formed using a portion of the first semiconductor region 6. That is, the diode region 70 has the same n-type impurity concentration as the first semiconductor region 6 and is exposed from the first main surface 3. Of course, the diode region 70 may be adjusted to have a higher n-type impurity concentration than the first semiconductor region 6 by selectively introducing n-type impurities. In this case, the diode region 70 may be formed in the surface layer portion of the first semiconductor region 6.

Semiconductor device 1B includes multiple trenches 10 and multiple impurity regions 12 formed in the second active region 8B. The multiple trenches 10 and multiple impurity regions 12 of semiconductor device 1B have the same layout as the multiple trenches 10 and multiple impurity regions 12 of semiconductor device 1A, except that they are formed in the second active region 8B (see also Figures 6 to 9). Description of the multiple trenches 10 and multiple impurity regions 12 is omitted.

Similar to semiconductor device 1A, semiconductor device 1B includes an outer impurity region 15 formed in the first semiconductor region 6 of the outer region 9 so as to define the active region 8. In this embodiment, the outer impurity region 15 is formed spaced apart from the multiple trenches 10 in a planar view and extends in a band shape along the first active region 8A and the second active region 8B. Specifically, the outer impurity region 15 is formed in a ring shape that collectively surrounds the first active region 8A and the second active region 8B in a planar view.

The semiconductor device 1B includes an n-type low-resistance region 71 formed in the first semiconductor region 6 in the outer region 9. The low-resistance region 71 has a higher n-type impurity concentration than the first semiconductor region 6. The low-resistance region 71 may have an n-type impurity concentration of 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less. The low-resistance region 71 penetrates the first semiconductor region 6 and is connected to the second semiconductor region 7. The low-resistance region 71, together with the second semiconductor region 7, forms a current path with lower resistance than the first semiconductor region 6.

The low-resistance region 71 includes a first region 72, at least one (a pair of in this embodiment) second region 73, and at least one (one in this embodiment) third region 74. The first region 72 is formed in the region of the first semiconductor region 6 on the fourth side surface 5D side. The first region 72 is formed in a quadrangular shape (specifically, a rectangular shape extending in the second direction Y) spaced inward from the periphery of the first main surface 3 in a plan view. The first region 72 faces the first active region 8A (diode region 70) across the second active region 8B (a group of multiple trenches 10).

The pair of second regions 73 extend from the first region 72 toward the third side surface 5C (the first active region 8A side). In this embodiment, the pair of second regions 73 extend in a strip shape from the first region 72 in the first direction X so as to sandwich the second active region 8B from both sides in the second direction Y in a plan view. The pair of second regions 73 face the second active region 8B (a group of multiple trenches 10) in the second direction Y in a plan view, and face the first active region 8A in the first direction X. The pair of second regions 73 are formed spaced apart inward from the periphery of the first main surface 3 in a plan view.

The third region 74 is extended from one or both of the pair of second regions 73 toward the third side surface 5C and extends in a band shape along the first active region 8A. In this embodiment, the third region 74 is extended from both of the pair of second regions 73 and surrounds the first active region 8A. The third region 74 is formed spaced inward from the periphery of the first main surface 3 in a planar view. The third region 74 has a width less than the width of the second region 73 in a planar view. Of course, the third region 74 may have a width approximately equal to the width of the second region 73 in a planar view.

In this way, the low-resistance region 71 faces the first active region 8A from multiple directions and faces the second active region 8B from multiple directions. Specifically, the low-resistance region 71 collectively surrounds the first active region 8A and the second active region 8B. The low-resistance region 71 reduces the resistance of the current path from the first active region 8A to the region on the fourth side surface 5D, and reduces the resistance of the current path from the second active region 8B to the region on the fourth side surface 5D. Of course, the low-resistance region 71 only needs to include at least one of the first to third regions 72 to 74, and does not necessarily have to include all of the first to third regions 72 to 74 simultaneously.

Similar to the semiconductor device 1A, the semiconductor device 1B includes an insulating film 20 formed on the first main surface 3. Similar to the semiconductor device 1A, the insulating film 20 has a layered structure including a first insulating film 23 and a second insulating film 24. In this embodiment, the insulating film 20 includes a first contact opening 75 and a second contact opening 76. The first contact opening 75 exposes the first active region 8A and the second active region 8B. The wall portion defining the first contact opening 75 is located directly above the outer impurity region 15. The second contact opening 76 is formed along the first to third regions 72 to 74 of the low-resistance region 71 so as to expose these regions.

Similar to semiconductor device 1A, semiconductor device 1B includes a first polarity electrode 25 formed on the first main surface 3. Similar to semiconductor device 1A, first polarity electrode 25 has a layered structure including a first electrode film 27, a second electrode film 28, and a third electrode film 29, which are layered in this order from the chip 2 side.

In this embodiment, the first polarity electrode 25 includes a first pad portion 80 and a first lead portion 81. The first pad portion 80 extends from above the insulating film 20 into the first contact opening 75 so as to cover the first active region 8A (the region on the third side surface 5C side of the first main surface 3). The first pad portion 80 is formed in a quadrangular shape (specifically, a rectangular shape extending in the second direction Y) spaced inward from the periphery of the first main surface 3 in a plan view. The first pad portion 80 is electrically connected to the outer impurity region 15 in the first active region 8A and forms a Schottky junction with the diode region 70 (first semiconductor region 6).

The first lead portion 81 extends from the first pad portion 80 toward the second active region 8B so as to cover the second active region 8B, and extends from above the insulating film 20 into the first contact opening 75. The first lead portion 81 is formed spaced inward from the periphery of the first main surface 3 in a plan view. The first lead portion 81 is electrically connected to the impurity region 12 and the outer impurity region 15 within the first contact opening 75, and forms a Schottky junction with the first semiconductor region 6.

Specifically, the first lead-out portion 81 covers the first major surface 3 in the second active region 8B and extends from the first major surface 3 into the multiple trenches 10. The first lead-out portion 81 is electrically connected to the impurity region 12 at the bottom wall of each trench 10 and forms a Schottky junction with the first semiconductor region 6 at the sidewall of each trench 10. The first lead-out portion 81 includes a portion that forms a Schottky junction with the first semiconductor region 6 at the bottom wall of each trench 10. Specifically, the first lead-out portion 81 forms a Schottky junction with the first semiconductor region 6 at the corners and peripheral edges of the bottom wall of each trench 10.

As such, a first SBD structure 82 (Schottky junction) is formed in the first active region 8A, and has a first polarity electrode 25 (first pad portion 80) as an anode and a diode region 70 (first semiconductor region 6) as a cathode. Furthermore, a second SBD structure 83 (Schottky junction) is formed in the second active region 8B, and has a first polarity electrode 25 (first lead portion 81) as an anode and a first semiconductor region 6 as a cathode. The second SBD structure 83 is connected in parallel to the first SBD structure 82.

Unlike semiconductor device 1A, semiconductor device 1B includes a second polarity electrode 37 formed on first main surface 3 instead of second main surface 4. The second polarity electrode 37 is disposed on first main surface 3 at a distance from the first polarity electrode 25 in the lateral direction along first main surface 3. In other words, semiconductor device 1B includes a lateral type SBD. In this form, second polarity electrode 37 has a layered structure including a first electrode film 27, a second electrode film 28, and a third electrode film 29 layered in this order from the chip 2 side, similar to the first polarity electrode 25.

The second polarity electrode 37 extends from above the insulating film 20 into the second contact opening 76. The second polarity electrode 37 is electrically connected to the low resistance region 71 within the second contact opening 76. Specifically, the second polarity electrode 37 forms ohmic contact with the low resistance region 71. In this embodiment, the second polarity electrode 37 includes a second pad portion 84, at least one (a pair in this embodiment) second lead portion 85, and at least one (one in this embodiment) third lead portion 86.

The second pad portion 84 extends from above the insulating film 20 into the second contact opening 76 so as to cover the first region 72 of the low-resistance region 71 (the region on the fourth side surface 5D side of the first main surface 3). The second pad portion 84 is electrically connected to the first region 72 within the second contact opening 76. The second pad portion 84 is formed in a quadrangular shape (specifically, a rectangular shape extending in the second direction Y) spaced inward from the periphery of the first main surface 3 in a plan view. The second pad portion 84 faces the first pad portion 80 across the first lead portion 81.

The pair of second lead-out portions 85 extend from the first pad portion 80 toward the third side surface 5C (the second active region 8B side) so as to cover the second region 73 of the low-resistance region 71, and extend from above the insulating film 20 into the second contact opening 76. In this configuration, the pair of second lead-out portions 85 extend in a strip-like manner from the first pad portion 80 in the first direction X so as to sandwich the first lead-out portion 81 (the second active region 8B) from both sides in the second direction Y in a plan view.

The pair of second lead portions 85 face the first pad portion 80 in the first direction X in a plan view, and face the first lead portion 81 in the second direction Y. The pair of second lead portions 85 are formed spaced apart inward from the periphery of the first main surface 3 in a plan view. The pair of second lead portions 85 are electrically connected to the second region 73 of the low-resistance region 71 within the second contact opening 76.

The third lead portion 86 is extended from one or both of the pair of second lead portions 85 toward the third side surface 5C so as to cover the third region 74 of the low-resistance region 71, and extends from above the insulating film 20 into the second contact opening 76. The third lead portion 86 is formed at a distance inward from the periphery of the first main surface 3 in a plan view, and extends in a strip shape along the first pad portion 80 (first active region 8A).

In this embodiment, the third lead-out portion 86 is led out from both of the pair of second lead-out portions 85 and surrounds the first pad portion 80 (first active region 8A). The third lead-out portion 86 is electrically connected to the third region 74 of the low-resistance region 71 within the second contact opening 76. The third lead-out portion 86 has a width less than the width of the second lead-out portion 85 in a planar view. Of course, the third lead-out portion 86 may also have a width approximately equal to the width of the second lead-out portion 85 in a planar view.

Although specific illustrations are omitted, the semiconductor device 1B includes a silicide layer 31 formed at the connection portion between the chip 2 and the first polarity electrode 25, and at the connection portion between the chip 2 and the second polarity electrode 37 (see also FIG. 7). Specifically, the silicide layer 31 is formed at the connection portion between the chip 2 and the first electrode film 27.

The semiconductor device 1B includes an insulating layer 90 that selectively covers the first polarity electrode 25 (the first polarity electrode 25 and the second polarity electrode 37). The insulating layer 90 includes a first pad opening 91 that exposes the first polarity electrode 25. Specifically, the first pad opening 91 exposes the first pad portion 80 of the first polarity electrode 25. The first pad opening 91 is formed in a quadrangular shape (specifically, a rectangular shape extending in the second direction Y) spaced inward from the periphery of the first pad portion 80 in a plan view.

The insulating layer 90 includes a second pad opening 92 that exposes the second polarity electrode 37 at a distance from the first pad opening 91. Specifically, the second pad opening 92 exposes the second pad portion 84 of the second polarity electrode 37. In this embodiment, the second pad opening 92 is formed in a quadrangular shape (specifically, a rectangular shape extending in the second direction Y) at a distance inward from the periphery of the second pad portion 84 in a plan view.

In this embodiment, the insulating layer 90 has a layered structure including an inorganic insulating film 93 and an organic insulating film 94, which are layered in this order from the first polarity electrode 25 side. The inorganic insulating film 93 may include at least one of a silicon oxide film and a silicon nitride film. In this embodiment, the inorganic insulating film 93 includes a silicon nitride film. The organic insulating film 94 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. In this embodiment, the organic insulating film 94 includes a polyimide film. Of course, the insulating layer 90 may have a single-layer structure consisting of the inorganic insulating film 93 or the organic insulating film 94.

The semiconductor device 1B includes a first terminal electrode 95 electrically connected to the first polarity electrode 25. The first terminal electrode 95 is disposed in the first pad opening 91 and is electrically connected to the first pad portion 80 within the first pad opening 91. The semiconductor device 1B includes a second terminal electrode 96 electrically connected to the second polarity electrode 37. The second terminal electrode 96 is disposed in the second pad opening 92 and is electrically connected to the second pad portion 84 within the second pad opening 92.

The first and second terminal electrodes 95-96 each have a layered structure including a Ni film 97, a Pd film 98, and an Au film 99, layered in this order from the chip 2 side. The Ni film 97 backfills the first and second pad openings 91-92 and may have a portion covering the main surface of the insulating layer 90. The Pd film 98 coats the main surface of the Ni film 97 in a film-like manner. The Pd film 98 may have a portion covering the outer surface of the insulating layer 90. The Au film 99 coats the outer surface of the Pd film 98 in a film-like manner. The Au film 99 may have a portion covering the main surface of the insulating layer 90.

The semiconductor device 1B includes a sidewall insulating film 100 that covers the first to fourth side surfaces 5A to 5D of the chip 2. The sidewall insulating film 100 covers the entire periphery of the first to fourth side surfaces 5A to 5D, exposing the second main surface 4. In this embodiment, the sidewall insulating film 100 may cover part or all of the sidewall of the insulating layer 90 so as to expose the main surface of the insulating layer 90. The sidewall insulating film 100 may include at least one of a silicon oxide film and a silicon nitride film.

As described above, the semiconductor device 1B includes a chip 2, a first semiconductor region 6, a trench 10, an impurity region 12, and a first polarity electrode 25 (main surface electrode). The chip 2 has a first main surface 3. The first semiconductor region 6 is formed within the chip 2 so as to be exposed from the first main surface 3. The trench 10 is formed in the first main surface 3 and has sidewalls and a bottom wall. The impurity region 12 is formed within the first semiconductor region 6 in a region along the bottom wall of the trench 10 so as to expose the entire sidewall of the trench 10. The first polarity electrode 25 covers the first main surface 3 and forms a Schottky junction with the first semiconductor region 6.

This structure makes it possible to provide a semiconductor device 1B with improved electrical characteristics. Specifically, by adjusting the layout of the trenches 10 and the layout of the impurity regions 12, it is possible to provide a semiconductor device 1B with improved forward voltage VF and reverse current IR characteristics, which are examples of electrical characteristics.

In this embodiment, an example has been shown in which multiple trenches 10 and multiple impurity regions 12 are formed in the second active region 8B. However, the multiple trenches 10 and multiple impurity regions 12 may be formed in the first active region 8A instead of the second active region 8B. In other words, the positions of the first SBD structure 82 and the second SBD structure 83 may be interchanged.

In this case, the multiple trenches 10 and multiple impurity regions 12 are connected to the first polarity electrode 25 (first pad portion 80) in the first active region 8A. Of course, the multiple trenches 10 and multiple impurity regions 12 may be formed in both the first active region 8A and the second active region 8B. In other words, the second SBD structure 83 may be formed in both the first active region 8A and the second active region 8B.

The above describes an embodiment, but the above-described embodiment can be implemented in further forms. For example, the outer trench 11 may have the layout shown in FIG. 17. FIG. 17 is a plan view showing an example layout of the outer trench 11 according to a modified example. Referring to FIG. 17, the outer trench 11 may be formed in a ring shape surrounding multiple trenches 10. The layout of the outer impurity region 15 relative to the layout of the outer trench 11 is the same as in the first embodiment (see also FIGS. 6 and 7).

The multiple trenches 10 may have a layout shown in FIG. 18. FIG. 18 is a plan view showing an example layout of trenches 10 according to a first modified example. Referring to FIG. 18, the multiple trenches 10 may be arranged in a matrix (dot-like) pattern with gaps in the first direction X and the second direction Y in a plan view. In this case, the outer trenches 11 may also be arranged in a dot-like pattern with gaps in the second direction Y according to the layout of the multiple trenches 10.

Of course, the multiple trenches 10 may be arranged in a staggered (dot-like) pattern with gaps in the first direction X and the second direction Y in a plan view. In this case, for example, the multiple trenches 10 located in the even-numbered columns (or odd-numbered columns) may be arranged offset in the second direction Y from the multiple trenches 10 located in the odd-numbered columns (or even-numbered columns). Of course, the multiple trenches 10 located in the even-numbered rows (or odd-numbered rows) may be arranged offset in the first direction X from the multiple trenches 10 located in the odd-numbered rows (or even-numbered rows).

The multiple trenches 10 may have a layout shown in FIG. 19. FIG. 19 is a plan view showing an example layout of trenches 10 according to a second modified example. Referring to FIG. 19, in this embodiment, the multiple trenches 10 include multiple first trenches 10A extending in a first direction X and multiple second trenches 10B extending in a second direction Y. The multiple second trenches 10B intersect with the multiple first trenches 10A and form a single lattice-shaped trench 10 together with the multiple first trenches 10A.

In this case, the multiple impurity regions 12 may include multiple first impurity regions 12A that respectively cover the bottom walls of the multiple first trenches 10A, and multiple second impurity regions 12B that respectively cover the bottom walls of the multiple second trenches 10B. The layout of the first impurity regions 12A relative to the layout of the first trenches 10A is the same as in the first embodiment (see also Figures 6 and 7).

The layout of the second impurity regions 12B relative to the layout of the second trenches 10B is the same as in the first embodiment (see also Figures 6 and 7). Of course, the multiple impurity regions 12 need only include either multiple first impurity regions 12A or multiple second impurity regions 12B, and do not necessarily need to include multiple first impurity regions 12A and multiple second impurity regions 12B at the same time.

Of course, the multiple trenches 10 may be formed in a concentric layout in plan view by combining multiple first trenches 10A and multiple second trenches 10B, or in a spiral layout. In these cases, the multiple impurity regions 12 may be formed in a concentric layout in plan view by combining multiple first impurity regions 12A and multiple second impurity regions 12B, or in a spiral layout.

In each of the above-described embodiments, when a chip 2 made of SiC single crystal is used, the chip 2 preferably includes a SiC single crystal made of a hexagonal system. The SiC single crystal may be a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, a 6H-SiC single crystal, or the like. Of the above polytypes, the chip 2 preferably consists of a 4H-SiC single crystal.

The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal. Of course, the first main surface 3 may be formed by the carbon surface, and the second main surface 4 may be formed by the silicon surface.

The first main surface 3 and the second main surface 4 may have an off-angle inclined at a predetermined angle in a predetermined off-direction relative to the c-plane of the SiC single crystal. The off-direction may be the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be 0° or more and 5° or less. The first direction X may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

In the above-described embodiments, the first direction X and the second direction Y are defined by the extension directions of the first to fourth side surfaces 5A to 5D. However, the first direction X and the second direction Y may be any directions as long as they maintain a mutually intersecting (specifically, perpendicular) relationship.

The following are examples of features extracted from this specification and drawings. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each item to the embodiments. The "semiconductor device" in the following items may be changed to "semiconductor rectifier device" or "chip component."

[A1] A semiconductor device (1A, 1B) including: a chip (2) having a principal surface (3); a semiconductor region (6) of a first conductivity type (n-type) formed in the chip (2) so as to be exposed from the principal surface (3); a trench (10) formed in the principal surface (3) and having sidewalls and a bottom wall; an impurity region (12) of a second conductivity type (p-type) formed in the semiconductor region (6) only in a region along the bottom wall of the trench (10) so as to expose the entire sidewall of the trench (10); and a principal surface electrode (25) covering the principal surface (3) and forming a Schottky junction with the semiconductor region (6).

[A2] A semiconductor device (1A, 1B) described in A1, wherein the principal surface electrode (25) is electrically connected to the impurity region (12) at the bottom wall of the trench (10) and forms a Schottky junction with the semiconductor region (6) at the side wall of the trench (10).

[A3] A semiconductor device (1A, 1B) according to A1 or A2, wherein the principal surface electrode (25) includes a portion that forms the Schottky junction with the semiconductor region (6) on the bottom wall of the trench (10).

[A4] A semiconductor device (1A, 1B) described in any one of A1 to A3, wherein the impurity region (12) is formed only in a region along the bottom wall of the trench (10) and spaced apart from the sidewall of the trench (10).

[A5] A semiconductor device (1A, 1B) described in any one of A1 to A4, in which when a reverse voltage VR of 3 V is applied to the Schottky junction in a temperature environment of 125°C, the reverse current IR is 10 mA or less.

[A6] A semiconductor device (1A, 1B) described in any one of A1 to A5, in which the forward voltage VF is 300 mV or less when a forward current I F of 7.5 mA is applied to the Schottky junction in a temperature environment of -40°C.

[A7] A semiconductor device (1A, 1B) according to any one of A1 to A6, in which, in a cross-sectional view, a plurality of the trenches (10) are formed at intervals on the main surface (3), and a plurality of the impurity regions (12) are formed only in regions along the bottom walls of the plurality of trenches (10), respectively, so as to expose the entire side walls of the plurality of trenches (10).

[A8] A semiconductor device (1A, 1B) according to A7, wherein the plurality of trenches (10) are formed in the main surface (3) at intervals of a first value a in a cross-sectional view, and each have a width of a second value b (b≦a) that is less than the first value a.

[A9] The semiconductor device (1A, 1B) described in A8, wherein the first value a is 0.4 μm or more and 1.4 μm or less.

[A10] The semiconductor device (1A, 1B) described in A8 or A9, wherein the second value b is 0.4 μm or more and 1.2 μm or less.

[A11] A semiconductor device (1A, 1B) described in any one of A8 to A10, wherein the plurality of trenches (10) are formed so that the first value a and the second value b satisfy the relationship "a > -b + 1.4".

[A12] The semiconductor device (1A, 1B) described in any one of A8 to A11, wherein the impurity regions (12) are formed in regions along the bottom walls of the trenches (10) at intervals of a third value c (a≦c) equal to or greater than the first value a in a cross-sectional view, and each have a width of a fourth value d (d≦b) equal to or less than the second value b.

[A13] The semiconductor device (1A, 1B) described in A12, wherein the third value c is 0.4 μm or more and 1.6 μm or less.

[A14] The semiconductor device (1A, 1B) described in A12 or A13, wherein the fourth value d is 0.35 μm or more and 1.2 μm or less.

[A15] The semiconductor device (1A, 1B) described in any one of A1 to A14 further includes an active region (8) defined in the main surface (3), an outer region (9) defined on the main surface (3) outside the active region (8), the trench (10) formed in the main surface (3) in the active region (8), an outer trench (11) formed in the main surface (3) in the outer region (9) to partition the active region (8), the outer trench (11 having an inner wall on the active region (8) side, an outer wall on the outer region (9) side, and a bottom wall connecting the inner wall and the outer wall, and a second conductivity type (p-type) outer impurity region (15) formed in the semiconductor region (6) of the outer region (9) in a region along the outer wall of the outer trench (11).

[A16] A semiconductor device (1A, 1B) described in A15, wherein the outer impurity region (15) is formed in a region along the outer wall and bottom wall of the outer trench (11) so as to expose the inner wall of the outer trench (11).

[A17] A semiconductor device (1A, 1B) described in A15 or A16, wherein the outer impurity region (15) exposes a portion of the bottom wall of the outer trench (11).

[A18] A method for manufacturing a semiconductor device (1A, 1B), comprising the steps of: preparing a wafer (40) having a main surface (41) on which a semiconductor region (6) of a first conductivity type (n-type) is exposed; forming a trench (10) having sidewalls and a bottom wall in the main surface (41) by removing unnecessary portions of the wafer (40) from the main surface (41); forming a second conductivity type (p-type) impurity region (12) in the semiconductor region (6) along only the bottom wall of the trench (10) by introducing a second conductivity type impurity only into the bottom wall of the trench (10); and forming a main surface electrode (25) on the main surface (41) that forms a Schottky junction with the semiconductor region (6).

[A19] A method for manufacturing a semiconductor device (1A, 1B) according to A18, further comprising the step of forming a shielding mask (44) on the main surface (41) that exposes the bottom wall of the trench (10) and covers the sidewall of the trench (10), and the step of forming the impurity region (12) includes the step of introducing the second conductivity type impurity only into the bottom wall of the trench (10) via the shielding mask (44).

[A20] A method for manufacturing a semiconductor device (1A, 1B) according to A18 or A19, wherein the step of forming the principal surface electrode (25) includes a step of forming the principal surface electrode (25) that is electrically connected to the impurity region (12) at the bottom wall of the trench (10) and forms the Schottky junction with the semiconductor region (6) at the side wall of the trench (10).

Although the embodiments have been described in detail, these are merely examples used to clarify the technical content, and the present invention should not be construed as being limited to these examples. The scope of the present invention is limited by the appended claims.

1A Semiconductor device 1B Semiconductor device 2 Chip 3 First main surface 6 Semiconductor region 8 Active region 9 Outer region 10 Trench 11 Outer trench 12 Impurity region 15 Outer impurity region 25 First polarity electrode (main surface electrode)
40 Wafer 41 Wafer main surface 44 Second resist mask (shielding mask)
a First value b Second value c Third value d Fourth value

Claims (19)

a chip having a major surface;
a semiconductor region of a first conductivity type formed in the chip so as to be exposed from the main surface;
a trench formed in the major surface, the trench having a sidewall and a bottom wall;
an impurity region of a second conductivity type formed only in a region along the bottom wall of the trench in the semiconductor region;
a principal surface electrode covering the principal surface and forming a Schottky junction with the semiconductor region;
The principal surface electrode includes a portion that forms the Schottky junction with the semiconductor region on the bottom wall of the trench . The semiconductor device of claim 1, wherein the principal surface electrode is electrically connected to the impurity region at the bottom wall of the trench and forms the Schottky junction with the semiconductor region at the sidewall of the trench. 3. The semiconductor device according to claim 1 , wherein said impurity region is formed only in a region along said bottom wall of said trench and spaced from said side wall of said trench. 4. The semiconductor device according to claim 1 , wherein when a reverse voltage VR of 3 V is applied to the Schottky junction in a temperature environment of 125° C., a reverse current IR is 10 mA or less. 5. The semiconductor device according to claim 1 , wherein when a forward current IF of 7.5 mA is applied to the Schottky junction in a temperature environment of −40° C., a forward voltage VF is 300 mV or less. In a cross-sectional view, the trenches are formed at intervals in the main surface,
6. The semiconductor device according to claim 1, wherein, in a cross-sectional view, the impurity regions are formed only in regions along the bottom walls of the plurality of trenches, respectively, so as to expose the entire side walls of the plurality of trenches . 7. The semiconductor device according to claim 6, wherein the plurality of trenches are formed in the main surface at intervals of a first value a in a cross-sectional view, and each have a width of a second value b (b≦a) that is less than the first value a . 8. The semiconductor device according to claim 7 , wherein the first value a is equal to or greater than 0.4 [mu]m and equal to or less than 1.4 [mu]m. 9. The semiconductor device according to claim 7 , wherein the second value b is equal to or greater than 0.4 [mu]m and equal to or less than 1.2 [mu]m. 10. The semiconductor device according to claim 7 , wherein the plurality of trenches are formed so that the first value a and the second value b satisfy the relational expression "a>-b+1.4". 11. The semiconductor device according to claim 7, wherein the plurality of impurity regions are formed in regions along the bottom walls of the plurality of trenches at intervals of a third value c (a≦c) equal to or greater than the first value a in a cross-sectional view, and each have a width of a fourth value d ( d ≦ b ) equal to or less than the second value b. The semiconductor device according to claim 11 , wherein the third value c is equal to or greater than 0.4 μm and equal to or less than 1.6 μm. 13. The semiconductor device according to claim 11 , wherein the fourth value d is equal to or greater than 0.35 [mu]m and equal to or less than 1.2 [mu]m. an active area defined on the main surface;
an outer region set outside the active region on the main surface;
the trench formed in the major surface in the active region;
an outer trench formed in the main surface of the outer region to partition the active region, the outer trench having an inner wall on the active region side, an outer wall on the outer region side, and a bottom wall connecting the inner wall and the outer wall;
14. The semiconductor device according to claim 1, further comprising: an outer impurity region of a second conductivity type formed in a region along the outer wall of the outer trench in the semiconductor region of the outer region. 15. The semiconductor device according to claim 14 , wherein said outer impurity region is formed in a region along said outer wall and said bottom wall of said outer trench so as to expose said inner wall of said outer trench. 16. The semiconductor device according to claim 14 , wherein the outer impurity region exposes a portion of the bottom wall of the outer trench. providing a wafer having a main surface on which a semiconductor region of a first conductivity type is exposed;
forming a trench having a sidewall and a bottom wall in the main surface by removing an unnecessary portion of the wafer from the main surface side;
forming an impurity region of the second conductivity type along only the bottom wall of the trench in the semiconductor region by introducing an impurity of the second conductivity type only into the bottom wall of the trench;
forming a main surface electrode on the main surface, the main surface electrode including a portion that forms a Schottky junction with the semiconductor region on the bottom wall of the trench . forming a shielding mask on the major surface to expose the bottom wall of the trench and cover the sidewall of the trench;
18. The method for manufacturing a semiconductor device according to claim 17 , wherein said step of forming said impurity region includes the step of introducing said second conductivity type impurity only into said bottom wall of said trench through said shielding mask. 19. The method for manufacturing a semiconductor device according to claim 17, wherein the step of forming the principal surface electrode includes the step of forming the principal surface electrode electrically connected to the impurity region on the bottom wall of the trench and forming the Schottky junction with the semiconductor region on the sidewall of the trench .