JP7777433B2 - Inspection apparatus, inspection method, inspection program, and method for manufacturing semiconductor devices - Google Patents

Description

The present invention relates to an inspection apparatus, an inspection method, and an inspection program for determining the quality of products manufactured through multiple processes. It also relates to a method for manufacturing semiconductor devices using such an inspection apparatus.

In the manufacture of semiconductor devices, a completed semiconductor device is operated continuously for a certain period of time, and then an evaluation process is carried out to inspect its characteristics. Patent Document 1 discloses a burn-in test device that can be used in this evaluation process.

Japanese Patent Application Laid-Open No. 2001-242215

The evaluation process typically requires that semiconductor devices be continuously energized for a certain period of time. Therefore, the evaluation process has been a serious bottleneck in improving semiconductor device production efficiency. For this reason, it is preferable to determine whether a semiconductor device will be a pass or fail before the evaluation process is carried out, and to skip the evaluation process for semiconductor devices that are determined to be failing. However, existing technologies for selecting pass or fail before the evaluation process (sorting technologies using optical or electrical inspection) are incomplete, and there is a need to establish a sorting technology that surpasses these existing technologies.

Furthermore, the realization of such technology will bring benefits not only to semiconductor devices, but to all products that are manufactured through multiple processes. If it is possible to predict whether a product will be good or bad before all processes are completed, subsequent processes can be omitted, thereby improving the production efficiency of that product.

One aspect of the present invention was made in consideration of the above-mentioned problems, and its purpose is to realize a technology that can determine the quality of a product that is manufactured through multiple processes before all of the processes are completed.

The inspection device according to aspect 1 of the present invention has at least one processor that executes a determination step of determining the quality of a product using a model constructed by machine learning, which receives process information relating to each of a plurality of processes as input and outputs a class indicating the quality of a product manufactured through the plurality of processes.

With the above configuration, the quality of a product that is manufactured through multiple processes can be determined before all of the processes are completed.

In addition to the configuration of aspect 1, the inspection device according to aspect 2 of the present invention employs a configuration in which the process information includes at least one of information about the materials used in the corresponding process, information about the product obtained in the corresponding process, information about the manufacturing equipment used in the corresponding process, and information about the environment in which the corresponding process was carried out.

With the above configuration, the quality of a product that is manufactured through multiple processes can be accurately determined before all of the processes are completed.

In addition to the configuration of aspects 1 or 2, the inspection device according to aspect 3 of the present invention employs a configuration in which the product is a semiconductor device manufactured through a pre-process leading up to the production of semiconductor chips and a post-process following the production of the semiconductor chips, and the input to the model is process information relating to the pre-process.

With the above configuration, the quality of semiconductor devices manufactured through pre-processing and post-processing can be determined before the post-processing is carried out.

In addition to the configuration of aspect 3, the inspection device according to aspect 4 of the present invention employs a configuration in which the process information relating to the pre-processing step includes first process information relating to the semiconductor wafer obtained in the crystal growth step and second process information relating to the semiconductor chip obtained in the separation step.

With the above configuration, the quality of semiconductor devices manufactured through pre-processing and post-processing can be accurately determined before the post-processing is carried out.

In addition to the configuration of Aspect 4, the inspection device according to Aspect 5 of the present invention employs a configuration in which the first process information is an image representing the appearance of the semiconductor wafer, and the second process information includes a numerical sequence representing the attributes of the semiconductor chip and an image representing the appearance of the semiconductor chip.

With the above configuration, the quality of semiconductor devices manufactured through pre-processing and post-processing can be determined with greater accuracy before the post-processing is carried out.

An inspection method according to aspect 6 of the present invention includes a determination step in which at least one processor determines the quality of the product using a model constructed by machine learning, which receives process information relating to each of a plurality of processes as input and outputs a class indicating the quality of the product manufactured through the plurality of processes.

With the above configuration, the quality of a product that is manufactured through multiple processes can be determined before all of the processes are completed.

The inspection program according to aspect 7 of the present invention is an inspection program for causing a computer equipped with the processor to operate as an inspection device according to any one of aspects 1 to 5, and causes the processor to execute the determination process.

With the above configuration, the quality of a product that is manufactured through multiple processes can be determined before all of the processes are completed.

A semiconductor device manufacturing method according to aspect 8 of the present invention includes a determination step in which the quality of the semiconductor device is determined using an inspection apparatus according to any one of aspects 3 to 5 before carrying out the post-processing step, and if the semiconductor device is determined to be a non-defective product in the determination step, the post-processing step is carried out, and if the semiconductor device is determined to be a defective product in the determination step, the post-processing step is omitted.

The above configuration can improve the production efficiency of semiconductor devices.

One aspect of the present invention makes it possible to realize a technology that determines the quality of a product that is manufactured through multiple processes before all of the processes are completed.

1 is a block diagram showing a configuration of an inspection device according to an embodiment of the present invention; 2 is a flow chart showing the flow of a semiconductor device manufacturing method carried out using the inspection apparatus shown in FIG. 1 . 2 is a graph showing the number of non-defective and defective products per lot, as determined by an existing sorting method in a later process, arranged in chronological order for semiconductor wafers, and shows one embodiment of the inspection apparatus shown in FIG. 1.

(Configuration of inspection device)
The configuration of an inspection apparatus 1 according to one embodiment of the present invention will be described with reference to Fig. 1. The inspection apparatus 1 is an apparatus that judges the quality of a product based on process information relating to multiple processes included in a manufacturing method of the product. In this embodiment, the product is assumed to be a semiconductor device including a semiconductor chip, and in particular a semiconductor laser unit including a semiconductor laser chip.

As shown in FIG. 1, the inspection device 1 includes a memory 11, a processor 12, and a storage 13. The memory 11, the processor 12, and the storage 13 are connected to one another via a bus (not shown). An input/output interface (not shown) and a communication interface (not shown) may also be connected to this bus. This input/output interface is used, for example, to input process information from an external device (e.g., a camera, test equipment, manufacturing equipment, etc.) to the inspection device 1, or to output inspection results from the inspection device 1 to an external device (e.g., a display, etc.). The communication interface is also used, for example, to allow the inspection device 1 to receive input images provided from an external device (e.g., a camera, test equipment, or another computer connected to the manufacturing equipment), or to allow the inspection device 1 to transmit inspection results to an external device (e.g., another computer connected to a display).

Memory 11 is configured to record an inspection program P for performing the determination process S104 described below, and a model M constructed by machine learning that is used in the determination process S104 described below. For example, semiconductor RAM (Random Access Memory) can be used as memory 11. For example, a CNN (Convolutional Neural Network) can be used as model M. A logistic regression model, a support vector machine, a random forest, or the like can also be used as model M.

The processor 12 is configured to execute the determination process S104, described below, in accordance with the inspection program P stored in the memory 11. The processor 12 may be, for example, a CPU (Central Processing Unit), GPU (Graphic Processing Unit), TPU (Tensor Processing Unit), digital signal processor, microprocessor, microcontroller, or a combination of these.

Storage 13 is configured to store (non-volatilely store) the above-mentioned inspection program P and the above-mentioned model M. When executing the determination step S104 described below, processor 12 expands and references the inspection program P and model M stored in storage 13 in memory 11. Note that storage 13 may be, for example, a flash memory, HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination of these.

Note that while the configuration described here is one in which the determination step S104, described below, is executed by a single processor 12 provided in a single computer, this is not limiting. In other words, it is also possible to adopt a configuration in which the determination step S104, described below, is executed jointly by multiple processors provided in a single computer or distributed across multiple computers.

Furthermore, while the configuration described here is one in which model M is stored in a single memory 11 provided in a single computer, this is not limiting. In other words, it is also possible to adopt a configuration in which model M is stored in a single computer or in multiple memories distributed across multiple computers.

The inspection program P for causing the processor 12 to execute the determination step S104 may be recorded on a computer-readable, non-transitory, tangible recording medium. This recording medium may be memory 11, storage 13, or another recording medium. For example, a tape, a disk, a card, a semiconductor memory, or a programmable logic circuit may be used as the other recording medium.

(Method for manufacturing semiconductor devices using an inspection device)
A method S100 for manufacturing a semiconductor device using the inspection apparatus 1 will be described with reference to Fig. 2. Fig. 2 is a flow chart showing the flow of the method S100 for manufacturing a semiconductor device. As described above, a semiconductor laser unit including a semiconductor laser chip is assumed as the semiconductor device.

As shown in Figure 2, the manufacturing method S100 includes a pre-process S110 for obtaining a semiconductor chip, and a post-process S120 for obtaining the semiconductor chip.

As shown in FIG. 2, the pre-process S110 is composed of a crystal growth process S111, an electrode formation process S112, a first separation process S113 (an example of a "separation process"), and a second separation process S114 (an example of a "separation process"). The crystal growth process S111 is a process for obtaining a semiconductor wafer by crystal growth. The electrode formation process S112 is a process for forming a front electrode and a back electrode on the semiconductor wafer. The first separation process S113 is a process for obtaining semiconductor bars by cleaving or dicing the semiconductor wafer. The first separation process S113 may include a process for coating the end faces of the obtained semiconductor bars. The second separation process S114 is a process for obtaining semiconductor chips by cleaving or dicing the semiconductor bars.

The post-process S120, as shown in FIG. 2, is composed of an assembly process S121 and an evaluation process S122. The assembly process S121 is a process of assembling a semiconductor device using semiconductor chips. The assembly process S121 is composed of, for example, die-bonding the semiconductor chip to a heat dissipation mount and wire-bonding to establish electrical connection. The evaluation process S122 is a process of evaluating the semiconductor device. The evaluation process S122 is composed of, for example, burning in the semiconductor device by continuously applying current for a certain period of time and inspecting the characteristics of the semiconductor device after burn-in.

A distinctive feature of the manufacturing method S100 according to this embodiment is that it includes a wafer imaging process S101, an attribute inspection process S102, a chip imaging process S103, and a judgment process S104, as shown in FIG. 2.

The wafer imaging process S101 is a process for obtaining images representing the appearance of each semiconductor chip included in the semiconductor wafer obtained in the crystal growth process S111 as process information related to the crystal growth process S111 (an example of "first process information"). The wafer imaging process S101 is performed, for example, by a camera, and the images obtained in the wafer imaging process S101 are supplied from the camera to the inspection device 1.

The attribute inspection process S102 is a process of obtaining a numerical sequence representing the attributes of the semiconductor chips obtained in the second separation process S114 as process information related to the second separation process S114 (an example of "second process information"). The attribute inspection process S102 is performed, for example, by a test device, and the numerical sequence obtained in the attribute inspection process S102 is supplied from the test device to the inspection device 1. The attribute inspection process S102 may also be a process of obtaining a numerical sequence representing the attributes of each semiconductor chip included in the semiconductor wafer obtained in the first separation process S113 as process information related to the first separation process S113.

The chip imaging process S103 is a process for obtaining an image showing the appearance of the semiconductor chip obtained in the second separation process S114 as process information related to the second separation process S114 (an example of "second process information"). The chip imaging process S103 is performed, for example, by a camera, and the image obtained in the chip imaging process S103 is supplied to the inspection device 1.

The judgment process S104 is a process in which the inspection device 1 judges the quality of the semiconductor chip using a model M constructed by machine learning. The inputs to the model M are (1) an image representing the appearance of the semiconductor chip to be judged, obtained in the wafer imaging process S101, (2) a numerical sequence representing the attributes of the semiconductor chip to be judged, obtained in the attribute inspection process S102, and (3) an image representing the appearance of the semiconductor chip to be judged, obtained in the chip imaging process S103. The output of the model M is a class indicating the quality of the semiconductor device manufactured by performing the post-process S120 on the semiconductor chip to be judged.

In machine learning, training data is used, which is a label linking (1) an image representing the appearance of the semiconductor chip to be judged obtained in the wafer imaging process S101, (2) numerical values representing the attributes of the semiconductor chip to be judged obtained in the attribute inspection process S102, and (3) an image representing the appearance of the semiconductor chip to be judged obtained in the chip imaging process S103 with (4) the inspection results of the semiconductor device including the semiconductor chip to be judged obtained in the evaluation process S122. The inspection results are, for example, either a pass or a fail. Typically, if degradation occurs in the semiconductor device in the evaluation process S122, the inspection result for that semiconductor device is a fail, and if no degradation occurs in the semiconductor device in the evaluation process S122, the inspection result for that semiconductor device is a pass. In addition to the function of judging the quality of the semiconductor device using the model M, the inspection apparatus 1 may also have the function of constructing the model M by performing such machine learning.

If the output of model M in the judgment process S104 is in the non-defective class, the post-process S120 is carried out on the semiconductor chip to be judged. On the other hand, if the output of model M in the judgment process S104 is in the defective class, the post-process S120 can be omitted for the semiconductor chip to be judged. In this case, it is possible to avoid the decrease in production efficiency that occurs when the evaluation process S122, which is time- and financially costly, is carried out on semiconductor chips that are likely to be defective. Therefore, it is possible to improve the production efficiency of semiconductor devices.

(Model performance)
The performance of the model M used in the determination step S104 will be described with reference to FIG.

Figure 3 is a graph showing the number of good products and the number of defective products contained in each lot in chronological order. Here, the number of good products is the number of semiconductor devices determined to be good in the evaluation process S122, and the number of defective products is the number of semiconductor devices determined to be defective in the evaluation process S122. From the graph shown in Figure 3, it can be seen that there are periods with many defective products and periods with few defective products.

Therefore, training, validation, and testing of Model M were performed for both periods with a high number of defective products and periods with a low number of defective products. Table 1 shows the number of semiconductor devices used in training, validation, and testing of Model M for periods with a high number of defective products, divided into good and defective products. Table 2 shows the number of semiconductor devices used in training, validation, and testing of Model M for periods with a low number of defective products, divided into good and defective products.

Table 3 shows the inference matrix for Model M for periods with high levels of defective products.

As shown in Table 3, of the 1,957 semiconductor chips included in semiconductor devices judged to be good in the evaluation process S122, 1,702 semiconductor chips were classified into the good product class in the judgment process S104. In other words, the good product reproduction rate was 86.97%. Furthermore, of the 153 semiconductor chips included in semiconductor devices judged to be defective in the evaluation process S122, 108 semiconductor chips were classified into the defective product class in the judgment process S104. In other words, the defective product reproduction rate was 70.59%.

Furthermore, as shown in Table 3, of the 1,747 semiconductor devices containing semiconductor chips classified as good products in the judgment process S104, 1,702 semiconductor devices were judged to be good products in the evaluation process S122. In other words, the good product conformance rate was 97.42%. Furthermore, of the 363 semiconductor devices containing semiconductor chips classified as bad products in the judgment process S104, 108 semiconductor devices were judged to be bad products in the evaluation process S122. In other words, the bad product conformance rate was 29.75%.

From these results, we can see that during periods with many defective products, Model M's F-value for non-defective products was 0.919, and its accuracy rate was 85.78%.

Table 4 shows the inference matrix for Model M for periods when there are few good products.

As shown in Table 4, of the 4,660 semiconductor chips included in semiconductor devices determined to be good in the evaluation process S122, 3,369 semiconductor chips were classified into the good product class in the determination process S104. In other words, the good product reproduction rate was 72.30%. Furthermore, of the 110 semiconductor chips included in semiconductor devices determined to be defective in the evaluation process S122, 67 semiconductor chips were classified into the defective product class in the determination process S104. In other words, the defective product reproduction rate was 60.91%.

Furthermore, as shown in Table 4, of the 3,412 semiconductor devices including semiconductor chips classified as good products in the judgment process S104, 3,369 semiconductor devices were judged to be good products in the evaluation process S122. In other words, the good product conformance rate was 98.74%. Furthermore, of the 1,358 semiconductor devices including semiconductor chips classified as bad products in the judgment process S104, 67 semiconductor devices were judged to be bad products in the evaluation process S122. In other words, the bad product conformance rate was 4.93%.

From these results, we concluded that during periods when there were few defective products, Model M's F-value for non-defective products was 0.8347, and that Model M's accuracy rate was 72.03%.

(Modification of the inspection device)
In this embodiment, the semiconductor device, particularly the semiconductor laser unit, is the subject of inspection, but the present invention is not limited to this. In other words, any product manufactured through multiple processes can be the subject of inspection.

In addition, in this embodiment, the image representing the appearance of the semiconductor wafer obtained in the crystal growth process S111, the numerical values representing the attributes of the semiconductor chips obtained in the second separation process S114, and the image representing the appearance of the semiconductor chips obtained in the second separation process S114 are input to model M, but the present invention is not limited to this. That is, process information related to any process can be input to model M. Process information related to each process includes information about the product obtained in that process, as well as information about the materials used in that process, information about the manufacturing equipment used in that process, and information about the environment in which that process is carried out. There is a certain correlation between this information and product quality. Therefore, by inputting this information to model M, product quality can be effectively estimated.

The process information may be represented by an image, a numerical value or a numerical string, or a character string. The process information may be acquired using various sensors, such as a camera, microphone, gas sensor, acceleration sensor, gyro sensor, current sensor, voltage sensor, temperature sensor, or humidity sensor. Information about manufacturing equipment (e.g., set values) may be acquired from a controller that controls the manufacturing equipment. Information about materials or products (e.g., characteristic values) may be acquired from testing equipment that tests the materials or products.

(Additional Notes)
The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in the above-described embodiments are also included in the technical scope of the present invention. Furthermore, the application of the present invention is not limited to semiconductor devices, and can be applied to general products manufactured through multiple processes.

REFERENCE SIGNS LIST 1 Inspection device 11 Memory 12 Processor 13 Storage P Inspection program M Model S100 Manufacturing method S101 Wafer imaging process S102 Attribute inspection process S103 Chip imaging process S104 Judgment process

Claims (8)

a single model that receives process information relating to each of a plurality of processes as an input and outputs a class indicating the quality of an individual product manufactured through the plurality of processes, the single model comprising at least one processor that executes a determination step of determining the quality of the product using a model constructed by machine learning ;
An inspection device characterized by : The process information includes at least one of information on materials used in the corresponding process, information on products obtained in the corresponding process, information on manufacturing equipment used in the corresponding process, and information on the environment in which the corresponding process was carried out.
2. The inspection device according to claim 1. The product is a semiconductor device manufactured through a pre-process to obtain a semiconductor chip and a post-process after obtaining the semiconductor chip,
The input of the model is process information related to the previous process.
3. The inspection device according to claim 1 or 2. The process information relating to the pre-process includes first process information relating to the semiconductor wafer obtained in the crystal growth process and second process information relating to the semiconductor chip obtained in the separation process.
4. The inspection device according to claim 3. the first process information is an image representing an appearance of the semiconductor wafer,
the second process information includes a numerical sequence representing an attribute of the semiconductor chip and an image representing an appearance of the semiconductor chip;
5. The inspection device according to claim 4. At least one processor receives process information relating to each of a plurality of processes as an input, and outputs a class indicating the quality of an individual product manufactured through the plurality of processes, and includes a determination step of determining the quality of the product using a single model constructed by machine learning .
An inspection method characterized by : An inspection program for causing a computer equipped with the processor to operate as the inspection device described in any one of claims 1 to 5, the inspection program causing the processor to execute the determination process. a determining step of determining the quality of the semiconductor device using the inspection apparatus according to any one of claims 3 to 5 before carrying out the post-process;
If the product is determined to be a non-defective product in the determination process, the post-process is carried out, and if the product is determined to be a defective product in the determination process, the post-process is omitted.
1. A method for manufacturing a semiconductor device, comprising: