JP7778271B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

This disclosure relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device having a structure that dissipates heat generated by a semiconductor element through a base plate.

One example of a semiconductor device with a structure that dissipates heat generated in a semiconductor element is the semiconductor device disclosed in Patent Document 1.

The conventional semiconductor device disclosed in Patent Document 1 is equipped with a heat dissipation mechanism that relieves thermal stress acting at the junction between the semiconductor element and the connecting wiring due to differences in the thermal expansion coefficients of the components. Specifically, the conventional semiconductor device achieves the heat dissipation mechanism by inserting a thermal stress buffer member between the semiconductor element and the connecting wiring and bonding the thermal stress buffer member to both the semiconductor element and the connecting wiring. The thermal stress buffer member used in the heat dissipation mechanism is composed of a composite material in which a sintered body of a carbon or metal base material is infiltrated and dispersed with a metal having a lower melting point than the aforementioned base material.

Japanese Patent Application Laid-Open No. 2008-42041

Conventional semiconductor devices with heat dissipation mechanisms typically use a single-sided cooling method, in which the semiconductor element is bonded via an insulating substrate, cooling the semiconductor element from the insulating substrate side. In conventional semiconductor devices, the top surface of the semiconductor element is sealed with an encapsulating resin layer, causing heat generated by the semiconductor element during power-on operation to accumulate within the encapsulating resin layer. Because the encapsulating resin layer is located on the opposite side of the insulating substrate from the semiconductor element, conventional heat dissipation mechanisms that use the single-sided cooling method described above have difficulty dissipating the heat accumulated within the encapsulating resin layer.

Generally, the thermal expansion coefficients of components (hereinafter sometimes abbreviated as "components") used in semiconductor devices are, for example, in the range of {2×10 ^-6 /K to 22×10 ^-6 /K} when the components in the device are semiconductor elements, connection wiring, insulating substrates, base plates, and sealing resin layers. Therefore, the maximum difference in linear expansion coefficient between components in conventional semiconductor devices can be as much as 20×10 ^-6 /K.

In general, it is considered desirable for the difference in thermal expansion coefficient between components to be 9×10 ⁻⁶ /K or less, so the maximum difference in thermal expansion coefficient in conventional semiconductor devices is not negligible. In particular, the connecting wiring and base plate tend to be components that increase the difference in thermal expansion coefficient.

Under these circumstances, the encapsulating resin layer is in contact with all components and is particularly affected by differences in thermal expansion coefficients. Components contained within a semiconductor device include the aforementioned semiconductor elements, connecting wiring, insulating substrates, base plates, etc.

Assuming that the junction temperature Tj of a semiconductor element rises to, for example, 125°C during power-on operation, conventional semiconductor devices have a cooling mechanism for single-sided cooling, so the temperature of each component remains close to the design temperature of the cooling mechanism. However, the encapsulating resin layer on the top surface of the semiconductor element rises to 125°C, and heat propagates throughout the encapsulating resin layer. As a result, differences in the thermal expansion coefficients of the components cause delamination, reducing the reliability of the semiconductor device.

The conventional semiconductor device disclosed in Patent Document 1 has a structure in which a thermal stress buffer member is inserted between the semiconductor element and the connecting wiring. Therefore, by cooling the heat generated by the semiconductor element when it is energized via the thermal stress buffer member, the thermal stress generated at the interface between the semiconductor element and the encapsulating resin layer is alleviated, preventing peeling between the semiconductor element and the encapsulating resin layer and improving the reliability of the device.

However, because the thermal stress buffer material is electrically connected to the semiconductor elements that make up the main current circuit and functions as part of the wiring of the semiconductor elements, there is a problem in that electrical loss occurs when the semiconductor elements are energized. One example of electrical loss is an increase in inductance.

The present disclosure aims to solve the above-mentioned problems and provide a semiconductor device structure that improves the reliability of the device without causing electrical loss during operation of the semiconductor element.

The semiconductor device disclosed herein comprises a base plate having a first main surface and a second main surface; an insulated circuit board having a circuit pattern and provided on the first main surface side of the base plate; at least one semiconductor element provided on the first main surface side of the insulated circuit board; a heat dissipation member that is conductive and includes a plurality of pillars and a plate portion provided between the plurality of pillars, the plate portion being located on the first main surface side of the insulated circuit board and the at least one semiconductor element, and the plurality of pillars being provided upright on the first main surface of the base plate; and a resin layer provided on the first main surface of the base plate, covering the insulated circuit board, the at least one semiconductor element, and the heat dissipation member; the heat dissipation member is provided at a distance from the at least one semiconductor element to prevent dielectric breakdown in the resin layer between the heat dissipation member and the at least one semiconductor element when the at least one semiconductor element is in operation, and the heat dissipation member is electrically insulated from the at least one semiconductor element.

The heat dissipation member in the semiconductor device disclosed herein is electrically insulated from at least one semiconductor element, so that the presence of the heat dissipation member does not cause electrical loss during operation of the at least one semiconductor element.

In addition, the heat dissipation member is located away from the at least one semiconductor element so that the resin layer does not experience dielectric breakdown when the at least one semiconductor element is operating, and therefore, dielectric breakdown does not occur in the resin layer when the at least one semiconductor element is operating.

Furthermore, the heat dissipation member is conductive and has a column portion that stands upright on the first main surface of the base plate, so that it can perform a heat dissipation function by dissipating heat that accumulates in the resin layer during operation of at least one semiconductor element through a heat dissipation path that includes the heat dissipation member and the base plate.

Therefore, the semiconductor device disclosed herein can mitigate the effects of differences in thermal expansion coefficients between the resin layer and other components, thereby reliably avoiding interfacial peeling between the resin layer and at least one semiconductor element, insulating circuit board, and base plate.

As a result, the semiconductor device disclosed herein can improve the reliability of the device without generating electrical losses during operation of at least one semiconductor element.

The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings.

1 is a plan view showing a top surface structure of a semiconductor device according to a first embodiment; 2 is a cross-sectional view (part 1) showing the cross-sectional structure of the semiconductor device according to the first embodiment shown in FIG. 1; 2 is a cross-sectional view (part 2) showing the cross-sectional structure of the semiconductor device according to the first embodiment shown in FIG. 1; FIG. FIG. 10 is a plan view showing the top surface structure of a semiconductor device according to a second embodiment; FIG. 11 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a third embodiment. FIG. 10 is a plan view showing the top surface structure of a semiconductor device according to a fourth embodiment. FIG. 7 is a cross-sectional view (part 1) showing the cross-sectional structure of the semiconductor device according to the fourth embodiment shown in FIG. 6; FIG. 7 is a cross-sectional view (part 2) showing the cross-sectional structure of the semiconductor device according to the fourth embodiment shown in FIG. 6; FIG. 10 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a fifth embodiment. FIG. 13 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a sixth embodiment.

First Embodiment
FIG. 1 is a plan view showing the top surface structure of a semiconductor device 51 according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view showing the A-A cross-sectional structure of the semiconductor device 51 according to the first embodiment shown in FIG. 1. FIG. 3 is a cross-sectional view showing the B-B cross-sectional structure of the semiconductor device 51 according to the first embodiment shown in FIG. 1 to FIG. 3 each show an XYZ orthogonal coordinate system. Note that FIG. 1 omits the illustration of the sealing resin layer 8 in order to clearly show the internal structure of the semiconductor device 51.

In the following description, the top of the page and the bottom of the page of each component of semiconductor device 51 shown in the cross-sectional views of Figures 2 and 3 will be referred to as the "first main surface" and the "second main surface," respectively. In other words, for each component of semiconductor device 51, the surface facing the +Z direction is the "first main surface," and the surface facing the -Z direction is the "second main surface."

For example, the top surface of the metal base plate 1, which serves as the base plate, is the first main surface, and the bottom surface is the second main surface. Furthermore, when explaining the structure of the semiconductor device 51, the +Z direction may be referred to as the first main surface side and the -Z direction may be referred to as the second main surface side, with each component as the reference.

As shown in Figures 1 to 3, a resin case 2 is provided on the first main surface of a metal base plate 1, which serves as a base plate. The metal base plate 1 is made of a material with excellent thermal conductivity, such as an aluminum alloy or copper.

The resin case 2 has a rectangular frame structure with four side walls when viewed in the XY plane, and is provided on the peripheral region of the first main surface of the metal base plate 1. A plurality of external electrodes 11 are provided on the upper surfaces of the side walls of the resin case 2. Figure 2 illustrates two external electrodes 11 as the plurality of external electrodes 11. The resin case 2 is made of a highly heat-resistant resin such as PPS (Poly Phenylene Sulfide) or PBT (Poly Butylen Terefthalate).

The combination of the metal base plate 1 and the resin case 2 forms an open-top housing with an internal storage area, with the metal base plate 1 as the bottom and the resin case 2 as the side.

A plurality of intermediate connection members 21 are provided in the resin case 2 from the inner surface of the side wall to the inside, corresponding to the plurality of external electrodes 11. In Figure 2, two intermediate connection members 21 are illustrated as the plurality of intermediate connection members 21. Corresponding external electrodes 11 and intermediate connection members 21 are electrically connected via embedded connection wires 22 between the plurality of external electrodes 11 and the plurality of intermediate connection members 21. The embedded connection wires 22 are embedded within the side wall of the resin case 2. In this way, there is a one-to-one correspondence between the plurality of external electrodes 11, the plurality of intermediate connection members 21, and the plurality of embedded connection wires 22.

An insulating circuit board 3 is provided on the first main surface of the metal base plate 1. The insulating circuit board 3 is provided in a manner that fits within the accommodating area formed by the combination of the metal base plate 1 and the resin case 2.

The insulating circuit board 3 is a substrate having a combined structure of an insulating layer 30 and a circuit pattern 5 provided on both sides of the insulating layer 30. The insulating layer 30 is made of a ceramic with excellent thermal conductivity, such as aluminum nitride or silicon nitride, or a resin.

Circuit patterns 5 are provided on both sides of the insulating layer 30. The circuit patterns 5 are made of aluminum alloy, copper, or other materials. Note that in Figures 2 and 3 and the cross-sectional views shown below, the circuit patterns 5 provided on the second main surface of the insulating layer 30 are not shown.

Furthermore, a plurality of semiconductor elements 6 are provided on the first main surface of the circuit pattern 5 via a conductive adhesive 10. Figures 1 to 3 illustrate two semiconductor elements 6 as the plurality of semiconductor elements. The conductive adhesive 10 is made of solder, soft solder, or the like. Therefore, the circuit pattern 5 of the insulating circuit board 3 and the plurality of semiconductor elements 6 are bonded via the conductive adhesive 10.

The multiple semiconductor elements 6 are each electrically connected to the intermediate connection member 21 via the electrical connection member 7. Therefore, signals that flow when the multiple semiconductor elements 6 are energized can be obtained from the multiple external electrodes 11.

It should be noted that silicon (Si) IGBTs (Insulated Gate Bipolar Transistors), diodes, and reverse conducting IGBTs are often used as each of the multiple semiconductor elements 6. Furthermore, each of the multiple semiconductor elements 6 may also be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) or Schottky diode made of a material with a larger band gap than Si, such as gallium nitride (GaN).

Furthermore, the number of semiconductor elements 6 mounted on the first main surface of the insulating circuit board 3 is not limited, and the required number of semiconductor elements 6 may be mounted depending on the application. In other words, the semiconductor device 51 of embodiment 1 is required to have at least one semiconductor element 6.

Hereinafter, the structure including the insulating circuit board 3, multiple semiconductor elements 6, and multiple conductive bonding materials 10 may be referred to as the "intermediate structure."

In addition, in the semiconductor device 51 of embodiment 1, the electrical connection member 7 is shown schematically. That is, the electrical connection member 7 includes a linear connection member such as a wire that is bonded and fixed by ultrasonic wire bonding processing, and a plate-shaped connection member whose main portion is formed in a plate shape. In Figures 1 to 3, the electrical connection member 7 is shown as a linear connection member.

In this configuration, a main current circuit is formed including multiple semiconductor elements 6, electrical connection members 7, and the circuit pattern 5 portion of the insulating circuit board 3. The main current circuit is the circuit through which the main current flows when the multiple semiconductor elements 6 are energized.

The semiconductor device 51 of embodiment 1 is characterized by further including a heat dissipation member 4. The heat dissipation member 4 is conductive, includes multiple pillars 4b and one plate 4a provided between the multiple pillars 4b, and has a flat gate shape in the XZ cross section as shown in Figure 3. Figure 3 illustrates two pillars 4b as the multiple pillars 4b. The plate 4a of the heat dissipation member 4 has a rectangular shape when viewed in plan in the XY plane as shown in Figure 1.

Furthermore, as shown in Figure 3, the second main surface of the plate portion 4a is arranged to face the first main surface of each component that constitutes the intermediate structure. Specifically, as shown in Figures 2 and 3, the plate portion 4a of the heat dissipation member 4 is arranged at a distance in the +Z direction from the first main surfaces of the insulating circuit board 3 and the multiple semiconductor elements 6. In other words, the plate portion 4a of the heat dissipation member 4 is located on the first main surface side of the insulating circuit board 3 and the multiple semiconductor elements 6.

As shown in Figure 3, the multiple pillars 4b are provided upright on the first main surface of the metal base plate 1 without contacting the intermediate structure. In other words, the lower ends of some or all of the multiple pillars 4b are in contact with the first main surface of the metal base plate 1. In this way, the heat dissipation member 4 is provided on the first main surface of the metal base plate 1 so as to straddle the intermediate structure.

Then, a resin layer, encapsulating resin layer 8, is provided to seal the storage area of resin case 2. In other words, the storage area is sealed by filling it with encapsulating resin layer 8. In this way, encapsulating resin layer 8 is provided on the first main surface of metal base plate 1, covering insulated circuit board 3, circuit pattern 5, multiple semiconductor elements 6, multiple electrical connection members 7, and heat dissipation member 4.

The sealing resin layer 8 is often made of silicone gel or epoxy resin, but is not limited to these. Any material can be used as long as it has the desired physical properties such as elastic modulus, heat resistance, adhesiveness, and linear expansion coefficient.

Therefore, the sealing resin layer 8 is present between the second main surface of the plate portion 4a of the heat dissipation member 4 and the intermediate structure. In other words, the sealing resin layer 8 is present between the second main surface of the plate portion 4a and the first main surface of each of the multiple semiconductor elements 6.

Furthermore, a cooling mechanism 9 is attached to the second main surface side of the metal base plate 1, which is the base plate. The cooling mechanism 9 employs a water-cooling method or an air-cooling method and performs a cooling operation to cool the metal base plate 1. Therefore, the heat dissipation member 4 is cooled by the cooling operation of the cooling mechanism 9 via the metal base plate 1.

The heat dissipation member 4 is positioned away from the multiple semiconductor elements 6 to prevent dielectric breakdown of the sealing resin layer 8 between the heat dissipation member 4 and the multiple semiconductor elements 6 when current is applied to the multiple semiconductor elements 6. In addition, the heat dissipation member 4 is electrically insulated from the multiple semiconductor elements 6, and the potential of the heat dissipation member 4 is set to 0V. The potential of the heat dissipation member 4 is set, for example, by setting the metal base plate 1 to a reference potential of 0V.

The placement of the heat dissipation member 4 will be described in detail below. For example, if the encapsulating resin layer 8 is made of an encapsulating resin with a breakdown voltage of 20 kV/mm and the operating voltage of the semiconductor elements 6 is 600 V, the heat dissipation member 4 is positioned at an insulation distance of more than 30 μm between the semiconductor elements 6 and the heat dissipation member 4 when the semiconductor elements 6 are in electrical conduction. "30 μm" is the value obtained by dividing the operating voltage of 600 V by the breakdown voltage of 20 kV/mm. In other words, the "insulation distance" can be calculated from two factors (the breakdown voltage of the encapsulating resin layer 8 and the voltage when the semiconductor elements 6 are in electrical conduction operation).

Specifically, the distance between the second main surface of the plate portion 4a of the heat dissipation member 4, which faces each other in the Z direction, and the first main surface of each of the multiple semiconductor elements 6 is set to satisfy the above-mentioned insulation distance. In addition, the shortest distance between each of the multiple column portions 4b and the side surface of each of the multiple semiconductor elements 6 is set to satisfy the above-mentioned insulation distance.

It is desirable that the shortest distance between each of the multiple pillar portions 4b and the side of each of the multiple circuit patterns 5 be set so as to satisfy the above-mentioned insulation distance, and that the shortest distance between each of the multiple electrical connection members 7 and the heat dissipation member 4 be set so as to satisfy the above-mentioned insulation distance.

In addition, the plate portion 4a and the multiple pillar portions 4b are positioned so that they do not come into contact with any of the multiple semiconductor elements 6, and by providing an encapsulating resin layer 8 between the heat dissipation member 4 and the multiple semiconductor elements 6, the heat dissipation member 4 is electrically insulated from the multiple semiconductor elements 6.

As such, the heat dissipation member 4 in the semiconductor device 51 of embodiment 1 is electrically insulated from the multiple semiconductor elements 6, and therefore the presence of the heat dissipation member 4 does not cause electrical loss when the multiple semiconductor elements 6 are operating.

In addition, the heat dissipation member 4 is positioned an insulating distance away from the multiple semiconductor elements 6 to prevent dielectric breakdown in the sealing resin layer 8, which is a resin layer, when current is applied to the multiple semiconductor elements 6. Therefore, dielectric breakdown does not occur in the sealing resin layer 8 when current is applied to the multiple semiconductor elements.

On the other hand, the heat dissipation member 4 is cooled via the metal base plate 1 by the cooling action of the cooling mechanism 9. Therefore, the heat dissipation member 4 can perform a heat dissipation function by dissipating the heat accumulated in the sealing resin layer 8 when the multiple semiconductor elements 6 are energized, via a heat dissipation path including the heat dissipation member 4 and the metal base plate 1.

In other words, since the second main surface of the plate portion 4a of the heat dissipation member 4 is in contact with the sealing resin layer 8, the heat accumulated in the sealing resin layer 8 can be effectively dissipated by the above-mentioned heat dissipation function of the heat dissipation member 4.

In this way, the semiconductor device 51 of embodiment 1 can mitigate the effects of differences in thermal expansion coefficients between the sealing resin layer 8 and each of the components through the heat dissipation function of the heat dissipation member 4, thereby reliably avoiding interfacial peeling between the sealing resin layer 8 and each of the multiple semiconductor elements 6, the insulating circuit board 3, and the metal base plate 1.

As a result, the semiconductor device 51 of embodiment 1 can improve the reliability of the device without generating electrical losses when multiple semiconductor elements 6 are energized.

Furthermore, in the semiconductor device 51 of embodiment 1, since no restrictions are imposed on the arrangement of the multiple electrical connection members 7, the degree of freedom in the arrangement of the multiple electrical connection members 7 is relatively high.

In addition, the semiconductor device 51 of embodiment 1 can perform a double-sided cooling operation on the sealing resin layer 8 by simultaneously performing a first cooling operation in which the first main surface side of the sealing resin layer 8 is cooled by the heat dissipation path of the heat dissipation member 4, the metal base plate 1, and the cooling mechanism 9, and a second cooling operation in which the second main surface side of the sealing resin layer 8 is cooled by the heat dissipation path of the insulating circuit board 3, the metal base plate 1, and the cooling mechanism 9.

In this way, by performing the double-sided cooling operation including the first and second cooling operations described above, the semiconductor device 51 of embodiment 1 can effectively dissipate the heat accumulated in the sealing resin layer 8 and mitigate the effects of differences in thermal expansion coefficients between the sealing resin layer 8 and each component part.

In addition, the semiconductor device 51 of embodiment 1 can simplify the device configuration by performing the cooling operation of the above-mentioned double-sided cooling method using a single cooling mechanism 9.

Although the semiconductor device 51 of embodiment 1 has been shown to have a structure having multiple semiconductor elements 6, the same effect can be achieved with a structure having one semiconductor element 6. In other words, the semiconductor device 51 of embodiment 1 can be applied to a structure having at least one semiconductor element 6.

<Second Embodiment>
Fig. 4 is a plan view showing the top surface structure of a semiconductor device 52 according to a second embodiment of the present disclosure. An XYZ Cartesian coordinate system is depicted in Fig. 4. Note that Fig. 4 does not show the sealing resin layer 8 in order to clearly show the internal structure of the semiconductor device 52. In other words, Fig. 4 shows the state before resin sealing with the sealing resin layer 8 is performed.

In the following, components similar to those of the semiconductor device 51 shown in Figures 1 to 3 will be given the same symbols and descriptions will be omitted as appropriate, and the description will focus on the characteristic parts of the semiconductor device 52 of embodiment 2.

The semiconductor device 52 of embodiment 2 has a structure in which the heat dissipation member 4 is replaced with a heat dissipation member 42.

The heat dissipation member 42 is conductive and includes a plurality of pillars 42b (not shown) and a plate 42a disposed between the pillars 42b. As shown in FIG. 4, the plate 42a of the heat dissipation member 42 has a rectangular shape in plan view and is positioned so as to overlap most of the semiconductor elements 6 in plan view. Specifically, except for the bonding areas with the electrical connection members 7 on the first main surfaces of the semiconductor elements 6, the plate 42a of the heat dissipation member 42 overlaps the first main surfaces of the semiconductor elements 6 in plan view.

Like the heat dissipation member 4 of embodiment 1, the heat dissipation member 42 is arranged so that the second main surface of the plate portion 42a faces the first main surface of the intermediate structure. Therefore, the plate portion 42a of the heat dissipation member 42 is arranged at a distance in the +Z direction from the first main surfaces of the insulating circuit board 3 and the multiple semiconductor elements 6. In other words, the plate portion 42a of the heat dissipation member 42 is located on the first main surface side of the insulating circuit board 3 and the multiple semiconductor elements 6.

The plurality of pillars 42b are provided in a manner that they stand upright on the first main surface of the metal base plate 1, similar to the plurality of pillars 4b in embodiment 1. That is, the heat dissipation member 42 is provided on the first main surface of the metal base plate 1 in a manner that straddles the intermediate structure, similar to the heat dissipation member 4 in embodiment 1.

The heat dissipation member 42, like the heat dissipation member 4 in embodiment 1, is located away from the semiconductor elements 6 so that the sealing resin layer 8 between the heat dissipation member 42 and the semiconductor elements 6 does not undergo dielectric breakdown when the semiconductor elements 6 are energized. Furthermore, like the heat dissipation member 4 in embodiment 1, the heat dissipation member 42 is electrically insulated from the semiconductor elements 6.

In this configuration, heat generated when multiple semiconductor elements 6 are energized is transmitted throughout the entire semiconductor device 52 via the sealing resin layer 8.

In the semiconductor device 52 of the second embodiment, most of the first main surface of each of the plurality of semiconductor elements 6 faces the second main surface of the plate portion 42a. Therefore, the first cooling operation, which cools along a heat dissipation path including the heat dissipation member 42, the metal base plate 1, and the cooling mechanism 9, dissipates heat generated from the plurality of semiconductor elements 6 and propagated to the encapsulating resin layer 8, thereby minimizing the temperature rise in the region of the encapsulating resin layer 8 close to the plurality of semiconductor elements 6.

Therefore, like the semiconductor device 51 of embodiment 1, the semiconductor device 52 of embodiment 2 can improve the reliability of the device without generating electrical losses during operation of the multiple semiconductor elements 6.

In addition, the semiconductor device 52 of embodiment 2, like embodiment 1, can simplify the device configuration by performing the cooling operation of the above-mentioned double-sided cooling method using a single cooling mechanism 9.

In addition, the multiple semiconductor elements 6 generate heat when power is applied, making it easier for warping to occur in the warping areas of the metal base plate 1 that overlap with the multiple semiconductor elements 6 in a planar view.

On the other hand, the second main surface of the plate portion 42a of the heat dissipation member 42 is provided over a relatively large area, overlapping most of the first main surface of each of the multiple semiconductor elements 6 in a planar view, and multiple column portions 42b are provided on the first main surface of the metal base plate 1, so that warpage fluctuations in the above-mentioned warpage-occurring region of the metal base plate 1 can be suppressed mainly by the action of the column portions 42b.

As a result, the semiconductor device 52 of embodiment 2 can further improve the reliability of the device by suppressing warping of the metal base plate 1, which is a factor in causing warping of the entire device, and preventing interfacial peeling between the sealing resin layer 8 and the metal base plate 1 due to fluctuations in warping of the metal base plate 1.

In order to effectively suppress warpage fluctuations in the warpage-occurring region of the metal base plate 1, it is desirable that the second main surface of the plate portion 42a of the heat dissipation member 42 overlap in a planar view by at least half the total area of the first main surfaces of the multiple semiconductor elements 6. By providing the plate portion 42a with the above structure, the area and volume of the plate portion 42a are expanded, which is expected to enhance the warpage fluctuation suppression effect of the metal base plate 1.

In addition, the semiconductor device 52 of embodiment 2 can also be applied to a structure having at least one semiconductor element 6, as in embodiment 1.

<Third Embodiment>
5 is a cross-sectional view showing a cross-sectional structure of a semiconductor device 53 according to a third embodiment of the present disclosure. An XYZ orthogonal coordinate system is depicted in FIG. 5. Note that FIG. 5 corresponds to the AA cross section of the semiconductor device 51 shown in FIG.

In the following, parts similar to those of the semiconductor device 51 shown in Figures 1 to 3 will be given the same symbols and descriptions will be omitted as appropriate, and the description will focus on the characteristic features of the semiconductor device 53 of embodiment 3.

The semiconductor device 53 of embodiment 3 has a structure in which the heat dissipation member 4 is replaced with a heat dissipation member 43.

The heat dissipation member 43 is electrically conductive and includes multiple pillars 43b (not shown) and plate portions 43a provided between the multiple pillars 43b. The shape of the heat dissipation member 43 is substantially the same as the heat dissipation member 4 of embodiment 1, with the multiple pillars 43b corresponding to the multiple pillars 4b and the plate portions 43a corresponding to the plate portions 4a.

Therefore, similar to the heat dissipation member 4 of embodiment 1, the heat dissipation member 43 is provided at a distance from the semiconductor elements 6 so that the sealing resin layer 8 between the heat dissipation member 43 and the semiconductor elements 6 does not undergo dielectric breakdown when the semiconductor elements 6 are energized. Furthermore, similar to the heat dissipation member 4 of embodiment 1, the heat dissipation member 43 is electrically insulated from the semiconductor elements 6.

As mentioned above, the semiconductor device 53 uses a variety of components, such as multiple semiconductor elements 6, multiple electrical connection members 7, an insulating circuit board 3, and a metal base plate 1, each of which has a different thermal expansion coefficient.

The multiple electrical connection members 7 are made of a conductive first material and are electrically connected to the multiple semiconductor elements 6.

In embodiment 3, the constituent material of the heat dissipation member 43 is matched to the material used in the semiconductor device 53, thereby reducing the mismatch in thermal expansion coefficients within the semiconductor device 53.

For example, if the first material constituting the electrical connection member 7 is aluminum or copper, the first material constituting the heat dissipation member 43 is also aluminum or copper. By using a first material with good thermal conductivity, such as aluminum or copper, as the first material constituting the heat dissipation member 43, the sealing resin layer 8 can be cooled efficiently.

In this way, the semiconductor device 53 of embodiment 3 is characterized in that the constituent material of the heat dissipation member 43 is the same first material as the constituent material of the electrical connection member 7, which is made of a conductive first material. Examples of the first material include aluminum, copper, etc., as described above.

Like the heat dissipation member 4 in embodiment 1, the heat dissipation member 43 is positioned away from the semiconductor elements 6 so that the sealing resin layer 8 between the heat dissipation member 43 and the semiconductor elements 6 does not undergo dielectric breakdown when the semiconductor elements 6 are energized. Furthermore, like the heat dissipation member 4 in embodiment 1, the heat dissipation member 43 is electrically insulated from the semiconductor elements 6.

Therefore, like embodiment 1, the semiconductor device 53 of embodiment 3 can improve the reliability of the device without generating electrical losses when the multiple semiconductor elements 6 are operating.

In addition, the semiconductor device 53 of embodiment 3, like embodiment 1, can simplify the device configuration by performing the cooling operation of the above-mentioned double-sided cooling method using a single cooling mechanism 9.

Furthermore, in the semiconductor device 53 of embodiment 3, the constituent material of the electrical connection member 7, which is an electrical connection member, and the constituent material of the heat dissipation member 43 are both the same first material, so that each of the multiple electrical connection members 7 and the heat dissipation member 43 have the same thermal expansion coefficient.

As a result, the semiconductor device 53 of embodiment 3 can reduce the difference in thermal expansion coefficient between the plurality of electrical connection members 7 and the heat dissipation member 43 within the sealing resin layer 8 to "0." Therefore, the semiconductor device 53 of embodiment 3 can enhance the heat dissipation effect of the heat dissipation member 43 and efficiently cool the sealing resin layer 8 without being affected by the difference in thermal expansion coefficient between the plurality of electrical connection members 7 and the heat dissipation member 43 in the sealing resin layer 8.

In addition, the semiconductor device 53 of embodiment 3 can also be applied to a structure having at least one semiconductor element 6, as in embodiments 1 and 2.

<Fourth Embodiment>
FIG. 6 is a plan view showing the top surface structure of a semiconductor device 54 according to a fourth embodiment of the present disclosure. FIG. 7 is a cross-sectional view showing the CC cross-sectional structure of the semiconductor device 54 according to the fourth embodiment shown in FIG. 6. FIG. 8 is a cross-sectional view showing the DD cross-sectional structure of the semiconductor device 54 according to the fourth embodiment shown in FIG. 6. An XYZ orthogonal coordinate system is depicted in each of FIGS. 6 to 8. Note that the heat dissipation member 4 and the sealing resin layer 8 are omitted from FIG. 6 to clearly show the internal structure of the semiconductor device 54.

In the following, parts similar to those of the semiconductor device 51 shown in Figures 1 to 3 will be given the same symbols and descriptions will be omitted as appropriate, and the description will focus on the characteristic features of the semiconductor device 54 of embodiment 4.

The semiconductor device 54 of embodiment 4 has a structure in which a metal lead wiring member 12 and a conductive bonding material 14 are newly provided, and the heat dissipation member 4 is replaced with a heat dissipation member 44.

The heat dissipation member 44 is electrically conductive and includes multiple pillars 44b (not shown) and plate portions 44a disposed between the pillars 44b. The plate portions 44a of the heat dissipation member 44 are rectangular in plan view and have a relatively large heat dissipation member forming region R44, as shown in Figure 7.

As shown in Figures 7 and 8, the semiconductor device 54 of embodiment 4 further includes a metal lead wiring member 12 and multiple conductive bonding materials 14 between the intermediate structure and the heat dissipation member 44. The semiconductor device 54 of embodiment 4 includes, as the electrical connection member 7, multiple wires 13 that serve as linear connection members and a metal lead wiring member 12 that serves as a plate-shaped connection member.

The multiple conductive bonding materials 14 correspond to the multiple semiconductor elements 6, and the second main surface of the metal lead wiring member 12 is electrically connected to the multiple semiconductor elements 6 via the multiple conductive bonding materials 14. In other words, the metal lead wiring member 12 is bonded to the multiple semiconductor elements 6 by the multiple conductive bonding materials 14. In this way, there is a one-to-one correspondence between the multiple semiconductor elements 6 and the multiple conductive bonding materials 14. The conductive bonding materials 14 are made of solder, soft solder, or the like.

The metal lead wiring member 12, which is a plate-shaped connecting member, has a plate portion 12a that is rectangular in plan view, and a connection portion 12b that extends in the -Y direction from a portion of the -Y direction side of the plate portion 12a when viewed in the XY plane, as shown in Figure 6. The plate portion 12a is the main portion of the metal lead wiring member 12. In this way, the metal lead wiring member 12 is a plate-shaped connecting member whose main portion is configured in a plate shape.

As shown in Figure 8, the connection portion 12b extends in the -Z direction, and the lower end of the connection portion 12b is provided on the first main surface of the circuit pattern 5 of the insulating circuit board 3. Therefore, the metal lead wiring member 12 is electrically connected to the circuit pattern 5 via the connection portion 12b. Furthermore, the first main surface of the plate portion 12a and the intermediate connection member 21 are electrically connected via the wire 13, and the first main surface of the semiconductor element 6 and the intermediate connection member 21 are connected via the wire 13.

In this way, the metal lead wiring member 12, together with the multiple wires 13, the multiple semiconductor elements 6, and the circuit pattern 5 of the insulating circuit board 3, constitutes a main current circuit. In particular, the area of the plate portion 12a through which current flows between the multiple semiconductor elements 6 via the multiple conductive bonding materials 14 becomes the main wiring region R12, and it is expected that a relatively large current will flow in the main wiring region R12.

As shown in Figures 6 to 8, the area on the first main surface of the metal lead wiring member 12 that overlaps or is close to one of the multiple conductive bonding materials 14 in a plan view is the wire bonding area. Electrical connection is made to the intermediate connection member 21 via the wire 13 at at least one location within the wire bonding area.

As shown in Figure 7, the intermediate connection member 21 is electrically connected to the external electrode 11 via the buried connection wire 22. Therefore, the wire bonding region of the metal lead wiring member 12 is electrically connected to the external electrode 11 via the wire 13, the intermediate connection member 21, and the buried connection wire 22.

In Figure 7, the external electrode 11, intermediate connection member 21, and embedded connection wire 22 are shown as independent components, but a metal plate serving as the external electrode 11, intermediate connection member 21, and embedded connection wire 22 may also be insert-molded into the resin case 2.

The electrical connection between the metal lead wiring member 12 and the external electrode 11 is not limited to the configurations shown in Figures 6 to 8. For example, the following first to third connection configurations are possible.

The first connection mode is a mode in which the wire bonding area of the metal lead wiring member 12 is directly connected to the external electrode 11 by a wire.

The second connection mode is a mode in which a conductive bonding material such as solder or soft solder is used instead of the wire 13, and the wire bonding area of the metal lead wiring member 12 and the intermediate connection member 21 are electrically connected by the conductive bonding member.

The third connection mode is a mode in which the plate portion 12a is extended along the +X direction toward the side wall of the metal lead wiring member 12, and the plate portion 12a is brought into contact with the embedded connection wire 22 provided within the side wall of the resin case 2, thereby integrating the external electrode 11 and embedded connection wire 22 provided on the +X direction side with the plate portion 12a.

Hereinafter, in embodiment 4, a structure including an insulating circuit board 3, a plurality of semiconductor elements 6, a plurality of conductive bonding materials 10, a metal lead wiring member 12, and a plurality of conductive bonding materials 14 may be referred to as an "extended intermediate structure."

Like the heat dissipation member 4 of embodiment 1, the heat dissipation member 44 is positioned so that the second main surface of the plate portion 44a faces the first main surface of the expanded intermediate structure. Therefore, the plate portion 44a of the heat dissipation member 44 is positioned at a distance from the first main surfaces of the metal lead wiring member 12, the insulating circuit board 3, and the multiple semiconductor elements 6.

The heat dissipation member 44 is provided in a manner similar to the heat dissipation member 4 of embodiment 1, with multiple pillar portions 44b standing upright on the first main surface of the metal base plate 1. In other words, the heat dissipation member 44 is provided on the first main surface of the metal base plate 1 so as to straddle the extended intermediate structure.

The heat dissipation member 44 is located away from the metal lead wiring member 12 and the semiconductor elements 6 so that the sealing resin layer 8 between the heat dissipation member 44 and the semiconductor elements 6 does not undergo dielectric breakdown when the semiconductor elements 6 are energized. Furthermore, the heat dissipation member 44 is electrically insulated from the metal lead wiring member 12 and the semiconductor elements 6.

In addition, the heat dissipation member forming region R44 of the heat dissipation member 44 is arranged to include the main wiring region R12 of the metal lead wiring member 12 in a planar view. In other words, the heat dissipation member forming region R44 is wider than the main wiring region R12 and includes the entire main wiring region R12 in a planar view.

In the structure of the semiconductor device 54 shown in Figures 6 to 8, the bonding area between the first main surface of the plurality of semiconductor elements 6 and the first main surface of the plate portion 12a by the plurality of conductive bonding materials 14 is larger than that of a wiring structure using linear connecting members such as wires, and therefore, a large amount of heat is transmitted when the plurality of semiconductor elements 6 are electrically connected.

In addition, the volume of the metal lead wiring member 12, which is a plate-shaped connecting member, is larger than the volume of linear connecting members such as the wire 13, and therefore has a large amount of thermal expansion.As a result, peeling occurs at the interface between the end of the metal lead wiring member 12 and the sealing resin layer 8, and cracks in the sealing resin layer 8 are likely to occur starting from this peeling point.

If a crack that occurs in the sealing resin layer 8 propagates to one of the multiple semiconductor elements 6, it can damage that semiconductor element 6, resulting in a decrease in the reliability of the device.

However, the semiconductor device 54 of embodiment 4 cools the sealing resin layer 8 through a heat dissipation path including the heat dissipation member 44, thereby suppressing thermal expansion of the metal lead wiring member 12, preventing peeling between the end of the metal lead wiring member 12 and the sealing resin layer 8, and maintaining high reliability of the device.

In particular, as mentioned above, the heat dissipation member forming region R44 of the plate portion 44a includes the main wiring region R12 of the metal lead wiring member 12, and since the heat dissipation member forming region R44 is wider than the main wiring region R12, thermal expansion of the metal lead wiring member 12 can be effectively suppressed.

In this configuration, when the multiple semiconductor elements 6 are energized, heat from the multiple semiconductor elements 6 and the metal lead wiring member 12 is propagated throughout the semiconductor device 54 via the sealing resin layer 8.

In the semiconductor device 54 of embodiment 4, a large portion of the first main surface of each of the plurality of semiconductor elements 6 faces the second main surface of the plate portion 44a, and the heat dissipation member forming region R44 is positioned to include the main wiring region R12 of the metal lead wiring member 12 in a planar view. Therefore, the first cooling operation, which cools via a heat dissipation path including the heat dissipation member 44, the metal base plate 1, and the cooling mechanism 9, dissipates heat generated from the plurality of semiconductor elements 6 and the metal lead wiring member 12 and propagated to the encapsulating resin layer 8, thereby minimizing the temperature rise in the region of the encapsulating resin layer 8 near the plurality of semiconductor elements 6 and the metal lead wiring member 12.

Therefore, like the semiconductor device 51 of embodiment 1, the semiconductor device 54 of embodiment 4 can improve the reliability of the device without generating electrical losses during operation of the multiple semiconductor elements 6.

In addition, the semiconductor device 54 of embodiment 4, like embodiment 1, can simplify the device configuration by performing the cooling operation of the above-mentioned double-sided cooling method using a single cooling mechanism 9.

On the other hand, since the metal lead wiring member 12, which is a plate-shaped connecting member, has a plate portion 12a as its main portion, a relatively large current can flow in the main wiring region R12 of the plate portion 12a when multiple semiconductor elements 6 are energized. In other words, the semiconductor device 54 of embodiment 4 can pass a relatively large current.

However, in the semiconductor device 54 of embodiment 4, a relatively large current flows through the main wiring region R12, making it more susceptible to peeling that originates at the interface between the plate portion 12a of the metal lead wiring member 12 and the encapsulating resin layer 8. When this peeling occurs, defects in the multiple semiconductor elements 6 are likely to occur, such as damage to some of the multiple semiconductor elements 6.

In the semiconductor device 54 of embodiment 4, the plate portion 44a of the heat dissipation member 44 overlaps the plate portion 12a of the metal lead wiring member 12 in a planar view, so that the metal lead wiring member 12 can be cooled by a first cooling operation that cools the metal lead wiring member 12 through a heat dissipation path including the heat dissipation member 44, thereby suppressing the above-mentioned peeling phenomenon.

In particular, the plate portion 44a of the heat dissipation member 44 in embodiment 4 includes the main wiring region R12 of the metal lead wiring member 12 in a planar view, thereby allowing the metal lead wiring member 12 to be cooled more effectively.

As a result, the semiconductor device 54 of embodiment 4 can reliably avoid malfunctions in multiple semiconductor elements 6 and improve the reliability of devices that pass relatively large currents.

In addition, since the metal lead wiring member 12 has a relatively large bonding area with multiple semiconductor elements 6 via the conductive bonding material 14, the semiconductor device 54 of embodiment 4 can achieve a large current and a long life.

Furthermore, since the metal lead wiring member 12, which is a plate-shaped connecting member, includes the main wiring region R12, a relatively large current flows through the main wiring region R12 when multiple semiconductor elements 6 are energized, resulting in a large amount of heat generation.

The plate portion 44a of the heat dissipation member 44 in embodiment 4 is positioned to include the main wiring region R12 in the metal lead wiring member 12 in a planar view, so that the main wiring region R12 can be effectively cooled by the first cooling operation that cools through a heat dissipation path that includes the plate portion 44a.

As a result, the semiconductor device 54 of embodiment 4 can reliably avoid problems associated with heat generation in the main wiring region R12, thereby improving the reliability of the semiconductor device 54, which passes a relatively large current.

In addition, the semiconductor device 54 of embodiment 4 can also be applied to a structure having at least one semiconductor element 6, as in embodiments 1 to 3.

<Fifth Embodiment>
9 is a cross-sectional view showing a cross-sectional structure of a semiconductor device 55 according to a fifth embodiment of the present disclosure. An XYZ orthogonal coordinate system is depicted in Fig. 9. Fig. 9 corresponds to the AA cross section of the semiconductor device 51 shown in Fig. 1.

In the following, parts similar to those of the semiconductor device 51 shown in Figures 1 to 3 will be given the same symbols and descriptions will be omitted as appropriate, and the description will focus on the characteristic features of the semiconductor device 55 of embodiment 5.

The semiconductor device 55 of embodiment 5 is characterized by using a plurality of wires 13, which are a plurality of linear connecting members, as the electrical connecting members 7 for a plurality of semiconductor elements 6. The wires 13 are generally made of a metal material with low electrical resistance, such as aluminum or copper.

The multiple wires 13, which are multiple linear connecting members, include a main wire 13m that electrically connects between multiple semiconductor elements 6. This main wire 13m serves as the main current wiring member.

In this way, the multiple wires 13, together with the multiple semiconductor elements 6 and the circuit pattern 5 of the insulating circuit board 3, form a main current circuit. Of the multiple wires 13, it is expected that a relatively large current will flow through the main wire 13m, which functions as a main current wiring member that passes current between the multiple semiconductor elements 6.

Incidentally, both ends of each of the multiple wires 13, including the main wire 13m, are joined to the object to be joined by ultrasonic wire bonding, which is an ultrasonic joining process. In the semiconductor device 55 shown in Figure 9, the object to be joined is the first main surface of either the intermediate connecting member 21 or one of the multiple semiconductor elements 6. In this way, both ends of the multiple wires 13 are joined to the object to be joined as joining ends by ultrasonic bonding.

Therefore, the manufacturing method of the semiconductor device 55 of embodiment 5 includes the following steps (a) and (b) as part thereof.

Step (a) is a step of placing an intermediate structure including an insulating circuit board 3 and multiple semiconductor elements 6 on the first main surface of the metal base plate 1.

Step (b) is a step of performing an ultrasonic bonding process to bond both ends of each of the plurality of wires 13 to a bonding object. Here, the bonding object includes the first main surface of any of the plurality of semiconductor elements 6 or the first main surfaces of the plurality of intermediate connection members 21. Therefore, step (b) includes a step of performing an ultrasonic bonding process to bond one end of each of the plurality of wires 13 to any of the plurality of semiconductor elements 6.

For example, ultrasonic bonding is performed to bond one end of the main wire 13m to the first main surface of one of the plurality of semiconductor elements 6, and the other end of the main wire 13m to the first main surface of the other of the plurality of semiconductor elements 6. In this case, both ends of the main wire 13m become bonding ends.

The above step (a) is performed using an existing manufacturing process, and the above step (b) is performed by performing an ultrasonic wire bonding process, and the ends of each of the multiple wires 13 subjected to the ultrasonic bonding process in the above step (b) become bonded ends.

Hereinafter, in embodiment 5, a structure including an insulating circuit board 3, multiple semiconductor elements 6, and multiple wires 13 may be referred to as an "extended intermediate structure."

Similar to the heat dissipation member 43 of embodiment 3, the heat dissipation member 45 is positioned so that the plate portion 45a overlaps most of the multiple semiconductor elements 6 when viewed in a plan view.

Like the heat dissipation member 4 of embodiment 1, the heat dissipation member 45 is positioned so that the second main surface of the plate portion 45a of the heat dissipation member 45 faces the first main surface of the extended intermediate structure. Therefore, the plate portion 45a of the heat dissipation member 45 is positioned at a distance from the first main surfaces of the insulating circuit board 3 and the multiple semiconductor elements 6.

The heat dissipation member 45 is provided in a manner similar to the heat dissipation member 4 of embodiment 1, with multiple pillar portions 45b standing upright on the first main surface of the metal base plate 1. In other words, the heat dissipation member 45 is provided on the first main surface of the metal base plate 1 so as to straddle the extended intermediate structure.

In the semiconductor device 55 of embodiment 5, the heat dissipation member 45 is located away from the main wire 13m and the multiple semiconductor elements 6 so that the sealing resin layer 8 between the heat dissipation member 45 and the multiple semiconductor elements 6 does not undergo dielectric breakdown when the multiple semiconductor elements 6 are energized. Furthermore, the heat dissipation member 45 is electrically insulated from the main wire 13m and the multiple semiconductor elements 6.

In addition, the heat dissipation member forming region R45 in the center of the heat dissipation member 45 is positioned to include the main wire 13m in a planar view. In other words, the main wire 13m is present within the heat dissipation member forming region R45 in a planar view.

In the semiconductor device 55 of embodiment 5 shown in Figure 9, a relatively large current flows through the main wire 13m that electrically connects multiple semiconductor elements 6 when the multiple semiconductor elements 6 are energized.

As a result, peeling occurs at the interface between the main wire 13m and the sealing resin layer 8, which tends to cause cracks in the sealing resin layer 8 to occur starting from this peeling point.

If a crack that occurs in the sealing resin layer 8 propagates to one of the multiple semiconductor elements 6, it can damage that semiconductor element 6, resulting in a decrease in the reliability of the device.

In the semiconductor device 55 of embodiment 5, the heat dissipation member forming region R45 is set to include the main wire 13m in a planar view.

In a semiconductor device 55 configured in this manner, heat generated when current is applied to the multiple semiconductor elements 6 and main wires 13m is propagated throughout the entire semiconductor device 55 via the encapsulating resin layer 8. At this time, the first cooling operation via a heat dissipation path including the heat dissipation member 45, the metal base plate 1, and the cooling mechanism 9 dissipates the heat generated from the multiple semiconductor elements 6 and main wires 13m and propagated to the encapsulating resin layer 8, thereby minimizing the temperature rise in the area of the encapsulating resin layer 8 close to the multiple semiconductor elements 6 and main wires 13m.

Therefore, like the semiconductor device 51 of embodiment 1, the semiconductor device 55 of embodiment 5 can improve the reliability of the device without generating electrical losses when the multiple semiconductor elements 6 are operating.

In addition, the semiconductor device 55 of embodiment 5, like embodiment 1, can simplify the device configuration by performing double-sided cooling operation using a single cooling mechanism 9.

In the semiconductor device 55 of embodiment 5, the joint ends of each of the multiple wires 13, which are multiple linear connecting members, may become disconnected and electrically disconnected from the multiple semiconductor elements 6 due to thermal expansion of the sealing resin layer 8.

In other words, when the encapsulating resin layer 8 thermally expands, the difference in thermal expansion coefficient between the semiconductor element 6 and the encapsulating resin layer 8 may cause stress at the joint between the semiconductor element 6 and the multiple wires 13, potentially causing the wires 13 to break.

The semiconductor device 55 of embodiment 5 can avoid the phenomenon in which any of the multiple wires 13 becomes disconnected by cooling the heat accumulated in the sealing resin layer 8 through a first cooling operation using a heat dissipation path including the plate portion 45a of the heat dissipation member 45, thereby improving the reliability of the semiconductor device.

In other words, the semiconductor device 55 of embodiment 5 cools the heat accumulated in the sealing resin layer 8 due to the presence of the heat dissipation member 45 provided inside the sealing resin layer 8, thereby suppressing expansion of the sealing resin layer 8 and preventing breakage of the wire 13.

In addition, the semiconductor device 55 of embodiment 5 uses multiple wires 13 as electrical connection members, allowing for a high degree of wiring freedom. Therefore, flexible circuit design can be performed for the semiconductor device 55.

Since the multiple wires 13 include a main wire 13m which serves as the main current wiring member, a relatively large current flows through the main wire 13m when the multiple semiconductor elements 6 are energized, resulting in a large amount of heat generation.

In the semiconductor device 55 of embodiment 5, the heat dissipation member forming region R45 in the plate portion 45a of the heat dissipation member 45 is positioned to include the main wire 13m in a planar view. Therefore, the main wire 13m can be effectively cooled by the first cooling operation via the heat dissipation path including the column portion 45b.

As a result, the semiconductor device 55 of embodiment 5 can reliably avoid problems associated with heat generation in the main wire 13m and improve the reliability of devices that pass relatively large currents through the main wire 13m.

Furthermore, the semiconductor device 55 of embodiment 5, which is manufactured using a manufacturing method including the above-mentioned steps (a) and (b), can ensure a highly stable electrical connection with any of the multiple semiconductor elements 6 at the joint ends of each of the multiple wires 13, which constitute the multiple linear connecting members, by the above-mentioned step (b).

In the structure shown in Figure 9, each of the multiple wires 13 is bonded to one of the multiple semiconductor elements 6 in single wiring units, but they may also be bonded to one of the multiple semiconductor elements 6 in multiple wiring units. Furthermore, when bonding multiple wiring units, they may be bonded using ribbon-shaped wiring in which multiple wirings are arranged.

In addition, the semiconductor device 55 of embodiment 5 can also be applied to a structure having at least one semiconductor element 6, as in embodiments 1 to 4.

Sixth Embodiment
10 is a cross-sectional view showing a cross-sectional structure of a semiconductor device 56 according to a sixth embodiment of the present disclosure. An XYZ orthogonal coordinate system is depicted in Fig. 10. Fig. 10 corresponds to the A-A cross section of the semiconductor device 51 shown in Fig. 1.

In the following, parts similar to those of the semiconductor device 51 shown in Figures 1 to 3 will be given the same symbols and descriptions will be omitted as appropriate, and the description will focus on the characteristic parts of the semiconductor device 56 of embodiment 6.

The semiconductor device 56 of embodiment 6 has a structure in which multiple semiconductor elements 6 are replaced with multiple SiC semiconductor elements 60.

In this configuration, heat generated when the multiple SiC semiconductor elements 60 are energized is propagated throughout the entire semiconductor device 56 via the encapsulating resin layer 8. Each of the multiple SiC semiconductor elements 60 is made of silicon carbide (SiC), and generates a greater amount of heat when energized than semiconductor elements made of Si. As a result, the operating temperature of the multiple SiC semiconductor elements 60 increases at a greater rate than the operating temperature of the multiple semiconductor elements 6.

As in embodiment 1, the heat dissipation member 4 is positioned away from the multiple SiC semiconductor elements 60 so that the sealing resin layer 8 between the heat dissipation member 4 and the multiple SiC semiconductor elements 60 does not undergo dielectric breakdown when the multiple SiC semiconductor elements 60 are energized. Furthermore, the heat dissipation member 4 is electrically insulated from the multiple SiC semiconductor elements 60.

Therefore, like embodiment 1, the semiconductor device 56 of embodiment 6 can improve the reliability of the device without generating electrical losses when multiple SiC semiconductor elements 60 are energized.

The semiconductor device 56 of embodiment 6 has multiple SiC semiconductor elements 60, and therefore basically has the SiC operating characteristics of being able to pass a relatively large current, operating at high frequencies, operating in high-temperature environments, having high insulation properties, and a low off-state voltage.

In addition, the semiconductor device 56 of embodiment 6, like embodiment 1, can simplify the device configuration by performing the cooling operation of the above-mentioned double-sided cooling method using a single cooling mechanism 9.

In the semiconductor device 56 of embodiment 6, the multiple SiC semiconductor elements 60 generate a relatively large amount of heat when powered on, resulting in a rise in operating temperature. This increases the impact of thermal stress caused by differences in the thermal expansion coefficients between the components of the semiconductor device 56, which can reduce the reliability of the device.

On the other hand, the semiconductor device 56 of embodiment 6 has a heat dissipation function that dissipates heat accumulated in the sealing resin layer 8 when multiple SiC semiconductor elements 60 are energized through a heat dissipation path including the heat dissipation member 4 and the metal base plate 1, thereby suppressing thermal expansion of the sealing resin layer 8.

As a result, the semiconductor device 56 of embodiment 6 can minimize the effects of thermal stress caused by differences in thermal expansion coefficients between the components of the semiconductor device 56, thereby improving the reliability of devices having the above-mentioned SiC operating characteristics.

In addition, in embodiment 6 shown in Figure 10, a structure in which multiple SiC semiconductor elements 60 are provided in the structure of embodiment 1 shown in Figures 1 to 3 is shown, but it is of course possible to modify the structure to one in which multiple SiC semiconductor elements 60 are provided in the structures of embodiments 2 to 5.

Furthermore, the semiconductor device 56 of embodiment 6 can be applied to a structure having at least one SiC semiconductor element 60, as in embodiments 1 to 5.

Although the present disclosure has been described in detail, the above description is illustrative in all respects and does not limit the present disclosure. It is understood that countless variations not illustrated can be envisioned without departing from the scope of the present disclosure.

1 Metal base plate, 2 Resin case, 3 Insulated circuit board, 4, 42-45 Heat dissipation member, 4a, 42a-45a Plate portion, 4b, 42b-45b Pillar portion, 5 Circuit pattern, 6 Semiconductor element, 7 Electrical connection member, 8 Sealing resin layer, 9 Cooling mechanism, 10, 14 Conductive bonding material, 11 External electrode, 12 Metal lead wiring member, 13 Wire, 13m Main wire, 21 Intermediate connection member, 22 Buried connection wire, 30 Insulating layer, 51-56 Semiconductor device, 60 SiC semiconductor element.

Claims (10)

a base plate having a first major surface and a second major surface;
an insulating circuit board provided on a first main surface side of the base plate and having a circuit pattern;
at least one semiconductor element provided on a first main surface side of the insulating circuit board;
a heat dissipation member that is electrically conductive and includes a plurality of pillar portions and plate portions provided between the plurality of pillar portions, the plate portions being located on a first main surface side of the insulating circuit board and the at least one semiconductor element, and the plurality of pillar portions being provided in an upright position on the first main surface of the base plate;
a resin layer provided on the first main surface of the base plate to cover the insulating circuit board, the at least one semiconductor element, and the heat dissipation member,
the heat dissipation member is provided at a distance from the at least one semiconductor element so that dielectric breakdown does not occur in the resin layer between the heat dissipation member and the at least one semiconductor element during operation of the at least one semiconductor element;
the heat dissipation member is electrically insulated from the at least one semiconductor element;
Semiconductor device. 2. The semiconductor device according to claim 1,
the plate portion of the heat dissipation member is provided so as to overlap with the at least one semiconductor element in a plan view;
Semiconductor device. 2. The semiconductor device according to claim 1 ,
an electrical connection member made of a first material having electrical conductivity and electrically connected to the at least one semiconductor element;
the resin layer is provided to further cover the electrical connection member,
The heat dissipation member is made of the first material.
Semiconductor device. 2. The semiconductor device according to claim 1 ,
Further, an electrical connection member is provided which is electrically conductive and electrically connected to the at least one semiconductor element,
the electrical connection member includes a plate-shaped connection member having a main portion configured in a plate shape,
the plate portion of the heat dissipation member overlaps with the plate-shaped connecting member in a plan view,
the plate-shaped connecting member is joined to the at least one semiconductor element via a conductive bonding material,
the heat dissipation member is provided at a distance from the plate-shaped connecting member so that dielectric breakdown does not occur in the resin layer between the heat dissipation member and the plate-shaped connecting member during operation of the at least one semiconductor element.
Semiconductor device. 5. The semiconductor device according to claim 4,
the at least one semiconductor device includes a plurality of semiconductor devices;
the plate-shaped connecting member includes a main wiring region through which current flows between the plurality of semiconductor elements,
the plate portion of the heat dissipation member is disposed to include the main wiring region in plan view;
Semiconductor device. 2. The semiconductor device according to claim 1 ,
Further, an electrical connection member is provided which is electrically conductive and electrically connected to the at least one semiconductor element,
the electrical connection members are a plurality of linear connection members,
each of the plurality of linear connecting members has a joining end portion to be joined to the at least one semiconductor element;
Semiconductor device. 7. The semiconductor device according to claim 6,
the at least one semiconductor device includes a plurality of semiconductor devices;
the plurality of linear connection members include a main current wiring member that passes current between the plurality of semiconductor elements,
the plate portion of the heat dissipation member is disposed to include the main current wiring member in a plan view.
Semiconductor device. 8. The semiconductor device according to claim 1,
The at least one semiconductor element includes at least one SiC semiconductor element each made of SiC.
Semiconductor device. 8. The semiconductor device according to claim 1,
the base plate includes a metal base plate;
The semiconductor device includes:
a cooling mechanism provided on the second main surface side of the metal base plate to cool the metal base plate;
Semiconductor device. A method for manufacturing a semiconductor device, comprising:
The semiconductor device includes the semiconductor device according to claim 6,
(a) placing an intermediate structure including the insulating circuit board and the at least one semiconductor element on a first main surface of the base plate;
(b) performing an ultrasonic bonding process to bond one end of each of the plurality of linear connecting members to any one of the at least one semiconductor element;
After step (b) is performed, one end of each of the plurality of linear connecting members becomes the joint end portion.
A method for manufacturing a semiconductor device.