JP7782159B2 - Short-circuit fault detection device and power conversion device - Google Patents

Description

The present invention relates to a short-circuit fault detection device and a power conversion device equipped with the same.

In power conversion devices that drive loads such as motors, excessive currents can flow through the semiconductor switching elements that make up the power conversion device. If such excessive currents flow for a long period of time, the semiconductor switching elements may be destroyed. Therefore, power conversion devices are equipped with short-circuit fault detection devices that detect excessive currents flowing through the semiconductor switching elements and shut down the power conversion device.

This type of short-circuit fault detection device uses shunt resistors, current transformers (CTs), or Rogowski coils to detect the current flowing through the semiconductor switching elements. Among these, Rogowski coils have the advantage of being coreless, allowing for the short-circuit fault detection device to be made smaller, and also being able to measure large currents.

The technology disclosed in Patent Document 1 is a power conversion device that has multiple arms, each containing a semiconductor switching element, and supplies power to a load via the multiple arms. Each of the multiple arms is provided with a Rogowski coil and a short-circuit detection circuit based on the output voltage of the Rogowski coil, and short-circuit faults in the power conversion device are detected.

Japanese Patent Application Laid-Open No. 2019-216540

The technology disclosed in the aforementioned Patent Document 1 requires a Rogowski coil and short-circuit detection circuit for each of the multiple arms, which increases costs and leads to the problem of the overall size of the power conversion device. Furthermore, in power conversion devices equipped with high-speed semiconductor switching elements such as SiC, the time gradient di/dt of the short-circuit current during a load short circuit is on the order of μs, while the time gradient di/dt of the short-circuit current during an arm short circuit is on the order of ns. This means that the number of turns of the Rogowski coil optimal for detecting load short circuits and arm short circuits differs significantly. This requires a design that can detect both load short circuits and arm short circuits, which leads to problems such as larger Rogowski coils and larger, more complex short-circuit detection circuits.

This invention was made in consideration of the above-described problems, and aims to provide a technical means for detecting short-circuit faults in a power conversion device while avoiding the overall size and complexity of the power conversion device.

One aspect of the present invention is a short-circuit fault detection device for a power conversion device that supplies power to a load via two or more arms, each of which includes a semiconductor switching element. The short-circuit fault detection device includes a Rogowski coil inserted in both a first current path through which a first current flows commonly to a first arm of the two or more arms and the load, and a second current path through which a second current flows commonly to a second arm of the two or more arms and the load, and detects a short-circuit fault in an arm of the power conversion device or the load based on a detection signal obtained from the Rogowski coil.

Another aspect of the present invention is a power conversion device that supplies power to a load via two or more arms, each of which includes a semiconductor switching element. A short-circuit fault detection device is provided in a first arm and a second arm of the two or more arms. The short-circuit fault detection device includes a Rogowski coil inserted in both a first current path through which a first current flows commonly to the first arm and the load, and a second current path through which a second current flows commonly to the second arm and the load, and a short-circuit determination circuit that detects a short-circuit fault in an arm of the power conversion device or the load based on a detection signal obtained from the Rogowski coil.

According to this invention, short-circuit faults are detected using a Rogowski coil and a short-circuit determination circuit provided in the first arm and second arm, making it possible to detect short-circuit faults in a power conversion device while avoiding the overall size and complexity of the power conversion device.

1 is a circuit diagram showing the configuration of a power conversion device including a short-circuit fault detection device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing the operation of the power conversion device. FIG. 4 is a waveform diagram showing the operation at normal turn-on in the embodiment. FIG. 2 is a circuit diagram showing the operation of the embodiment at normal turn-on. FIG. 4 is a waveform diagram showing the operation when an arm short circuit occurs in the embodiment. FIG. 4 is a circuit diagram showing the operation of the embodiment when an arm short circuit occurs. 4 is a waveform diagram showing the operation of the embodiment when a load short circuit occurs. FIG. FIG. 2 is a circuit diagram showing the operation of the embodiment when a load short circuit occurs. FIG. 10 is a circuit diagram showing the configuration of a power conversion device including a short-circuit fault detection device according to another embodiment of the present invention. FIG. 2 is a side view showing an example of mounting the power conversion device shown in FIG. 1 . FIG. FIG. 10 is a side view showing an example of mounting the power conversion device shown in FIG. 9 . FIG. 10 is a plan view showing another implementation example of the power conversion device shown in FIG. 9 . FIG. FIG. 16 is a side view showing a modification of the mounting example of FIGS. 14 and 15.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing the configuration of a power conversion device 100 including a short-circuit fault detection device 50 according to an embodiment of the present invention. The power conversion device 100 corresponds to one phase of an inverter and includes an upper arm 110, which is a first arm, and a lower arm 120, which is a second arm. The upper arm 110 and the lower arm 120 are connected in series between a high-potential power supply line 101P connected to the positive pole of a power supply (not shown) and a low-potential power supply line 101N connected to the negative pole of the power supply, with their common connection point serving as an AC output terminal 102 of the power conversion device 100. A load Z, such as a motor winding, is connected to the AC output terminal 102. The power conversion device 100 configures an inverter by connecting the upper arms 110 and the lower arms 120 for multiple phases in parallel between the high-potential power supply line 101P and the low-potential power supply line 101N.

The upper arm 110 is composed of a semiconductor switching element Q1 and a diode D1 connected in anti-parallel to it. Similarly, the lower arm 120 is composed of a semiconductor switching element Q2 and a diode D2 connected in anti-parallel to it. The semiconductor switching elements Q1 and Q2 are transistors such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and are composed of wide bandgap semiconductor elements whose main material is at least one of silicon carbide, gallium nitride, gallium oxide, and diamond.

The power conversion device 100 also has an upper arm gate drive circuit 10 that drives the semiconductor switching element Q1 of the upper arm 110 on/off based on an upper arm control signal supplied from a control unit (not shown), and a lower arm gate drive circuit 20 that drives the semiconductor switching element Q2 of the lower arm 120 on/off based on a lower arm control signal supplied from the control unit. The power conversion device 100 supplies AC power to the load Z via the upper arm 110 and the lower arm 120, which include semiconductor switching elements Q1 and Q2 that are driven on/off by the upper arm gate drive circuit 10 and the lower arm gate drive circuit 20.

In the power conversion device 100 shown in FIG. 1, for example, if a short-circuit fault occurs in the upper arm 110, an arm short-circuit current will flow in both the upper arm 110 and the lower arm 120 when the lower arm 120 is turned on. Furthermore, if a short-circuit fault occurs in the lower arm 120, an arm short-circuit current will flow in both the upper arm 110 and the lower arm 120 when the upper arm 110 is turned on. Furthermore, in the power conversion device 100, if a short-circuit fault occurs in the load Z, a load short-circuit current will flow in the upper arm 110 or the lower arm 120.

If such an arm short-circuit current or load short-circuit current flows through the upper arm 110 or the lower arm 120 for a long period of time, there is a risk that the semiconductor switching element Q1 of the upper arm 110 or the semiconductor switching element Q2 of the lower arm 120 will be destroyed. Therefore, the power conversion device 100 is provided with a short-circuit fault detection device 50 that detects the occurrence of an arm short-circuit or load short-circuit and stops the driving of semiconductor switching element Q1 by the upper arm gate drive circuit 10 and the driving of semiconductor switching element Q2 by the lower arm gate drive circuit 20.

The short-circuit fault detection device 50 has a Rogowski coil 40 provided for the upper arm 110 (first arm) and the lower arm 120 (second arm), and a short-circuit determination circuit 30 that detects a short-circuit fault in the power conversion device 100 based on the induced voltage Vm, which is a detection signal obtained from the Rogowski coil 40.

In this embodiment, the Rogowski coil 40 is inserted into both the first current path 103P, through which a first current flows commonly to the upper arm 110 and the load Z, and the second current path 103N, through which a second current flows commonly to the lower arm 120 and the load Z. Specifically, as described above, the upper arm 110 and the lower arm 120 are connected in series between the high-potential power supply line 101P and the low-potential power supply line 101N, and the load Z is connected to the AC output terminal 102, which is the common connection point of the upper arm 110 and the lower arm 120. The first current path 103P is the current path between the upper arm 110 and the AC output terminal 102, and the second current path 103N is the current path between the lower arm 120 and the AC output terminal 102. The first current path 103P and the second current path 103N are inserted through the Rogowski coil 40 so that the direction from the upper arm 110 of the first current path 103P toward the load Z and the direction from the lower arm 120 of the second current path 103N toward the load Z are the same within the Rogowski coil 40.

In this configuration, when a current flows through the first current path 103P or the second current path 103N, a circular magnetic field is generated centered on that current path. When the current flowing through that current path changes, an induced voltage Vm proportional to the time gradient di/dt of that current is output from the Rogowski coil 40. This induced voltage Vm is the detection signal obtained from the Rogowski coil 40.

The short-circuit determination circuit 30 includes an induced voltage detection circuit 31, a zero-voltage period determination circuit 32, a voltage value comparison circuit 33, and an OR gate 34.

The induced voltage detection circuit 31 detects the induced voltage value Vm, which is a detection signal obtained from the Rogowski coil 40, and outputs it to the voltage value comparison circuit 33. The induced voltage detection circuit 31 also outputs a zero voltage period signal E0 during the period when the induced voltage value Vm is zero voltage, specifically, while the absolute value of the induced voltage value Vm is less than a small threshold value.

The zero voltage period determination circuit 32 is a circuit that detects an arm short circuit based on the zero voltage period signal E0. More specifically, in this embodiment, if an abnormality such as a short circuit or false turn-on occurs in one of the upper arm 110 or the lower arm 120, causing an arm short circuit, when the other arm is turned on, currents of the same magnitude but opposite polarity continue to flow through the first current path 103P and the second current path 103N for a long period of time, causing the induced voltage Vm obtained from the Rogowski coil 40 to remain at zero voltage for a long period of time. Therefore, the zero voltage period determination circuit 32 outputs an arm short circuit detection signal E1 indicating the occurrence of an arm short circuit when the zero voltage period signal E0 continues for a predetermined reference time Δt0 or longer from the start of turn-on of the upper arm 110 or the lower arm 120.

The voltage value comparison circuit 33 is a circuit that detects a load short circuit based on the induced voltage value Vm. More specifically, in this embodiment, when a short circuit occurs in the load Z, a current greater than normal flows through the first current path 103P or the second current path 103N, and the current value increases over time, causing an induced voltage Vm greater than normal to be output from the Rogowski coil 40. Therefore, the voltage value comparison circuit 33 outputs a load short circuit detection signal E2 when the absolute value of the induced voltage Vm detected by the induced voltage detection circuit 31 exceeds the reference value V0, which is the second threshold value.

When an arm short-circuit detection signal E1 or a load short-circuit detection signal E2 is output, the OR gate 34 outputs a short-circuit detection signal E to the upper arm gate drive circuit 10 and the lower arm gate drive circuit 20, stopping the upper arm gate drive circuit 10 from driving the semiconductor switching element Q1 and the lower arm gate drive circuit 20 from driving the semiconductor switching element Q2.

The upper arm gate drive circuit 10 includes a drive circuit 11, a short-circuit current interruption circuit 12, and a switching circuit 13. An upper arm control signal is supplied to the drive circuit 11 to instruct the semiconductor switching element Q1 to be on or off. When an upper arm control signal instructing the semiconductor switching element Q1 to be on is supplied, the drive circuit 11 outputs a gate-source voltage VGS(Q1) that turns on the semiconductor switching element Q1. When an upper arm control signal instructing the semiconductor switching element Q1 to be off is supplied, the drive circuit 11 outputs a gate-source voltage VGS(Q1) that turns off the semiconductor switching element Q1. The short-circuit current interruption circuit 12 outputs a gate-source voltage VGS(Q1) that can interrupt the flow of short-circuit current through the semiconductor switching element Q1. When the short-circuit detection signal E is not output, the switching circuit 13 supplies the gate-source voltage VGS(Q1) output from the drive circuit 11 between the gate and source of the semiconductor switching element Q1. Furthermore, when a short-circuit detection signal E is output, the switching circuit 13 supplies the gate-source voltage VGS (Q1) output from the short-circuit current interruption circuit 12 between the gate and source of the semiconductor switching element Q1.

The lower arm gate drive circuit 20 includes a drive circuit 21 similar to those provided in the upper arm gate drive circuit 10, a short-circuit current interruption circuit 22, and a switching circuit 23. When a short-circuit detection signal E is not output, the switching circuit 23 supplies the gate-source voltage VGS(Q2) output from the drive circuit 21 between the gate and source of the semiconductor switching element Q2. When a short-circuit detection signal E is output, the switching circuit 23 supplies the gate-source voltage VGS(Q2) output from the short-circuit current interruption circuit 22 between the gate and source of the semiconductor switching element Q1.

Next, the operation of this embodiment will be described. Figure 2 is a circuit diagram showing a typical example of operation of the power conversion device 100. In the example shown in Figure 2, power is supplied to the load Z through an upper-arm ON operation in which the upper arm 110 and the lower arm of another phase (not shown) are turned on when the lower arm 120 is off, followed by an upper-arm OFF operation (freewheel mode) in which the upper arm 110 and the lower arm of another phase (not shown) are turned off, and a lower-arm ON operation in which the lower arm 120 and the upper arm of another phase (not shown) are turned on, followed by a lower-arm OFF operation (freewheel mode) in which the lower arm 120 and the upper arm of another phase (not shown) are turned off.

When the upper arm is turned on, the gate-source voltage VGS (Q1) that turns on the semiconductor switching element Q1 is output from the upper arm gate drive circuit 10. At this time, the semiconductor switching element of the lower arm of the other phase (not shown) is turned on simultaneously with the semiconductor switching element Q1. When the semiconductor switching element Q1 and the lower arm of the other phase are turned on, an upper arm current I110 (which is a drain current) flows from the high-potential power line 101P through the semiconductor switching element Q1. This upper arm current I110 flows to the load Z via the first current path 103P in the Rogowski coil 40 (solid line arrow). During this upper arm on operation, the upper arm current I110, which increases over time, flows through the first current path 103P from the upper arm 110 to the load Z. In this embodiment, the Rogowski coil 40 is positioned so that when the current flowing to the load Z via the semiconductor switching element Q1 increases, the Rogowski coil 40 outputs a positive induced voltage Vm.

During the subsequent upper arm OFF operation, the upper arm gate drive circuit 10 outputs a gate-source voltage VGS(Q1) that turns off the semiconductor switching element Q1, turning it OFF. At the same time, the lower arm of the other phase (not shown), which was ON, also turns OFF. As a result, an electromotive force is generated in the load Z that maintains the current that had been flowing through the load Z up to that point. Lower arm current I120, a reflux current, flows from the low-potential power line 101N to the load Z via diode D2 and the second current path 103N in the Rogowski coil 40 (dashed arrow). During this upper arm OFF operation, the lower arm current I120 (reflux current), which decreases over time, flows through the second current path 103N from the lower arm 120 side to the load Z side. In other words, during the upper arm OFF operation, the current passing through the Rogowski coil 40 flows in the same direction as during the upper arm ON operation, but the rate of change of the current is negative. Therefore, the Rogowski coil 40 outputs a negative induced voltage Vm.

During the subsequent lower-arm ON operation, the gate-source voltage VGS (Q2) that turns on the semiconductor switching element Q2 is output from the lower-arm gate drive circuit 20. At this time, the semiconductor switching element of the upper arm of the other phase (not shown) is turned on simultaneously with the semiconductor switching element Q2. When the semiconductor switching element Q2 and the upper arm of the other phase are turned on, a drain current, or lower-arm current I120, flows from the load Z to the low-potential power line 101N via the second current path 103N in the Rogowski coil 40 and the semiconductor switching element Q2 (solid arrow). During this lower-arm ON operation, the lower-arm current I120, which increases over time, flows from the load Z side to the lower arm 120 side through the second current path 103N. In other words, during the lower-arm ON operation, the rate of change of the current passing through the Rogowski coil 40 has the same polarity as during the upper-arm ON operation, but the direction of the current passing through the Rogowski coil 40 is opposite. Therefore, the Rogowski coil 40 outputs a negative induced voltage Vm.

During the subsequent lower-arm OFF operation, the gate-source voltage VGS(Q2) that turns off the semiconductor switching element Q2 is output from the lower-arm gate drive circuit 20, turning off the semiconductor switching element Q2. At the same time, the upper arm of the other phase (not shown) that was ON also turns OFF. As a result, an electromotive force is generated in the load Z that maintains the current that had been flowing through the load Z up to that point. A return current, the upper-arm current I110, flows from the load Z to the high-potential power line 101P via the first current path 103P and diode D1 in the Rogowski coil 40 (dashed arrow). During this lower-arm OFF operation, the upper-arm current I110, which decreases over time, flows from the load Z side to the upper arm 110 side through the first current path 103P. In other words, during the lower-arm OFF operation, the direction of the current passing through the Rogowski coil 40 is opposite to that during the upper-arm ON operation, and the current change rate is also negative. Therefore, the Rogowski coil 40 outputs a positive induced voltage Vm. The above is an example of the general operation of the power conversion device 100 shown in Figure 2.

Figure 3 is a waveform diagram showing the waveforms of each part in an example of operation in which normal turn-on without a short-circuit fault occurs during switching of the upper arm 110. Figure 4 is a circuit diagram showing the operating state of the power conversion device 100 during periods A, B, and C in Figure 3.

In the operation example shown in Figures 3 and 4, switching of the upper arm 110, i.e., the upper arm ON operation and upper arm OFF operation (freewheel mode) shown in Figure 2, are alternately repeated. Figures 3 and 4 show the upper arm OFF operation and the subsequent upper arm ON operation from this repeated series of operations.

The boundary between Period A and Period B in Figure 3 is the timing when the upper arm 110 starts to turn on. During Period A before the upper arm 110 starts to turn on, as shown in Figure 4, a lower arm current I120, which is a reflux current, flows from the low-potential power line 101N to the load Z via diode D2 and the second current path 103N in the Rogowski coil 40. Since this operating mode results in upper arm off operation, as shown in Figure 3, a negative induced voltage Vm is output from the Rogowski coil 40 during Period A.

When the upper arm 110 begins to turn on and period B begins, as shown in FIG. 4, upper arm current I110, which is the drain current, flows from the high-potential power line 101P through the semiconductor switching element Q1. During period B, the drain-source voltage VDS(Q1) of switching element Q1 decreases over time, and upper arm current I110, which is the drain current, increases. At the start of period B, a reflux current flows through diode D2 in the lower arm 120. Then, during period B, upper arm current I110 passes through the first current path 103P in the Rogowski coil 40, then the second current path 103N, and flows toward the lower arm 120, reducing the reflux current of diode D2. Therefore, during period B, the negative lower arm current I120, which is the reflux current, tends toward zero over time. Then, as the upper arm current I110 increases, the lower arm current (freewheeling current) 120 flowing through diode D2 becomes zero. The upper arm current I110 then becomes a reverse recovery current that eliminates the minority carriers accumulated in diode D2 during forward bias. Once this reverse recovery current flows, the lower arm current 120 then reaches a positive peak and begins to decrease. In this way, diode D2 turns off, and the drain-source voltage VDS(Q2) of semiconductor switching element Q2 in the lower arm 120 increases.

During the period until diode D2 turns off, the upper arm current I110 that passed through the first current path 103P passes through the second current path 103N toward the lower arm 120. That is, currents of opposite polarity and the same rate of change flow through the first current path 103P and the second current path 103N. In this case, magnetic flux cancels out within the Rogowski coil 40, causing the Rogowski coil 40 to output zero voltage as the induced voltage Vm. After diode D2 turns off, the upper arm current I110 that passed through the first current path 103P no longer flows through the second current path 103N, but instead flows to the load Z. This period is period C shown in Figure 3. During this period C, the upper arm is turned on, causing the Rogowski coil 40 to output a positive induced voltage Vm.

When there is no arm short circuit, the period during which zero voltage occurs as the induced voltage Vm is a short period determined by the characteristics of diode D2. In the example shown in Figure 3, the period during which zero voltage occurs as the induced voltage Vm is shorter than the predetermined reference time Δt0, so the arm short circuit detection signal E1 is not output.

Furthermore, when there is no load short circuit, excessive upper arm current I110 or lower arm current I120 does not flow, and therefore the induced voltage Vm obtained from the Rogowski coil 40 does not become large. In the example shown in Figure 3, the induced voltage Vm obtained from the Rogowski coil 40 does not fall outside the range of the predetermined reference value ±V0, so the voltage value comparison signal E2 is not output. Therefore, in the example shown in Figure 3, the short circuit detection signal E is not output.

Figure 5 is a waveform diagram showing waveforms at various parts in an example of operation in which a short-circuit fault occurs in the lower arm 120 during switching of the upper arm 110. Figure 6 is a circuit diagram showing the operating state of the power conversion device 100 during periods A, B, and D in Figure 5.

Similar to Figures 3 and 4 above, in the operation examples shown in Figures 5 and 6, switching of the upper arm 110, i.e., the upper arm ON operation and upper arm OFF operation (freewheel mode) shown in Figure 2, are alternately repeated.

The boundary between Period A and Period B in Figure 5 is the timing when the upper arm 110 starts to turn on. The operation during Period A is the same as the operation during normal turn-on described above (Figures 3 and 4).

When the upper arm 110 starts to turn on and period B begins, as shown in Figure 6, upper arm current I110, which is a drain current, flows from the high-potential power line 101P through the semiconductor switching element Q1. Similar to the normal turn-on operation described above, during period B, upper arm current I110 flows through the first current path 103P and the second current path 103N toward the lower arm 120, reducing the reflux current of diode D2 and then becoming the reverse recovery current of diode D2.

On the other hand, if there is a short-circuit fault in the semiconductor switching element Q2 of the lower arm 120, during period B, the upper arm current I110 flows to the semiconductor switching element Q2 via the first current path 103P and the second current path 103N. Here, a short-circuit fault in the semiconductor switching element Q2 includes faults such as breakdown of the semiconductor switching element Q2, as well as faults where the semiconductor switching element Q2 is erroneously turned on due to noise or other factors.

When an arm short circuit occurs in the lower arm 120 in this way, during period B, the reflux current of diode D2 is reduced, followed by the process of flowing a reverse recovery current through diode D2 and the process of flowing upper arm current I110 through semiconductor switching element Q2 of the lower arm 120, which proceed simultaneously and in parallel. As a result, currents of opposite polarity and the same rate of change continue to flow through first current path 103P and second current path 103N for a long period of time, the period during which induced voltage Vm of Rogowski coil 40 remains at zero voltage exceeds reference time Δt0, and arm short circuit detection signal E1 is output. As a result, short circuit detection signal E is output.

When a short-circuit detection signal E is output, in the upper arm gate drive circuit 10, the switching circuit 13 switches the supply source of the gate-source voltage VGS (Q1) from the drive circuit 11 to the short-circuit current interruption circuit 12, and the upper arm gate drive circuit 10 outputs the gate-source voltage VGS (Q1) that turns off the semiconductor switching element Q1. When a short-circuit detection signal E is output, in the lower arm gate drive circuit 20, the switching circuit 23 switches the supply source of the gate-source voltage VGS (Q2) from the drive circuit 21 to the short-circuit current interruption circuit 22, and the lower arm gate drive circuit 20 outputs the gate-source voltage VGS (Q2) that turns off the semiconductor switching element Q2.

As a result, period D begins, during which both the upper arm current I110 and the lower arm current I120 decrease. In this manner, in this embodiment, the arm short-circuit current is interrupted upon detection of an arm short-circuit fault.

The operation of arm short-circuit detection has been explained above using the example of a short-circuit fault in the lower arm when the upper arm is switching, but an arm short-circuit can also be detected by a similar operation if a short-circuit fault in the upper arm occurs when the lower arm is switching. That is, even if a short-circuit fault in the upper arm occurs when the lower arm is switching, after the lower arm begins to turn on, currents of the same magnitude but opposite polarity flow through the first current path 103P and the second current path 103N, and the induced voltage Vm of the Rogowski coil 40 becomes zero voltage for a reference time Δt0 or more, and an arm short-circuit is detected based on the duration of this zero voltage.

Figure 7 is a waveform diagram showing waveforms at various parts in an example of operation in which a short-circuit fault occurs in load Z during switching of upper arm 110. Figure 8 is a circuit diagram showing the operating state of power conversion device 100 during periods A, B, C, and E in Figure 7.

Similar to Figures 3 and 4, which show normal turn-on operation, the operation examples shown in Figures 7 and 8 alternate between switching the upper arm 110, i.e., the upper arm ON operation and upper arm OFF operation (freewheel mode) shown in Figure 2.

The boundary between period A and period B in Figure 7 is the timing when the upper arm 110 starts to turn on. The operations during periods A, B, and C are the same as those during periods A, B, and C during normal turn-on described above (Figures 3 and 4).

When a short-circuit fault occurs in load Z, during period C, the upper arm current I110, which increases over time, becomes excessive, and the time gradient di/dt of the upper arm current I110 flowing through the first current path 103P also becomes excessive. As a result, the induced voltage Vm of the Rogowski coil 40 exceeds the threshold value +V0. As a result, the load short-circuit detection signal E2 and short-circuit detection signal E are output, and period E begins.

During period E, in response to short-circuit detection signal E, the upper arm gate drive circuit 10 outputs a gate-source voltage VGS (Q1) that turns off semiconductor switching element Q1, and the lower arm gate drive circuit 20 outputs a gate-source voltage VGS (Q2) that turns off semiconductor switching element Q2. This interrupts the load short-circuit current.

As described above, according to this embodiment, arm short circuits and load short circuits in the power conversion device 100 can be detected and the short-circuit current can be cut off using one Rogowski coil 40 and one short-circuit determination circuit 30 provided for both the upper arm 110 and the lower arm 120. Therefore, according to this embodiment, it is possible to detect short-circuit faults in the power conversion device 100 while avoiding the overall size and complexity of the power conversion device 100.

<Other Embodiments>
Although one embodiment of the present invention has been described above, other embodiments of the present invention are also possible, for example as follows.

(1) Figure 9 is a circuit diagram showing the configuration of a power conversion device 100 equipped with a short-circuit fault detection device 50' according to another embodiment of the present invention. In the above embodiment (Figure 1), the Rogowski coil 40 of the short-circuit fault detection device 50 was inserted with a first current path 103P between the upper arm 110 and the common connection point of the upper arm 110 and the lower arm 120, and a second current path 103N between the lower arm 120 and the common connection point of the upper arm 110 and the lower arm 120. In contrast, in the short-circuit fault detection device 50' shown in Figure 9, the Rogowski coil 40' is inserted with a first current path 103P' between the upper arm 110 and the high-potential power supply line 101P and a second current path 103N' between the lower arm 120 and the low-potential power supply line 101N. In this embodiment, when an arm short circuit occurs, currents of the same magnitude but opposite polarity flow through the first current path 103P' and the second current path 103N', making it possible to detect the arm short circuit. Furthermore, in this embodiment, when a load short circuit occurs, an excessive current that increases over time flows through the first current path 103P' or the second current path 103N', making it possible to detect the load short circuit.

(2) This invention may also be applied to power conversion devices other than inverters that convert DC power to AC power, such as DC/DC converters and AC/AC converters.

(3) In the above embodiment, a MOSFET is given as an example of a semiconductor switching element, but the semiconductor switching element is not limited to this and may be another semiconductor switching element, such as an IGBT (Insulated Gate Bipolar Transistor).

(4) In the above embodiment, the reference time Δt0 and the reference value ±V0 may be adjustable by operating the controls.

(5) A control signal that is active during the supply period of the upper arm control signal and the lower arm control signal and inactive during other periods may be received from a higher-level device that controls the power conversion device 100, and the logical product of this control signal and the short-circuit detection signal E may be supplied to the switching circuits 13, 23. By taking the logical product of this control signal and the short-circuit detection signal E, it is possible to prevent the switching circuits 13, 23 from switching the drive section of the semiconductor switching elements Q1, Q2 from the drive circuits 11, 21 to the short-circuit current interruption circuits 12, 22 if the output voltage Vm of the Rogowski coil 40 remains at zero voltage for more than the reference time Δt0 when the semiconductor switching elements Q1, Q2 are not operating.

(6) Figure 10 is a side view showing an example implementation of the power conversion device of Figure 1 described above. In Figure 10, semiconductor module 210 has package 210p and three terminals 211 to 213 protruding from the bottom surface of package 210p. Also, semiconductor module 220 has package 220p and three terminals 221 to 223 protruding from the bottom surface of package 220p. Package 210p houses semiconductor switching element Q1, which constitutes upper arm 110 shown in Figure 1, and diode D1 connected in anti-parallel thereto. Here, terminal 211 is connected to the gate of semiconductor switching element Q1, terminal 212 is connected to the drain of semiconductor switching element Q1, and terminal 213 is connected to the source of semiconductor switching element Q1. Also, package 220p houses semiconductor switching element Q2, which constitutes lower arm 120 shown in Figure 1, and diode D2 connected in anti-parallel thereto. Here, terminal 221 is connected to the gate of semiconductor switching element Q2, terminal 222 is connected to the drain of semiconductor switching element Q2, and terminal 223 is connected to the source of semiconductor switching element Q2.

The terminals 211-213 of the semiconductor module 210 and the terminals 221-223 of the semiconductor module 220 are aligned in a straight line with a gap between them, and each of these terminals penetrates the gate wiring board 230, the Rogowski wiring board 240, and the main circuit wiring board 250.

The gate wiring board 230 is formed with the upper arm gate drive circuit 10, the lower arm gate drive circuit 20, and the short circuit determination circuit 30 shown in Figure 1. The gate wiring board 230 also has a conductor pattern formed thereon to which the output signal of the upper arm gate drive circuit 10 is supplied, and terminal 211 is connected to this conductor pattern. The gate wiring board 230 also has a conductor pattern formed thereon to which the output signal of the lower arm gate drive circuit 20 is supplied, and terminal 221 is connected to this conductor pattern.

A conductor pattern corresponding to the high-potential power line 101P shown in FIG. 1 is formed on the main circuit wiring board 250, and terminal 212 is connected to this conductor pattern. Furthermore, a conductor pattern corresponding to the low-potential power line 101N shown in FIG. 1 is formed on the main circuit wiring board 250, and terminal 223 is connected to this conductor pattern. Furthermore, a conductor pattern corresponding to the output terminal 102 shown in FIG. 1 is formed on the main circuit wiring board 250, and terminals 213 and 222 are connected to this conductor pattern. That is, in this example, terminals 213 and 222 are the first current path 103P and second current path 103N in FIG. 1.

A Rogowski coil 243 corresponding to the Rogowski coil 40 shown in FIG. 1 is formed on the Rogowski wiring board 240. FIG. 11 is a plan view of the Rogowski wiring board 240 as seen from the semiconductor modules 210 and 220. As shown in FIG. 11, the Rogowski coil 243 consists of a spiral coil 241 and a return wire 242 that runs from the end point of the coil 241 back to the start point. The Rogowski coil 243 surrounds terminals 213 and 222 (i.e., the first current path 103P and the second current path 103N in FIG. 1), and the ends of the coil 241 and the return wire 242 of the Rogowski coil 243 are connected to the short-circuit determination circuit 30 on the gate wiring board 230 via through-hole wiring (not shown).

Accordingly, this embodiment achieves the same effects as the embodiment shown in Figure 1 above. Note that, although the Rogowski wiring board 240 on which the Rogowski coil 243 is mounted and the gate wiring board 230 are separate boards in this embodiment, they may also be mounted on the same board. The same applies to the implementation examples shown in Figures 12 and 13, which will be described later.

(7) Figure 12 is a side view showing an example implementation of the power conversion device shown in Figure 9 above. Similar to the implementation examples shown in Figures 10 and 11 above, the power conversion device has semiconductor modules 210 and 220, a gate wiring board 230, a Rogowski wiring board 240, and a main circuit wiring board 250. Figure 13 is a plan view of the Rogowski wiring board 240 as seen from the semiconductor modules 210 and 220 side.

This implementation example differs from the implementation examples of Figures 10 and 11 only in the following respect. In the implementation examples of Figures 10 and 11, the Rogowski coil 243 on the Rogowski wiring board 240 collectively surrounds terminals 213 and 222 (i.e., first current path 103P and second current path 103N in Figure 1). In contrast, in the implementation examples of Figures 12 and 13, the Rogowski coil 243 on the Rogowski wiring board 240 collectively surrounds terminals 212 and 223 (i.e., first current path 103P' and second current path 103N' in Figure 9).

Therefore, this embodiment achieves the same effects as the embodiment shown in Figure 9 above.

(8) Figure 14 is a plan view showing another implementation example of the power conversion device of Figure 9 described above. Figure 15 is a side view of the same implementation example. In Figures 14 and 15, semiconductor module 300 is a 2-in-1 type semiconductor module and houses the elements that make up upper arm 110 and lower arm 120 of Figure 9. Spacers 311, 312, and 313 made of an insulator are provided on the upper surface of semiconductor module 300. Terminal portions 361, 362, and 363 are formed on the upper portions of spacers 311, 312, and 313, respectively. In addition, circuit board 320 is arranged to surround spacers 312 and 313. A drive control circuit unit 330 is mounted on this circuit board 320. This drive control circuit unit 330 includes upper arm gate drive circuit 10, lower arm gate drive circuit 20, and short-circuit determination circuit 30 shown in Figure 9.

In the semiconductor module 300, the source of the semiconductor switching element Q1 of the upper arm 110 and the drain of the semiconductor switching element Q2 of the lower arm 120 are commonly connected, and this common connection point is connected to terminal 361. In other words, terminal 361 corresponds to output terminal 102 in Figure 9 and is connected to a load (not shown).

In addition, within the semiconductor module 300, the drain of the semiconductor switching element Q1 of the upper arm 110 is connected to the terminal 362. This terminal 362 corresponds to the high-potential power supply line 101P in FIG. 9. That is, in this example, the wiring connecting the terminal 362 and the drain of the semiconductor switching element Q1 of the upper arm 110 contained within the semiconductor module 300 becomes the first current path 103P' in FIG. 9.

In addition, within the semiconductor module 300, the source of the semiconductor switching element Q2 of the lower arm 120 is connected to terminal 363. This terminal 363 corresponds to the low-potential power supply line 101N in FIG. 9. In other words, in this example, the wiring connecting terminal 363 and the source of the semiconductor switching element Q2 contained within the semiconductor module 300 becomes the second current path 103N' in FIG. 9.

As shown in FIG. 14, a Rogowski coil 340 is formed on the circuit board 320, surrounding the first current path 103P' extending from the semiconductor module 300 to the terminal portion 362 and the second current path 103N' extending from the semiconductor module 300 to the terminal portion 363. This Rogowski coil 340 consists of a spiral coil 341 and a return wire 342 that runs from the end point of this coil 341 back to the start point. The ends of the coil 341 and the return wire 342 of the Rogowski coil 340 are connected to the short-circuit determination circuit 30 in the drive control circuit portion 330.

Accordingly, this embodiment achieves the same effects as the embodiment shown in FIG. 9 described above. Furthermore, this embodiment has the terminal portion 362 corresponding to the high-potential power supply line 101P and the terminal portion 363 corresponding to the low-potential power supply line 101N adjacent to each other as shown in FIG. 14, and the Rogowski coil 340 surrounds the first current path 103P' and the second current path 103N' connected to these adjacent terminal portions 362 and 363, resulting in a simplified configuration.

(9) In the above implementation example, the Rogowski coil is provided outside the semiconductor module. However, the Rogowski coil may also be embedded within the semiconductor module.

Figure 16 is a side view showing a modified example of the implementation example shown in Figures 14 and 15. Note that in Figure 16, parts corresponding to those shown in Figures 14 and 15 are designated by the same reference numerals, and their explanations will be omitted.

In the implementation example shown in Figure 16, the circuit board 320a corresponds to the circuit board 320 in Figure 14, but does not have the Rogowski coil 340 in Figure 14. Instead, in the implementation example shown in Figure 16, a Rogowski coil 340a is embedded in the semiconductor module 320a, and this Rogowski coil 340a is connected to the drive control circuit section 330 (see Figure 14) of the circuit board 320a.

More specifically, in FIG. 16, the elements that make up the upper arm 110 and lower arm 120 in FIG. 9 are formed in element formation region 370 within semiconductor module 300a. In element formation region 370, the source of semiconductor switching element Q1 of upper arm 110 and the drain of semiconductor switching element Q2 of lower arm 120 are commonly connected, and this common connection point is connected to terminal portion 361 via conductor layer 361a.

Furthermore, in the element formation region 370, the drain of the semiconductor switching element Q1 of the upper arm 110 is connected to the terminal portion 362 via the conductor layer 362a. That is, in this example, the conductor layer 362a connecting the terminal portion 362 and the drain of the semiconductor switching element Q1 of the upper arm 110 included in the semiconductor module 300a serves as the first current path 103P' in FIG. 9.

Furthermore, in the element formation region 370, the source of the semiconductor switching element Q2 of the lower arm 120 is connected to the terminal portion 363 via the conductor layer 363a. That is, in this example, the conductor layer 363a connecting the terminal portion 363 and the source of the semiconductor switching element Q2 contained in the semiconductor module 300a becomes the second current path 103N' in FIG. 9. Thus, in the implementation example shown in FIG. 16, in addition to the upper arm 110 and lower arm 120, the first current path 103P' and the second current path 103N' are housed within the semiconductor module 300.

In the implementation example of Figure 16, a Rogowski coil 340a is embedded in the semiconductor module 300a, surrounding the conductor layers 362a and 363a, i.e., the first current path 103P' and the second current path 103N'. Various methods can be considered for embedding the Rogowski coil 340a in the semiconductor module 300a. For example, a space may be formed in the semiconductor module that surrounds the first current path 103P' and the second current path 103N', and the Rogowski coil 340a may be inserted into this space. Alternatively, the Rogowski coil 340a may be formed in the semiconductor module 300a that surrounds the first current path 103P' and the second current path 103N', and then sealed with an insulating material such as resin.

The implementation example of Figure 16 achieves the same effects as the implementation examples of Figures 14 and 15. Furthermore, the implementation example of Figure 16 embeds the Rogowski coil 340a within the semiconductor module 300a, making the implementation simpler than the implementation examples of Figures 14 and 15. Furthermore, compared to the implementation examples of Figures 14 and 15, it is possible to suppress a decrease in the creepage distance between spacers 311 and 312 and between spacers 312 and 313.

100...power conversion device, 101P...high potential power supply line, 101N...low potential power supply line, 110...upper arm, 120...lower arm, Q1, Q2...semiconductor switching element, D1, D2...diode, 10...upper arm gate drive circuit, 20...lower arm gate drive circuit, 11, 21...drive circuit, 21, 22...short circuit current interruption circuit, 13, 23...switching circuit, 50, 50'...short circuit fault detection device, 40, 40'...Rogowski coil, 102...AC output terminal, 103P, 103P'...first current path, 103N, 103N'...second current path, 30...short circuit determination circuit, 31...induced voltage detection circuit, 32...zero current Pressure period determination circuit, 33...voltage value comparison circuit, 34...OR gate, 210, 220, 300, 300a...semiconductor module, 210p, 220p...package, 211-213, 221-223...terminals, 240, 320, 320a...circuit board, 243, 340, 340a...Rogowski coil, 241, 341...coil, 242, 342...return line, 311-313...spacer, 320...circuit board, 330...drive control circuit section, 361-363...terminal section, 361a-363a...conductor layer, 370...element formation region, 230...gate wiring board, 240...Rogowski wiring board, 250...main circuit wiring board.

Claims (10)

1. A short-circuit fault detection device for a power conversion device that supplies power to a load via two or more arms each including a semiconductor switching element,
a Rogowski coil inserted in both a first current path through which a first current flows commonly to a first arm of the two or more arms and the load, and a second current path through which a second current flows commonly to a second arm of the two or more arms and the load,
detecting a short-circuit fault in an arm of the power conversion device and the load based on a detection signal obtained from the Rogowski coil ;
A short-circuit fault detection device, characterized in that a short-circuit fault in the arm is detected based on the duration of a state in which the absolute value of the detection signal is within a first threshold value . the first arm and the second arm are connected in series between a high potential power supply line and a low potential power supply line, and the load is connected to a common connection point of the first arm and the second arm;
the first current path is a current path between the first arm and the common connection point;
The short-circuit fault detection device according to claim 1 , wherein the second current path is a current path between the second arm and the common connection point. the first arm is housed in a first semiconductor module and is connected to the high-potential power supply line by a terminal of the first semiconductor module;
the second arm is housed in a second semiconductor module and is connected to the low-potential power supply line by a terminal of the second semiconductor module;
The short-circuit fault detection device according to claim 2 , wherein the Rogowski coil surrounds a terminal of the first semiconductor module and a terminal of the second semiconductor module together. the first arm and the second arm are connected in series between a high potential power supply line and a low potential power supply line, and the load is connected to a common connection point of the first arm and the second arm;
the first current path is a current path between the first arm and the high potential power supply line,
The short-circuit fault detection device according to claim 1 , wherein the second current path is a current path between the second arm and the low-potential power supply line. the first arm is housed in a first semiconductor module and connected to the common connection point by a terminal of the first semiconductor module;
the second arm is housed in a second semiconductor module and is connected to the common connection point by a terminal of the second semiconductor module;
The short-circuit fault detection device according to claim 4 , wherein the Rogowski coil surrounds the terminals of the first semiconductor module and the terminals of the second semiconductor module together. the first arm and the second arm are housed in a semiconductor module, the first arm is connected to the high potential power supply line outside the semiconductor module via the first current path, and the second arm is connected to the low potential power supply line outside the semiconductor module via the second current path ;
the high potential power supply line and the low potential power supply line are adjacent to each other outside the semiconductor module;
The short-circuit fault detection device according to claim 4 , wherein the Rogowski coil surrounds the first current path and the second current path together. the first arm and the second arm, and the first current path and the second current path are housed in a semiconductor module, the first arm is connected to the high potential power supply line outside the semiconductor module via the first current path, and the second arm is connected to the low potential power supply line outside the semiconductor module via the second current path ;
The short-circuit fault detection device according to claim 4 , wherein the Rogowski coil is embedded in the semiconductor module and surrounds the first current path and the second current path together. 8. The short-circuit fault detection device according to claim 1, wherein a short-circuit fault in the load is detected when the absolute value of the detection signal is equal to or greater than a second threshold value. 9. The short-circuit fault detection device according to claim 1, wherein when a short-circuit fault is detected, driving of each semiconductor switching element of the first arm and the second arm is stopped. 1. A power conversion device that supplies power to a load via two or more arms each including a semiconductor switching element,
a short-circuit fault detection device is provided in a first arm and a second arm of the two or more arms;
The short circuit fault detection device includes:
a Rogowski coil inserted in both a first current path through which a first current flows commonly to the first arm and the load and a second current path through which a second current flows commonly to the second arm and the load;
a short-circuit determination circuit that detects a short-circuit fault in an arm of the power conversion device and the load based on a detection signal obtained from the Rogowski coil,
The power conversion device according to claim 1, wherein the short-circuit determination circuit detects a short-circuit fault in the arm based on a duration of a state in which the absolute value of the detection signal is within a first threshold value.