JP7782602B2 - Power Module - Google Patents

Description

The present invention relates to a power module.

Conventionally, there is a three-phase bridge inverter circuit in which six diodes are bridge-connected (see Patent Document 1). Also known is a power module in which power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) are mounted on a substrate, and the necessary circuits are configured using wiring conductors and bonding wires formed on the substrate. In such power modules, it is important to optimize the layout of the power semiconductor elements in order to reduce wiring inductance, which causes noise (see Patent Document 2).

Special Publication No. 7-40790 JP 2017-55610 A

In silicon (hereafter referred to as Si)-based power semiconductor elements, increasing the switching speed increases the ON voltage of the power semiconductor element, resulting in greater losses in the steady ON state. For this reason, new power semiconductor elements are being developed that use silicon carbide (hereafter referred to as SiC) and gallium nitride (GaN) as materials that are less likely to increase the ON voltage even when switching quickly.

Unlike IGBTs and power MOS (Metal-Oxide-Semiconductor) FETs used in conventional power modules, GaN-FETs (GaN Field-Effect Transistors) have all three electrodes (drain electrode, source electrode, and gate electrode) on one surface. If the surface of this GaN-FET with the three electrodes is called the front surface and the opposite surface is called the back surface, then when the GaN-FET is placed on a substrate, the back surface is oriented toward the substrate (bottom).

For this reason, even if the optimized layout within a power module for IGBTs or power MOSFETs, which have electrodes on the backside, is used as is, it is difficult to sufficiently reduce the wiring inductance that causes noise when a large current flows through the wiring pattern within the power module. In other words, it cannot be said that the chip layout on the power board has been fully optimized in power modules equipped with GaN-FETs.

This disclosure therefore proposes a power module equipped with GaN-based power semiconductor elements that can reduce noise generation by optimizing the placement of elements on the power board and reducing wiring inductance.

A power module according to one aspect of the present disclosure comprises a power board on which switching elements constituting at least six arms are mounted on a single circuit board, and a driver board equipped with drivers for driving each of the at least six arms. The power board and driver board are arranged at a distance in the thickness direction of the board, and when the board is virtually divided into an upper arm side and a lower arm side, and the upper arm side is further virtually divided so that each board is divided into four blocks, the corresponding blocks on each board overlap in the thickness direction of the board.

This disclosure makes it possible to reduce wiring inductance.

FIG. 1 is a diagram showing an example of a GaN-FET circuit. FIG. 2 is a diagram showing an example of a circuit of a cascade type GaN-FET. FIG. 3 is a diagram showing an example of a GaN-FET chip. FIG. 4 is a diagram showing an example of a Si-FET chip. FIG. 5 is a diagram showing an example of mounting a cascade GaN-FET. FIG. 6 is a diagram showing a circuit that inputs DC and outputs three-phase AC. FIG. 7 is a diagram showing a circuit that receives DC as input, boosts the input current while improving the power factor, and outputs single-phase AC. FIG. 8 is a diagram (1) for explaining points to be noted in order to reduce the wiring inductance in the power module according to the first embodiment. FIG. 9 is a diagram (2) for explaining points to be noted in order to reduce the wiring inductance in the power module according to the first embodiment. FIG. 10 is a diagram for explaining the optimum arrangement of the first to sixth switching elements Q1 to Q6 and the capacitor C1 in the power module according to the first embodiment. FIG. 11 is a diagram showing an optimum layout when GaN-FETs are used instead of cascade-type GaN-FETs. FIG. 12 is a diagram showing an example of the circuit of the circuit block A. FIG. 13 is a cross-sectional view and a top view showing the configuration of the power module according to the first embodiment. FIG. 14 is a diagram for explaining that the power module according to the first embodiment achieves an optimal layout. FIG. 15 is a diagram for explaining the circuit loops 1-1 to 1-6 in the power module according to the first embodiment. FIG. 16 is a diagram for explaining the circuit loop 2-1 in the power module according to the first embodiment. FIG. 17 is a diagram for explaining circuit loops 3-1, 3-2, and 3-3 in the power module according to the first embodiment. FIG. 18 is a diagram for explaining the common impedance in the power module according to the first embodiment. FIG. 19 is a top view showing the configuration of a power module in a reference example. FIG. 20 is a diagram for explaining circuit loops 1-1 to 1-6 in the power module in the reference example. FIG. 21 is a diagram for explaining a circuit loop 2-1 in a power module in a reference example. FIG. 22 is a diagram for explaining the circuit loop 3-1 in the power module in the reference example. FIG. 23 is a diagram for explaining the common impedance in the power module in the reference example. FIG. 24 is a diagram showing a first modification in which three capacitors are arranged. FIG. 25 is a diagram showing a modification of the circuit shown in FIG. FIG. 26 is a diagram showing a power board of the circuit shown in FIG. 25 as a second modified example. FIG. 27 is a diagram for explaining the common impedance in the power module in the second modification. FIG. 28 is a diagram showing the circuit configuration of the power module according to the second embodiment. FIG. 29 is a cross-sectional view and a top view showing the configuration of a power module according to the second embodiment. FIG. 30 is a diagram in which the power module according to the second embodiment is virtually divided into blocks for each circuit with high affinity. FIG. 31 is a diagram in which the power board of the power module according to the second embodiment is divided into blocks in the manner shown in FIG. FIG. 32 is a diagram in which the driver board of the power module according to the second embodiment is divided into blocks in the manner shown in FIG. FIG. 33 is a diagram showing the blocks on the power board and the blocks on the driver board of the power module according to the second embodiment superimposed on each other.

Embodiments of the power module disclosed herein will be described in detail below with reference to the accompanying drawings. Note that the present disclosure is not limited to the embodiments shown below. It should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from reality. Furthermore, there may be parts in which the dimensional relationships and ratios differ between the drawings.

Conventionally, power modules have been known in which power semiconductor elements such as IGBTs are mounted on a power board and the necessary circuits are constructed by wiring them with bonding wires. In such power modules, it is important to optimize the layout of the power semiconductor elements in order to reduce wiring inductance, which causes noise.

On the other hand, GaN-FETs, a power semiconductor element that has been developed in recent years, differ from the IGBTs and power MOSFETs used in conventional power modules in that all three electrodes (drain electrode, source electrode, and gate electrode) are located on the front surface.

For this reason, even if the optimized internal layout of a power module for IGBTs or power MOSFETs, which have electrodes on the backside, is used as is, it is difficult to sufficiently reduce wiring inductance. In other words, in a power module equipped with GaN-FETs, the chip layout on the circuit board cannot be said to be optimized.

This is because, in conventional power semiconductor elements where the collector electrode and drain electrode are provided on the back surface, wiring is formed to the electrodes on the back surface using the circuit pattern on the power substrate, whereas in GaN-FETs where the drain electrode is provided on the front surface, wiring is formed to the drain electrode using a bonding wire.

Therefore, there is a need for technology that can reduce wiring inductance in power modules equipped with GaN-FETs.

<Configuration of switching element>
The present disclosure relates to a power module using a switching element that is a GaN-FET or a cascade-type GaN-FET. To facilitate understanding of each embodiment of the present disclosure, GaN-FETs and cascade-type GaN-FETs applicable to each embodiment will be described with reference to FIGS.

Figure 1 shows an example of a GaN-FET circuit. In a GaN-FET, the current flowing from the drain to the source is controlled by controlling the voltage applied to the gate.

Figure 2 shows an example circuit of a cascade GaN-FET. As shown in Figure 2, inside the cascade GaN-FET, the source terminal of the GaN-FET and the drain terminal of the Si-FET are electrically connected, and the source terminal of the Si-FET and the gate terminal of the GaN-FET are electrically connected.

The drain terminal of the GaN-FET becomes the drain electrode of the cascade GaN-FET, the source terminal of the Si-FET becomes the source electrode of the cascade GaN-FET, and the gate terminal of the Si-FET becomes the gate electrode of the cascade GaN-FET.

In a cascade GaN-FET with this circuit configuration, a normally-on GaN-FET can be driven as a normally-off switching element. That is, in a cascade GaN-FET, the element can be turned off by inputting a low-level signal to the gate electrode (i.e., the gate terminal of the Si-FET). In addition, in a cascade GaN-FET, the element can be turned on by inputting a high-level signal to the gate electrode.

The cascade GaN-FET has high breakdown voltage characteristics because it can utilize the breakdown voltage characteristics of GaN-FETs. Furthermore, the cascade GaN-FET can utilize the characteristics of low-breakdown-voltage Si-FETs to drive the gate, making it possible to drive the GaN-FET at high voltages without compromising its high speed.

Figure 3 shows an example of a GaN-FET. This GaN-FET is a bare chip without a package, and Figure 3 is a top view of it. The GaN-FET has a rectangular outer shape with long and short sides. A drain pad is provided on the front surface of the GaN-FET near one of the long sides. This drain pad is provided along one of the long sides. A source pad is provided near the other long side. This source pad is provided along the other long side. In addition, a pair of gate pads are provided on the front surface of the GaN-FET along the other long side, sandwiching the source pad.

Figure 4 shows an example of a Si-FET. This Si-FET is a bare chip without a package, and Figure 4 is a top view of it. As shown in Figure 4, the Si-FET has a source pad and a gate pad on the front surface, and a drain pad on the back surface.

Figure 5 shows an example of a cascade GaN-FET implementation. Figure 5(a) shows the cascade GaN-FET before resin sealing, and Figure 5(b) shows the cascade GaN-FET after resin sealing. As shown in Figure 5(a), the cascade GaN-FET is composed of a rectangular GaN-FET stacked on a rectangular Si-FET that is smaller than the GaN-FET. The source pad on the front surface of the GaN-FET and the drain pad on the back surface of the Si-FET are electrically and mechanically connected using a conductive bonding material such as solder or conductive adhesive. As a result, the drain of the GaN-FET corresponds to the drain of the cascade GaN-FET, the source of the Si-FET corresponds to the source of the cascade GaN-FET, and the gate of the Si-FET corresponds to the gate of the cascade GaN-FET.

In addition, one drain lead frame of the GaN-FET is provided along the long side along which the drain pad of the cascade GaN-FET is located, a source lead frame is provided along the other long side of the GaN-FET, and a gate lead frame is provided along the short side of the GaN-FET on the side where the gate pad of the cascade GaN-FET is located. The drain pad and drain lead frame are connected by a bonding wire such as AL (Aluminum) wire, the source pad and source lead frame are connected by a bonding wire such as AL wire, and the gate pad and gate lead frame are connected by AL wire or the like. In addition, the two gate pads of the GaN-FET are connected to the source lead frame by AL wire or the like.

Furthermore, as shown in Figure 5(b), after resin sealing, the drain pad, source pad, and gate pad are sealed with resin, and only a portion of the drain, source, and gate lead frames are connected to the outside.

In addition to stacking a GaN-FET chip and a Si-FET chip (Chip on Chip), cascade GaN-FETs also include two chips arranged in parallel and connected by wires, patterns, lead frames, etc.

<Circuit Configuration of Power Module (First Embodiment)>
Next, the circuit configuration of the power module according to the first embodiment will be described with reference to FIGS. 6 to 12. FIGS. 6 and 7 are diagrams showing examples of circuits that can be realized using the power module according to the first embodiment. FIG. 6 is a diagram showing a circuit that inputs DC and outputs three-phase AC. In FIG. 6, a three-phase motor is shown as an example of an output application. Hereinafter, the circuit in FIG. 6 may be referred to as a motor control circuit. FIG. 7 shows a circuit that inputs DC, boosts the input current while improving its power factor, and outputs single-phase AC. Hereinafter, the circuit in FIG. 7 may be referred to as a boost-type single-phase inverter output circuit.

As shown in Figures 6 and 7, circuit block A includes six switching elements, the first switching element Q1 through the sixth switching element Q6. Circuit block B includes circuit block A and six drive circuits, the Q1-GaN-FET drive circuit through the Q6-GaN-FET drive circuit. Circuit block A and circuit block B can be applied to power conversion devices with various circuit configurations. An example of a power conversion device is an inverter. The power module 1 according to the first embodiment corresponds to a circuit block obtained by adding capacitor C1 to circuit block A.

The first to sixth switching elements Q1 to Q6 are all configured with switching elements Q that are cascade-type GaN-FETs, and have approximately the same breakdown voltage characteristics and switching characteristics. Note that the first to sixth switching elements Q1 to Q6 may all be GaN-FETs.

The drain terminal of the first switching element Q1 is connected to the positive terminal P, and the source terminal of the first switching element Q1 is connected to the drain terminal of the second switching element Q2. The gate terminal of the first switching element Q1 is connected to the gate terminal Q1-G, and the source terminal of the first switching element Q1 is connected to the source terminal Q1-S.

The drain terminal of the second switching element Q2 is connected to the source terminal of the first switching element Q1, and the source terminal of the second switching element Q2 is connected to the negative terminal N. The gate terminal of the second switching element Q2 is connected to the gate terminal Q2-G, and the source terminal of the second switching element Q2 is connected to the source terminal Q2-S.

The drain terminal of the third switching element Q3 is connected to the positive terminal P, and the source terminal of the third switching element Q3 is connected to the drain terminal of the fourth switching element Q4. The gate terminal of the third switching element Q3 is connected to the gate terminal Q3-G, and the source terminal of the third switching element Q3 is connected to the source terminal Q3-S. Note that the gate terminal Q3-G and source terminal Q3-S are omitted in Figures 6 and 7.

The drain terminal of the fourth switching element Q4 is connected to the source terminal of the third switching element Q3, and the source terminal of the fourth switching element Q4 is connected to the negative terminal N. The gate terminal of the fourth switching element Q4 is connected to the gate terminal Q4-G, and the source terminal of the fourth switching element Q4 is connected to the source terminal Q4-S. Note that the gate terminal Q4-G and source terminal Q4-S are omitted from Figures 6 and 7.

The drain terminal of the fifth switching element Q5 is connected to the positive terminal P, and the source terminal of the fifth switching element Q5 is connected to the drain terminal of the sixth switching element Q6. The gate terminal of the fifth switching element Q5 is connected to the gate terminal Q5-G, and the source terminal of the fifth switching element Q5 is connected to the source terminal Q5-S. Note that the gate terminal Q5-G and source terminal Q5-S are omitted from Figures 6 and 7.

The drain terminal of the sixth switching element Q6 is connected to the source terminal of the fifth switching element Q5, and the source terminal of the sixth switching element Q6 is connected to the negative terminal N. The gate terminal of the sixth switching element Q6 is connected to the gate terminal Q6-G, and the source terminal of the sixth switching element Q6 is connected to the source terminal Q6-S. Note that the gate terminal Q6-G and source terminal Q6-S are omitted from Figures 6 and 7.

Capacitor C1 is a noise-removing capacitor connected between positive terminal P and negative terminal N. Circuit block A also has output terminals OUT1, OUT2, and OUT3.

The output terminal OUT1 of the power module 1 in FIG. 6 is connected between the source terminal of the first switching element Q1 and the drain terminal of the second switching element Q2. The output terminal OUT2 is connected between the source terminal of the third switching element Q3 and the drain terminal of the fourth switching element Q4. The output terminal OUT3 is connected between the source terminal of the fifth switching element Q5 and the drain terminal of the sixth switching element Q6.

The Q1-GaN-FET drive circuit drives the first switching element Q1, and the Q2-GaN-FET drive circuit drives the second switching element Q2. Although not shown in Figures 6 and 7, the Q3-GaN-FET drive circuit drives the third switching element Q3, the Q4-GaN-FET drive circuit drives the fourth switching element Q4, the Q5-GaN-FET drive circuit drives the fifth switching element Q5, and the Q6-GaN-FET drive circuit drives the sixth switching element Q6. The overall control block controls the Q1-GaN-FET drive circuit through the Q6-GaN-FET drive circuit.

In power conversion devices such as those shown in Figures 6 and 7, reducing the wiring inductance within circuit block A is important in order to reduce the noise generated by the large currents that are intermittently switched on and off by switching elements, and to achieve even more efficient power conversion. Therefore, the points to note in reducing the wiring inductance within circuit block A will be explained with reference to Figures 8 and 9.

Figure 8 is a diagram (1) for explaining points to note in order to reduce wiring inductance in the power module 1 according to the first embodiment. As shown in Figure 8, within the power module 1, circuit loops of various paths are formed by the current flow indicated by the arrows.

For example, within power module 1, a circuit loop 1-1 is formed in which the current output from the Q1-GaN-FET drive circuit that drives the first switching element Q1 returns in the following order: the gate terminal of the first switching element Q1, the source terminal of the first switching element Q1, and the Q1-GaN-FET drive circuit.

In addition, within the power module 1, a circuit loop 1-2 is formed in which the current output from the Q2-GaN-FET drive circuit that drives the second switching element Q2 returns in the following order: the gate terminal of the second switching element Q2, the source terminal of the second switching element Q2, and the Q2-GaN-FET drive circuit.

Similarly, within the power module 1, a circuit loop 1-3 is formed for the third switching element Q3, a circuit loop 1-4 is formed for the fourth switching element Q4, a circuit loop 1-5 is formed for the fifth switching element Q5, and a circuit loop 1-6 is formed for the sixth switching element Q6.

In addition, within the power module 1, a circuit loop 2-1 is formed in which a current flows in sequence from the positive terminal P through the first switching element Q1, the second switching element Q2, the negative terminal N, the fourth switching element Q4, the third switching element Q3, and the positive terminal P.

In addition, within the power module 1, a circuit loop 2-2 is formed in which current flows in sequence from the positive terminal P to the third switching element Q3, the fourth switching element Q4, the negative terminal N, the sixth switching element Q6, the fifth switching element Q5, and the positive terminal P.

In addition, within the power module 1, a circuit loop 3-1 is formed in which current flows in sequence from the capacitor C1 to the positive terminal P, the first switching element Q1, the second switching element Q2, the negative terminal N, and the capacitor C1.

In addition, within the power module 1, a circuit loop 3-2 is formed in which current flows in sequence from capacitor C1 to the positive terminal P, the third switching element Q3, the fourth switching element Q4, the negative terminal N, and capacitor C1.

In addition, within the power module 1, a circuit loop 3-3 is formed in which current flows in sequence from capacitor C1 to the positive terminal P, fifth switching element Q5, sixth switching element Q6, negative terminal N, and capacitor C1.

The power module 1 according to the first embodiment minimizes the lengths of the circuit loops 1-1 to 1-6, circuit loops 2-1 and 2-2, and circuit loops 3-1 to 3-3, and minimizes the areas (loop areas) enclosed by these circuit loops, thereby reducing the noise generated from the circuit loops (hereinafter also referred to as generated noise) (reducing wiring inductance).

Figure 9 is a diagram (2) for explaining points to note in order to reduce wiring inductance in the power module 1 according to the first embodiment. As shown in Figure 9, a large current line IL is formed in the first switching element Q1 in the power module 1, through which a large current flows from the drain terminal to the source terminal.

In addition, a small current line IS is formed in the first switching element Q1 within the power module 1, which passes a control signal from the gate terminal to the source terminal.

In the power module 1 according to the first embodiment, the common impedance CI at the portion where the currents flowing through the large current line IL and the small current line IS mentioned above flow together is minimized, thereby reducing wiring inductance.

Note that while the example in Figure 9 shows the first switching element Q1, the same applies to the second switching element Q2 through the sixth switching element Q6. By minimizing this common impedance CI, wiring inductance can be reduced.

The circuits shown in Figures 8 and 9 are common to the circuits in Figures 6 and 7. That is, the points explained using Figures 8 and 9 are valid for both the circuits in Figures 6 and 7, and are also valid for a wide variety of circuits that have circuit block A and circuit block B shown in Figures 6 and 7. Note that while Figures 8 and 9 use cascade GaN-FETs as switching elements, all switching elements may be GaN-FETs.

Next, based on the points to note explained so far, specific means for reducing wiring inductance within the power module 1 will be explained with reference to Figures 10 and 11.

Figure 10 is a diagram illustrating the optimal layout of the first to sixth switching elements Q1 to Q6 and capacitor C1 in the power module 1 according to the first embodiment. Figure 10(a) shows the circuit, and Figure 10(b) shows the optimal layout. In this disclosure, as shown in Figure 10(a), the wiring formed inside the power module 1 is virtually divided into several groups (hereinafter also referred to as wiring sections).

Specifically, the wiring section from capacitor C1 via positive terminal P to the drain terminal of the first switching element Q1, the drain terminal of the third switching element Q3, or the drain terminal of the fifth switching element Q5 is referred to as network P-NET. Furthermore, the wiring section from gate terminal Q1G to the gate terminal of the first switching element Q1, from that gate terminal via the inside of the Si-FET to the source terminal of the first switching element Q1, and from that source terminal to source terminal Q1S via that source terminal is referred to as network Q1G-NET.

The wiring section from the output terminal OUT1 to the source terminal of the first switching element Q1 and the drain terminal of the second switching element Q2 is referred to as the network OUT1-NET. The wiring section from the gate terminal Q2G to the gate terminal of the second switching element Q2, from that gate terminal via the inside of the Si-FET to the source terminal of the second switching element Q2, and from that source terminal to the source terminal Q2S is referred to as the network Q2G-NET.

The wiring section from the gate terminal Q3G to the gate terminal of the third switching element Q3, from this gate terminal through the inside of the Si-FET to the source terminal of the third switching element Q3, and via this source terminal to the source terminal Q3S is referred to as the network Q3G-NET. The wiring section from the output terminal OUT2 to the source terminal of the third switching element Q3 and the drain terminal of the fourth switching element Q4 is referred to as the network OUT2-NET.

The wiring section from the gate terminal Q4G to the gate terminal of the fourth switching element Q4, from that gate terminal via the inside of the Si-FET to the source terminal of the fourth switching element Q4, and via that source terminal to the source terminal Q4S, is referred to as network Q4G-NET. The wiring section from the gate terminal Q5G to the gate terminal of the fifth switching element Q5, from that gate terminal via the inside of the Si-FET to the source terminal of the fifth switching element Q5, and via that source terminal to the source terminal Q5S is referred to as network Q5G-NET. The wiring section from the output terminal OUT3 to the source terminal of the fifth switching element Q5 and the drain terminal of the sixth switching element Q6 is referred to as network OUT3-NET.

The wiring section from the gate terminal Q6G to the gate terminal of the sixth switching element Q6, from that gate terminal via the inside of the Si-FET to the source terminal of the sixth switching element Q6, and via that source terminal to the source terminal Q6S is referred to as the network Q6G-NET. The wiring section from capacitor C1 via the negative terminal N to the source terminal of the second switching element Q2, the source terminal of the fourth switching element Q4, or the source terminal of the sixth switching element Q6 is referred to as the network N-NET.

The P-NET AREA, Q-NET AREA, OUT1-NET AREA, OUT2-NET AREA, OUT3-NET AREA, Q1G-NET AREA, Q2G-NET AREA, Q3G-NET AREA, Q4G-NET AREA, Q5G-NET AREA, and Q6G-NET shown in Figure 10(b) Each AREA is a patterning area corresponding to P-NET, Q-NET, OUT1-NET, OUT2-NET, OUT3-NET, Q1G-NET, Q2G-NET, Q3G-NET, Q4G-NET, Q5G-NET, and Q6G-NET shown in Figure 10(a).

As shown in (b) of Figure 10, in the power module 1 of the first embodiment, the upper arm switching elements (Q1, Q3, Q5) are arranged so that the gates of the Si-FETs are above the central portion 4 of the power module 1 where the capacitor C1 is located. A P-NET is arranged on the drain side of each GaN-FET, and OUT1-NET to OUT3-NET are arranged on the source side of each GaN-FET. Furthermore, the lower arm switching elements (Q2, Q4, Q6) are arranged so that the gates of the Si-FETs are below the central portion 4. An N-NET is arranged on the source side of each GaN-FET, and OUT1-NET to OUT3-NET are arranged on the drain side of each GaN-FET. Furthermore, the P-NET and N-NET are arranged to run parallel between the upper arm and lower arm switching elements. Capacitor C1 is located between the third switching element Q3 and the fourth switching element Q4, i.e., in the central portion 4 of the power board where the first to sixth switching elements Q1 to Q6 are located.

The intersections between OUT2-NET to OUT3-NET and P-NET and N-NET are wired on separate layers on multi-layer boards, and connected with jumper wires on single-phase boards. In Figure 10(b), OUT2-NET AREA and OUT3-NET AREA are cut at the top and bottom, and the cut points are connected with wire bonding.

By arranging the first through sixth switching elements Q1-Q6 and capacitor C1 in this way, noise is not unbalanced among the six switching elements, and the wiring length can be shortened, reducing noise generation. This prevents an increase in noise generated by extremely long wiring patterns, while also ensuring a good current path for large currents. Note that each example of the present invention describes an example in which the switching elements and capacitor C1 are arranged based on this central portion 4.

The first to sixth switching elements Q1 to Q6 are arranged so that the first switching element Q1, the third switching element Q3, and the fifth switching element Q5 are aligned on a single straight line (a virtual straight line (not shown)). The second switching element Q2, the fourth switching element Q4, and the sixth switching element Q6 are aligned on a single straight line (a virtual straight line (not shown)). These virtual straight lines are substantially parallel. The line (not shown) connecting the first switching element Q1 and the second switching element Q2, the line (not shown) connecting the third switching element Q3 and the fourth switching element Q4, and the line (not shown) connecting the fifth switching element Q5 and the sixth switching element Q6 are substantially parallel.

Figure 11 shows the optimal layout when a GaN-FET is used instead of a cascade GaN-FET. In Figure 11, the cascade GaN-FET in Figure 10 has been replaced with a GaN-FET.

<Configuration of Power Module (First Embodiment)>
Next, the configuration of the power module 1 employing the optimal layout shown in FIG. 10 will be described with reference to FIGS. 12 and 13. FIG. 12 is a diagram showing an example of a circuit block A. Compared to the circuit block A shown in FIGS. 6 and 7, the circuit block A in FIG. 12 is provided with a thermistor. Two terminals TH1 and TH2 are connected to the thermistor. The thermistor is provided to detect the temperature of the substrate.

Figure 13 shows a cross-sectional view and a top view illustrating the configuration of a power module 1 according to the first embodiment. Figure 13(a) shows the cross-sectional view, and Figure 13(b) shows the top view. The cross-sectional area shown in the cross-sectional view is shown in the top view. Figure 13(a) is a schematic view viewed in the direction of the arrow from the cross-sectional line in the top view shown in Figure 13(b). As shown in Figure 13(a), the power module 1 according to the first embodiment includes a power board 10, a case 11, a lid 12, and silicone gel 13 as a resin sealant. The power board 10 is an example of a circuit board.

The power board 10 is composed of a circuit board with high heat resistance and high heat dissipation properties, such as a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazing) board. The front surface of the power board 10 is mounted with the first through sixth switching elements Q1 through Q6, a capacitor C1, and other components.

The case 11 has a frame shape and is provided to surround the front surface of the power board 10. The case 11 houses each element mounted on the power board 10. The case 11 also has mounting holes formed therein that are used to secure the power module 1 inside the power conversion device.

The case 11 is formed from, for example, polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, or acrylonitrile butadiene styrene (ABS) resin.

The lid 12 covers the front surface of the power board 10 housed in the case 11 and is provided to close the top of the frame-shaped case 11. The lid 12 is formed, for example, from the same resin as the case 11. Silicon gel 13 is filled inside the case 11 and seals the various elements mounted on the front surface of the power board 10. An external output PIN is provided on the power board 10. For example, Figure 13(b) shows a diagram of the external output PIN provided on the negative terminal N, viewed from above (top view) and from the side (side view).

The power board 10 and the case 11, and the case 11 and the lid 12 are joined together with adhesive (not shown).

As shown in Figure 13 (b), capacitor C1 and first to sixth switching elements Q1 to Q6 are mounted on the front surface of power board 10. Capacitor C1 is located in central portion 4 of power board 10. The upper arm switching elements (Q1, Q3, Q5) are located so that the gates of their Si-FETs are located above central portion 4 of power board 10. The lower arm switching elements (Q2, Q4, Q6) are located so that the gates of their Si-FETs are located below central portion 4 of power board 10.

Circuit patterns 21-43 that make up the wiring section are provided on the front surface of the power board 10. Note that these circuit patterns 21-43 are provided independently of each other on an insulating layer included in the power board 10, and therefore are not electrically connected to each other.

These circuit patterns 21 to 43 will be explained with reference to Figure 14. Figure 14 is a diagram illustrating how the power module 1 according to the first embodiment achieves an optimal layout. (a) of Figure 14 is a diagram showing the front surface of the power board 10 shown in Figure 13, and (b) of Figure 14 is a diagram showing the correspondence between the circuit patterns and the parts shown in Figure 10.

As shown in Figure 14(a), the size of the power board 10 is 37.50 mm x 28.50 mm.

When the first switching element Q1 and the second switching element Q2 are used as references, a circuit pattern 21 is formed in the area on the opposite side of the first switching element Q1 and the second switching element Q2 from the area where the capacitor C1 is located. Most of this circuit pattern 21 corresponds to the network OUT1-NET.

Circuit patterns 22 are formed in the region on the drain terminal side of the first switching element Q1, the region on the drain terminal side of the third switching element Q3, the region on the drain terminal side of the fifth switching element Q5, and the region connecting these three regions on the lower arm side. These circuit patterns 22 correspond to the network P-NET.

Circuit patterns 23 are formed in the region on the source terminal side of the second switching element Q2, the region on the source terminal side of the fourth switching element Q4, the region on the source terminal side of the sixth switching element Q6, and the region connecting these three regions on the upper arm side. Most of these circuit patterns 23 correspond to the network N-NET.

When the first switching element Q1 is used as a reference, circuit patterns 24 and 25 are arranged in an area on the opposite side of the first switching element Q1 from the area in which the second switching element Q2 is arranged. These circuit patterns 24 and 25 correspond to part of the network Q1G-NET.

When the second switching element Q2 is used as a reference, circuit patterns 26 and 27 are arranged in an area on the opposite side of the second switching element Q2 from the area in which the second switching element Q1 is arranged. These circuit patterns 26 and 27 correspond to part of the network Q2G-NET.

When the third switching element Q3 is used as a reference, circuit patterns 28, 29, and 30 are arranged in an area on the opposite side of the third switching element Q3 from the area in which the fourth switching element Q4 is arranged. Circuit pattern 28 extends to the area on the source side of the third switching element Q3. Circuit pattern 28 corresponds to part of network OUT2-NET. Circuit patterns 29 and 30 correspond to part of network Q3G-NET.

Circuit pattern 31 is arranged in the region on the drain side of the fourth switching element Q4. Furthermore, when the fourth switching element Q4 is used as a reference, circuit patterns 32 and 33 are arranged in the region on the opposite side of the fourth switching element Q4 from the region in which the third switching element Q3 is arranged. Circuit pattern 31 corresponds to part of network OUT2-NET. Furthermore, circuit patterns 32 and 33 correspond to part of network Q4G-NET.

When the fifth switching element Q5 is used as a reference, circuit patterns 34, 35, and 36 are arranged in an area on the opposite side of the fifth switching element Q5 from the area in which the sixth switching element Q6 is arranged. Circuit pattern 34 includes the area on the source side of the fifth switching element Q5. Circuit pattern 34 corresponds to part of the network OUT3-NET. Furthermore, circuit patterns 35 and 36 correspond to part of the network Q5G-NET.

Circuit pattern 37 is arranged in the region on the drain side of sixth switching element Q6. Furthermore, when sixth switching element Q6 is used as a reference, circuit patterns 38 and 39 are arranged in the region on the opposite side of sixth switching element Q6 from the region in which fifth switching element Q5 is arranged. Circuit pattern 37 corresponds to part of network OUT3-NET. Furthermore, circuit patterns 38 and 39 correspond to part of network Q6G-NET.

When the portion of circuit pattern 21 adjacent to the second switching element Q2 is used as a reference, circuit patterns 40 and 41 are arranged in the region on the opposite side of the second switching element Q2 from the portion adjacent to the second switching element Q2. Circuit patterns 42 and 43 are arranged in the region sandwiched between the first switching element Q1 and the second switching element Q2.

As explained above, in the power module 1 according to the first embodiment, the capacitor C1, the first to sixth switching elements Q1 to Q6, and the wiring sections are optimally arranged as shown in Figure 11(b).

The specific wiring configuration for these circuit patterns 21-43 is as follows. The source electrode (source pad) of the first switching element Q1, the gate electrode (gate pad) of the GaN-FET of the first switching element Q1, and the drain electrode (drain pad) of the second switching element Q2 are electrically connected to circuit pattern 21 via bonding wire W. Furthermore, a source terminal Q1-S is provided in a portion of circuit pattern 21 adjacent to circuit pattern 24, and, when using source terminal Q1-S as a reference, an output terminal OUT1 is provided in the circuit pattern 21 on the opposite side of source terminal Q1-S from the area in which circuit pattern 24 is located.

The drain electrode of the first switching element Q1, the drain electrode of the third switching element Q3, and the drain electrode of the fifth switching element Q5 are electrically connected to the circuit pattern 22 via bonding wires W. In addition, a positive terminal P is provided on the circuit pattern 22 near the fifth switching element Q5.

A capacitor C1 is provided between circuit pattern 22 and circuit pattern 23, and circuit pattern 22 and circuit pattern 23 are electrically connected via this capacitor C1.

The circuit pattern 23 is electrically connected via bonding wires W to the source electrode of the second switching element Q2, the gate electrode of the GaN-FET of the second switching element Q2, the source electrode of the fourth switching element Q4, the gate electrode of the GaN-FET of the fourth switching element Q4, the source electrode of the sixth switching element Q6, and the gate electrode of the GaN-FET of the sixth switching element Q6.

A negative terminal N is provided in the vicinity of the sixth switching element Q6 on the circuit pattern 23. A source terminal Q2-S is provided in the vicinity of circuit pattern 26 on the circuit pattern 23, a source terminal Q4-S is provided in the vicinity of circuit pattern 32 on the circuit pattern 23, and a source terminal Q6-S is provided in the vicinity of circuit pattern 38 on the circuit pattern 23.

A gate terminal Q1-G is provided on circuit pattern 24. A resistor R1-1 is provided between circuit pattern 24 and circuit pattern 25, and circuit pattern 24 and circuit pattern 25 are electrically connected via resistor R1-1.

The gate electrode of the first switching element Q1 is electrically connected to the circuit pattern 25 via a bonding wire W. A resistor R1-2 is provided between the circuit pattern 25 and the circuit pattern 21, and the circuit pattern 25 and the circuit pattern 21 are electrically connected via this resistor R1-2.

A gate terminal Q2-G is provided on circuit pattern 26. A resistor R2-1 is provided between circuit pattern 26 and circuit pattern 27, and circuit pattern 26 and circuit pattern 27 are electrically connected via resistor R2-1.

The gate electrode of the second switching element Q2 is electrically connected to the circuit pattern 27 via a bonding wire W. A resistor R2-2 is provided between the circuit pattern 27 and the circuit pattern 23, and the circuit pattern 27 and the circuit pattern 23 are electrically connected via this resistor R2-2.

The source electrode of the third switching element Q3 and the gate electrode of the GaN-FET of the third switching element Q3 are electrically connected to circuit pattern 28 via bonding wire W. Circuit pattern 31 is also electrically connected to circuit pattern 28 via bonding wire W. A source terminal Q3-S is provided in a portion of circuit pattern 28 adjacent to circuit pattern 29, and an output terminal OUT2 is provided on the circuit pattern 28 on the opposite side of circuit pattern 29 from source terminal Q3-S.

A gate terminal Q3-G is provided on circuit pattern 29. A resistor R3-1 is provided between circuit pattern 29 and circuit pattern 30, and circuit pattern 29 and circuit pattern 30 are electrically connected via resistor R3-1.

The gate electrode of the third switching element Q3 is electrically connected to the circuit pattern 30 via a bonding wire W. A resistor R3-2 is provided between the circuit pattern 30 and the circuit pattern 28, and the circuit pattern 30 and the circuit pattern 28 are electrically connected via this resistor R3-2.

The drain electrode of the fourth switching element Q4 is electrically connected to the circuit pattern 31 via a bonding wire W.

A gate terminal Q4-G is provided on circuit pattern 32. A resistor R4-1 is provided between circuit pattern 32 and circuit pattern 33, and circuit pattern 32 and circuit pattern 33 are electrically connected via resistor R4-1.

The source electrode of the fourth switching element Q4 is electrically connected to the circuit pattern 33 via a bonding wire W. A resistor R4-2 is provided between the circuit pattern 33 and the circuit pattern 23, and the circuit pattern 33 and the circuit pattern 23 are electrically connected via this resistor R4-2.

The source electrode of the fifth switching element Q5 and the gate electrode of the GaN-FET of the fifth switching element Q5 are electrically connected to circuit pattern 34 via bonding wire W. Circuit pattern 37 is also electrically connected to circuit pattern 34 via bonding wire W. Capacitor C1 is located in an area sandwiched between wires connecting the drain electrode of the GaN-based switching element of the upper arm and the source electrode of the GaN-based switching element of the lower arm. Specifically, capacitor C1 is located in an area sandwiched between the bonding wire W connecting circuit pattern 28 and circuit pattern 31 and the bonding wire W connecting circuit pattern 34 and circuit pattern 37. A source terminal Q5-S is provided in a portion of circuit pattern 34 adjacent to circuit pattern 35. When using source terminal Q5-S as a reference, an output terminal OUT3 is provided on the circuit pattern 34 on the opposite side of source terminal Q5-S from the area where circuit pattern 35 is located.

A gate terminal Q5-G is provided on circuit pattern 35. A resistor R5-1 is provided between circuit pattern 35 and circuit pattern 36, and circuit pattern 35 and circuit pattern 36 are electrically connected via resistor R5-1.

The gate electrode of the fifth switching element Q5 is electrically connected to the circuit pattern 36 via a bonding wire W. A resistor R5-2 is provided between the circuit pattern 36 and the circuit pattern 34, and the circuit pattern 36 and the circuit pattern 34 are electrically connected via this resistor R5-2.

The drain electrode of the sixth switching element Q6 is electrically connected to the circuit pattern 37 via a bonding wire W.

A gate terminal Q6-G is provided on circuit pattern 38. A resistor R6-1 is provided between circuit pattern 38 and circuit pattern 39, and circuit pattern 38 and circuit pattern 39 are electrically connected via resistor R6-1.

The source electrode of the sixth switching element Q6 is electrically connected to circuit pattern 39 via a bonding wire W. A resistor R6-2 is provided between circuit pattern 39 and circuit pattern 23, and circuit pattern 39 and circuit pattern 23 are electrically connected via resistor R6-2.

Circuit pattern 40 has a terminal TH1 that is connected to one electrode of the thermistor. Circuit pattern 42 is electrically connected to circuit pattern 40 via a bonding wire W. Circuit pattern 41 has a terminal TH2 that is connected to the other electrode of the thermistor. Circuit pattern 41 is electrically connected to circuit pattern 43 via a bonding wire W.

In addition, the positive terminal P, negative terminal N, output terminals OUT1 to OUT3, gate terminals Q1-G to Q6-G, source terminals Q1-S to Q6-S, and terminals TH1 and TH2 are all made of conductive materials such as metal, and are electrically and mechanically connected to each circuit pattern with conductive bonding materials such as solder or conductive adhesive.

Figure 15 is a diagram for explaining the circuit loops 1-1 to 1-6 within the power module 1 according to the first embodiment. As shown in Figure 15, in the power module 1 according to the first embodiment, the lengths of the circuit loops 1-1 to 1-6 are made as short as possible, and the loop areas of the circuit loops 1-1 to 1-6 are made as small as possible.

Figure 16 is a diagram for explaining the circuit loop 2-1 in the power module 1 according to the first embodiment. As shown in Figure 16(a), in the power module 1 according to the first embodiment, the length of the circuit loop 2-1 is made as short as possible, and the loop area of the circuit loop 2-1 is made as small as possible. Also, as shown in Figure 16(b), the length of the circuit loop 2-2 is made as short as possible, and the loop area of the circuit loop 2-2 is made as small as possible.

As explained above, the length of each of the circuit loops 1-1 to 1-6 and circuit loops 2-1 and 2-2 within the power module 1 is minimized, and the loop area is also minimized. This has the effect of reducing noise generated in each circuit loop. Furthermore, because circuit loops 1-1 to 1-6 and circuit loops 2-1 and 2-2 do not pass through capacitor C1, the effect of reducing wiring inductance in each circuit loop can be achieved even if capacitor C1 is not installed.

Figure 17 is a diagram for explaining the circuit loops 3-1, 3-2, and 3-3 within the power module 1 according to the first embodiment. As shown in Figure 17, in the power module 1 according to the first embodiment, the lengths of the circuit loops 3-1, 3-2, and 3-3 passing through the capacitor C1 are minimized, and the loop areas of these circuit loops 3-1, 3-2, and 3-3 are minimized. Therefore, in addition to the above effects, the power module 1 equipped with the capacitor C1 also achieves the effect of reducing wiring inductance in the circuit loops.

Figure 18 is a diagram illustrating the common impedance CI within the power module 1 according to the first embodiment. (a) of Figure 18 is a diagram illustrating the area around the first switching element Q1, and (b) of Figure 18 is a diagram illustrating the area around the second switching element Q2.

As shown in (a) of Figure 18, in the first switching element Q1, the location where the bonding wire W extending from the source electrode of the Si-FET (i.e., the source electrode of the first switching element Q1) is connected to the circuit pattern 21 is referred to as the first connection portion 51.

Furthermore, in the first switching element Q1, the location where the bonding wire W extending from the gate electrode of the GaN-FET is connected to the circuit pattern 21 is referred to as the second connection portion 52.

In the first embodiment, the first connection portion 51 is closer to the short side (the left side in FIG. 18 ) of the power board 10 than the second connection portion 52. In other words, the first connection portion 51 is positioned farther away from the first switching element Q1 to which they are connected than the second connection portion 52. This makes it possible to minimize the overlapping portion (i.e., common impedance CI) between the large current line IL flowing from the drain terminal to the source terminal of the first switching element Q1 and the small current line IS flowing from the gate electrode to the source terminal of the first switching element Q1.

Therefore, according to the first embodiment, the common impedance CI can be reduced, thereby reducing the impact of noise generated on the large current line IL on the small current line IS.

Note that while Figure 18(a) shows the first switching element Q1, the common impedance CI can be minimized by similarly providing the first connection portion 51 and the second connection portion 52 on the circuit patterns 28 and 34 for the third switching element Q3 and the fifth switching element Q5.

Also, as shown in (b) of Figure 18, in the second switching element Q2, the location where the bonding wire W extending from the source electrode of the Si-FET (i.e., the source electrode of the second switching element Q2) is connected to the circuit pattern 23 is referred to as the third connection portion 53.

Furthermore, in the second switching element Q2, the location where the bonding wire W extending from the gate electrode of the GaN-FET is connected to the circuit pattern 23 is referred to as the fourth connection portion 54.

In the first embodiment, the third connection portion 53 is closer to the center of the power board 10 than the fourth connection portion 54. In other words, the third connection portion 53 is positioned farther away from the second switching element Q2 to which they are connected than the fourth connection portion 54. This makes it possible to minimize the overlapping portion (i.e., common impedance CI) between the large current line IL flowing from the drain terminal to the source terminal of the second switching element Q2 and the small current line IS flowing from the gate electrode to the source terminal of the second switching element Q2.

Therefore, according to the first embodiment, the common impedance CI can be reduced, thereby reducing the impact of noise generated on the large current line IL on the small current line IS.

Note that while Figure 18(b) shows the second switching element Q2, the common impedance CI can also be minimized by providing the third connection portion 53 and the fourth connection portion 54 in the circuit pattern 23 for the fourth switching element Q4 and the sixth switching element Q6.

Next, we will compare the wiring inductance between the power module 1 according to the first embodiment described above and a power module 100 of a reference example, which is arranged based on a different concept from the first embodiment. Figure 19 is a top view showing the configuration of the power module 100 of the reference example. This reference example uses a component arrangement and patterning method that is commonly adopted in power modules using Si-FETs and Si-IGBTs.

As shown in Figure 19, the size of the power board of the power module 100 is 58.00 mm x 29.00 mm. Compared to Figure 14(a), the size of the power board of the power module 100 is larger, even though the same elements are used to form the same circuit.

Figure 20 is a diagram for explaining the circuit loops 1-1 to 1-6 within the power module 100 of the reference example. Comparing Figure 15 and Figure 20, there is no difference in merit between the power module 1 of the first embodiment and the power module 100 of the reference example.

Figure 21 is a diagram for explaining the circuit loop 2-1 in the power module 100 of the reference example. Comparing Figure 16 and Figure 21, in the power module 100 of the reference example, the length of the circuit loop 2-1 is longer and the loop area of the circuit loop 2-1 is larger than in the first embodiment.

Figure 22 is a diagram for explaining the circuit loop 3-1 in the power module 100 of the reference example. Comparing Figure 17 and Figure 22, in the power module 100 of the reference example, the length of the circuit loop 3-1 is longer and the loop area of the circuit loop 3-1 is larger than in the first embodiment.

In other words, the power module 1 according to the first embodiment has shorter circuit loops 2-1 and 3-1 and a smaller loop area than the power module 100 according to the reference example. This allows the wiring inductance of the power module 1 to be reduced in the first embodiment.

Figure 23 is a diagram for explaining the common impedance CI within the power module 100 in the reference example. Comparing Figure 18(a) with Figure 23, there is no difference in merit between the power module 1 in accordance with the first embodiment and the power module 100 in the reference example.

<Modification of the first embodiment>
So far, we have described the case where only one capacitor C1 is arranged, but more capacitors may be arranged in the power module 1. Fig. 24 is a diagram showing Modification 1 in which three capacitors are arranged. Fig. 24(a) shows the arrangement of the capacitors, and Fig. 24(b) shows the circuit loops 3-1 to 3-3.

As shown in (a) of Figure 24, capacitor C1 is located in a region sandwiched between a bonding wire W connected to the drain electrode of the third switching element Q3 and a bonding wire W connected to the source electrode of the fourth switching element Q4. Capacitor C2 is located in a region sandwiched between a bonding wire W connected to the drain electrode of the first switching element Q1 and a bonding wire W connected to the source electrode of the second switching element Q2. Capacitor C3 is located in a region sandwiched between the source electrode of the fifth switching element Q5 and the source electrode of the sixth switching element Q6.

The area where capacitor C1 is placed and the area where capacitor C2 is placed are separated by a bonding wire W that connects circuit pattern 28 and circuit pattern 31. The area where capacitor C1 is placed and the area where capacitor C3 is placed are separated by a bonding wire W that connects circuit pattern 34 and circuit pattern 37.

As shown in (b) of Figure 24, in variant 1, a circuit loop 3-1 including capacitor C2 is formed, a circuit loop 3-2 including capacitor C1 is formed, and a circuit loop 3-3 including capacitor C3 is formed. Compared to the circuit loops 3-1 to 3-3 shown in (b) of Figure 24, the lengths of the circuit loops 3-1 to 3-3 shown in (b) of Figure 24 are shorter, and the loop areas of the circuit loops 3-1 to 3-3 are smaller.

Figure 25 shows a modified example of the motor control circuit shown in Figure 6. Compared to Figure 6, the circuit shown in Figure 25 has negative terminals N1 to N3 instead of negative terminal N. In addition, current detection circuits are provided between negative terminal N1 and the negative DC input terminal, between negative terminal N2 and the negative DC input terminal, and between negative terminal N3 and the negative DC input terminal.

Figure 26 is a diagram showing a power board 10 of the circuit shown in Figure 25 as variant 2. Compared to Figure 14, a negative terminal N1 is provided in the vicinity of source terminal Q2-S of circuit pattern 23, a negative terminal N2 is provided in the vicinity of source terminal Q4-S of circuit pattern 23, and a negative terminal N3 is provided in the vicinity of source terminal Q6-S of circuit pattern 23.

In the power board 10 shown in Figure 26, as with the power board 10 shown in Figure 14, the length of each circuit loop 1-1 to 1-6, 2-1, 2-2, 3-1 to 3-3 within the power module 1 is made as short as possible, and the loop area of each loop is made as small as possible.

Figure 27 is a diagram for explaining the common impedance CI within the power module 1 in Modification 2. Figure 27 shows the area around Q2. As with the explanation in Figure 18(b), in Modification 2, the common impedance CI within the power module 1 can also be minimized.

Second Embodiment
Next, a power module 1 according to a second embodiment will be described with reference to Fig. 28 to Fig. 33. Fig. 28 is a diagram showing the circuit configuration of the power module 1 according to the second embodiment.

As shown in Figure 28, the power module 1 of the second embodiment includes a power board 10 and a driver board 3. Note that the circuit configuration of the power board 10 is the same as in the first embodiment, so a detailed description will be omitted.

Driver board 3 has GaN-FET drive circuits DR1 to DR6 and an interface circuit IF.

The GaN-FET drive circuit DR1 is connected to the source terminal A (Q1-S) and gate terminal B (Q1-G), and drives the first switching element Q1 via the source terminal Q1-S and gate terminal Q1-G. A predetermined control signal is input to the GaN-FET drive circuit DR1 from the interface circuit IF, and a predetermined control voltage is input from the upper arm power supply input terminal VU1.

The GaN-FET drive circuit DR2 is connected to the gate terminal G (Q2-G) and source terminal H (Q2-S), and drives the second switching element Q2 via the gate terminal Q2-G and source terminal Q2-S. A predetermined control signal and a predetermined control voltage are input to the GaN-FET drive circuit DR2 from the interface circuit IF.

The GaN-FET drive circuit DR3 is connected to the source terminal C (Q3-S) and gate terminal D (Q3-G), and drives the third switching element Q3 via the source terminal Q3-S and gate terminal Q3-G. A predetermined control signal is input to the GaN-FET drive circuit DR3 from the interface circuit IF, and a predetermined control voltage is input from the upper arm power supply input terminal VU2.

The GaN-FET drive circuit DR4 is connected to the gate terminal I (Q4-G) and source terminal J (Q4-S), and drives the fourth switching element Q4 via the gate terminal Q4-G and source terminal Q4-S. A specified control signal and a specified control voltage are input to the GaN-FET drive circuit DR4 from the interface circuit IF.

The GaN-FET drive circuit DR5 is connected to the source terminal C (Q5-S) and gate terminal D (Q5-G), and drives the fifth switching element Q5 via the source terminal Q5-S and gate terminal Q5-G. A predetermined control signal is input to the GaN-FET drive circuit DR5 from the interface circuit IF, and a predetermined control voltage is input from the upper arm power supply input terminal VU3.

The GaN-FET drive circuit DR6 is connected to the gate terminal K (Q6-G) and source terminal L (Q6-S), and drives the sixth switching element Q6 via the gate terminal Q6-G and source terminal Q6-S. A predetermined control signal and a predetermined control voltage are input to the GaN-FET drive circuit DR6 from the interface circuit IF.

Predetermined control signals are input to the interface circuit IF from the outside via interface terminals IF1-IFn. Predetermined control voltages are also input to the interface circuit IF from the lower arm power supply input terminals VL1-VL3. These predetermined control voltages input from the lower arm power supply input terminals VL1-VL3 are voltages used to drive the GaN-FET drive circuits DR2, DR4, and DR6, respectively.

Figure 29 is a cross-sectional view and a top view showing the configuration of a power module 1 according to the second embodiment. Figure 29(a) shows a cross-sectional view, and Figure 29(b) shows a top view. Note that the configuration of the power board 10 is the same as that of the first embodiment described above, so illustrations and detailed description will be omitted.

As shown in Figure 29(a), in the power module 1 according to the second embodiment, the driver board 3 is disposed between the power board 10 and the lid 12, approximately parallel to the power board 10 and the lid 12. The driver board 3 is received in a driver board receiver 11a of the case 11. The interior of the case 11, including the driver board 3, is filled with silicone gel 13.

As shown in Figure 29(b), the driver board 3 is provided with GaN-FET drive circuits DR1 to DR6, interface terminals IF1 to IFn, upper arm power supply input terminals VU1 to VU3, and lower arm power supply input terminals VL1 to VL3. Although not shown in Figure 29, the driver board 3 is also provided with an interface circuit IF.

In the second embodiment, in a plan view, a GaN-FET drive circuit DR1 is provided near the first switching element Q1, and a GaN-FET drive circuit DR2 is provided near the second switching element Q2. Furthermore, a GaN-FET drive circuit DR3 is provided near the third switching element Q3, and a GaN-FET drive circuit DR4 is provided near the fourth switching element Q4. Furthermore, a GaN-FET drive circuit DR5 is provided near the fifth switching element Q5, and a GaN-FET drive circuit DR6 is provided near the sixth switching element Q6.

In addition, in the second embodiment, in a plan view, the upper arm power supply input terminal VU1 is provided near the GaN-FET drive circuit DR1, the upper arm power supply input terminal VU2 is provided near the GaN-FET drive circuit DR3, and the upper arm power supply input terminal VU3 is provided near the GaN-FET drive circuit DR5.

Figure 30 is a diagram showing a virtual division of high-affinity circuits into blocks in the power module 1 according to the second embodiment. As shown in Figure 30, the circuits formed in the power module 1 according to the second embodiment are divided into four blocks, A, B, C, and D, according to high-affinity circuits.

Here, a "circuit with high affinity" refers to a circuit that is grouped together at a similar potential. Within this circuit with high affinity, malfunctions due to noise, etc. are unlikely to occur even if the various parts are placed close to each other. On the other hand, if circuits belonging to different blocks are placed close to each other, they are more likely to malfunction due to noise, etc., due to the influence of different potentials.

As shown in Figure 30, block A includes a first switching element Q1, a GaN-FET drive circuit DR1, a gate terminal B, a source terminal A, an output terminal OUT1, and an upper arm power supply input terminal VU1.

Block A corresponds to one of the upper arms of the power module 1. Therefore, in block A, the potential swings widely between a high voltage (e.g., 400 V) and a low voltage (e.g., 0 V) each time the first switching element Q1 is turned on or off.

Block B includes a third switching element Q3, a GaN-FET drive circuit DR3, a gate terminal D, a source terminal C, an output terminal OUT2, and an upper arm power input terminal VU2.

Block B corresponds to one of the upper arms of power module 1. Therefore, in block B, the potential swings widely between a high voltage (e.g., 400 V) and a low voltage (e.g., 0 V) each time the third switching element Q3 is turned on or off.

Block C includes a fifth switching element Q5, a GaN-FET drive circuit DR5, a gate terminal F, a source terminal E, an output terminal OUT3, and an upper arm power input terminal VU3.

Block C corresponds to one of the upper arms of the power module 1. Therefore, in block C, the potential swings widely between a high voltage (e.g., 400 V) and a low voltage (e.g., 0 V) each time the fifth switching element Q5 is turned on or off.

Block D includes the second switching element Q2, the fourth switching element Q4, the sixth switching element Q6, GaN-FET drive circuits DR2, DR4, and DR6, the interface circuit IF, gate terminals G, I, and K, source terminals H, J, and L, interface terminals IF1 to IFn, and power input terminals VL1 to VL3 for the lower arm.

Such block D corresponds to the three lower arms of the power module 1. Therefore, in such block D, even when the second switching element Q2, the fourth switching element Q4, or the sixth switching element Q6 is turned on or off, the potential does not swing significantly between high and low voltages, and the potential is maintained near a low voltage (e.g., 0 V).

Figure 31 is a diagram showing the power board 10 of the power module 1 according to the second embodiment divided into blocks using the method shown in Figure 30. As shown in Figure 31, on the power board 10, most of block A is arranged along the upper portion of the left short side and the left portion of the upper long side. On the power board 10, most of block C is arranged along the upper portion of the right short side and the right portion of the upper long side. On the power board 10, most of block B is arranged so as to be sandwiched between blocks A and C. On the power board 10, block D is arranged roughly in the lower half.

Figure 32 is a diagram showing the driver board 3 of the power module 1 according to the second embodiment divided into blocks using the method shown in Figure 30. As shown in Figure 32, on the driver board 3, block A is arranged in a rectangular shape along the upper part of the left short side and the left part of the upper long side. On the driver board 3, block C is arranged in a rectangular shape along the upper part of the right short side and the right part of the upper long side. On the driver board 3, block B is arranged so as to be sandwiched between blocks A and C. On the driver board 3, block D is arranged in a rectangular shape in the lower half.

Figure 33 is a diagram showing the overlapping of blocks on the power board 10 and blocks on the driver board 3 of the power module 1 according to the second embodiment. In Figure 33, the shaded areas indicate where different blocks overlap. As shown in Figure 33, in the power module 1 of the second embodiment, block A corresponding to one of the upper arms, block B corresponding to one of the upper arms, block C corresponding to one of the upper arms, and block D corresponding to the three lower arms are each designed to overlap as much as possible in the thickness direction. There are areas where block A and block D partially overlap, areas where block A and block D partially overlap, and areas where block C and block D partially overlap.

This prevents circuits belonging to different blocks from being placed close to each other. Therefore, according to the second embodiment, malfunctions due to noise, etc. can be suppressed.

In the second embodiment, as shown in FIG. 29(b), gate terminal B and source terminal A belonging to block A, gate terminal D and source terminal C belonging to block B, and gate terminal F and source terminal E belonging to block C are arranged in an area away from block D. Furthermore, gate terminals G, I, K and source terminals H, J, L belonging to block D are arranged in an area away from blocks A, B, and C.

This prevents noise from different blocks from being input to the gate terminals B, D, F, G, I, and K and the source terminals A, C, E, H, J, and L. Therefore, according to the second embodiment, it is possible to prevent the first switching element Q1 to the sixth switching element Q6 from malfunctioning due to noise or the like.

Although the above describes various embodiments of the present disclosure, the present disclosure is not limited to the above embodiments, and various modifications are possible without departing from the spirit of the present disclosure.

For example, in each of the above-described embodiments, an example was shown in which capacitor C1 was composed of a single capacitor, but capacitor C1 does not have to be composed of a single capacitor. Capacitor C1 may be composed of multiple capacitors connected in series, or multiple capacitors connected in parallel. Capacitor C1 may also be composed of a capacitor and a resistor connected in series.

In addition, in the above-described embodiments, examples have been shown in which the electrodes of the first to sixth switching elements Q1 to Q6 are connected to the corresponding circuit patterns by bonding wires W. However, the members connecting the electrodes of the first to sixth switching elements Q1 to Q6 to the circuit patterns are not limited to bonding wires W. For example, the electrodes of the first to sixth switching elements Q1 to Q6 may be electrically connected to the circuit patterns by a lead frame or the like.

Furthermore, in each of the above embodiments, GaN-FETs have been described, but the GaN-FETs may be other GaN-based switching elements. Furthermore, in each of the above embodiments, Si-FETs have been described, but the Si-FETs may be other Si-based switching elements.

In addition, in the second embodiment described above, an example was shown in which capacitor C1 was mounted on the power board 10, but capacitor C1 may also be mounted on the driver board 3, or on a separately provided printed circuit board 2. In this case, capacitor C1 only needs to be located in the center portion 4 of the power board 10 in a plan view.

As described above, the power module 1 according to each embodiment includes a power board 10 having three upper arms, namely, the first switching element Q1, the third switching element Q3, and the fifth switching element Q5, and three lower arms, namely, the second switching element Q2, the fourth switching element Q4, and the sixth switching element Q6. The power module 1 according to each embodiment also includes a capacitor C1 in the center of the power board 10. The three upper arm switching elements and the three lower arm switching elements are arranged on either side of the capacitor C1. Each switching element has a rectangular shape with long and short sides, with a drain electrode provided on one long side and a gate electrode provided on the other long side. The three upper arm switching elements and the three lower arm switching elements are arranged so that the drain electrode and gate electrode are oriented in opposite directions. This allows circuit loops 1-1 to 1-6, circuit loops 2-1 to 2-2, and circuit loops 3-1 to 3-3 to be as short as possible, and also minimizes the loop area of these circuit loops. This reduces the wiring inductance of the power module 1.

In addition, in the power module 1 according to each embodiment, a drain electrode is provided along one long side of the switching element, and a source electrode is provided along the other long side. Furthermore, each switching element is arranged so that its short side faces the long side of the power board 10. This reduces the wiring inductance of the power module 1.

In addition, in the power module 1 according to each embodiment, the location where the bonding wire W extending from the source electrode of the Si-FET is connected to the circuit pattern 21 is designated as the first connection portion 51, and the location where the bonding wire W extending from the gate electrode of the GaN-FET is connected to the circuit pattern 21 is designated as the second connection portion 52. The first connection portion 51 is located closer to the short side of the power substrate 10 than the second connection portion 52. This reduces the overlap between the large current line including the first connection portion 51 and the small current line including the second connection portion 52. This minimizes the common impedance CI of the power module 1.

In addition, in the power module 1 according to each embodiment, the point where the bonding wire W extending from the source electrode of the Si-FET in the second switching element Q2 connects to the circuit pattern 23 is designated as the third connection portion 53, and the point where the bonding wire W extending from the gate electrode of the GaN-FET connects to the circuit pattern 23 is designated as the fourth connection portion 54. The third connection portion 53 is located closer to the center of the power board 10 than the fourth connection portion 54. This reduces the overlap between the large current line IL flowing from the drain terminal to the source terminal of the second switching element Q2 and the small current line IS flowing from the gate electrode to the source terminal of the GaN-FET included in the second switching element Q2. This minimizes the common impedance CI of the power module 1.

Furthermore, in the power module 1 according to each embodiment, capacitor C1 is placed in an area sandwiched between the bonding wire W connecting circuit pattern 28 and circuit pattern 31 and the bonding wire W connecting circuit pattern 34 and circuit pattern 37. This allows the power module 1 to be made smaller.

In the power module 1 according to Variation 1 of the first embodiment, capacitor C1 is located in a region sandwiched between a bonding wire W connected to the drain electrode of the third switching element Q3 and a bonding wire W connected to the source electrode of the fourth switching element Q4. Capacitor C2 is located in a region sandwiched between a bonding wire W connected to the drain electrode of the first switching element Q1 and a bonding wire W connected to the source electrode of the second switching element Q2. Capacitor C3 is located in a region sandwiched between the source electrode of the fifth switching element Q5 and the source electrode of the sixth switching element Q6. This shortens the circuit loops 3-1 to 3-3 and further reduces the loop areas of these circuit loops. This further reduces the wiring inductance of the power module 1.

The power module 1 according to the second embodiment includes a power board 10 mounted with six arms, the first switching element Q1 through the sixth switching element Q6, and a driver board 3 mounted with GaN-FET drive circuits DR1 through DR6 that drive the first switching element Q1 through the sixth switching element Q6, respectively. The driver board 3 is positioned between the power board 10 and the lid 12, approximately parallel to the power board 10 and the lid 12. The power board 10 and the driver board 3 are divided into four blocks A, B, C, and D, each with a high degree of affinity for the circuit. Blocks A through D of the power board 10 are positioned to overlap blocks A through D of the driver board 3, respectively. This prevents the first switching element Q1 through the sixth switching element Q6 from malfunctioning due to noise or other factors.

Furthermore, in the power module 1 according to each embodiment, the capacitor C1 is mounted in the central portion 4 on the power board 10. This eliminates the need to provide a separate printed circuit board 2 to mount the capacitor C1, thereby reducing the manufacturing cost of the power module 1.

In addition, in the power module 1 according to each embodiment, the first to sixth switching elements Q1 to Q6 are cascade GaN-FETs in which the source electrode located on the front surface of the GaN-FET is electrically and mechanically connected to the drain electrode located on the back surface of the Si-FET. This allows the normally-on GaN-FET to be driven as a normally-off switching element.

The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. Indeed, the above-described embodiments may be embodied in a variety of forms. Furthermore, the above-described embodiments may be omitted, substituted, or modified in various ways without departing from the scope and spirit of the appended claims.

REFERENCE SIGNS LIST 1 Power module 2 Printed circuit board 3 Driver board 4 Central portion 10 Power board 21 to 43 Circuit pattern 51 First connection portion 52 Second connection portion P Positive terminal N Negative terminal C1 to C3 Capacitors Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element Q5 Fifth switching element Q6 Sixth switching element W Bonding wire

Claims (3)

a power board on which switching elements constituting the three upper arms and three lower arms are mounted on a single circuit board;
a driver board including drivers for driving the three upper arms and the three lower arms,
A power module in which the power board and the driver board are arranged to be spaced apart in a thickness direction of the boards,
an area included in the power board and the driver board, the area including three blocks each including a circuit that operates using a potential of the source electrode of the switching elements that configure the three upper arms as a reference potential; and a block including a circuit that operates using a potential of a common source electrode of the three switching elements that configure the three lower arms as a reference potential;
the three blocks corresponding to the upper arm on the power board and the three blocks corresponding to the upper arm on the driver board are arranged at positions where blocks having the same reference potential substantially overlap each other in a thickness direction of the board;
the block corresponding to the lower arm on the power board and the block corresponding to the lower arm on the driver board are disposed at positions that substantially overlap each other in a thickness direction of the boards,
the three blocks corresponding to the upper arms on the power board each include an area for inter-arm wiring connecting the upper arms and the lower arms;
the three blocks corresponding to the upper arms on the power board and the block corresponding to the lower arms on the driver board do not overlap in a thickness direction of the board in an area other than an area of the inter-arm wiring. The power module of claim 1, wherein wiring supplying power to the three upper arms is arranged near the boundary between the three blocks on the power board corresponding to the upper arms and the block on the power board corresponding to the lower arm. 3. The power module according to claim 2 , wherein wiring for supplying power to the three lower arms is arranged substantially parallel to wiring for supplying power to the three upper arms.