JP7783064B2 - Power interruption protection circuit, power interruption protection circuit control method, power interruption protection controller, and data storage device - Google Patents

Description

This disclosure relates to a power interruption protection circuit.

A stable supply of power voltage is essential for electronic components. A momentary power interruption in storage devices such as solid-state drives and hard disks poses the risk of data corruption or loss. Even after the input voltage is cut off, it is necessary to maintain the power voltage for the load to perform necessary protection processes, such as data evacuation. This type of function is known as power interruption protection, PLP (Power Loss Protection), PLI (Power Loss Imminent), or PFP (Power Failure Protection).

1 is a block diagram of a system with a PLP function. The system 2 includes a main power supply 10, a load 20, and a power interruption protection circuit 30. The main power supply 10 generates an input voltage V _IN of approximately 12 V. The load 20 includes a PMIC (power management circuit) 22 and multiple electronic components 24_1 to 24_n. The PMIC 22 receives a 12 V power supply voltage V _DD , boosts or lowers it, and supplies it to the electronic components 24_1 to 24_n.

The power interruption protection circuit 30 is provided between the main power supply 10 and the load 20. The power interruption protection circuit 30 includes a switch 32, a backup capacitor 34, and a step-up/step-down bidirectional DC/DC converter 36.

The switch 32, also referred to as an electronic fuse, is provided on a power supply line 38 connecting the main power supply 10 and the load 20. While a valid input voltage _VIN is supplied, the switch 32 is on, and the input voltage _VIN is supplied to the load 20 as the power supply voltage _VDD . An input terminal IN of a DC/DC converter 36 is connected to the power supply line 38, and an output terminal OUT is connected to the backup capacitor 34. While the input voltage _VIN is being supplied, the DC/DC converter 36 boosts the input voltage _VIN and charges the backup capacitor 34. If the capacitance of the backup capacitor 34 is C and the voltage generated in the backup capacitor 34 is _VSTR , the charge Q and energy E stored in the backup capacitor 34 are expressed by the following equations:
Q = C.V. _STR
E is E=C・V _STR ² /2

When the power supply interruption protection circuit 30 detects an interruption (loss) of the input voltage _VIN , it turns off the switch 32. Then, the DC/DC converter 36 operates in the reverse direction as a step-down converter with the OUT side as the input and the IN side as the output, and steps down the capacitor voltage _VSTR of the backup capacitor 34 to the voltage level of the power supply voltage _VDD and supplies it to the load 20.

Japanese Patent Application Laid-Open No. 2021-5924

Causes of power loss to the load 20 include loss/reduction of the input voltage _VIN , a ground fault at the input terminal, an increase in the input voltage, and an increase in the current of the load 20. In other words, if the load current becomes an overcurrent and the power from the main power supply 10 becomes insufficient, the power supply voltage _VDD will drop.

This disclosure has been made in light of these issues, and one exemplary purpose of one aspect thereof is to provide a power interruption protection circuit that is robust against overcurrent.

A power interruption protection circuit according to one embodiment of the present disclosure includes an input line for receiving an input voltage, an output line for connection to a load, a backup capacitor, a switching power supply that is switchable between step-up mode and step-down mode and is connected to the output line and the backup capacitor, and that, in step-up mode, steps up the bus voltage of the output line to charge the backup capacitor, and, in step-down mode, steps down the voltage of the backup capacitor and supplies it to the output line, an electronic fuse circuit that is provided between the input line and the output line and is electrically switchable between an on state and an off state and has a current clamping function in the on state, an undervoltage lockout circuit that asserts an undervoltage lockout signal when the bus voltage of the output line falls below a threshold, and control logic that, when the undervoltage lockout signal is asserted, turns off the electronic fuse circuit and switches the switching power supply to step-down mode.

Another aspect of the present disclosure is a power interruption protection controller. This power interruption protection controller includes an input pin for receiving an input voltage, an output pin for connection to a load, a capacitor connection pin for connection to a backup capacitor, at least one switching pin for connection to the output pin via an external inductor, a converter block switchable between step-up mode and step-down mode, connected to the at least one switching pin, the output pin, and the capacitor connection pin, and stabilizing the voltage of the backup capacitor at a first target level in step-up mode and stabilizing the voltage of the output pin at a second target level in step-down mode, an electronic fuse circuit disposed on a power supply line connecting the input pin and the output pin, electrically switchable between an on state and an off state, and having a current clamp function in the on state, an undervoltage lockout circuit that asserts an undervoltage lockout signal when the voltage of the output pin falls below a threshold, and control logic that, when the undervoltage lockout signal is asserted, turns off the electronic fuse circuit and switches the converter block to step-down mode.

In addition, any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or this disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention.

Certain aspects of the present disclosure can provide robust power interruption protection even against overcurrent.

FIG. 1 is a block diagram of a system with PLP functionality. FIG. 2 is a block diagram of a system including a power interruption protection circuit according to the first embodiment. FIG. 3 is an operational waveform diagram of the power supply cutoff protection circuit of FIG. FIG. 4 is an operational waveform diagram of the comparative technique. FIG. 5 is a circuit diagram of an example of the configuration of an electronic fuse and an overcurrent detection circuit. FIG. 6 is a block diagram of a system including a power interruption protection circuit according to the second embodiment. FIG. 7 is an operational waveform diagram of the power cutoff protection circuit of FIG. FIG. 8 is a circuit diagram of a system including a power interruption protection circuit according to the third embodiment. FIG. 9 is a circuit diagram of a system including a power interruption protection circuit according to the fourth embodiment. FIG. 10 is a block diagram of a data storage device with a PLP function.

(Outline of the embodiment)
A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

One embodiment of a power interruption protection circuit includes an input line for receiving an input voltage, an output line for connection to a load, a backup capacitor, a switching power supply that is switchable between step-up mode and step-down mode and is connected to the output line and the backup capacitor, and that, in step-up mode, steps up the bus voltage of the output line to charge the backup capacitor, and, in step-down mode, steps down the voltage of the backup capacitor and supplies it to the output line, an electronic fuse circuit that is provided between the input line and the output line and is electrically switchable between an on state and an off state and has a current clamping function in the on state, an undervoltage lockout circuit that asserts an undervoltage lockout signal when the bus voltage of the output line falls below a threshold, and control logic that, when the undervoltage lockout signal is asserted, turns off the electronic fuse circuit and switches the switching power supply to step-down mode.

In normal operating mode (normal state), the switching power supply operates in boost mode and stores power in the backup capacitor. In normal operating mode, when the load current increases, the current clamp circuit of the electronic fuse circuit is activated and the current flowing through the electronic fuse circuit is clamped. As a result, the bus voltage of the output line drops. When the drop in bus voltage is detected by the undervoltage lockout circuit, the electronic fuse circuit is turned off and the switching power supply switches to buck mode, supplying the power stored in the backup capacitor to the load. This configuration provides robust power interruption protection even against overcurrent.

In one embodiment, the power interruption protection circuit may further include an overcurrent detection circuit that has a threshold lower than the limit current of the electronic fuse circuit and asserts an overcurrent detection signal when the current on the input line exceeds the threshold. The assertion of the overcurrent detection signal may be transmitted to the load.

In one embodiment, the switching power supply may include a step-up/step-down bidirectional DC/DC converter that is reversible in the direction of power transmission between step-up mode and step-down mode.

In one embodiment, the power interruption protection circuit may further include a protection switch connected between the inductor of the step-up/step-down bidirectional DC/DC converter and the output line. If the backup capacitor fails in short mode, power can be continued to be supplied to the load by turning off the protection switch.

In one embodiment, the switching power supply may include a boost converter that is active in boost mode and has an input node connected to the output line and an output node connected to the backup capacitor, and a buck converter that is active in buck mode and boost mode and has an input node connected to the output line and an output node connected to the backup capacitor. In a configuration using a bidirectional DC/DC converter, a control delay occurs when switching the operating mode of the bidirectional DC/DC converter, which can cause a drop in power supply voltage. In contrast, in a configuration where the switching power supply includes a boost converter and a buck converter, by keeping the buck converter operating at all times, there is no need to wait for the buck converter to start up when a power loss occurs, and power stored in the backup capacitor can be quickly supplied to the load.

In one embodiment, the power interruption protection circuit may further include a protection switch connected between the inductor of each of the boost converter and the buck converter and the output line. If the backup capacitor fails in short-circuit mode, turning off the protection switch allows power to continue being supplied to the load.

In one embodiment, the load may be a solid state drive (SSD).

A data storage device according to one embodiment may include any of the power interruption protection circuits described above.

In one embodiment, the power interruption protection controller includes an input pin for receiving an input voltage, an output pin for connecting to a load, a capacitor connection pin for connecting a backup capacitor, at least one switching pin for connecting to the output pin via an external inductor, a converter block that is switchable between step-up mode and step-down mode and is connected to at least one switching pin, the output pin, and the capacitor connection pin, and that stabilizes the voltage of the backup capacitor at a first target level in step-up mode and the voltage of the output pin at a second target level in step-down mode, an electronic fuse circuit that is provided on a power supply line connecting the input pin and the output pin, is electrically switchable between an on state and an off state, and has a current clamping function in the on state, an undervoltage lockout circuit that asserts an undervoltage lockout signal when the voltage of the output pin falls below a threshold, and control logic that, when the undervoltage lockout signal is asserted, turns off the electronic fuse circuit and switches the converter block to step-down mode.

In one embodiment, the power interruption protection controller may further include an overcurrent detection circuit that has a threshold lower than the limit current of the electronic fuse circuit and asserts an overcurrent detection signal when the current on the power line exceeds the threshold. The assertion of the overcurrent detection signal may be transmitted to the load.

In one embodiment, the converter block may include a step-up/step-down bidirectional DC/DC converter that can reverse the direction of power transfer between step-up mode and step-down mode.

In one embodiment, the converter block may include a boost converter that is active in boost mode and has the capacitor connection pin as its output, and a buck converter that is active in both boost mode and buck mode and has the capacitor connection pin as its input.

In one embodiment, the power interruption protection controller may be monolithically integrated on a single semiconductor substrate. "Monolithic integration" includes cases where all of the circuit components are formed on a semiconductor substrate, or where the main circuit components are monolithically integrated; some resistors and capacitors for adjusting circuit constants may be provided outside the semiconductor substrate. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be maintained uniformly.

In one embodiment, the load may be a solid state drive (SSD).

(Embodiment)
Preferred embodiments will be described below with reference to the drawings. Identical or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted where appropriate. Furthermore, the embodiments are illustrative and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, "a state in which component A is connected to component B" includes not only cases in which components A and B are directly physically connected, but also cases in which components A and B are indirectly connected via other components that do not affect the electrical connection or impair function. Furthermore, "a state in which component C is provided between components A and B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which components C and A are indirectly connected via other components that do not affect the electrical connection or impair function.

(Embodiment 1)
2 is a block diagram of a system 2A including a power interruption protection circuit 100A according to embodiment 1. The system 2A includes a main power supply 10, a load 20, and a power interruption protection circuit 100A. The main power supply 10 is, for example, an AC/DC converter or a USB (Universal Serial Bus) bus, and supplies a DC input voltage V _IN of a predetermined first voltage level (hereinafter, 12 V) to the power interruption protection circuit 100A.

The power interruption protection circuit 100A receives an input voltage V _IN and supplies a bus voltage V _BUS to a load 20 .

The power interruption protection circuit 100A includes an input line 104, an output line 108, an electronic fuse circuit 220, a backup capacitor 102, a switching power supply 110A, a UVLO (undervoltage lockout) circuit 230, control logic 240A, and an overcurrent detection circuit 250.

A bus line connects the main power supply 10 and the load 20. An electronic fuse circuit 220 is provided on the bus line. The bus line is defined as an input line 104 on the main power supply 10 side of the electronic fuse circuit 220, and as an output line 108 on the load 20 side of the electronic fuse circuit 220. An input voltage _VIN is supplied to the input line 104. The load 20 is connected to the output line 108.

The electronic fuse circuit 220 is provided between the input line 104 and the output line 108, and is electrically switchable between an ON state and an OFF state. The electronic fuse circuit 220 has a current clamping function (current limiting function), and in the ON state, limits the current I _IN flowing through the electronic fuse circuit 220 so that it does not exceed a predetermined limit current I _LIM (I _IN <I _LIM ).

The backup capacitor 102 is connected to the backlap line 106.

The switching power supply 110A is connected to the output line 108 and the backup capacitor 102. The switching power supply 110A is switchable between a step-up mode and a step-down mode, and in the step-up mode, it steps up the bus voltage V _BUS of the output line 108 and charges the backup capacitor 102. By this charging, the voltage V _STR of the backup capacitor 102 is stabilized at a predetermined voltage level.

In the step-down mode, the switching power supply 110A steps down the voltage _VSTR of the backup capacitor 102 and supplies the voltage to the output line 108. In this embodiment, the switching power supply 110A is a step-up/step-down bidirectional DC/DC converter, and the direction of power transmission can be reversed between the step-up mode and the step-down mode.

UVLO circuit 230 asserts an undervoltage lockout signal UVLO when the bus voltage V _BUS on output line 108 falls below a predetermined threshold V _UVLO .

The control logic 240A comprehensively controls the PLP controller 200A. Specifically, the control logic 240A controls the on/off state of the electronic fuse circuit 220 and also controls the operating mode of the converter block 210A.

When the UVLO signal is asserted, the control logic 240A turns off the electronic fuse circuit 220 and switches the switching power supply 110A to step-down mode.

The overcurrent detection circuit 250 has a threshold value _{I_OCP} that is lower than the limit current _{I_LIM} of the electronic fuse circuit 220, and asserts an overcurrent detection signal OCD when the bus current _{I_BUS} flowing through the bus line exceeds the threshold value _{I_OCP} . When the OCD signal is asserted, the control logic 240A notifies the load 20. In this embodiment, the overcurrent detection signal OCD does not affect the control of the electronic fuse circuit 220 or the switching power supply 110A.

Some of the components of the power interruption protection circuit 100A are integrated into a power interruption protection controller (hereinafter referred to as the PLP controller) 200A. Specifically, the PLP controller 200A is a functional integrated circuit (IC) that includes a converter block 210A, an electronic fuse circuit 220, a UVLO circuit 230, control logic 240A, and an overcurrent detection circuit 250, and is integrated onto a single semiconductor substrate.

The PLP controller 200A includes an input pin VIN, an output pin VBUS, a switching pin LX, a capacitor connection pin STR, and feedback pins FB1 and FB2. The input pin VIN is connected to a main power supply 10 and receives an input voltage _VIN . The output pin VBUS is connected to a load 20. The electronic fuse circuit 220 is connected between the input pin VIN and the output pin VBUS.

The switching power supply 110A includes a converter block 210A, an inductor L1, and a capacitor C1. The capacitor C1 is connected to the output line 108. The switching pin LX is connected to the output line 108 via the external inductor L1.

The converter block 210A includes a high-side transistor M1, a low-side transistor M2, and a feedback controller 212. The feedback controller 212 receives a feedback voltage _VFB1 corresponding to the voltage _VSTR of the backup capacitor 102 via a feedback pin FB1. The feedback voltage _VFB1 may be a voltage obtained by dividing the voltage _VSTR .

In the boost mode, the feedback controller 212 drives the high-side transistor M1 and the low-side transistor M2 so that the feedback voltage _VFB1 approaches its target level.

The feedback controller 212 receives, via a feedback pin FB2, a feedback voltage _VFB2 that corresponds to the bus voltage _VBUS of the output line 108. The feedback voltage _VFB2 may be a voltage obtained by dividing the bus voltage _VBUS .

In the buck mode, the feedback controller 212 drives the high-side transistor M1 and the low-side transistor M2 so that the feedback voltage _VFB2 approaches its target level.

The above is the configuration of the power interruption protection circuit 100A. Next, we will explain its operation.

3 is an operation waveform diagram of the power supply interruption protection circuit 100A of FIG. 2. Before time _t0 , during the normal operation period, the control logic 240A turns on the electronic fuse circuit 220 and sets the switching power supply 110A to the boost mode. With the switching power supply 110A in the boost mode, the voltage V _STR of the backup capacitor 102 is stabilized at a target level, and energy E=½×C·V _STR ² is stored in the backup capacitor 102. During the normal operation period, the load current I _OUT and the input current I _IN are equal.

At time _t0 , the load current _IOUT flowing through the load 20 increases. Following the increase in the load current _IOUT , the input current _IIN also increases. When the input current _IIN exceeds the threshold value _IOCP of the overcurrent detection circuit 250 at time _t1 , the OCD signal is asserted. The control logic 240A does not use the assertion of the OCD signal to control the electronic fuse circuit 220 or the switching power supply 110A.

The input current I _IN is clamped to the limit current I _LIM by the electronic fuse circuit 220. Then, I _OUT > _IN , and the capacitor C1 is discharged, causing the bus voltage V _BUS to decrease over time.

At time _t2 , when the bus voltage V _BUS falls below the threshold voltage V _UVLO of the UVLO circuit 230, the UVLO signal is asserted. In response to the assertion of the UVLO signal, the control logic 240A turns off the electronic fuse circuit 220, thereby cutting off the input current I _IN . In addition, in response to the assertion of the UVLO signal, the control logic 240A switches the switching power supply 110A to the step-down mode, thereby supplying the backup current I _STR to the load 20 as the load current I _OUT from the switching power supply 110A. The voltage V _STR of the backup capacitor 102 decreases over time.

This completes the operation of the power supply interruption protection circuit 100A.

This power supply interruption protection circuit 100A can provide robust power supply interruption protection functionality even against overcurrent.

The advantages of the power interruption protection circuit 100A become clear when compared with the comparative technology. Figure 4 is an operational waveform diagram of the comparative technology. In the comparative technology, in response to the assertion of the OCD signal at time _t1 , the electronic fuse circuit 220 is turned off and the switching power supply 110A switches to the step-down mode. In other words, in the comparative technology, when an overcurrent occurs, the power supply is immediately switched from the main power supply 10 to the backup capacitor 102.

Returning to the power interruption protection circuit 100A, in the power interruption protection circuit 100A, when the load 20 enters an overcurrent state (I _IN > I _OCP ), the electronic fuse circuit 220 is not immediately turned off, but rather the normal operating state is maintained, and the current I _IN limited to the limit current I _LIM is supplied from the main power supply 10 to the load 20. Then, when the bus voltage V _BUS drops to the threshold value V _UVLO , the power supply is switched from the main power supply 10 to the backup capacitor 102. In other words, compared to the comparative technology, the period during which the main power supply 10 can be used is extended by the length of t ₁ to t ₂ in FIG. 3 , and in exchange, the start of energy release from the backup capacitor 102 can be delayed. This delays the drop in the bus voltage V _BUS , and extends the period during which the load 20 can operate.

Figure 5 is a circuit diagram of an example configuration of the electronic fuse circuit 220 and overcurrent detection circuit 250. The electronic fuse circuit 220 includes transistors M11 to M15, resistor R11, external resistor R12, operational amplifier 222, voltage source 224, operational amplifier 226, and gate driver 228. Transistors M11 and M12 are switches that switch on and off between the input pin VIN and the output pin.

Transistors M13 and M14 are replicas of transistors M11 and M12, and are provided to detect the current I _IN flowing through the bus line. The gates of transistors M11 to M14 are connected in common. Transistor M15 is connected to transistor M14. An operational amplifier 222 receives the voltage at one end of transistor M14 and the voltage at the corresponding end of transistor M12 (i.e., the output pin VBUS). The output of operational amplifier 222 is connected to the gate of transistor M15. The operational amplifier 222 applies feedback so that the voltage at one end of transistor M14 becomes equal to the voltage at the corresponding end of transistor M12, that is, so that the voltage across transistors M11 and M12 becomes equal to the voltage across transistors M13 and M14. At this time, a detection current I _CS proportional to the input current I _IN flows through transistors M13 and M14.

Resistors R11 and R12 are connected between the drain of the transistor M15 and ground. For example, the PLP controller 200A may include a current sense pin CS, and the resistor R12 may be externally connected to the current sense pin CS. A voltage drop _VCS proportional to the detected current _ICS occurs across the resistor R12.

The voltage source 224 generates _a reference voltage V that defines the limit current _I. For example, the voltage source 224 may be a D/A converter that receives a digital setting value of the limit current _I and converts it into an analog voltage. The voltage source 224 may also be a constant voltage source.

The operational amplifier 226 receives the current detection signal _VCS and the reference voltage _VLIM and generates a voltage _VERR corresponding to the error between them. The gate driver 228 applies a high gate voltage _VG to the gates of the transistors M11 and M12 during the period when the electronic fuse circuit 220 should be turned on, thereby fully turning on the transistors M11 and M12. The gate driver 228 may have a soft start (SS) function to prevent inrush current. When turning on the electronic fuse circuit 220, the gate driver 228 with soft start gradually changes the gate voltage _VG , causing a gradual transition from the off state to the on state.

When V _CS < V _LIM , the gate driver 228 reduces the gate voltage _VG in accordance with the error voltage _VERR . This increases the resistance of the transistors M11 and M12, and feedback is applied in the direction of decreasing the input current I _IN . This feedback clamps the input current I _IN so that it does not exceed the limit current I _LIM .

The overcurrent detection circuit 250 includes a voltage source 252 and a comparator 254. The voltage source 252 generates a threshold voltage V _OCP that defines the overcurrent threshold I _OCP . For example, the voltage source 252 may be a D/A converter that receives a digital setting value that defines the overcurrent threshold I _OCP and converts it into an analog voltage. The voltage source 252 may also be a constant voltage source. The comparator 254 compares the current detection signal V _CS with the threshold voltage V _OCP and outputs an OCD signal that is high (asserted) when V _CS >V _OCP .

Note that the configurations of the electronic fuse circuit 220 and the overcurrent detection circuit 250 are not limited to those shown in FIG. 5. For example, transistors M11 to M14 of the electronic fuse circuit 220 may be PMOS transistors.

Furthermore, the method of current detection is not limited to the combination of replica transistors and resistors. For example, a sense resistor may be inserted in series with transistors M11 and M12 that make up the switch, and current clamping or overcurrent detection may be performed based on the voltage drop across the sense resistor.

Alternatively, the current can be detected based on the potential difference between the VIN terminal and the VBUS terminal, i.e., the voltage across transistors M11 and M12, and current clamping or overcurrent control can be performed based on the detected current.

(Embodiment 2)
6 is a block diagram of a system 2B including a power interruption protection circuit 100B according to embodiment 2. In the power interruption protection circuit 100B of FIG. 6, the configuration of a switching power supply 110B is different from that of the switching power supply 110A of FIG.

The switching power supply 110B includes a step-down converter 112 and a step-up converter 114. The PLP controller 200B has two switching pins LX1 and LX2 and two feedback pins FB1 and FB2. An inductor L1 is connected to the switching pin LX1, and an inductor L2 is connected to the switching pin LX2. A feedback voltage VFB1 corresponding to the output voltage _VBUS supplied to the load 20 is fed back to the feedback pin _FB1 . A feedback voltage VFB2 corresponding to the voltage _VSTR generated in the backup capacitor 102 is fed back to the feedback pin _FB2 .

Buck converter 112 is active in both the step-up mode and the step-down mode, and its input node is connected to backup capacitor 102 and its output node is connected to output line 108. Buck converter 112 includes a high-side transistor M1, a low-side transistor M2, and a feedback controller 214. Feedback controller 214 receives a feedback voltage _VFB2 that corresponds to a _bus voltage VBUS supplied to load 20, and drives high-side transistor M1 and low-side transistor M2 so that bus voltage _VBUS approaches its target level _VREF(BUCK) .

Preferably, the target voltage _VREF(BUCK) of the output voltage of the step-down converter 112 is set lower than the normal level of the input voltage _VIN (for example, 12 V). More preferably, it is set lower than the lower limit _VMIN of the normal voltage range of the load 20.
V _{REF (BUCK)} < V _MIN

For example, the target voltage _VREF(BUCK) of the buck converter 112 is set to 8 V. In this embodiment, the buck converter 112 has only a current source capability and does not have a current sink capability. Therefore, when the bus voltage _VBUS is higher than the target voltage _VREF(BUCK) , the buck converter 112 operates but does not affect the bus voltage _VBUS .

The boost converter 114 is disabled in the buck mode. The boost converter 114 is enabled in the boost mode, with its input node connected to the output line 108 and its output node connected to the backlap line 106. The boost converter 114 includes a high-side transistor M3, a low-side transistor M4, and a feedback controller 216. The feedback controller 216 receives a feedback voltage _VFB2 and drives the high-side transistor M3 and the low-side transistor M4 so that the voltage _VSTR generated across the backup capacitor 102 approaches its target level _VREF(BOOST) . The boost converter 114 may be a diode-rectified type in which the high-side transistor M3 is replaced with a diode.

Control logic 240B controls the operating mode of converter block 210B based on the UVLO signal generated by UVLO circuit 230. Specifically, under normal conditions, control logic 240B supplies a high enable signal EN_BOOST to feedback controller 216, enabling boost converter 114. When the UVLO signal is asserted, control logic 240B changes enable signal EN_BOOST to low, thereby disabling boost converter 114.

The above is the configuration of the PLP controller 200B. Next, we will explain its operation.

7 is an operational waveform diagram of the power interruption protection circuit 100B of FIG. 6. Before time _t0 , the normal operation period is reached, and the control logic 240B turns on the electronic fuse circuit 220. The control logic 240B also turns the enable signal EN_BOOST for the boost converter 114 high, setting the switching power supply 110B into boost mode.

The voltage _VSTR of ^the backup capacitor 102 is stabilized at the target level _VREF(BOOST) by the switching power supply 110B in boost mode, and energy E=1/2×C· _VSTR2 is stored in the backup capacitor 102. During normal operation, the load current _IOUT and the input current _IIN are equal. Also, as described above, the step-down converter 112 is operating, but does not affect the bus voltage _VBUS , so _{that VBUS≈VIN .}

At time _t0 , the load current _IOUT flowing through the load 20 increases. Following the increase in the load current _IOUT , the input current _IIN also increases. When the input current _IIN exceeds the threshold value _IOCP of the overcurrent detection circuit 250 at time _t1 , the OCD signal is asserted. The assertion of the OCD signal by the control logic 240B is not used to control the electronic fuse circuit 220 or the switching power supply 110B.

The input current I _IN is clamped to the limit current I _LIM by the electronic fuse circuit 220. Then, I _OUT > _IN , and the capacitor C1 is discharged, causing the bus voltage V _BUS to decrease over time.

At time _t2 , when the bus voltage V _BUS falls below the threshold voltage V _UVLO of the UVLO circuit 230, the UVLO signal is asserted. In response to the assertion of the UVLO signal, the control logic 240B turns off the electronic fuse circuit 220, thereby cutting off the input current I _IN . In addition, in response to the assertion of the UVLO signal, the control logic 240B switches the enable signal EN_BOOST for the boost converter 114 to low, switching the switching power supply 110B to the buck mode. As a result, the backup current I _STR is supplied from the switching power supply 110B to the load 20 as the load current I _OUT . The voltage V _STR of the backup capacitor 102 decreases over time.

This completes the operation of the power supply interruption protection circuit 100B.

In the power interruption protection circuit 100A of Fig. 2, the switching power supply 110A is configured with a single bidirectional DC/DC converter and is capable of switching between step-up mode and step-down mode. In this case, if there is a large delay in switching from step-up mode to step-down mode, the bus voltage _VBUS may drop during this delay. In contrast, in the power interruption protection circuit 100B of Fig. 6, there is no need to switch the converter from step-up operation to step-down operation, so there is no delay associated with the switching. Therefore, it is possible to prevent the bus voltage _VBUS from dropping.

Specifically, even when the input voltage _VIN is normal, the step-down converter 112 continues to operate without affecting the bus voltage _VBUS . Therefore, immediately after the electronic fuse circuit 220 turns off at time _t2 , the bus voltage _VBUS can be immediately stabilized to the target voltage _VREF(BUCK) .

The boost converter 114 may be a diode rectifier type, in which case the high-side transistor M1 may be configured as a diode.

(Embodiment 3)
8 is a circuit diagram of a system 2C including a power interruption protection circuit 100C according to the third embodiment. The power interruption protection circuit 100C includes a protection switch 260 in addition to the components of the power interruption protection circuit 100A in FIG. 2. The inductor L1 is connected to the VBUS pin via the protection switch 260. In other words, the inductor L1 and the VBUS pin can be electrically separated.

The protection switch 260 may be integrated into the PLP controller 200C. The PLP controller 200C further includes an inductor connection pin VB. The inductor L1 is externally connected between the VB pin and the LX pin. The protection switch 260 is connected between the VBUS pin and the VB pin.

Control logic 240C controls protection switch 260. Control logic 240C turns protection switch 260 on in step-up mode and step-down mode. For example, control logic 240C turns protection switch 260 off when it detects a short-circuit mode failure of backup capacitor 102 (a ground fault at the STR pin). Furthermore, control logic 240C may turn protection switch 260 off when it detects a ground fault at the LX pin.

The configuration of converter block 210C is similar to that of converter block 210A in Figure 2.

According to embodiment 3, in a situation where the backup capacitor 102 fails in short mode, the VBUS pin can be disconnected from the failure point, allowing power to continue to be supplied from the main power supply 10 to the load 20.

(Embodiment 4)
9 is a circuit diagram of a system 2D including a power interruption protection circuit 100D according to the fourth embodiment. The power interruption protection circuit 100D includes a protection switch 260 in addition to the components of the power interruption protection circuit 100B in FIG. 6. The inductors L1 and L2 are connected to the VBUS pin via the protection switch 260. That is, the inductors L1 and L2 can be electrically separated from the VBUS pin.

The protection switch 260 may be integrated into the PLP controller 200D. The PLP controller 200D further includes a VB pin. An inductor L1 is externally connected between the VB pin and the LX1 pin, and an inductor L2 is externally connected between the VB pin and the LX2 pin. The protection switch 260 is connected between the VBUS pin and the VB pin.

Control logic 240D controls protection switch 260. Control logic 240D turns protection switch 260 on in step-up mode and step-down mode. For example, control logic 240D turns protection switch 260 off when it detects a short-circuit mode failure of backup capacitor 102 (a ground fault at the STR pin). Furthermore, control logic 240D may turn protection switch 260 off when it detects a ground fault at the LX pin.

The configuration of converter block 210D is similar to that of converter block 210B in Figure 6.

According to embodiment 4, in a situation where the backup capacitor 102 fails in short mode, the VBUS pin can be disconnected from the failure point, allowing power to continue to be supplied from the main power supply 10 to the load 20.

(Application)
Power interruption protection circuits 100A to 100D (hereinafter collectively referred to as 100) according to the embodiments can be used in a data storage device 300. Fig. 10 is a block diagram of the data storage device 300 with a PLP function. The data storage device 300 is, for example, an SSD (Solid State Drive), and includes the power interruption protection circuit 100, a PMIC 302, a controller 304, a NAND memory 306, a cache memory 308, and an interface 310.

The data storage device 300 may be for a server, built into a computer, or a portable SSD.

The power interruption protection circuit 100 receives a DC input voltage V _DC from an AC/DC converter or a USB bus (the above-mentioned main power supply 10, not shown in FIG. 10 ), and supplies a power supply voltage V _DD of a predetermined voltage level to the PMIC 302. The PMIC 302 supplies the power supply voltage to the controller 304, NAND memory 306, cache memory 308, and interface 310.

Note that the power interruption protection circuit 100 is not limited to use in data storage devices 300, but can also be used in applications where the power supply voltage must be maintained for a certain period of time after power is interrupted.

The embodiments are illustrative, and it will be understood by those skilled in the art that there are various variations in the combination of each component and each treatment process, and that such variations are also within the scope of this disclosure or the present invention.

2 System 10 Main power supply 20 Load 22 PMIC
24 Electronic component 100 Power interruption protection circuit 102 Backup capacitor 104 Input line 106 Back-up line 108 Output line 110 Switching power supply 112 Step-down converter 114 Step-up converter 200 PLP controller 210 Converter block 212 Feedback controller 220 Electronic fuse circuit 230 UVLO circuit 240 Control logic 250 Overcurrent detection circuit 260 Protection switch LX Switching pin FB Feedback pin VIN Input pin VBUS Output pin VB Inductor connection pin 300 Data storage device 302 PMIC
304 Controller 306 NAND memory 308 Cache memory 310 Interface

Claims (17)

an input line to receive an input voltage;
an output line to be connected to a load;
a capacitor connected to the output line;
A backup capacitor;
a switching power supply that is switchable between a step-up mode and a step-down mode, is connected to the output line and the backup capacitor, and in the step-up mode, steps up a bus voltage of the output line to charge the backup capacitor, and in the step-down mode, steps down the voltage of the backup capacitor and supplies it to the output line;
an electronic fuse circuit provided between the input line and the output line, the electronic fuse circuit being electrically switchable between an on state and an off state and having a current clamping function in the on state;
an undervoltage lockout circuit that asserts an undervoltage lockout signal when the bus voltage on the output line falls below a threshold;
control logic that, when the undervoltage lockout signal is asserted, turns off the electronic fuse circuit and switches the switching power supply to the step-down mode;
A power cutoff protection circuit comprising: an overcurrent detection circuit having a threshold lower than the limit current of the electronic fuse circuit and asserting an overcurrent detection signal when the current on the input line exceeds the threshold;
2. The power interruption protection circuit according to claim 1, wherein the assertion of the overcurrent detection signal is transmitted to the load. The power supply interruption protection circuit of claim 1 or 2, wherein the switching power supply includes a step-up/step-down bidirectional DC/DC converter that can reverse the direction of power transmission between the step-up mode and the step-down mode. The power interruption protection circuit of claim 3, further comprising a protection switch connected between the inductor of the step-up/step-down bidirectional DC/DC converter and the output line. The switching power supply
a boost converter active in the boost mode, the boost converter having an input node connected to the output line and an output node connected to the backup capacitor;
a step-down converter that is active in the step-up mode and the step-down mode, and has an input node connected to the output line and an output node connected to the backup capacitor;
3. The power supply interruption protection circuit according to claim 1, comprising: The power interruption protection circuit of claim 5, further comprising a protection switch connected between the inductor of each of the boost converter and the buck converter and the output line. A power interruption protection circuit according to any one of claims 1 to 6, wherein the load is an SSD (Solid State Drive). A data storage device equipped with a power interruption protection circuit according to any one of claims 1 to 7. an input pin for receiving an input voltage;
an output pin to be connected to a load and a capacitor ;
a capacitor connection pin to which a backup capacitor is to be connected;
at least one switching pin to be connected to the output pin via an external inductor;
a converter block that is switchable between a step-up mode and a step-down mode, that is connected to the at least one switching pin, the output pin, and the capacitor connection pin, that stabilizes the voltage of the backup capacitor at a first target level in the step-up mode, and that stabilizes the voltage of the output pin at a second target level in the step-down mode;
an electronic fuse circuit provided on a power supply line connecting the input pin and the output pin, the electronic fuse circuit being electrically switchable between an on state and an off state and having a current clamping function in the on state;
an undervoltage lockout circuit that asserts an undervoltage lockout signal when the voltage at the output pin falls below a threshold;
control logic that, when the undervoltage lockout signal is asserted, turns off the electronic fuse circuit and switches the converter block to the buck mode;
A power interruption protection controller comprising: an overcurrent detection circuit having a threshold lower than a limit current of the electronic fuse circuit and asserting an overcurrent detection signal when the current of the electronic fuse circuit exceeds the threshold;
10. The power interruption protection controller of claim 9, further comprising: transmitting assertion of the overcurrent detection signal to the load. The power interruption protection controller of claim 9 or 10, wherein the converter block includes a step-up/step-down bidirectional DC/DC converter whose power transmission direction is reversible between the step-up mode and the step-down mode. an inductor connection pin to be connected to one end of the inductor of the step-up/step-down bidirectional DC/DC converter;
a protection switch connected between the output pin and the inductor connection pin;
The power interruption protection controller of claim 11 further comprising: The converter block comprises:
a boost converter that is active in the boost mode and has the capacitor connection pin as its output;
a step-down converter that is active in the step-up mode and the step-down mode and has the capacitor connection pin as an input;
11. A power interruption protection controller according to claim 9 or 10, comprising: an inductor connection pin to be connected to one end of an inductor of each of the step-up converter and the step-down converter;
a protection switch connected between the output pin and the inductor connection pin;
The power interruption protection controller of claim 13 further comprising: A power interruption protection controller according to any one of claims 9 to 14, monolithically integrated on a single semiconductor substrate. A power interruption protection controller according to any one of claims 9 to 15, wherein the load is an SSD (Solid State Drive). A control method for a power cutoff protection circuit,
The power supply cutoff protection circuit includes:
an input line to receive an input voltage;
an output line to be connected to a load;
a capacitor connected to the output line;
A backup capacitor;
a switching power supply that is switchable between a step-up mode and a step-down mode, is connected to the output line and the backup capacitor, and in the step-up mode, steps up a bus voltage of the output line to charge the backup capacitor, and in the step-down mode, steps down the voltage of the backup capacitor and supplies it to the output line;
an electronic fuse circuit disposed between the input line and the output line;
Equipped with
The control method includes:
clamping a current flowing through the electronic fuse circuit;
asserting an undervoltage lockout signal when the bus voltage on the output line falls below a threshold;
when the undervoltage lockout signal is asserted, turning off the electronic fuse circuit and switching the switching power supply to the step-down mode;
A control method comprising: