JP7785399B2 - Semiconductor device, its use, and its manufacturing method - Google Patents

Description

The present invention relates to a semiconductor device, its uses (particularly, a power device having the semiconductor device), and its manufacturing method.

In the field of electronic devices that use semiconductors, such as semiconductor devices that use β-Ga ₂ O ₃ crystals as their material and power semiconductors (sometimes referred to as "power devices") that incorporate such semiconductor devices, active research and development is being conducted on semiconductor devices such as Schottky barrier diodes (SBDs) and metal oxide semiconductor transistors (MOSFETs). This research and development is also progressing with the study of structures such as trenches (concave) and fins (convex), which can theoretically improve the breakdown voltage of these devices, and many prototype results have been reported, as can be seen in Non-Patent Documents 1 and 2. Currently, these structures are formed by anisotropic dry etching (also commonly referred to as "reactive ion etching").
However, it has been pointed out that the following problems arise when dry etching (mainly anisotropic dry etching) is used to form trenches (concave) or fins (convex) in semiconductor devices using β-Ga ₂ O ₃ crystals or power devices having such semiconductor devices.

(1) When dry etching is used, the sidewall surfaces (also referred to simply as "side surfaces" in this application) of the trenches (concave) and fins (convex) that are formed are damaged during processing. Therefore, after dry etching, it is necessary to remove the damage by a wet process using an alkali or acid.
(2) The sidewall surface (side surface) formed by dry etching does not reflect the crystal facets, and therefore has a high density of dangling bonds, which leads to an increase in the density of crystal surface states and junction interface states, degrading device characteristics.
(3) Dry etching is difficult to fabricate narrow, deep trenches and perfectly vertical sidewalls, which are desirable for device applications. Such limited processing shapes place constraints on device design.

Meanwhile, in _the field _of semiconductor devices that use α- _Ga2O3 (α- _Ga2O3 ) _crystals , which are a different crystal polymorph from β- _Ga2O3 (β- _Ga2O3 ) _crystals , research is being conducted primarily with the aim of reducing dislocation density using selective growth techniques developed for silicon and III-V semiconductors and selective lateral overgrowth techniques that promote lateral growth. Furthermore, it is known that this selective growth technique can grow α- _Ga2O3 crystals that have a _three -dimensional structure surrounded by stable facets with low surface energy, as disclosed in Non-Patent Document 3.
However, in the field of semiconductor devices using β-Ga ₂ O ₃ crystals, the selective growth technique has only been reported in a few special applications, such as selective growth of highly doped layers to reduce the contact resistance of electrodes (Non-Patent Document 4).

F. Otsuka et al. , Appl. Phys. Express, 15, 016501 (2022) https://doi. org/10.35848/1882-0786/ac4080 W. Li et al. , IEEE International Electron Devices Meeting (IEDM), (2019) https://doi. org/10.1109/IEDM19573.2019.8993526 Y. Oshima et al. , APL Mater. , 7, 022503 (2019) https://doi. org/10.1063/1.5051058 A. Bhattacharyya et al. , Appl. Phys. Express, 14, 076502 (2021) https://doi. org/10.35848/1882-0786/ac07ef

The present invention aims to solve the above problems of semiconductor devices including β- _Ga2O3 crystals having the above-mentioned conventional trench or fin structure (specifically, semiconductor devices including β- _Ga2O3 crystals having trenches (concave) or fins (convex) formed by using the above-mentioned conventional dry etching), and to provide a semiconductor device using a semiconductor made of β- _{Ga2O3 crystals (} β- _Ga2O3 crystalline semiconductor) that suffers little processing damage, suppresses the generation of interface states on the crystal surface _or junction interface, thereby obtaining good device characteristics and is suitable for microfabrication, a power device including the semiconductor device (particularly a power device that makes use of the characteristics of the _β - _Ga2O3 crystalline _{semiconductor} ), and a method for manufacturing the semiconductor device.

The configuration of the present invention is shown below.
(Configuration 1)
It has a semiconductor layer made of β-Ga ₂ O ₃ crystal,
the semiconductor layer has a three-dimensional structure of linear protrusions or grooves on a first main surface;
The semiconductor device, wherein the side surface of the three-dimensional structure is a (100) facet.
(Configuration 2)
2. The semiconductor device according to claim 1, wherein the side surface is perpendicular to a substrate surface of the semiconductor device.
(Configuration 3)
a semiconductor layer having a three-dimensional structure consisting of linear protrusions or grooves formed on a substrate;
The semiconductor layer is made of β-Ga ₂ O ₃ crystal,
A semiconductor device, wherein the longitudinal direction of the linear protrusion or groove is parallel to the intersection line between the substrate surface and the (100) plane of the substrate.
(Configuration 4)
4. The semiconductor device according to claim 3, wherein the side surfaces of the linear protrusions or grooves are perpendicular to the surface of the substrate.
(Configuration 5)
5. The semiconductor device according to structure 3 or 4, wherein the substrate surface is a (010) plane and the longitudinal direction is a [001] direction.
(Configuration 6)
4. The semiconductor device according to configuration 3, wherein the substrate surface is a (001) plane and the longitudinal direction is a [010] direction.
(Configuration 7)
5. The semiconductor device according to structure 3 or 4, wherein the substrate surface is a (-102) plane and the longitudinal direction is a [010] direction.
(Configuration 8)
8. The semiconductor device according to any one of configurations 1 to 7, wherein at least a portion of at least one side surface of the linear protrusion or groove is a channel.
(Configuration 9)
9. The semiconductor device according to any one of configurations 1 to 8, comprising a Fin-type MOSFET structure in which a gate electrode is disposed so as to cover at least one side surface of the three-dimensional structure or the entire three-dimensional surface.
(Configuration 10)
the three-dimensional structure has a groove shape;
an anode electrode is formed so as to cover at least a portion of the three-dimensional structure via an insulating film disposed on at least a portion of a side surface and a bottom surface of the groove;
8. The semiconductor device according to any one of structures 1 to 7, wherein the anode electrode has a trench-type MOSSBD structure in which the anode electrode is in Schottky contact with the semiconductor layer in a part of the three-dimensional structure.
(Configuration 11)
A power device comprising the semiconductor device according to any one of configurations 1 to 10.
(Configuration 12)
Preparing a semiconductor substrate made of β-Ga ₂ O ₃ crystal;
forming a linear or stripe-shaped masking pattern having a longitudinal direction parallel to an intersection line between the substrate surface and a (100) plane of the semiconductor substrate;
and selectively growing β-Ga ₂ O ₃ crystals in the openings of the masking pattern where the β-Ga ₂ O ₃ crystals are exposed by a deposition method using a vapor phase.
(Configuration 13)
13. The method for manufacturing a semiconductor device according to claim 12, wherein the deposition method is a vapor deposition method.

According to the present invention, there is provided a semiconductor device having a trench (concave ₎ or fin (convex) structure using β- _Ga2O3 crystal as a semiconductor material, which has little processing damage, suppresses the generation of interface states on the crystal surface or junction interface, and is suitable for microfabrication, particularly a power device that makes use of the properties of β- _{Ga2O3 crystal} semiconductor, and a method for manufacturing the same.

1 is a cross-sectional view illustrating a fin structure (trench structure) using a β-Ga ₂ O ₃ crystal according to the present invention. 1 is a process diagram showing, in cross section, the manufacturing process of a fin structure using a β-Ga ₂ O ₃ crystal of the present invention, in which (a) to (f) indicate each manufacturing step in the manufacturing process. 1 is a process diagram showing, in cross section, a manufacturing process of a fin structure by a conventional manufacturing method, in which (a) to (e) show each manufacturing step in the manufacturing process. FIG. 1 is a flowchart showing the manufacturing process of a fin structure using the β-Ga ₂ O ₃ crystal of the present invention. 1A to 1E are cross-sectional views showing the manufacturing process of a trench MOSSBD according to the present invention, in which (a) to (e) show the respective manufacturing steps in the manufacturing process. 1A to 1D are cross-sectional views showing the manufacturing process of a trench MOSSBD according to the present invention, in which (a) to (d) show the respective manufacturing steps in the manufacturing process. 1A and 1B are explanatory diagrams of a lateral FinFET device structure, in which (a) is a bird's-eye view and (b) is a cross-sectional view. 1 is a cross-sectional view illustrating the element structure of a vertical FinFET. 1A and 1B are SEM photographs of a β-Ga ₂ O ₃ crystal film prepared by vapor phase growth. (a) in the figure is an SEM photograph when HCl is added, and (b) in the figure is an SEM photograph when HCl is not added. These are SEM photographs of fins made of β- _{Ga2O3 crystals} fabricated by vapor phase epitaxy. (a) in the figure is an SEM photograph when a substrate with a (001) plane as the substrate surface was used, and (b) in the figure is an SEM photograph when a substrate with a (010) plane as the substrate surface was used. These are SEM photographs of fins made of β- _{Ga2O3 crystals} fabricated by vapor phase epitaxy. (a) in the figure is an SEM photograph when a substrate with a (001) plane as the substrate surface was used, and (b) in the figure is an SEM photograph when a substrate with a (010) plane as the substrate surface was used. These are SEM photographs of the cross section of a fin made of β- _{Ga2O3 crystals} fabricated by vapor phase growth. (a) in the figure is an SEM photograph when a substrate with a (001) plane as the substrate surface was used, and (b) in the figure is an SEM photograph when a substrate with a (010) plane as the substrate surface was used. 1A and 1B are schematic cross-sectional views illustrating the shape of a fin made of β- _{Ga2O3 crystal} fabricated by vapor phase epitaxy, where (a) is a schematic cross-sectional view when a substrate having a (001) plane as its substrate surface is used, and (b) is a schematic cross-sectional view when a substrate having a (010) plane as its substrate surface is used. 1 is a diagram (apparatus configuration explanatory diagram) showing an outline of the configuration of a vapor phase growth apparatus (HVPE apparatus) described in a first embodiment. [0023]FIG. 1 is a SEM photograph of a fin made of β-Ga ₂ O ₃ crystal produced by vapor phase epitaxy using a substrate having a (−102) plane as the substrate surface. In the figure, (a), (b), and (c) are SEM photographs of fins made of β-Ga ₂ O ₃ crystals fabricated by vapor phase epitaxy using a substrate with a (−102) plane as the substrate surface. (a) in the figure is an SEM photograph of the cross section of a fin made of β-Ga ₂ O ₃ crystal fabricated by vapor phase epitaxy using a substrate with a (−102) plane as the substrate surface, and (b) in the figure is a schematic diagram of the cross-sectional shape traced based on the photograph.

(Embodiment 1)
In the first embodiment, a method for forming trenches (concave) and fins (convex) used in a power semiconductor (power device) having a semiconductor device using β-type Ga ₂ O ₃ (β-Ga ₂ O ₃ ) crystals by selective growth technology (particularly, "selective lateral overgrowth technology") will be described.
This method involves forming a mask with a linear opening on the surface of a substrate made of β- _Ga2O3 crystal, and forming a semiconductor layer made of β- _Ga2O3 crystal with a three-dimensional structure in which linear crystals surrounded by facets obtained by selective growth technology are regarded as fins, and the gaps between these crystals (i.e., _linear crystals ( _fins ) surrounded by facets obtained by selective growth technology) are regarded as trenches. Here, the orientation of the linear opening is set so that the (100) plane, which has the lowest surface energy and is the most stable, becomes the sidewall surface (side surface) of the trench or fin.
Incidentally, in this application, unless otherwise specified, a "fin" (sometimes referred to as a "fin (convex)") refers to a crystal having a linear shape surrounded by facets, has a convex shape (three-dimensional structure), and is also simply referred to as a "linear protrusion." In addition, in this application, a "trench" (sometimes referred to as a "trench (concave)") refers to a gap that appears between adjacent fins when there are two or more crystals (fins) having a linear shape surrounded by facets, and has a concave shape (three-dimensional structure), and is also simply referred to as a "groove."
In addition, in the present application, the term "linear protrusions or grooves" is as described below.
In the "semiconductor device" of the present invention, the three-dimensional structure of the semiconductor layer made of β-Ga ₂ O ₃ crystals has a structure formed by linear protrusions ("fins"). In this case, when focusing on the linear protrusions ("fins"), the semiconductor layer is composed of linear protrusions (fins), and is therefore considered to have a three-dimensional structure made of linear protrusions (i.e., a convex shape). However, since grooves appear in the gaps between adjacent linear protrusions ("fins") in the semiconductor layer, when focusing on the grooves (trenches), the semiconductor layer is considered to be composed of trenches. In this case, the semiconductor layer is considered to have a three-dimensional structure made of grooves (i.e., a concave shape). Therefore, the semiconductor layer having the three-dimensional structure made of linear protrusions (i.e., a convex shape) and the semiconductor layer having the three-dimensional structure made of grooves (i.e., a concave shape) are the same. In other words, in the "semiconductor device" of the present invention, as described above, there are two ways to view (evaluate) the three-dimensional structure of the semiconductor layer made of β-Ga ₂ O ₃ crystal: focusing on the linear protrusions ("fins") and focusing on the grooves (trenches). Therefore, in the "semiconductor device" of the present invention, the three-dimensional structure of the semiconductor layer made of β-Ga ₂ O ₃ crystal is simply defined as a "linear protrusion or groove." Therefore, in this application, "linear protrusion or groove" means a case where the three-dimensional structure of the semiconductor layer made of β-Ga ₂ O ₃ crystal is considered to consist only of linear protrusions by focusing on the linear protrusions ("fins"), or a case where the gaps between adjacent linear protrusions are considered to be grooves by focusing on the grooves and considered to consist only of the grooves.
In the present application, the surface having a semiconductor layer made of β-Ga ₂ O ₃ crystals is also referred to as the “first main surface.” This surface may be, for example, the surface of a substrate or the surface of a layer formed on a substrate, as long as it has a semiconductor layer made of β-Ga ₂ O ₃ crystals.
In addition, in this application, the term "semiconductor device" refers to a device defined as a semiconductor device in the configuration of the present invention described above. Specifically, it refers to a semiconductor device (semiconductor element) made of a semiconductor material, and commonly known examples include semiconductor devices (semiconductor elements) such as semiconductor diodes, transistors, ICs, and LSIs.
In addition, in this application, the term "power device" (also referred to as "power semiconductor") refers to a device defined as a power device in the configuration of the present invention described above. Specific examples include semiconductor elements used in power converters such as inverters and converters. Compared to semiconductor devices (semiconductor elements) such as ICs and LSIs, a power device is characterized by the large current that flows within the semiconductor circuit.
The sidewall surfaces (side faces) of trenches (concave) and fins (convex) fabricated by crystal growth using this method are formed on the most stable (100) facet, resulting in few dangling bonds and a low surface state density. Therefore, devices utilizing these (i.e., the sidewall surfaces of the trenches and fins formed on the most stable (100) facet, with few dangling bonds and a low surface state density) can achieve excellent characteristics. Furthermore, by using narrow, deep trenches (concave) and a substrate surface with an appropriately controlled off-angle, it is easy to fabricate perfectly vertical sidewall surfaces (side faces), enabling ideal device design.

As shown in FIG. 1, the semiconductor device 101 of the first embodiment includes a semiconductor layer 14 made of β-Ga ₂ O ₃ crystals formed on an exposed surface of a substrate 11 made of β-Ga ₂ O ₃ crystals at an opening 13 in a mask 12. That is, the semiconductor layer 14 has a three-dimensional structure of linear protrusions or grooves on a first main surface, and the side surfaces of the three-dimensional structures form (100) facets. Here, the first main surface, according to FIG. 1, refers to the surface of the substrate 11 that is used to form the semiconductor layer 14. The grooves, according to FIG. 1, refer to concave three-dimensional structures formed as gaps in fins 14 made of β-Ga ₂ O ₃ crystals. The linear protrusions, according to FIG. 1, refer to convex three-dimensional structures (i.e., fins 14) made of β-Ga ₂ O ₃ crystals. According to FIG. 1, the sidewall surfaces (side surfaces) of the grooves are also the sidewall surfaces (side surfaces) of the linear protrusions.
Alternatively, the semiconductor device 101 of the first embodiment includes a semiconductor layer 14 having a three-dimensional structure consisting of linear protrusions or grooves formed on a substrate 11 made of β-Ga ₂ O ₃ crystal, the semiconductor layer 14 being made of β-Ga ₂ O ₃ crystal, and the longitudinal direction of the linear protrusions or grooves being parallel to the intersection of the substrate surface and the (100) plane of the substrate.
Here, it is preferable that the substrate surface of the substrate 11 is a (010) plane and the longitudinal direction is the [001] direction, or that the substrate surface of the substrate 11 is a (001) plane and the longitudinal direction is the [010] direction.

In this way, the (100) plane, which has the lowest surface energy and is stable, becomes the side of the three-dimensional structure, i.e., the side of the fin or trench. The side of the semiconductor layer 14 made of β-Ga ₂ O ₃ crystal having a three-dimensional structure like a fin or trench formed with the most stable (100) facet plane has few dangling bonds and a low surface state density. Therefore, the semiconductor device of the first embodiment, which utilizes this sidewall surface (side), has excellent electrical characteristics, such as excellent leakage current, mobility, reliability, and breakdown voltage.
In particular, when at least one sidewall surface (side surface) of the linear protrusion or groove serves as a channel of the semiconductor device, the channel has few dangling bonds and a low surface state density, and therefore the semiconductor device has excellent leakage current, mobility, and reliability.

The sidewall surfaces (side faces) of the three-dimensional structures of the semiconductor layer 14 , that is, the sidewall surfaces (side faces) of the linear protrusions or grooves of the semiconductor layer 14 are preferably perpendicular to the substrate surface of the substrate 11 .
If the sidewall surfaces (side surfaces) are vertical, the interlayer film covering the semiconductor layer 14, the insulating film such as the gate insulating film, the gate electrode, etc. can be formed symmetrically with respect to the semiconductor layer 14, and defects such as voids are less likely to occur in the film covering the semiconductor layer 14. If the sidewall surfaces (side surfaces) are vertical, the sidewall surfaces (side surfaces) are highly useful when used as a channel, etc.

Here, when a substrate having a (010) plane as the substrate surface is used as the substrate 11 and the longitudinal direction of the mask opening 13 is set to the [001] direction, the crystal grows with minimal energy, and the semiconductor layer 14 that is automatically formed becomes a three-dimensional structure (such as a fin (linear protrusion) or a trench (groove)) made of β-Ga ₂ O ₃ crystal with vertical sidewall surfaces (side surfaces).

On the other hand, when a substrate having a (001) plane as the substrate surface is used as the substrate 11, the longitudinal direction of the mask opening 13 in which a three-dimensional structure having a stable shape is formed is the [010] direction, and the three-dimensional structure is formed in a direction tilted by 13.7° from the vertical.
In view of this, when a substrate having a (001) plane as its substrate surface is used as the substrate 11, it is preferable to provide an off-angle of 13.7° in the substrate 11. By using the substrate 11 made of β-Ga ₂ O ₃ crystal, having a (001) plane as its substrate surface and provided with an off-angle of 13.7°, it becomes possible to provide a three-dimensional structure and a semiconductor device having a semiconductor layer 14 made of β-Ga ₂ O ₃ crystal with vertical sidewall surfaces (side surfaces).

Next, a manufacturing method of the semiconductor device (fin structure) 101 will be described with reference to Figures 2 and 4. Note that the semiconductor device will be described as the fin structure 101, focusing on the fin (linear protrusion) portion, which is a convex pattern. If the focus is on the trench (groove) portion, which is a concave pattern, the semiconductor device can also be considered as a trench structure 101.
In the first step, a substrate (semiconductor substrate) 11 made of β-Ga ₂ O ₃ crystal with a (010) or (001) crystal plane is prepared (step S11 in FIG. 4, FIG. 2(a)). When using a substrate with a (001) plane as the substrate plane, it is preferable to set an off-angle of 13.7° as described above.
In the second step, a linear or stripe-shaped (i.e., parallel line-shaped) masking pattern 12 is formed with its longitudinal direction parallel to the intersection line between the substrate surface and the (100) plane (step S12).
Specifically, a thin film 12a made of _SiO2 or the like is formed on a substrate 11 (FIG. 2(b)), and a resist pattern 15 with linear or stripe-shaped openings is formed on the thin film 12a (FIG. 2(c)). Then, using the resist pattern 15 as a mask, wet or dry etching is performed to form openings 13 in the thin film 12a (FIG. 2(d)). Subsequently, the resist pattern 15 is stripped using oxygen plasma ashing, ozone ashing, or a resist stripper to form a mask 12 with linear or stripe-shaped openings 13 (FIG. 2(e)). The thickness of the mask 12 is preferably 1 nm or more but not more than 1000 nm. A thickness of 1 nm or more is preferable from the viewpoint of effectively preventing the generation of foreign matter derived from _Ga2O3 crystals on the mask due to film defects _, etc. The mask 12 is a dummy object not essential to the semiconductor device being manufactured, and its thickness is preferably 1000 nm or less from the viewpoint of suppressing the generation of cracks in the mask.

In the third step, a β-Ga ₂ O ₃ crystal (fin) 14 is selectively grown in the opening 13 of the masking pattern 12 using a vapor phase epitaxy method to manufacture a fin structure (semiconductor device) 101 using the β-Ga ₂ O ₃ crystal (step S13, FIG. 2(f)).
The openings in the mask 12 can be easily microfabricated by using a thin film 12a made of an easily processable material such as SiO _2. Therefore, this method makes it possible to easily manufacture a fin structure 101 using fine β-Ga ₂ O ₃ crystals.

One of the deposition methods using the vapor phase used in this invention is chemical vapor deposition (CVD), which includes halide vapor phase epitaxy (HVPE), low-pressure chemical vapor deposition (LPE), metal organic vapor phase epitaxy (MCVD), and mist chemical vapor deposition (MCVD).

The vapor phase growth method used in the present invention and its features will be explained below, taking HVPE as an example.
The vapor phase growth method of the present invention is characterized in that β-Ga ₂ O ₃ crystals are selectively grown on the exposed surface of the substrate made of β-Ga ₂ O ₃ crystals as nuclei, and β-Ga ₂ O ₃ crystals are not grown on the mask surface such as SiO ₂ .
For this reason, the vapor phase growth method of the present invention is preferably characterized by adding a reactive gas having the property of etching Ga ₂ O ₃ to a gas consisting of a gallium source gas and an oxygen source gas (i.e., a gas for growing β-Ga ₂ O ₃ crystal).

As an example of an apparatus used in the vapor phase growth method, a schematic configuration of a vapor phase growth apparatus (HVPE apparatus) 2001 is shown in FIG.
The vapor phase growth apparatus 2001 has a reactor 1001 that can be heated to a desired temperature by a heater 1012 .
The reactor 1001 is equipped with a gallium precursor supply source 1002 , an oxygen precursor supply pipe 1006 , an etching gas supply pipe 1008 , and a substrate holder 1010 , and the gas supplied to the reactor 1001 is exhausted through an exhaust pipe 1011 .
Gallium source supply source 1002 contains gallium metal 1003. Gallium compound gas 1004 supplied to gallium source supply source 1002 reacts with gallium metal to produce gallium source gas, which is then supplied to a sample placed on substrate holder 1010 through gallium source gas supply pipe 1005.
An oxygen source supply pipe 1006 supplies a controlled amount of oxygen source gas 1007 to a sample placed on a substrate holder 1010 .
An etching gas supply pipe 1008 controls and supplies a predetermined amount of etching gas (reducing gas) 1009 to a sample placed on a substrate holder 1010 .

Here, the gallium compound gas 1004 may be a halogen gas or a hydrogen halide gas, for example, _Cl2 and HCl, and the oxygen source gas 1007 may be one or more gases selected from the group consisting of _O2 , _H2O and _N2O , with _O2 being particularly preferred.
The etching gas 1009 may be a reducing gas such as HCl, HF, HBr, _H2 , or _Cl2 . Among reducing gases, HCl is particularly preferred because it has low reactivity with quartz and is easy to handle.
Gallium halide and oxygen source react easily to produce gallium oxide. The Ga halide preferably contains GaCl and/or GaCl _3. These halides (i.e., GaCl and/or GaCl ₃ ) have excellent reactivity and promote the growth of gallium oxide.
These gases (i.e., the gallium compound gas 1004 and the etching gas 1009) may be supplied together with a carrier gas that is an inert gas, such as nitrogen (N ₂ ) gas, helium (He) gas, neon (Ne) gas, argon (Ar) gas, and krypton (Kr) gas.

If a tetravalent dopant is to be introduced into the β-Ga ₂ O ₃ crystal of the fin portion, a source material containing an element having a tetravalent valence may be supplied. If the source material containing an element having a tetravalent valence is a gas, it may be mixed and flowed from the gallium source supply source 1002, or a separate source material may be provided. If the source material containing an element having a tetravalent valence is a solid or liquid, it may be placed on the gallium source supply source 1002, like gallium metal 1003.

A gallium compound gas 1004, an oxygen source gas 1007, and an etching gas 1009 are supplied to a sample placed on a substrate holder 1010 in a temperature environment of 700°C or higher and 1300°C or lower, preferably 800°C or higher and 1200°C or lower, and more preferably 950°C or higher and 1100°C or lower, to grow a β-Ga ₂ O ₃ crystal.

By the above-mentioned HVPE method, the β-Ga ₂ O ₃ crystal formed on the substrate having the (010) plane as the substrate surface or the substrate having the (001) plane as the substrate surface made of β-Ga ₂ O ₃ crystal grows only on the surface (13) where the β-Ga ₂ O ₃ crystal is exposed, and does not grow on the mask 12, resulting in selective growth.
Furthermore, the side surfaces of the β-Ga ₂ O ₃ crystal formed by this growth reflect the facets of the crystal, and have a low density of dangling bonds, resulting in a low density of crystal defects and interface states on the crystal surface.

For reference, a method for manufacturing a β-Ga ₂ O ₃ fin structure 301 by a conventional method using dry etching will be described with reference to FIG.
First, a substrate (semiconductor substrate) 11 made of β-Ga ₂ O ₃ crystal is prepared (FIG. 3(a)).
Next, a β-Ga ₂ O ₃ crystal film (31a) is epitaxially grown on the substrate 11 (FIG. 3(b)).
Thereafter, a resist pattern 32 is formed on the β-Ga ₂ O ₃ crystal film (31 a) (FIG. 3(c)), and the β-Ga ₂ O ₃ crystal film (31 a) is etched by dry etching to form β-Ga ₂ O ₃ crystals 31 with fins (linear protrusions) (or, if you look at it from a different perspective, trenches, which are concave patterns) (FIG. 3(d)).
Finally, the resist pattern 32 is peeled off, and the β-Ga ₂ O ₃ crystal fin structure 301 is manufactured as a semiconductor device (FIG. 3(e)). The semiconductor device (fin structure 301) can also be regarded as the trench structure 101 when focusing on the trench (groove) portion, which is a concave pattern.

As already mentioned, the conventional method of manufacturing the β-Ga ₂ O ₃ crystal fin structure 301 using dry etching has the following problems.
(1) The sidewall surfaces (side faces) of the trenches and fins that are formed are damaged during processing. Therefore, after dry etching, it is necessary to remove the damage using a wet process using alkali or acid. However, even with wet etching, the damage may not be completely repaired.
(2) The sidewall surface (side surface) formed by dry etching does not reflect the crystal facets, and therefore has a high density of dangling bonds, which leads to an increase in the density of states on the crystal surface and at the junction interface, degrading device characteristics.
(3) Dry etching is difficult to fabricate narrow, deep trenches and perfectly vertical sidewalls, which are desirable for device applications. Such limited processing shapes place constraints on device design.

(Embodiment 2)
In the second embodiment, a trench metal oxide semiconductor Schottky barrier diode (MOSSBD) 201, which is one of the semiconductor devices suitable for use as a power device, will be described, along with its manufacturing method.

A method for manufacturing the Trench MOSSBD (201) will be described with reference to FIGS.
First, a sample (FIG. 5(a ₎ ) is prepared according to embodiment 1, which includes a substrate 51 made of β- _{Ga2O3 crystal} , an _SiO2 mask 52, and a β- _Ga2O3 crystal pattern (β- _{Ga2O3 crystal} semiconductor layer) 53 grown in the opening of the mask. The substrate 51 made of β- _Ga2O3 crystal is preferably doped with Si, Sn _, or the like at a concentration of ¹⁰¹⁷ cm ^-3 or more and ¹⁰¹⁹ cm ^-3 or less.
In the first embodiment, as explained above using Figures 2 and 4, the β-Ga ₂ O ₃ crystal patterns 53 are expressed as convex patterns, i.e., fins (linear protrusions), whereas in the second embodiment, the β-Ga ₂ O ₃ crystal patterns 53 are expressed as concave patterns, i.e., trenches, focusing on the grooves formed between the β-Ga 2 O 3 crystal patterns 53.

Next, as shown in FIG. 5B, an insulating film 54a is conformally formed. The insulating film 54a is preferably one having few levels and defects and excellent withstand voltage, and examples thereof include one or more selected from the group consisting of HfO ₂ , Al ₂ O ₃ , SiO ₂ , Ta ₂ O ₅ , HfSiO ₂ , Si ₃ N ₄ , and SiON. A single-layer film or a multilayer film selected from these films may be used. The film formation method is not particularly limited, and examples thereof include CVD, sputtering, and ALD (Atomic Layer Deposition). The thickness of the insulating film 54a is not particularly limited, but may be 10 nm or more and 100 nm or less.

5(c), the upper surface portion of the insulating film 54a is removed so as to expose at least the upper surface portion 55 of the β-Ga ₂ O ₃ crystal pattern 53 (i.e., the β-Ga ₂ O ₃ crystal exposed portion 55 appears), resulting in the first insulating film 54. Examples of this processing method include CMP (Chemical Mechanical Polishing), etch-back, and a combination thereof.

Thereafter, an insulating film 56a is deposited (FIG. 5(d)), followed by forming a resist pattern 57 having openings exposing desired regions where trenches are to be formed (FIG. 5(e)). Examples of the insulating film 56a include _SiO2 , SiON, SOG (Spin on Glass), and polyimide. Examples of methods for forming the insulating film include CVD, sputtering, and coating.
Thereafter, the insulating film 56a is etched (FIG. 6(a)), and then the resist pattern 57 is removed by oxygen gas ashing, ozone treatment, and a stripping solution, etc., to form a second insulating film 56 (e.g., _SiO2 ) on at least a part of the field portion other than the trench region (FIG. 6(b)).

Next, after thoroughly cleaning the upper surface portion 55 of the β-Ga ₂ O ₃ crystal pattern 53 where the β-Ga ₂ O ₃ crystals are exposed (i.e., the exposed β-Ga ₂ O ₃ crystal portion) and the exposed surface of the first insulating film 54, a conductive film 58a that will serve as an anode is formed on the surface (upper surface) on the β-Ga ₂ O ₃ crystal pattern 53 side, and a conductive film 59 that will serve as a cathode is formed on the back surface (Figure 6(c)).
Examples of the conductive film 58a include Pt, Au, Ni, Ag, Ru, Rh, Pd, W, Mo, Ta, and Cu. Examples of the method for forming the conductive film 58a include vapor deposition, sputtering, and MOCVD.
Examples of the conductive film 59 include at least one selected from the group consisting of Ti, Al, Au, Pt, and ITO, and alloys containing at least one selected from these groups. Examples of methods for forming the conductive film 59 include vapor deposition, sputtering, and MOCVD. It is preferable that the conductive film 59 be in ohmic contact with the substrate 51 made of β-Ga ₂ O ₃ crystal. Taking this into consideration, it is also preferable to control the doping of the substrate 51 made of β-Ga ₂ O ₃ crystal and form the conductive film 59 as a laminated film.

Finally, the conductive film 58a is processed by lithography and etching to produce a trench MOSSBD (201) having the desired anode electrode 58 and cathode electrode (conductive film) 59. The anode electrode 58 may be formed by a lift-off method instead of the formation method using film deposition, lithography, and etching.
The anode electrode 58 has a _structure in which it is Schottky-connected to the upper surface portion (β- _{Ga2O3 crystal} exposed portion) 55 of the β- _Ga2O3 crystal pattern (β- _{Ga2O3 crystal} semiconductor layer) 53 where the β- _{Ga2O3 crystal} is exposed, and therefore the upper surface portion (β- _{Ga2O3 crystal} exposed portion) 55 can also be said to be a Schottky-connected portion.
As shown in FIG. 6( d ), in the Trench MOSSBD (201), when focusing on the grooves formed between the β-Ga ₂ O ₃ crystal patterns 53, the three-dimensional structure of the semiconductor layer made of β-Ga ₂ O ₃ crystals has a trench (groove) shape, and an anode electrode 58 is formed so as to cover the trench (groove) of the three-dimensional structure (here, it is sufficient that the anode electrode 58 covers at least a part of the trench (groove)) via an insulating film 54 arranged on the sidewall surface (side surface) of the trench (groove) and the bottom surface of the trench (here, it is sufficient that the insulating film 54 is arranged on at least a part of the sidewall surface (side surface) of the trench (groove)). Also, the anode electrode 58 has a structure in which it is in Schottky contact with the semiconductor layer made of β-Ga ₂ O ₃ crystal in a part of the three-dimensional structure (i.e., the trench (groove)).

In the manufactured Trench MOSSBD (201), the semiconductor layer (i.e., the β- _{Ga2O3 crystal} semiconductor layer) 53 made of β- _Ga2O3 crystals is in Schottky contact with the anode electrode 58, and the sidewall surfaces (side surfaces) of the β _{- Ga2O3} crystal semiconductor layer 53 in the grooves reflect the crystal facets _, resulting in a low density of dangling bonds, resulting in a semiconductor device with low crystal defects and low interface state density on the crystal surface. The combination of this high-quality β- _{Ga2O3 crystal} semiconductor layer 53 and the Trench MOSSBD structure that can bring out such high breakdown voltage characteristics allows the manufactured Trench MOSSBD (201) to be a high-voltage diode, which is a semiconductor device with excellent leakage current characteristics that is particularly suitable for power device applications.

(Embodiment 3)
In the third embodiment, as shown in Fig. 7, the fin structure 101 using the β-Ga ₂ O ₃ crystal of the first embodiment is applied to a (lateral) FinFET (202). The third embodiment will be described below with reference to Fig. 7. In this application, the structure of the (lateral) FinFET (202) is referred to as a "Fin-type MOSFET structure."

As shown in (a) and (b) of Figure 7, the lateral FinFET (202) is composed of an insulating substrate 61 made of β- _{Ga2O3 crystal} , a fin 62 made of a β- _{Ga2O3 crystal} semiconductor, a mask 63 made of thin _SiO2 or the like, an insulating film 64 made of _SiO2 or the like, a gate insulating film 65, and a gate electrode 66. A source 67 is connected to one end of the fin 62, and a drain 68 is connected to the other end, sandwiching the gate electrode 66. In this structure, in addition to the top surface of the fin 62, at least a portion of its side surface serves as a channel, resulting in good FET electrical characteristics. Here, if the substrate 61 is insulating as described above, the insulating film 64 can be omitted.

In the lateral FinFET (202), a fin structure having fins 62 formed in openings in a mask 63 formed on a substrate 61 by the method described in embodiment 1 is prepared, then an insulating film 64 is formed by CVD, sputtering, or the like, and a gate insulating film 65 is formed thereon. A gate electrode 66 is then formed so as to cover at least a portion of one sidewall surface (first side surface), the top surface, and the other sidewall surface (second side surface) facing the first side surface of the fin 62, i.e., the top surface and both sidewall surfaces (both side surfaces) of the fin three-dimensional structure. Then, a source 67 is connected to one end of the fin 62 and a drain 68 is connected to the other end of the fin 62, sandwiching the gate electrode 66 therebetween.
Here, as the gate insulating film 65, it is preferable to use a so-called high-k film such as HfO ₂ , HfSiO ₂ , Al ₂ O ₃ and Si ₃ N ₄ in addition to SiO ₂ .
As shown in FIG. 7, the FinFET (202) has a structure in which the gate electrode 66 is arranged (formed) so as to cover at least one sidewall surface (side surface) of the three _- dimensional structure (specifically, the fin 62) of the semiconductor layer made of β-Ga 2 O ₃ crystal, or the top surface and side surface of the three-dimensional structure (i.e., the entire surface of the three-dimensional structure).

The lateral FinFET (202) is a semiconductor device with low crystal defects and low interface state density on the crystal surface because the sidewall surfaces (side surfaces) of the fins 62, which form the channel and are made of β-Ga ₂ O ₃ crystalline semiconductor, reflect the crystal facets and have a low density of dangling bonds. The FinFET (202) is a FET (Field Effect Transistor) with excellent current characteristics, due to the combination of the fins 62 made of such high-quality β-Ga ₂ O ₃ crystalline semiconductor and a FinFET structure that can extract excellent electrical characteristics. In other words, the lateral FinFET (202) is a power device.

(Embodiment 4)
In the fourth embodiment, as shown in Fig. 8, the fin structure 101 made of the β-Ga ₂ O ₃ crystal of the first embodiment is applied to a (vertical) FinFET (203). The fourth embodiment will be described below with reference to Fig. 8. In this application, the structure of the FinFET (203) is referred to as a "Fin-type MOSFET structure" in the same manner as the structure of the (lateral) FinFET (202).

The vertical FinFET (203) includes a substrate 71 made of β-Ga ₂ O ₃ crystal, an epitaxial β-Ga ₂ O ₃ crystal formation layer 72, a fin 73 made of β-Ga ₂ O ₃ crystal, a mask 74 made of SiO ₂ or the like that serves as a template when forming the fin 73, an insulating film 75 that functions as a gate insulating film, a gate electrode 76, an insulating layer 77 that serves to electrically isolate the gate electrode from the source electrode, etc., an n ⁺ layer 78 that provides ohmic contact between the fin 73 and the source electrode 79 and has the function of reducing the contact resistance, and a drain electrode 80.
As shown in FIG. 8, the FinFET (203) has a structure in which the gate electrode 76 is arranged (formed) so as to cover at least one sidewall surface (side surface) of the three _- dimensional structure (specifically, the _fin 73) of the semiconductor layer made of β-Ga 2 O 3 crystal.

In terms of electrical resistance, it is preferable to use a substrate 71 doped with Si, Sn, or the like at a concentration of ¹⁰ cm ⁻³ or more and ¹⁰ cm ⁻³ or less. The epitaxial β-Ga ₂ O ₃ crystal formation layer 72 is a β-Ga ₂ O ₃ crystal formed by a HVPE method or the like and having a dopant concentration of ¹⁰ cm ⁻³ or more and ¹⁰ cm ⁻³ or less, and its thickness is preferably 1 μm or more and 50 μm or less.
The fin 73 is formed on the epitaxial β-Ga ₂ O ₃ crystal formation layer 72 using a mask 74 in the same manner as in the first embodiment. Here, the doping amount of the fin 73 is preferably set to 10 ¹⁵ cm ⁻³ or more and 10 ¹⁷ cm ⁻³ or less. The surface layer of the sidewall surface (side surface) of the fin 73 functions as a channel layer.
As the insulating film (gate insulating film) 75, it is preferable to use a so-called high-k film such as HfO ₂ , HfSiO ₂ , Al ₂ O ₃ or Si ₃ N ₄ in addition to SiO _2. The thickness thereof is preferably 10 nm or more and 100 nm or less.

Pt, Cr, Au, Ni, Ag, Ru, Rh, Pd, W, Mo, Ta, PolySi (polysilicon), and Cu are preferably used for the gate electrode 76, and at least one selected from the group consisting of Ti, Al, Au, Pt, and ITO (indium tin oxide), or an alloy containing at least one selected from these groups, are preferably used for the source electrode 79 and the drain electrode 80. Considering adhesion, which is important in microfabrication, for example, the source electrode 79 is preferably a laminated film in which Ti, Al, and Pt are laminated in this order from the bottom up, and the drain electrode 80 is preferably a two-layered film in which Ti and Au are laminated in this order from the bottom up.
The insulating layer 77 may be made of, for example, SiO ₂ , SiON, SOG (Spin on Glass), or polyimide.
The n ⁺ layer 78 can be formed by ion implantation. The dopant can be Si or Sn, and the dopant amount can be in the range of 10 ¹⁸ cm ⁻³ to 10 ²⁰ cm ⁻³ . The thickness can be 50 nm to 500 nm. From the viewpoint of ease of fabrication, the n ⁺ layer 78 may be omitted depending on the doping amount of the fin 73.

The vertical FinFET (203) is manufactured by preparing a fin structure having fins 73 formed in openings of a mask 74 formed on an epitaxial β- _Ga2O3 crystal formation layer ₇₂ by the method described in the first embodiment, forming an insulating film (gate insulating film) 75 by a CVD method, a sputtering method, or the like, forming a gate electrode 76 in an area including at least a part of the sidewall surface (side surface) of the fin 73 by a vapor deposition method, a sputtering method, a CVD method, a MOCVD method, or the like, forming an insulator layer 77 by a sputtering method, a CVD method, or a coating method, and forming a source electrode 79 and a drain electrode 80 thereon.

The vertical FinFET (203) is a semiconductor device with low crystal defects and low interface state density on the crystal surface because the sidewall surfaces (side surfaces) of the fins 73, which form the channel layer and are made of a β- _{Ga2O3 crystalline} semiconductor, reflect the crystal facets and have a low density of dangling bonds. The FinFET (203) is an FET with excellent current characteristics, due to the combination of the fins 73 made of such high-quality β- _{Ga2O3 crystalline} semiconductor and the vertical FinFET structure, which can bring out excellent electrical characteristics.
Furthermore, it is desirable for the channel layer in the vertical FinFET (203) to have as large an area as possible, since current can be generated more efficiently. In the structure of the vertical FinFET (203), the surface area of the channel layer can be increased by forming a large number of fins 73 per unit area through microfabrication. According to the present invention, it is possible to form fins 73 with high packing density, fineness, and a high aspect ratio. Therefore, the vertical FinFET (203) according to the fourth embodiment has excellent electrical characteristics, making it particularly suitable for use in power devices. In other words, the vertical FinFET (203) serves as a power device.

Example 1
In Example 1, samples were prepared and evaluated using substrates made of β-Ga ₂ O ₃ crystals with the (001) and (010) planes as the substrate surfaces. The results are described below together with the sample preparation method.

<Sample preparation>
As shown in FIG. 2(a), a substrate 11 made of β-Ga ₂ O ₃ crystal was prepared, and a thin film 12a made of amorphous SiO ₂ was formed on the substrate 11 (FIG. 2(b)).
Here, the substrate 11 made of β-Ga ₂ O ₃ crystal was a commercially available substrate from Novel Crystal Technology with the (001) and (010) planes as the substrate surface.
The amorphous SiO ₂ thin film 12a was formed by plasma enhanced chemical vapor deposition using tetraethoxysilane (TEOS) as a precursor, and had a thickness of 100 nm.

Thereafter, a resist pattern 15 having a groove-shaped opening pattern was formed (FIG. 2(c)). After that, wet etching was performed using a hydrofluoric acid buffer solution (FIG. 2(d)). Subsequently, the resist pattern 15 was stripped to form a mask 12 made of SiO ₂ (12) having groove-shaped openings 13 (FIG. 2(e)). Here, the resist was stripped using acetone and oxygen plasma ashing, and the exposed portion of the substrate made of β-Ga ₂ O ₃ crystal (exposed portion of the β-Ga ₂ O ₃ crystal substrate) 13a was degreased.
The opening 13 in the mask 12 was formed so as to be parallel to the [010] direction in the substrate 11 whose substrate surface was the (001) plane, and parallel to the [001] direction in the substrate 11 whose substrate surface was the (010) plane. The opening 13 was 1.2 μm wide and 100 μm long.

2(f), selective growth of β-Ga ₂ O ₃ crystal was performed by halide vapor phase epitaxy to form a semiconductor layer 14 made of β-Ga ₂ O ₃ crystal in the mask opening 13. The details are given below.
_The halide vapor phase epitaxy was performed using a custom-built device. The gases used for growing the β- _Ga2O3 crystal were _O2 (purity >99.99999%) (oxygen source gas) and GaCl precursor (gallium compound gas), which were supplied separately to the substrate in the production reaction zone of a quartz reactor heated to 1040°C at partial pressures of 1.25 and 0.125 kPa, respectively. The GaCl precursor was synthesized upstream of the quartz reactor by chemically reacting Ga metal (purity >99.99999%) with HCl gas (purity >99.999%) (gallium compound gas) at 820°C.
In addition, HCl gas was supplied directly to the reaction zone as an etching gas at a partial pressure of 0.25 kPa. HCl gas has the property of etching _{Ga2O3 crystals} . The introduction of this gas was intended to avoid parasitic gas-phase reactions and more effectively prevent the formation of _{Ga2O3 crystal} nuclei on the mask 12.
Purified _N gas (dew point <-110°C) was used as the carrier gas. The flow rate was 7870 sccm. The film formation time (growth time) was 15 minutes, and film formation was performed under the same conditions on both the (001) and (010) surfaces of the substrate 11.
As a comparative example, film formation was also performed under conditions where HCl gas, which is an etching gas for preventing nucleation on the mask 12, was not supplied.
Through the above steps, a concave-convex structure was formed on the linear mask opening, with the (100) facet plane serving as the sidewall surface (side surface).

<Evaluation>
First, it was confirmed that the introduction of HCl gas could prevent the formation of β-Ga ₂ O ₃ crystals on the mask 12 .
Figure 9 shows an example of a comparison of the results of SEM observation from above when HCl gas was introduced (Figure 9(a)) and when it was not introduced (Figure 9(b)). The SEM used here was an SU8230 (manufactured by Hitachi High-Technologies).
When HCl gas is introduced, it can be seen from FIG. 9(a) that a linear pattern of β-Ga ₂ O ₃ crystals is formed in the location corresponding to the mask opening 13, while the area where the mask 12 is formed remains bare (as it is, with nothing formed).
On the other hand, when HCl gas was not introduced, deposits derived from Ga ₂ O ₃ crystals were also formed on the mask 12, as shown in FIG. 9(b).
From the above, it was confirmed that β-Ga ₂ O ₃ crystals can be selectively grown in the mask openings 13 by introducing HCl gas.

Deposits were confirmed on the mask 12 at a distance of 100 μm or more from the mask opening 13. To prevent such deposits from becoming a problem in manufacturing a semiconductor device, it is preferable to form a resist pattern having an opening in a field portion at a distance of 100 μm or more from the mask opening 13 after forming the β-Ga ₂ O ₃ crystal, and then remove the unnecessary Ga ₂ O ₃ crystal deposits by wet etching or the like, or to form a dummy β-Ga ₂ O ₃ crystal pattern by forming a dummy opening in advance in the field portion at a distance of 100 μm or more from the mask opening 13. Alternatively, it is also effective to promote the desorption reaction by increasing the amount of HCl gas introduced or by reducing the supply amount of growth precursor (e.g., the supply amount of GaCl precursor).

Next, the in-plane orientation dependency of the β-Ga ₂ O ₃ crystal pattern formed on the substrate crystal plane was investigated using a sample with radial mask openings 13. The results (SEM images) are shown in Figure 10. Here, (a) in the figure shows the case where a substrate with a (001) plane as the substrate surface was used, and (b) shows the case where a substrate with a (010) plane as the substrate surface was used.
When the line direction deviated slightly from the [010] or [001] direction, step-like sidewall surfaces (side faces) parallel to the [010] and [001] directions were observed.
When a substrate having a (001) plane as its substrate surface is used and the line direction deviates significantly from the [010] direction, randomly oriented polycrystalline grains appear. When a substrate having a (010) plane as its substrate surface is used and the line direction deviates significantly from the [001] direction, the density of the microsteps increases and the area of the (100) facet plane is maximized, resulting in a zigzag sidewall surface (side surface).
From the above, it _was confirmed that in order to obtain a β- _Ga2O3 crystal pattern with a smooth (100) facet sidewall surface (side surface), the direction of the linear mask opening (i.e., corresponding to the longitudinal direction of the groove (trench) or linear protrusion (fin) formed on the substrate) must be parallel to the intersection of the (100) plane and the substrate surface (i.e., the substrate surface of the substrate). Here, for substrates with (001) and (010) planes as the substrate surface, this direction corresponds to the [010] and [001] directions, respectively.

Next, Fig. 11(a) shows an example of a β-Ga ₂ O ₃ crystal pattern formed on a substrate with a (001) plane as the substrate surface, with the longitudinal direction of the mask opening 13 set in the [010] direction, and Fig. 11(b) shows an example of a β-Ga ₂ O ₃ crystal pattern formed on a substrate with a (010) plane as the substrate surface, with the longitudinal direction set in the [001] direction. It can be seen that a good stripe pattern with smooth sidewall surfaces (side faces) is formed.

For detailed evaluation, a cross section of a β-Ga ₂ O ₃ crystal pattern was cut out by Ga focused ion milling with the (001) plane as the substrate surface and the longitudinal direction as the [010] direction, and observed using an SEM. Note that for this observation, the surface was covered with a protective film made of carbon.
The result is shown in FIG. 12(a), which shows that a concave-convex structure was obtained in which the sidewall surfaces (side faces) were (100) facets inclined at 13.7° from the perpendicular direction to the surface.
If we focus on these convex portions, we can consider them as fins (linear protrusions), and if we focus on these concave portions, we can consider them as trenches (grooves). In reality, there may be a certain percentage of lateral growth relative to vertical growth, so this percentage cannot be completely ignored. However, overall, the desired trench (groove) or fin (linear protrusion) structure can be obtained mainly by the mask opening width and opening period. The 13.7° tilt of the facets can be eliminated by using a substrate with a (-102) plane as the substrate surface, which is a substrate with a surface orientation that offsets this tilt.

As shown in FIG. 12(b), the substrate having the (010) plane as its substrate surface provided a textured structure with a higher aspect ratio than the substrate having the (001) plane as its substrate surface.
This reflects the fact that the growth rate in the [010] direction is high, resulting in a much larger vertical growth component than the lateral growth component. The facet sidewall surfaces (side faces) of the (100) plane are perpendicular to the substrate surface. This characteristic suggests that the (010) plane is more suitable than the (001) plane for forming trenches and fins (linear protrusions) when using selective growth techniques.
For ease of understanding, a cross-sectional schematic diagram of the inclination angle of the β-Ga ₂ O ₃ crystal pattern (specifically, SAG (Selective Area Growth) island) and the height of the formed β-Ga ₂ O ₃ crystal pattern is shown in FIG. 13.
This example demonstrates that, for both substrates with a (010) plane as the substrate surface and substrates with a (010) plane as the substrate surface, trench (groove) and fin (linear protrusion) structures with the (001) plane facet as the sidewall surface (side surface) can be formed by selective growth technology.

Example 2
In Example 2, samples were prepared and evaluated using substrates made of β-Ga ₂ O ₃ crystals with the (-102) plane as the substrate surface. The results are described below along with the sample preparation method. The (-102) plane substrate is expected to form fins (linear protrusions) that are highly useful in device applications because the (-102) plane and the (100) plane fin (linear protrusion) sidewall surfaces (side faces) are perpendicular to each other. This was demonstrated in Example 2.

<Sample preparation>
A sample (semiconductor device 101 according to FIG. 1) was fabricated using the same process as in Example 1, except that a substrate with a (-102) plane as the substrate surface was used. Here, the substrate made of β-Ga ₂ O ₃ crystal with a (-102) plane as the substrate surface was manufactured by Novel Crystal Technology Co., Ltd., and the sample size was 10 × 15 mm ² and the thickness was 0.65 mm. The dopant was Sn, as in Example 1, and the carrier concentration was 4.9 × 10 ¹⁸ cm ^-3 . The fact that the substrate had a (-102) plane as the substrate surface was confirmed by X-ray diffraction measurement.

<Evaluation>
First, the radial window pattern was observed from above using an SEM. The results are shown in Figure 15. Growth of a semiconductor layer (fin) (semiconductor layer (fin) 14 according to Figure 1) was observed when the window was oriented near the [010] direction. On the other hand, growth of the semiconductor layer (fin) was not observed when the window was oriented near the [201] direction. This is thought to be because the (010) plane, which is easy to etch, cannot form a sidewall surface (side surface).

Next, the fabricated fin with a window orientation of [010] (window width: 1.4 μm, mask width: 2.6 μm) was observed using an SEM. The results are shown in Figure 16, and show that the fin structure is formed with an orderly facet shape.

Furthermore, cross sections of these structures were cut out using a focused ion beam system (FIB) and observed using a scanning electron microscope (SEM). The inclination angle was 54°, and a protective film made of carbon was formed on the surface to prevent surface deformation.
Figure 17(a) shows the results, and Figure 17(b) is a schematic diagram of the cross-sectional shape obtained by tracing the SEM observation shape.
The sidewall surfaces (side faces) of the fins (linear protrusions) are (100) facets perpendicular to the main surface of the substrate. It has been demonstrated that by using a substrate whose substrate surface is the (-102) plane, it is possible to form fins (linear protrusions) whose sidewall surfaces (side faces) are vertical and have (100) facets.
The upper surface of the fin (linear protrusion) is mainly a (-201) facet. If it is difficult to fabricate a semiconductor device with this inclined upper surface shape, a horizontal upper surface can be obtained by processing the fin (linear protrusion) by a method such as CMP or etch-back after selective growth.

The present invention provides a semiconductor device using a β- _Ga2O3 crystalline semiconductor that is suitable for microfabrication and that can achieve good device characteristics by suppressing the generation of interface states, etc. Here, this semiconductor device has a trench (groove) or fin (linear protrusion) structure, and brings out the characteristics of the β- _{Ga2O3 crystalline} semiconductor that has high breakdown voltage and a wide band gap, making _it particularly suitable as a high-performance power device.
Power devices are used in a variety of fields, including powertrains for electric and hybrid vehicles, power supplies for servers, renewable energy equipment, industrial equipment, and railroad cars, and are considered essential devices for realizing a smart society. For this reason, we believe that this invention will have a significant impact on society and have a significant influence on industry.

11 Substrate (β-Ga ₂ O ₃ crystal)
12 Mask, masking pattern (e.g., SiO ₂ )
12a Thin film (SiO ₂ )
13 Opening 13a β-Ga ₂ O ₃ crystal exposing opening 14 Semiconductor layer, β-Ga ₂ O ₃ crystal, fin 15 Resist pattern 31 β-Ga ₂ O ₃ crystal 31a β-Ga ₂ O ₃ crystal film 32 Resist pattern 51 Substrate (β-Ga ₂ O ₃ crystal)
52 Mask (SiO ₂ )
53 β-Ga ₂ O ₃ crystal pattern, β-Ga ₂ O ₃ crystal semiconductor layer 54 First insulating film 54a Insulating film 55 β-Ga ₂ O ₃ crystal exposed portion (Schottky junction portion)
56 Second insulating film (e.g., SiO ₂ )
56a insulating film (e.g., SiO ₂ )
57 resist pattern 58 electrode (anode electrode)
58a Conductive film 59 Conductive film (cathode electrode)
61 Insulating substrate (β-Ga ₂ O ₃ crystal)
62 Fin (β-Ga ₂ O ₃ crystal)
63 Mask (e.g., SiO ₂ )
64 insulating film (e.g., SiO ₂ )
65 Gate insulating film (e.g., SiO ₂ )
66 Gate electrode 67 Source 68 Drain 71 Substrate (β-Ga ₂ O ₃ crystal)
72 Epitaxial β-Ga ₂ O ₃ crystal formation layer 73 Fin (β-Ga ₂ O ₃ crystal)
74 Mask (e.g., SiO ₂ )
75 Insulating film (gate insulating film)
76 Gate electrode 77 Insulator layer 78 n ⁺ layer 79 Source electrode 80 Drain electrode 101 Semiconductor device, fin structure, trench structure 201 Trench MOSSBD
202 (Horizontal) FinFET
203 (Vertical) FinFET
301 semiconductor device, fin structure, trench structure 1001 reactor 1002 gallium raw material supply source 1003 gallium metal 1004 gallium compound gas (halogen gas or hydrogen halide gas)
1005 Gallium source gas supply pipe 1006 Oxygen source supply pipe 1007 Oxygen source gas 1008 Etching gas supply pipe 1009 Etching gas (reducing gas)
1010: Substrate holder 1011: Exhaust pipe 1012: Heater 2001: Vapor phase growth apparatus

Claims (13)

It has a semiconductor layer made of β-Ga ₂ O ₃ crystal,
the semiconductor layer has a three-dimensional structure of linear protrusions or grooves on a first main surface;
The semiconductor device, wherein the side surface of the three-dimensional structure is a (100) facet. The semiconductor device of claim 1, wherein the side surface is perpendicular to the substrate surface of the semiconductor device. a semiconductor layer having a three-dimensional structure consisting of linear protrusions or grooves formed on a substrate;
The semiconductor layer is made of β-Ga ₂ O ₃ crystal,
A semiconductor device, wherein the longitudinal direction of the linear protrusion or groove is parallel to the intersection line between the substrate surface and the (100) plane of the substrate. The semiconductor device of claim 3, wherein the side surfaces of the linear protrusions or grooves are perpendicular to the substrate surface. A semiconductor device according to claim 3 or 4, wherein the substrate surface is a (010) plane and the longitudinal direction is a [001] direction. The semiconductor device of claim 3, wherein the substrate surface is a (001) plane and the longitudinal direction is a [010] direction. A semiconductor device according to claim 3 or 4, wherein the substrate surface is the (-102) plane and the longitudinal direction is the [010] direction. The semiconductor device described in claim 1 or 3, wherein at least a portion of at least one side surface of the linear protrusion or groove is a channel. The semiconductor device described in claim 1 or 3, comprising a Fin-type MOSFET structure in which a gate electrode is arranged to cover at least one side surface of the three-dimensional structure or the entire three-dimensional surface. the three-dimensional structure has a groove shape;
an anode electrode is formed so as to cover at least a portion of the three-dimensional structure via an insulating film disposed on at least a portion of a side surface and a bottom surface of the groove;
4. The semiconductor device according to claim 1, further comprising a trench-type MOSSBD structure in which the anode electrode is in Schottky contact with the semiconductor layer at a part of the three-dimensional structure. A power device comprising the semiconductor device according to claim 1 or 3. Preparing a semiconductor substrate made of β-Ga ₂ O ₃ crystal;
forming a linear or stripe-shaped masking pattern having a longitudinal direction parallel to an intersection line between the substrate surface and a (100) plane of the semiconductor substrate ;
and selectively growing β-Ga ₂ O ₃ crystals in the openings of the masking pattern where the β-Ga ₂ O ₃ crystals are exposed by a deposition method using a vapor phase. The method for manufacturing a semiconductor device according to claim 12, wherein the deposition method is a vapor phase growth method.