JP7786759B1 - Slave device, processing system, processing method, and program - Google Patents

Abstract

A system allows multiple slave devices with the same I2C address to exist, and provides a slave device, processing system, processing method, and program that transmits data at an appropriate timing even when a read request is made from a master device.
[Solution] In a processing system, a plurality of slave devices 20 that communicate using an Inter-Integrated Circuit communication method include a receiving means that receives a read request from a master device, and an output means that, when the receiving means receives the read request, outputs data at a timing according to a set identifier.
[Selected Figure] Figure 10

Description

This disclosure relates to a slave device, a processing system, a processing method, and a program.

Communication using the Inter-Integrated Circuit (I2C) communication method is used in a variety of fields. Patent Document 1 discloses a related technology for communication between devices in a master-slave relationship.

Special Publication No. 2017-500631

In the field of I2C communications related to Patent Document 1, multiple slave devices with the same I2C address can exist in a system, and there is a demand for technology that can transmit data at the appropriate time even when a read request is made by a master device.

One of the objectives of each aspect of the present disclosure is to provide a slave device, processing system, processing method, and program that can solve the above-mentioned problems.

According to one aspect of the present disclosure, the slave device is a slave device that communicates using an Inter-Integrated Circuit communication method, and includes a receiving means that receives a read request from a master device, and an output means that, when the receiving means receives the read request, outputs data at a timing according to a set identifier.

According to another aspect of the present disclosure, a processing system includes the above-mentioned slave device and a master device that sends a read request to the slave device.

According to another aspect of the present disclosure, a processing method is executed by a slave device that communicates using an Inter-Integrated Circuit communication method, and includes receiving a read request from a master device, and, upon receiving the read request, outputting data at a timing according to a set identifier.

According to another aspect of the present disclosure, a program causes a computer of a slave device that communicates using an Inter-Integrated Circuit communication method to receive a read request from a master device, and, upon receiving the read request, output data at a timing according to a set identifier.

According to each aspect of the present disclosure, multiple slave devices with the same I2C address can exist in a system, and even when a read request is received from a master device, data can be transmitted at the appropriate time.

FIG. 1 illustrates an example of a configuration of a processing system according to some embodiments of the present disclosure. FIG. 10 is a diagram illustrating a write process performed by a master device according to some embodiments of the present disclosure. FIG. 1 illustrates an example of packaging for a slave device according to some embodiments of the present disclosure. FIG. 10 illustrates an example of setting an I2C address according to some embodiments of the present disclosure. FIG. 10 is a diagram illustrating an example of ID setting according to some embodiments of the present disclosure. FIG. 10 is a diagram illustrating a read process performed by a master device according to some embodiments of the present disclosure. FIG. 1 illustrates an example of a configuration of a processing system according to some embodiments of the present disclosure. FIG. 2 illustrates an example of timing in a write cycle of a processing system according to some embodiments of the present disclosure. FIG. 10 illustrates an example of timing in a read cycle of a processing system according to some embodiments of the present disclosure. FIG. 1 illustrates an example of a configuration of a slave device according to some embodiments of the present disclosure. FIG. 10 illustrates an example of a processing flow of a slave device according to some embodiments of the present disclosure. FIG. 1 is a schematic block diagram illustrating the configuration of a computer according to at least one embodiment.

Hereinafter, the embodiments will be described in detail with reference to the drawings.
<Embodiment>
A processing system 1 according to an embodiment of the present disclosure will be described with reference to the drawings. The processing system 1 is a system that enables simultaneous access to the same Inter-Integrated Circuit (hereinafter referred to as "I2C") address. Specifically, the processing system 1 keeps the I2C address of the I2C bus at 7 bits and has a device identifier (IDentifier, hereinafter referred to as "ID") separate from the I2C address, thereby increasing the number of devices that can be connected to the I2C bus and enabling simultaneous access. The processing system 1 will be described below to clarify this point.

(Configuration of processing system)
1 is a diagram illustrating an example of a configuration of a processing system 1 according to some embodiments of the present disclosure. As shown in FIG. 1 , the processing system 1 according to one embodiment of the present disclosure includes a master device 10, slave devices 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, and 20a16, and an I2C bus 30. The slave devices 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, and 20a16 may be collectively referred to as slave devices 20a.

The master device 10 simultaneously writes data to the slave devices 20a having the same I2C address. Figure 2 is a diagram illustrating a write process performed by the master device 10 according to some embodiments of the present disclosure. Figure 2 shows an example of a write cycle of the I2C bus when the master device 10 simultaneously writes 16 bits (2 bytes) of data to the slave devices 20a5, 20a6, 20a7, and 20a8 at I2C address x1. As shown in Figure 2, the master device 10 can execute the write indicated in the write cycle to the slave device 20a having the same I2C address x1 without violating the I2C standard.

The master device 10 also reads data from the slave device 20a having the same I2C address. The master device 10 has pre-registered the slave device 20a having the same I2C address, and is therefore aware of the slave device 20a. Alternatively, the master device 10's upper control unit (not shown) may have pre-registered the slave device 20a, and the master device 10 may obtain information about the slave device 20a from the upper control unit, thereby becoming aware of the slave device 20a. Details of the processing performed by the master device 10 will be described later.

Slave devices 20a1, 20a2, 20a3, and 20a4 each have an address value x0 indicating the same I2C address. Slave devices 20a5, 20a6, 20a7, and 20a8 each have an address value x1 indicating the same I2C address. Slave devices 20a9, 20a10, 20a11, and 20a12 each have an address value x2 indicating the same I2C address. Slave devices 20a13, 20a14, 20a15, and 20a16 each have an address value x3 indicating the same I2C address.

Furthermore, slave devices 20a1, 20a5, 20a9, and 20a13 each have an ID value of ID0. Slave devices 20a2, 20a6, 20a10, and 20a14 each have an ID value of ID1. Slave devices 20a3, 20a7, 20a11, and 20a15 each have an ID value of ID2. Slave devices 20a4, 20a8, 20a12, and 20a16 each have an ID value of ID3.

Figure 3 is a diagram illustrating an example of packaging for a slave device 20a according to some embodiments of the present disclosure. For example, each of the slave devices 20a includes terminals T1, T2, T3, T4, T5, T6, T7, and T8, as shown in Figure 3. For example, terminal T1 is a ground terminal. For example, terminal T2 is a terminal corresponding to the most significant bit of the two least significant bits in a seven-bit I2C address. For example, terminal T3 is a terminal corresponding to the least significant bit of the two least significant bits in a seven-bit I2C address. For example, terminal T4 is one of two terminals for setting an ID. For example, terminal T5 is a power supply terminal. For example, terminal T6 is the other of two terminals for setting an ID. For example, terminal T7 is a clock terminal. This clock terminal is sometimes referred to as an SCL (Serial Clock) terminal. For example, terminal T8 is a data terminal. This data terminal is sometimes called an SDA (Serial DATA) terminal.

Figure 4 shows an example of I2C address settings according to some embodiments of the present disclosure. For example, the upper five bits of the seven-bit I2C address are device-specific, and the lower two bits allow four different addresses to be set. These lower two bits can be set depending on the state of terminals T2 and T3.

For example, as shown in FIG. 4, by connecting terminal T2 to a wiring with a high potential (e.g., a wiring connected to a power supply terminal) via a pull-up resistor and connecting terminal T3 to a wiring with a high potential via a pull-up resistor, the address value of slave device 20a can be set to x3. Also, as shown in FIG. 4, by connecting terminal T2 to a wiring with a high potential via a pull-up resistor and connecting terminal T3 to a wiring with a low potential (e.g., a wiring connected to a ground terminal) via a pull-down resistor, the address value of slave device 20a can be set to x2. Also, as shown in FIG. 4, by connecting terminal T2 to a wiring with a low potential via a pull-down resistor and connecting terminal T3 to a wiring with a high potential via a pull-up resistor, the address value of slave device 20a can be set to x1. Also, for example, as shown in FIG. 4, by connecting terminal T2 to a wiring with a low-level potential via a pull-down resistor and connecting terminal T3 to a wiring with a low-level potential via a pull-down resistor, the address value of slave device 20a can be set to x0.

FIG. 5 illustrates an example of ID setting according to some embodiments of the present disclosure. For example, as shown in FIG. 5, the ID value of the slave device 20a can be set to ID3 by connecting terminal T4 to a wiring having a high potential via a pull-up resistor and terminal T6 to a wiring having a high potential via a pull-up resistor. Alternatively, as shown in FIG. 5, the ID value of the slave device 20a can be set to ID2 by connecting terminal T4 to a wiring having a high potential via a pull-up resistor and terminal T6 to a wiring having a low potential via a pull-down resistor. Alternatively, as shown in FIG. 5, the ID value of the slave device 20a can be set to ID1 by connecting terminal T4 to a wiring having a low potential via a pull-down resistor and terminal T6 to a wiring having a high potential. Alternatively, as shown in FIG. 5, the ID value of the slave device 20a can be set to ID0 by connecting terminal T4 to a wiring having a low potential via a pull-down resistor and terminal T6 to a wiring having a low potential via a pull-down resistor.

Figure 6 is a diagram illustrating a read process performed by the master device 10 according to some embodiments of the present disclosure. Figure 6 shows an example of an I2C read cycle in which the master device 10 reads a total of eight bytes of data, two bytes each, from the slave devices 20a9, 20a10, 20a11, and 20a12 at I2C address x2. As shown in Figure 6, the master device 10 initiates a read cycle 170. In response to the read cycle 170 by the master device 10, the slave device 20a9, whose ID value is ID0, outputs a total of two bytes of data, data 171 and 172. Subsequently, in response to the read cycle 170 by the master device 10, the slave device 20a10, whose ID value is ID1, outputs a total of two bytes of data, data 173 and 174. Subsequently, in response to the read cycle 170 by the master device 10, the slave device 20a11, whose ID value is ID2, outputs a total of two bytes of data, data 175 and 176. Next, in response to read cycle 170 by master device 10, slave device 20a12, whose ID value is ID3, outputs a total of two bytes of data, data 177 and 178. In this way, slave device 20a with the same I2C address outputs data in a predetermined order of ID values (e.g., ascending order) in response to the A (acknowledge) signal output by master device 10 (i.e., outputs data at a timing according to its own ID value), thereby achieving the desired read. Details of the processing performed by slave device 20a will be described later.

The I2C bus connects the master device 10 and the slave device 20a. The I2C bus transmits data during communication between the master device 10 and the slave device 20a.

Note that the above-described processing performed by the processing system 1 according to one embodiment of the present disclosure is merely an example, and is not limited to the above-described processing. For example, the processing system 1 may perform the processing described below.

(Processing performed by the processing system)
The following describes processing performed by the processing system 1. FIG. 7 is a diagram illustrating an example of the configuration of the processing system 1 according to some embodiments of the present disclosure. As shown in FIG. 7, the processing system 1 described here includes a master device 10, slave devices 20a21, 20a22, 20a23, and 20a24, and pull-up resistors 180 and 181. The pull-up resistor 180 is a resistor that pulls up the SCL signal line. The pull-up resistor 181 is a resistor that pulls up the SDA signal line.

Note that by using at least one of a pull-up resistor and a pull-down resistor to set the potential of terminals T2 and T3, each of slave devices 20a21, 20a22, 20a23, and 20a24 is set to the same I2C address xN. Note that I2C address xN is one of I2C addresses x0, x1, x2, or x3.

Slave device 20a21 has its ID value set to ID0 by using a pull-down resistor to set terminals T4 and T6 to low potential. Slave device 20a22 has its ID value set to ID1 by using a pull-down resistor to set terminal T4 to low potential and a pull-up resistor to set terminal T6 to high potential. Slave device 20a23 has its ID value set to ID2 by using a pull-up resistor to set terminal T4 to high potential and a pull-down resistor to set terminal T6 to low potential. Slave device 20a24 has its ID value set to ID3 by using a pull-up resistor to set terminals T4 and T6 to high potential.

The clock terminals of the master device 10 and slave devices 20a21, 20a22, 20a23, and 20a24 are connected to the SCL signal line of the I2C bus. The data terminals of the master device 10 and slave devices 20a21, 20a22, 20a23, and 20a24 are connected to the SDA signal line of the I2C bus. The clock and data terminals of the master device 10 and slave devices 20a21, 20a22, 20a23, and 20a24 are open drain. In other words, the clock and data terminals of the master device 10 and slave devices 20a21, 20a22, 20a23, and 20a24 output low-level signals only when the I2C bus is set to low. The high level of the I2C bus is achieved by pulling up the SCL and SDA signal lines of the I2C bus to the power supply voltage VCC using pull-up resistors. Note that a slave device 20a having an I2C address different from slave devices 20a21, 20a22, 20a23, and 20a24 may be connected to the SCL and SDA signal lines of the I2C bus.

(Write process)
First, the write process performed by the processing system 1 will be described. FIG. 8 is a diagram illustrating an example of the timing of a write cycle in the processing system 1 according to some embodiments of the present disclosure. FIG. 8 illustrates an example in which the master device 10 issues a write cycle command and writes 8-bit data. Part (a) of FIG. 8 illustrates a clock signal propagating through the SCL signal line of the I2C bus. Part (b) of FIG. 8 illustrates a data signal propagating through the SDA signal line of the I2C bus. Part (c) of FIG. 8 illustrates a data signal output by the master device 10. Part (d) of FIG. 8 illustrates a data signal output by the slave device 20a21. Part (e) of FIG. 8 illustrates a data signal output by the slave device 20a22. Part (f) of FIG. 8 illustrates a data signal output by the slave device 20a23. Part (g) of FIG. 8 illustrates a data signal output by the slave device 20a24.

The data signal shown in part (b) of Figure 8 is a combination of the data signals output by all devices connected to the SDA signal line of the I2C bus (i.e., master device 10 and slave devices 20a21, 20a22, 20a23, and 20a24). The dotted lines in Figure 8 indicate that the data signal output by master device 10 and slave devices 20a21, 20a22, 20a23, and 20a24 is off, and is at a high level potential due to pull-up resistor 181 connected to the SDA signal line of the I2C bus.

The master device 10 outputs a low-level data signal 201 indicating a Start Condition, which is a signal to start a write cycle. Next, the master device 10 outputs a 7-bit I2C address 202. The master device 10 then outputs a low-level data signal 203 indicating a write access. Slave devices 20a21, 20a22, 20a23, and 20a24, which have the same I2C address, simultaneously output an A signal 204 indicating a positive response.

In response to the A signal 204, the master device 10 outputs a write data signal 205, which is a data signal for writing 8 bits. Upon receiving the write data signal 205, each of the slave devices 20a21, 20a22, 20a23, and 20a24 simultaneously outputs an acknowledgement A signal 206. The master device 10 outputs a low-level data signal 207, which indicates a stop condition, signaling the end of the write cycle. This is how the write cycle ends.

(Reading process)
Next, a read process performed by the processing system 1 will be described. FIG. 9 is a diagram illustrating an example of timing in a read cycle of the processing system 1 according to some embodiments of the present disclosure. FIG. 9 illustrates an example in which the master device 10 issues a read cycle command and reads a total of 32 bits of data, 8 bits each, from each of the slave devices 20a21, 20a22, 20a23, and 20a24. Part (a) in FIG. 9 illustrates a clock signal propagating through the SCL signal line of the I2C bus. Part (b) in FIG. 9 illustrates a data signal propagating through the SDA signal line of the I2C bus. Part (c) in FIG. 9 illustrates a data signal output by the master device 10. Part (d) in FIG. 9 illustrates a data signal output by the slave device 20a21. Part (e) in FIG. 9 illustrates a data signal output by the slave device 20a22. Part (f) in FIG. 9 illustrates a data signal output by the slave device 20a23. Part (g) in FIG. 9 shows the data signal output by the slave device 20a24.

The master device 10 outputs a low-level data signal 301 indicating a Start Condition, which is a signal to start a read cycle. Next, the master device 10 outputs a 7-bit I2C address 302. Then, the master device 10 outputs a high-level data signal 303 indicating a read access.

Slave devices 20a21, 20a22, 20a23, and 20a24, which correspond to the information indicated by the lowest two bits of the 7-bit I2C address 302 output by master device 10, simultaneously output an A signal 304 indicating an affirmative response. Upon receiving the A signal 304, master device 10 begins reading four 8-bit data bits, for a total of 32 bits.

For example, slave device 20a21 outputs 8-bit data 305. Slave device 20a21 then waits for a low-level data signal 207, which indicates a Stop Condition, and stops output. While slave device 20a21 is outputting 8-bit data 305, slave devices 20a22, 20a23, and 20a24 are each in a standby state. Master device 10 receives 8-bit data 305. Master device 10 then outputs an A signal 306, indicating an affirmative response.

Slave devices 20a22, 20a23, and 20a24 each confirm the A signal 306. Slave device 20a22 then outputs 8-bit data 307. Slave device 20a22 then waits for a low-level data signal 207, indicating a Stop Condition, and stops output. While slave device 20a22 is outputting 8-bit data 307, each of slave devices 20a21, 20a23, and 20a24 is in a standby state. Master device 10 receives the 8-bit data 307. Master device 10 then outputs an A signal 308, indicating an acknowledgment.

Slave devices 20a23 and 20a24 each confirm the A signal 308. Slave device 20a23 then outputs 8-bit data 309. Slave device 20a23 then waits for a low-level data signal 207, which indicates a Stop Condition, and stops output. While slave device 20a23 is outputting 8-bit data 309, each of slave devices 20a21, 20a22, and 20a24 is in a standby state. Master device 10 receives 8-bit data 309. Master device 10 then outputs an A signal 310, indicating an acknowledgment.

The slave device 20a24 confirms the A signal 310. Then, the slave device 20a24 outputs 8-bit data 311. The slave device 20a24 waits for a low-level data signal 207, which indicates a stop condition, and stops output. While the slave device 20a24 is outputting the 8-bit data 311, each of the slave devices 20a21, 20a22, and 20a23 is in a standby state. The master device 10 receives the 8-bit data 311. Then, the master device 10 outputs an Ab signal 312, which indicates a negative response. The master device 10 outputs a low-level data signal 207, which indicates a stop condition. This completes the read cycle.

(Advantages)

The processing system 1 according to some embodiments of the present disclosure has been described above. In the processing system 1, the slave device 20a is a slave device that communicates using the Inter-Integrated Circuit communication method. The slave device 20a receives a read request from the master device 10. When the slave device 20a receives the read request, it outputs data at a timing according to the set identifier.

This slave device 20a allows multiple slave devices 20a with the same I2C address to exist in the processing system 1, and even when a read request is received from the master device, data can be transmitted at the appropriate time.

Next, a slave device 20 according to some embodiments of the present disclosure will be described. Figure 10 is a diagram showing an example of the configuration of a slave device 20 according to some embodiments of the present disclosure. The slave device 20 is a slave device that communicates using an Inter-Integrated Circuit communication method. As shown in Figure 10, the slave device 20 includes a receiving means 801 and an output means 802.

The receiving means 801 receives a read request from the master device. When the receiving means 801 receives the read request, the output means 802 outputs data at a timing according to the set identifier.

The slave device 20 can be realized, for example, using the functions possessed by slave devices 20a, 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, and 20a16 described in Figure 1, and slave devices 20a21, 20a22, 20a23, and 20a24 described in Figure 7. That is, the receiving means 801 and the output means 802 can be realized using, for example, the functions of the slave devices 20a, 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, and 20a16 shown in FIG. 1 and the slave devices 20a21, 20a22, 20a23, and 20a24 shown in FIG. 7.

Next, processing performed by the slave device 20 according to some embodiments of the present disclosure will be described. Figure 11 is a diagram showing an example of the processing flow of the slave device 20 according to some embodiments of the present disclosure. Here, processing by the slave device 20 will be described with reference to Figure 11.

In the slave device 20, the receiving means 801 receives a read request from the master device (step S101). When the receiving means 801 receives the read request, the output means 802 outputs data at a timing according to the set identifier (step S102).

The above describes the slave device 20 according to some embodiments of the present disclosure. This slave device 20 allows multiple slave devices with the same I2C address to exist in the system, and can transmit data at the appropriate time even when a read request is received from the master device.

Note that the order of the processes in each embodiment of the present disclosure may be changed as long as appropriate processing is performed.

Each embodiment of the present disclosure has been described. However, the processing system 1, master device 10, slave devices 20a, 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, 20a16, 20a21, 20a22, 20a23, 20a24, and other control devices may have an internal computer system. The above-described processing steps are stored in the form of a program on a computer-readable recording medium, and the above processing is performed by reading and executing this program by a computer. Specific examples of computers are shown below.

Figure 12 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. As shown in Figure 12, the computer 5 includes a CPU (Central Processing Unit) 6, main memory 7, storage 8, and an interface 9.

For example, the above-mentioned processing system 1, master device 10, slave devices 20a, 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, 20a16, 20a21, 20a22, 20a23, 20a24, and other control devices are each implemented in computer 5. The operation of each of the above-mentioned processing units is stored in the form of a program in storage 8. CPU 6 reads the program from storage 8, expands it in main memory 7, and executes the above-mentioned processing in accordance with the program. Furthermore, CPU 6 allocates storage areas in main memory 7 corresponding to each of the above-mentioned storage units in accordance with the program.

Examples of storage 8 include HDD (Hard Disk Drive), SSD (Solid State Drive), magnetic disk, magneto-optical disk, CD-ROM (Compact Disc Read Only Memory), DVD-ROM (Digital Versatile Disc Read Only Memory), semiconductor memory, etc. Storage 8 may be internal media directly connected to the bus of computer 5, or external media connected to computer 5 via interface 9 or a communication line. Furthermore, if this program is distributed to computer 5 via a communication line, the computer 5 that receives the program may expand the program into main memory 7 and execute the above-mentioned processing. In at least one embodiment, storage 8 is a non-transitory, tangible storage medium.

The program may also implement some of the functions described above. Furthermore, the program may be a file that can implement the functions described above in combination with a program already recorded on the computer system, a so-called differential file (differential program).

Several embodiments of the present disclosure have been described, but these embodiments are merely examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and modifications may be made to these embodiments without departing from the spirit of the disclosure.

Note that some or all of the above embodiments can also be described as, but are not limited to, the following notes.

(Appendix 1)
A slave device that communicates using an Inter-Integrated Circuit communication method,
receiving means for receiving a read request from a master device;
an output means for outputting data at a timing according to a set identifier when the receiving means receives the read request;
a slave device comprising:

(Appendix 2)
The identifier is set by a number,
The output means
outputting the data at a timing determined in ascending order of the number or at a timing determined in ascending order of the number;
2. The slave device of claim 1.

(Appendix 3)
One of a plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system,
The output means
When the receiving means receives the read request in the plurality of slave devices assigned the same address, the data is output at a timing according to the set identifier.
3. The slave device of claim 1 or 2.

(Appendix 4)
One of a plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system,
The output means
When the receiving means receives the read request, the receiving means enters a standby state while a slave device other than the receiving means itself among the plurality of slave devices outputs data.
4. The slave device of claim 1.

(Appendix 5)
a slave device according to any one of Supplementary Note 1 to Supplementary Note 4;
a master device that transmits a read request to the slave device;
A processing system comprising:

(Appendix 6)
A processing method executed by a slave device that communicates using an Inter-Integrated Circuit communication method, comprising:
receiving a read request from a master device;
When the read request is received, outputting the data at a timing according to the set identifier;
A processing method comprising:

(Appendix 7)
The identifier is set by a number,
outputting the data at a timing determined in ascending order of the numbers or at a timing determined in ascending order of the numbers;
7. The method of claim 6, comprising:

(Appendix 8)
A processing method executed by one of a plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system, comprising:
When the read request is received, the plurality of slave devices assigned the same address output the data at a timing according to the set identifier;
8. The method of claim 6 or 7, comprising:

(Appendix 9)
A processing method executed by one of a plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system, comprising:
When the read request is received, the device enters a standby state while a slave device other than the device itself among the plurality of slave devices outputs data;
9. The processing method according to any one of claims 6 to 8, comprising:

(Appendix 10)
A slave device computer that communicates using the Inter-Integrated Circuit communication method,
receiving a read request from a master device;
When the read request is received, outputting the data at a timing according to the set identifier;
A program that executes the following.

(Appendix 11)
The identifier is set by a number,
outputting the data at a timing determined in ascending order of the numbers or at a timing determined in ascending order of the numbers;
11. The program according to claim 10, which causes the computer to execute the above steps.

(Appendix 12)
In the Inter-Integrated Circuit communication system, a computer of one of a plurality of slave devices assigned the same address is
When the read request is received, the plurality of slave devices assigned the same address output the data at a timing according to the set identifier;
12. The program according to claim 10 or 11, which causes the program to execute the above steps.

(Appendix 13)
In the Inter-Integrated Circuit communication system, a computer of one of a plurality of slave devices assigned the same address is
When the read request is received, the device enters a standby state while a slave device other than the device itself among the plurality of slave devices outputs data;
13. The program according to any one of claims 10 to 12,

1... Processing system 5... Computer 6... CPU
7... Main memory 8... Storage 9... Interface 10... Master device 20, 20a, 20a1, 20a2, 20a3, 20a4, 20a5, 20a6, 20a7, 20a8, 20a9, 20a10, 20a11, 20a12, 20a13, 20a14, 20a15, 20a16, 20a21, 20a22, 20a23, 20a24... Slave device 180, 181... Pull-up resistor 801... Receiving means 802... Output means T1, T2, T3, T4, T5, T6, T7, T8... Terminal

Claims (7)

A slave device that communicates using an Inter-Integrated Circuit communication method,
receiving means for receiving a read request from a master device;
an output means for outputting data at a timing according to a set identifier when the receiving means receives the read request;
a slave device comprising: The identifier is set by a number,
The output means
outputting the data at a timing determined in ascending order of the number or at a timing determined in ascending order of the number;
2. The slave device of claim 1. One of a plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system,
The output means
When the receiving means receives the read request in the plurality of slave devices assigned the same address, the data is output at a timing according to the set identifier.
2. The slave device of claim 1. One of a plurality of slave devices assigned the same address in the Inter-Integrated Circuit communication system,
The output means
When the receiving means receives the read request, the receiving means enters a standby state while a slave device other than the receiving means itself among the plurality of slave devices outputs data.
2. The slave device of claim 1. A slave device according to any one of claims 1 to 4;
a master device that transmits a read request to the slave device;
A processing system comprising: A processing method executed by a slave device that communicates using an Inter-Integrated Circuit communication method, comprising:
receiving a read request from a master device;
When the read request is received, outputting the data at a timing according to the set identifier;
A processing method comprising: A slave device computer that communicates using the Inter-Integrated Circuit communication method,
receiving a read request from a master device;
When the read request is received, outputting the data at a timing according to the set identifier;
A program that executes the following.