JP7790145B2 - Information processing device, control method, and program - Google Patents

Description

The present invention relates to an information processing device, a control method, and a program.

Patent Document 1 below discloses an algorithm that controls the CPU clock frequency based on the number of packets received within a certain period of time in order to reduce power consumption.

However, because the technology in Patent Document 1 controls the CPU clock frequency based on the number of packets per unit time, it is unable to maintain power-saving mode when packets are sent simultaneously from multiple terminals.

Specifically, with the technology in Patent Document 1, when a communications device is in power-saving mode and a large number of SNMP packets are sent in a short period of time from a terminal on the same network, the packets cannot be processed in time and overflow from the buffer. As the packets must be processed by the main system, the device returns from power-saving mode to normal mode, which can result in significant power consumption.

The present invention aims to solve the problems of the conventional technology described above by enabling a power-saving mode to be maintained when packets are sent simultaneously from multiple terminals.

To solve the above-mentioned problems, an information processing device according to one embodiment includes a communication means and a control unit that controls the CPU clock frequency based on the number of terminals connected to the communication means.

In one embodiment, the detection mechanism allows a device to maintain power-saving mode when packets are sent simultaneously from multiple devices.

FIG. 1 is a diagram showing a first example of a system configuration of an information processing apparatus according to an embodiment; FIG. 1 is a diagram showing a first example of a functional configuration of an information processing device according to an embodiment; FIG. 10 is a diagram showing a second example of the system configuration of an information processing apparatus according to an embodiment; FIG. 10 is a diagram showing a second example of the functional configuration of an information processing device according to an embodiment; FIG. 10 is a diagram showing an example of a procedure for mode switching processing by an information processing apparatus according to an embodiment; FIG. 10 is a diagram showing an example of a burst table used by an information processing device according to an embodiment; FIG. 10 is a diagram showing an example of a procedure for burst table processing by an information processing device according to an embodiment; FIG. 10 is a diagram showing an example of a control table used by an information processing apparatus according to an embodiment; FIG. 10 is a diagram showing an example of a procedure for periodic event processing by an information processing apparatus according to an embodiment; FIG. 10 is a diagram showing an example of a procedure for a normal mode return process performed by an information processing apparatus according to an embodiment; FIG. 10 is a diagram showing an example of a procedure for a normal mode return process performed by an information processing apparatus according to an embodiment;

One embodiment will be described below with reference to the drawings.

First, an example of the system configuration and functional configuration of an information processing device 10 according to one embodiment will be described with reference to Figures 1 to 4. The information processing device 10 according to one embodiment is a device that is equipped with at least a power saving mode and is capable of wireless or wired communication with multiple terminals. Examples of information processing devices 10 include various image processing devices (printers, scanners, MFPs (Multifunction Peripherals), etc.), projectors, IWBs (Interactive Whiteboards), PCs, smartphones, telephones, television receivers, etc.

The information processing devices 10 include those with two CPUs (Central Processing Units) and those with one CPU. Figures 1 and 2 show an example of the system configuration and functional configuration of an information processing device 10-1 with two CPUs. Figures 3 and 4 show an example of the system configuration and functional configuration of an information processing device 10-2 with one CPU.

(First example of system configuration)
1 is a diagram showing a first example of the system configuration of an information processing device 10 according to an embodiment. As shown in FIG. 1, the information processing device 10-1 includes a printer 11, a scanner 12, a FAX 13, a main system 10A, and a subsystem 10B.

The printer 11, scanner 12, and fax 13 are image processing modules provided in the information processing device 10-1.

The main system 10A operates to control the entire information processing device 10-1 when the information processing device 10-1 is in "normal mode." The main system 10A has a main CPU 14A and a main memory 15A. The main CPU 14A is a processor that controls the main system 10A. The main memory 15A stores programs, various data, etc. related to the control of the main system 10A. Examples of the main memory 15A include ROM (Read Only Memory) and RAM (Random Access Memory).

When the information processing device 10-1 is in "power saving mode," the subsystem 10B operates to control the entire information processing device 10-1 in place of the main system 10A. The subsystem 10B has a sub-CPU 14B and a sub-memory 15B. The sub-CPU 14B is a processor that controls the subsystem 10B. The sub-memory 15B stores programs, various data, etc. related to the control of the subsystem 10B. Examples of the sub-memory 15B include ROM (Read Only Memory) and RAM (Random Access Memory).

Subsystem 10B also has a network I/F 16 and a filter DMAC 17. Network I/F 16 is an example of a "communication means" and is an interface for sending and receiving packet data between multiple terminals. Filter DMAC 17 has the function of filtering packets received by network I/F 16 and the function of a DMAC (Direct Memory Access Controller).

(First example of functional configuration)
FIG. 2 is a diagram illustrating a first example of a functional configuration of the information processing device 10 according to an embodiment.

As shown in FIG. 2, the information processing device 10-1 includes a main supplicant 26A in a main system 10A.

The main supplicant 26A processes network packets related to each image processing module when the information processing device 10-1 is in "normal mode."

In addition, the information processing device 10-1 includes a packet filter 20, an SNMP processing unit 21, a terminal information storage unit 22, a system management unit 23, a clock control unit 24, and a sub-supplicant 26B in the subsystem 10B.

The packet filter 20 performs a predetermined filtering process on packets received from the terminal. This filtering process, for example, extracts SNMP packets and excludes other packets.

The SNMP processing unit 21 receives SNMP packets from the packet filter 20 and processes the internal information of the SNMP packets.

The terminal information storage unit 22 stores the terminal identification information (MAC address), packet reception time, and burst traffic period time extracted by the SNMP processing unit 21.

The system management unit 23 checks the information in the terminal information storage unit 22 when a packet is received or as a periodic event, and processes it as necessary.

The clock control unit 24 changes the CPU clock frequency according to instructions from the system management unit.

When the information processing device 10-1 is in "power saving mode," the sub-supplicant 26B receives packets from the packet filter 20 and outputs packets related to each image processing module to the main supplicant 26A. Alternatively, when the information processing device 10-1 is in "power saving mode," the sub-supplicant 26B processes network packets related to each image processing module.

(Second example of system configuration)
3 is a diagram showing a second example of the system configuration of the information processing device 10 according to an embodiment. The information processing device 10-2 shown in FIG. 3 differs in system configuration from the information processing device 10-1 shown in FIG. 1 in that it does not have a subsystem 10B (i.e., a sub-CPU 14B and a sub-memory 15B). In accordance with this change, in the information processing device 10-2 shown in FIG. 3, the network I/F 16 and the filter DMAC 17 are provided in the main system 10A.

(Second example of functional configuration)
4 is a diagram showing a second example of the functional configuration of the information processing device 10 according to an embodiment. The information processing device 10-2 shown in FIG. 3 differs in functional configuration from the information processing device 10-1 shown in FIG. 3 in that it does not have a subsystem 10B (i.e., a sub-CPU 14B and a sub-memory 15B). In accordance with this change, in the information processing device 10-2 shown in FIG. 4, the packet filter 20, the SNMP processing unit 21, the terminal information storage unit 22, the system management unit 23, and the clock control unit 24 are provided in the main system 10A.

Note that each function of the information processing device 10 shown in Figures 2 and 4 can be realized by one or more processing circuits. Here, the term "processing circuit" as used herein includes processors programmed to perform each function by software, such as processors implemented by electronic circuits, as well as devices such as ASICs (Application Specific Integrated Circuits), DSPs (Digital Signal Processors), FPGAs (Field Programmable Gate Arrays), and conventional circuit modules designed to perform each of the functions described above.

(Example of a procedure for mode switching processing)
FIG. 5 is a diagram showing an example of a procedure of a mode switching process by the information processing device 10 according to an embodiment.

First, when a predetermined mode switching event occurs, the information processing device 10 switches from "normal mode" to "power saving mode" (step S501).

Next, the information processing device 10 executes a predetermined periodic event process (step S502). The periodic event process increases the CPU clock frequency when burst traffic is predicted. Details of the periodic event process will be described later using Figure 9.

Next, when the information processing device 10 receives a packet from the terminal (step S503), it determines whether the packet received from the terminal is SNMP (step S504).

If it is determined in step S504 that the packet received from the terminal is SNMP (step S504: Yes), the information processing device 10 executes predetermined burst table processing (step S505). Burst table processing is a process in which, if SNMP packets are received consecutively from the terminal within a unit time, it determines that burst traffic is occurring, and records the MAC address of the terminal, the time the burst traffic occurred, etc. in the burst table illustrated in FIG. 6. Details of burst table processing will be described later using FIG. 7. The information processing device 10 then proceeds to step S506.

On the other hand, if it is determined in step S504 that the packet received from the terminal is not SNMP (step S504: No), the information processing device 10 proceeds to step S506.

In step S506, the information processing device 10 determines whether the buffer for storing packets is full.

If it is determined in step S506 that the buffer for storing packets is not full (step S506: No), the information processing device 10 returns to step S502.

On the other hand, if it is determined in step S506 that the buffer for storing packets is full (step S506: Yes), the information processing device 10 executes a predetermined normal mode return process (step S507). The normal mode return process is a process for returning to normal mode. Details of the normal mode return process will be described later using Figure 7. Thereafter, the information processing device 10 ends the series of processes shown in Figure 5.

(An example of a burst table)
6 is a diagram showing an example of a burst table used by the information processing device 10 according to an embodiment. As shown in FIG. 6, the burst table stores information relating to the occurrence of burst traffic, such as the MAC address of a terminal, the burst traffic occurrence period (burst period), and the time when the last burst traffic occurred, in association with each other. Based on this burst table, the information processing device 10 can predict the time when the next burst traffic will occur for each terminal, based on the time when the last burst traffic occurred and the burst traffic occurrence period (burst period). The burst table is stored in the terminal information storage unit 22.

When the information processing device 10 (system management unit 23) receives consecutive SNMP packets from a certain terminal within a predetermined time period (e.g., 1 second), it determines that burst traffic has occurred at that terminal and registers information about that terminal in the burst table shown in Figure 6.

In addition, when a predetermined time (e.g., one second) has elapsed since the last time burst traffic occurred at a certain terminal, the information processing device 10 (system management unit 23) deletes the information about that terminal from the burst table shown in Figure 6.

(Example of Burst Table Processing Procedure)
FIG. 7 is a diagram showing an example of a procedure for burst table processing by the information processing device 10 according to an embodiment.

First, the information processing device 10 determines whether the burst flag, which indicates whether burst traffic is occurring, is ON (step S701).

If it is determined in step S701 that the burst flag is not ON (step S701: No), the information processing device 10 switches the burst flag to ON (step S702) and terminates the series of processes shown in Figure 7.

On the other hand, if it is determined in step S701 that the burst flag is ON (step S701: Yes), the information processing device 10 determines whether SNMP packets have been received consecutively within a unit time (step S703).

If it is determined in step S703 that no SNMP packets have been received consecutively within the unit time (step S703: No), the burst flag is switched OFF (step S702), and the series of processes shown in Figure 7 is terminated.

On the other hand, if it is determined in step S703 that SNMP packets have been received consecutively within the unit time (step S703: Yes), the information processing device 10 refers to the burst table illustrated in FIG. 6 (step S705) and determines whether the MAC address of the terminal is registered in the burst table (step S706).

If it is determined in step S706 that the MAC address of the terminal is not registered in the burst table (step S706: No), the information processing device 10 (system management unit 23) registers the MAC address of the terminal and the time when the burst traffic occurred in the burst table (step S707), and ends the series of processes shown in Figure 7.

On the other hand, if it is determined in step S706 that the terminal's MAC address is registered in the burst table (step S706: Yes), the information processing device 10 determines whether the burst traffic occurrence period (burst period) is registered in the burst table (step S708).

If it is determined in step S708 that the burst traffic occurrence period (burst period) is not registered in the burst table (step S708: No), the information processing device 10 (system management unit 23) registers the burst traffic occurrence period (burst period) in the burst table (step S709), and terminates the series of processes shown in FIG. 7. For example, when burst traffic occurs twice with the same MAC address, the information processing device 10 calculates the burst traffic occurrence period (burst period) based on the difference between the occurrence time of the current burst traffic and the occurrence time of the previous burst traffic, and registers the burst traffic occurrence period (burst period) in the burst table.

On the other hand, if it is determined in step S708 that the burst traffic occurrence period (burst period) is registered in the burst table (step S708: Yes), the information processing device 10 terminates the series of processes shown in FIG. 7.

(Example of a control table)
FIG. 8 is a diagram illustrating an example of a control table used by the information processing device 10 according to an embodiment. As illustrated in FIG. 8, the control table stores the number of terminals connected to the information processing device 10 (i.e., the number of terminals registered in the burst table) and the CPU clock frequency, in association with each other. In the example illustrated in FIG. 8, the control table is configured so that the greater the number of terminals registered in the burst table, the higher the CPU clock frequency. Based on this control table, the information processing device 10 (clock control unit 24) can change the CPU clock frequency in accordance with the number of terminals registered in the burst table. For example, if the number of terminals registered in the burst table decreases, the information processing device 10 (clock control unit 24) can increase power saving effects by lowering the CPU clock frequency based on this control table. The control table is stored, for example, in the terminal information storage unit 22.

(Example of a procedure for processing a periodic event)
FIG. 9 is a diagram showing an example of a procedure for periodic event processing by the information processing device 10 according to an embodiment.

First, the information processing device 10 switches the burst flag to OFF (S901). Next, the information processing device 10 (system management unit 23) references the burst table illustrated in FIG. 6 (step S902), predicts the predicted time of burst traffic occurrence (step S903), and determines whether the predicted time of burst traffic occurrence is approaching (step S904).

If it is determined in step S904 that the predicted time of burst traffic occurrence is approaching (step S904: Yes), the information processing device 10 (clock control unit 24) increases the CPU clock frequency based on the control table shown in FIG. 8 and the number of terminals (MAC addresses) connected to the information processing device 10 (the number of terminals registered in the burst table) (step S905). The information processing device 10 then terminates the series of processes shown in FIG. 9.

On the other hand, if it is determined in step S904 that the predicted time of burst traffic occurrence is not approaching (step S904: No), the information processing device 10 (clock control unit 24) lowers the CPU clock frequency based on the control table shown in FIG. 8 and the number of terminals (MAC addresses) connected to the information processing device 10 (the number of terminals registered in the burst table) (step S906). Thereafter, the information processing device 10 ends the series of processes shown in FIG. 9.

(Example of normal mode return process procedure)
10 and 11 are diagrams showing an example of the procedure of the normal mode return process by the information processing device 10 according to an embodiment. Fig. 10 shows the normal mode return process when the information processing device 10 is an information processing device 10-1 having two CPUs. Fig. 11 shows the normal mode return process when the information processing device 10 is an information processing device 10-2 having one CPU.

As shown in FIG. 10, the information processing device 10-1 first returns the main system 10A to "normal mode" (S1001). Next, the information processing device 10-1 transfers packets to the main system 10A (S1002). Next, the information processing device 10-1 executes packet processing by the main system 10A (S1003). Thereafter, the information processing device 10-1 ends the series of processes shown in FIG. 10.

As shown in FIG. 11, the information processing device 10-2 first returns the main system 10A to "normal mode" (S1101). Next, the information processing device 10-2 executes packet processing by the main system 10A (S1102). Thereafter, the information processing device 10-2 ends the series of processes shown in FIG. 11.

As described above, the information processing device 10 according to one embodiment learns the burst traffic occurrence period, predicts the predicted time of burst traffic occurrence based on the burst traffic occurrence period, and can increase the CPU clock frequency based on the number of terminals (MAC addresses) experiencing burst traffic before the predicted time of burst traffic occurrence arrives.

As a result, the information processing device 10 according to one embodiment can process packets sent simultaneously from multiple terminals while maintaining power saving mode, even when the packets are sent simultaneously from multiple terminals.

In addition, the information processing device 10 according to one embodiment can increase the CPU clock frequency when there are a large number of terminals (MAC addresses) generating burst traffic, thereby improving packet processing capability while maintaining power saving mode.

In addition, the information processing device 10 according to one embodiment can lower the CPU clock frequency when the number of terminals (MAC addresses) generating burst traffic is small, thereby improving power saving effects.

(effect)
As described above, the information processing device 10 according to one embodiment includes a network I/F 16 (communication means) and a clock control unit 24 that controls the CPU clock frequency based on the number of terminals connected to the network I/F 16.

As a result, the information processing device 10 according to one embodiment can appropriately control the CPU clock frequency depending on the number of terminals connected to the network I/F 16.

Furthermore, in an information processing device 10 according to one embodiment, the clock control unit 24 increases the CPU clock frequency as the number of terminals experiencing burst traffic increases.

As a result, the information processing device 10 according to one embodiment can appropriately control the CPU clock frequency depending on the number of terminals experiencing burst traffic.

Furthermore, in one embodiment of the information processing device 10, the clock control unit 24 uses the number of MAC addresses included in packets received by the network I/F 16 as the number of terminals connected to the network I/F 16.

As a result, the information processing device 10 according to one embodiment can control the CPU clock frequency with high precision when in a network environment where burst traffic occurs from multiple terminals, compared to when the CPU clock frequency is controlled based on the number of packets.

In addition, the information processing device 10 according to one embodiment includes a terminal information storage unit 22 that stores information relating to the occurrence of burst traffic for each terminal where burst traffic has occurred, and a system management unit 23 that predicts the predicted time at which burst traffic will occur based on the information relating to the occurrence of burst traffic stored in the terminal information storage unit 22, and a clock control unit 24 that controls the CPU clock frequency at a timing before the predicted time arrives.

As a result, the information processing device 10 according to one embodiment can predict the occurrence of burst traffic and control the CPU clock frequency in advance before the burst traffic occurs.

Furthermore, in an information processing device 10 according to one embodiment, information relating to the occurrence of burst traffic includes the time at which the burst traffic occurred and the period during which the burst traffic occurred.

As a result, the information processing device 10 according to one embodiment can accurately predict the occurrence of burst traffic and control the CPU clock frequency in advance before the burst traffic occurs.

Furthermore, in an information processing device 10 according to one embodiment, when packets are received consecutively from the same terminal within a predetermined period of time, the system management unit 23 determines that burst traffic has occurred at that terminal, and registers or updates information regarding the occurrence of burst traffic related to that terminal in the terminal information storage unit 22.

As a result, the information processing device 10 according to one embodiment can accurately determine the number of terminals experiencing burst traffic and appropriately control the CPU clock frequency according to the number of terminals experiencing burst traffic.

In addition, in one embodiment of the information processing device 10, if packets are not received consecutively from the same terminal within a predetermined time, the system management unit 23 deletes information regarding the occurrence of burst traffic related to that terminal from the terminal information storage unit 22.

As a result, the information processing device 10 according to one embodiment can accurately determine the number of terminals experiencing burst traffic and appropriately control the CPU clock frequency according to the number of terminals experiencing burst traffic.

Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited to these embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as set forth in the claims.

10, 10-1, 10-2 Information processing device 10A Main system 10B Subsystem 11 Printer 12 Scanner 13 FAX
14A Main CPU
15A Main memory 14B Sub CPU
15B Sub-memory 16 Network I/F
17 Filter DMAC
20 Packet filter 21 SNMP processing unit 22 Terminal information storage unit 23 System management unit 24 Clock control unit 26A Main supplicant 26B Sub-supplicant

Japanese Patent Application Laid-Open No. 2006-345093

Claims (8)

means of communication;
a clock control unit that controls a CPU clock frequency based on the number of terminals connected to the communication means ,
The clock control unit
The more the number of terminals generating burst traffic, the higher the CPU clock frequency.
1. An information processing device comprising: The clock control unit
2. The information processing apparatus according to claim 1 , wherein the number of MAC addresses contained in packets received by said communication means is used as the number of said terminals connected to said communication means. a terminal information storage unit that stores information about the occurrence of burst traffic for each of the terminals in which the burst traffic occurs;
a system management unit that predicts the time of occurrence of the burst traffic based on information about the occurrence of the burst traffic stored in the terminal information storage unit,
The clock control unit
3. The information processing apparatus according to claim 1 , wherein the CPU clock frequency is controlled at a timing before the predicted occurrence time arrives. 4. The information processing device according to claim 3 , wherein the information regarding the occurrence of burst traffic includes the time when the burst traffic occurred and the occurrence period of the burst traffic. The system management unit
The information processing device according to claim 3 or 4, characterized in that when packets are received consecutively from the same terminal within a predetermined time, it is determined that the burst traffic has occurred in that terminal, and information regarding the occurrence of the burst traffic related to that terminal is registered or updated in the terminal information storage unit. The system management unit
6. The information processing device according to claim 3 , wherein, when packets are not received consecutively from the same terminal within a predetermined time, information regarding the occurrence of the burst traffic related to the terminal is deleted from the terminal information storage unit. A control method for an information processing device having a communication means,
a control step of controlling a CPU clock frequency of the information processing device based on the number of terminals connected to the communication means ,
In the control step,
The more the number of terminals generating burst traffic, the higher the CPU clock frequency.
A control method comprising: A program for controlling an information processing device having a communication means,
Computer,
a control unit that controls a CPU clock frequency of the information processing device based on the number of terminals connected to the communication means ;
The control unit
The more the number of terminals generating burst traffic, the higher the CPU clock frequency.
program.