JP7790591B2 - Node assembly, concept sequencer, node assembly generation program, and node assembly generation method - Google Patents

Description

The disclosed technology relates to a node assembly using an artificial neural network, a concept sequencer, a node assembly generation program, and a node assembly generation method.

Artificial neural networks can store numerical values in their parameters (see, for example, non-patent literature: Takayuki Okatani, "Deep Learning," Journal of the Institute of Image Information and Television Engineers, Vol. 68, No. 6, 2014, pp. 466-471). These parameters are parameters of a function that converts input to output, and do not refer to any concept. In other words, they are not conceptual memories.

Although unrelated to artificial neural networks, memory elements used in computers can also store numerical values. Therefore, by associating numbers with concepts, concepts can be stored in memory elements. However, concepts stored in memory elements do not change. Furthermore, concepts stored in memory elements do not interact with other concepts to create new concepts, as do concepts stored by humans.

Supervised learning in artificial neural networks can reproduce the input and output that it has been taught. Furthermore, for inputs that it has not been taught, supervised learning in artificial neural networks can search for similar inputs that it has already been taught and select the corresponding output. However, supervised learning in artificial neural networks cannot select an output if the input is not similar to the inputs that it has already been taught. Furthermore, supervised learning in artificial neural networks cannot create new outputs other than the outputs that it was originally taught.

On the other hand, reinforcement learning in artificial neural networks can find unknown inputs that maximize rewards when given a reward. However, because rewards are given, reinforcement learning in artificial neural networks cannot create rewards on its own. Nor can it find true rewards when the reward is unknown.

This fact arises from the fact that existing artificial neural networks are unable to generate concepts on their own. The inability to generate concepts on their own also means that existing artificial neural networks cannot possess intelligence.

The disclosed technology has been developed in consideration of the above points, and aims to provide a node assembly, a concept sequencer, a node assembly generation program, and a node assembly generation method that can generate concepts on their own.

A first aspect of the present disclosure is a node assembly used by a computer having an external input unit, an edge information transmission efficiency change unit, an edge selection unit, and a storage unit, and including at least one or more nodes connected by at least one or more edges that transmit bit information , the node assembly being configured with a network stored in the storage unit, wherein the internal state of each of the nodes is expressed by the sum of a predetermined function that is a value that numerically represents the internal state of the node and is expressed by potentials and time that affect the firing state of the node, and a sum of input values input to each of the nodes from all of the connected edges, and The external state of the network is determined to be an ignition state or a non-ignition state by comparing the potential with a predetermined ignition threshold, and the edge selection unit changes the information transmission efficiency , which represents the transmission efficiency of bit information at each edge selected from the network, by the edge information transmission efficiency change unit according to the difference in ignition time at each node connected to both ends of the edge.When the external input unit inputs bit information to the network, the node assembly is composed of all nodes that are connected to other nodes other than themselves by a single edge, out of the nodes that fire within a predetermined threshold time from a specific time.

A second aspect of the present disclosure is a conceptual sequencer that includes a plurality of the node assemblies described in the first aspect and at least one or more edges that connect the node assemblies to each other by connecting any of the nodes included in each of the node assemblies, and is a closed circuit that is generated when the external input unit continues to input bit information to the edges connected to the nodes that make up the node assembly even after the node assembly has been generated, and is a network that includes at least one recursive circuit in which the plurality of node assemblies are connected in a circular manner by the edges.

A third aspect of the present disclosure is a node assembly generation program that causes a computer to execute a process to generate a node assembly including all nodes that are connected to other nodes by a single edge from each node that has fired within a predetermined threshold time from a specific time, by expressing the internal state of each node as the sum of a predetermined function that is a value that numerically represents the internal state of the node and is expressed by a potential and time that affects the firing state of the node, and the sum of the input values input to each node from all connected edges, determining the external state of each node as fired or non-fired by comparing the potential with a predetermined firing threshold, and changing the information transmission efficiency that represents the efficiency of transmission of bit information on each edge according to the difference in firing time at each node connected to both ends of the edge.

A fourth aspect of the present disclosure is a node assembly generation method in which a computer executes a process to generate a node assembly including all nodes that are connected to other nodes other than itself by one edge, out of the nodes that have fired within a predetermined threshold time from a specific time, by expressing the internal state of each of the nodes as the sum of a predetermined function that is expressed by a value that numerically expresses the internal state of the node and is expressed by a potential that affects the firing state of the node and time, and a sum of input values that are input to each of the nodes from all of the connected edges, determining the external state of each of the nodes to be in an fired state or a non-fired state by comparing the potential with a predetermined firing threshold, and changing an information transmission efficiency that represents the transmission efficiency of the bit information on each of the edges according to the difference in firing time at each of the nodes connected to both ends of the edge.

The node assembly, concept sequencer, node assembly generation program, and node assembly generation method disclosed herein have the effect of enabling users to create concepts on their own.

FIG. 1 illustrates an example of an artificial neural network. FIG. 1 illustrates an example of a node assembly. FIG. 2 is a diagram illustrating an example of a functional configuration of an information processing device. FIG. 2 is a block diagram illustrating an example of a hardware configuration of an information processing device. 10 is a flowchart illustrating an example of the flow of a node assembly generation process. FIG. 1 is a diagram illustrating an example of a node assembly that configures a recursive circuit. FIG. 10 is a diagram showing an example of a conceptual sequencer including node assemblies that do not constitute a recursive circuit. FIG. 1 illustrates an example of a conceptual sequencer with multiple recursive circuits. FIG. 1 illustrates an example network including a concept sequencer and a node assembly that accepts input from outside the network. FIG. 1 illustrates an example of a concept sequencer that recalls memories without external input. 10 is a flowchart showing an example of the flow of a growth process.

An example of an embodiment of the disclosed technology will be described below with reference to the drawings. Note that identical or equivalent components, parts, and processes will be denoted by the same reference numerals throughout the drawings, and redundant explanations will be omitted.

Figure 1 shows an example of an artificial neural network 1 including nodes 2 and edges 3. For ease of explanation, the artificial neural network 1 will be referred to as "Network 1."

In network 1, edge 3 transmits input values (referred to as "bit information") unidirectionally along the direction of the arrow. Node 2, which is the source of the bit information flowing through edge 3, is defined as the "origin node 2," and node 2, which receives the bit information from edge 3, is defined as the "end node 2." Furthermore, when there is no need to distinguish between the origin node 2 and the end node 2, they will be referred to as "node 2."

Network 1 includes at least one or more nodes 2 connected by one or more edges 3.

Node 2 has an internal state with a potential v, a firing threshold θ, a reset value r, and a refractory period rp, and an external state with a firing bit. The firing bit can take the value "0" or "1." The firing bit is an output that represents the firing state at node 2.

Edge 3 has a delay d in its internal state and an information transmission efficiency w. Also, for Network 1, we define the time of the entire Network 1, i.e., network time t.

Here, the potential v of node 2 is a value that numerically represents the internal state of node 2 and affects the firing state of node 2. The potential v of node 2 is expressed as the sum of two terms. The first term is a predetermined function expressed by the potential v and the network time t. The second term is the sum of the bit information input to node 2 from all connected edges 3.

The internal state of node 2 is expressed, for example, by equation (1). In equation (1), "v" is the internal state of node 2, i.e., the potential of node 2, "t" is network time, and "Σw" is the sum of the products of the bit information input to each edge 3 connected to node 2 and the information transmission efficiency w of edge 3 at network time t.

(Equation 1)
dv/dt=Σw... (1)

The internal state of node 2 can also be expressed, for example, by equations (2) and (3). "u" is a variable used only in equations (2) and (3) and is a recovery variable that recovers the potential v of node 2 that has fired. "a" is a time constant that controls how much the recovery variable u decays over time. "b" is a constant that affects the sensitivity of the recovery variable u to the internal state of node 2.

(Equation 2)
dv/dt=0.04v ² +5v+140-u+Σw... (2)
du/dt=a(bv-u)... (3)

Furthermore, the internal state of node 2 is also represented by a system of differential equations called the Hodgkin-Huxley model (see, for example, <https://compneuro-julia.github.io/neuron-model/hodgkin-huxley.html>).

In network 1, node 2 fires when the potential v of node 2 exceeds the firing threshold θ. When node 2 fires, the firing bit of node 2 becomes "1" only until a predetermined time has elapsed since node 2 fired. When node 2 fires, the potential v of node 2 is set to a reset value r, and after the predetermined time has elapsed, the firing bit of node 2 becomes "0". Once node 2 fires, it will not fire even if the potential v of node 2 exceeds the firing threshold θ until the refractory period rp has elapsed from the time node 2 fires.

The bit information that flows through edge 3 when node 2 fires is the firing bit of node 2. When the time represented by delay d has passed since the firing time when source node 2 of edge 3 fires, the firing bit arrives at destination node 2 of edge 3, and the real value of firing bit x information transmission efficiency w is input to destination node 2. In other words, information transmission efficiency w represents the transmission efficiency of bit information on each edge 3. When source node 2 is not firing, the firing bit of source node 2 is "0", so "0" is input to destination node 2.

The information transmission efficiency w of edge 3 has the property of changing depending on the firing timing of both end nodes 2 of edge 3, i.e., the difference in firing time, between the starting node 2 and the ending node 2. Furthermore, the information transmission efficiency w of edge 3 may have the property of changing depending on the instructions of the edge information transmission efficiency change unit 5A (see Figure 3), which will be explained later. The property of the information transmission efficiency w changing depending on the firing timing of both end nodes 2 is called the "plasticity of edge 3."

The change in information transmission efficiency w due to the firing timing of the end nodes 2 is determined by which of the end nodes 2 fires first, and the positive or negative sign representing the increase or decrease in information transmission efficiency w is determined by the magnitude of the difference in firing times of the end nodes 2.

When multiple nodes 2 fire by providing input to a network 1 such as that shown in Figure 1, in which nodes 2 are fully or randomly connected, the information transmission efficiency w of edges 3 is autonomously strengthened or weakened due to the plasticity of edges 3. A group of nodes that are strongly connected due to changes in the information transmission efficiency w of edges 3 is defined as a "node assembly 4." The measure of the strength of the connections in a node group is time. A threshold time (e.g., 10 ms) is set as a measure of the strength of the connections in a node group, and the node assembly 4 is the set of all nodes 2 that fire within the threshold time from a specific time and are connected to other nodes 2 by a single edge 3.

Figure 2 is a diagram showing an example of a node assembly 4. In network 1 in Figure 2, a node assembly 4 is a set of nodes 2 connected by edges 3 that are thicker than the other edges 3. A state in which one or more nodes 2 in a node assembly 4 are firing is expressed as "node assembly 4 is activated." When multiple inputs are repeatedly input to network 1, node assemblies 4 that are likely to be activated in response to specific inputs are generated. The node assemblies 4 generated in this way represent concepts related to input.

Figure 3 shows an example functional configuration of an information processing device 5 that generates such a node assembly 4.

The information processing device 5 includes an edge information transmission efficiency change unit 5A, a reward evaluation unit 5B, an edge selection unit 5C, an external input unit 5D, and a memory unit 5E.

Network 1 is stored in memory unit 5E, and edge information transmission efficiency change unit 5A changes the information transmission efficiency w of edge 3 selected by edge selection unit 5C (described later) in accordance with the reward evaluation result evaluated by reward evaluation unit 5B.

The reward evaluation unit 5B evaluates the degree of match between the contents of the output bit string generated by arranging firing bits representing the firing states at a predetermined number of nodes 2 included in the network 1 and the contents of the expected output bit string as a reward, and notifies the edge information transmission efficiency change unit 5A of the reward evaluation result.

The edge selection unit 5C selects edges 3 from the network 1 whose information transmission efficiency w is changed by the edge information transmission efficiency modification unit 5A. There are two methods for selecting edges 3 in the edge selection unit 5C. The first is a selection method that selects all edges 3 included in the network 1. The second is a selection method that prioritizes the selection of edges 3 whose evaluation time at which the reward is evaluated by the reward evaluation unit 5B is closer to the firing time of the connected node 2. Specifically, from nodes 2 that are in an firing state at a judgment time that is a predetermined time away from the evaluation time at which the reward is evaluated by the reward evaluation unit 5B, all edges 3 that input bit information to each node 2 selected according to a predetermined probability are selected. The edge selection method in the edge selection unit 5C will be explained in detail later.

The external input unit 5D inputs bit information from outside the network 1 to at least one node 2 of the network 1.

On the other hand, the node assembly 4 illustrated in Figure 2 not only receives input, but also outputs bit information to other nodes 2. Therefore, the information transmission efficiency w of edge 3 may change depending on the input from outside network 1 via external input unit 5D and the input from node assembly 4 within network 1, resulting in the generation of a new node assembly 4. The newly generated node assembly 4 represents a concept that combines the concept represented by the input from outside network 1 with a concept related to the concept represented by node assembly 4 within network 1. In other words, the concept represented by the newly generated node assembly 4 is a new concept that is different from both the concept represented by the input from outside network 1 and the concept represented by node assembly 4 within network 1. In this way, the node assembly 4 generates its own concept.

Furthermore, after a node assembly 4 is generated, the information transmission efficiency w of edge 3 may change due to input from outside network 1 via external input unit 5D and input from other node assemblies 4 within network 1, i.e., existing node assemblies 4, and the number of nodes included in the existing node assembly 4 may change. Such events represent the expansion or contraction of the concept of the existing node assembly 4. The expansion or contraction of concepts helps to change concepts and create new concepts.

When network 1 includes a recursive circuit, node 2 within network 1 may continue to fire solely through input from within network 1, without any external input. Here, a "recursive circuit" refers to a closed circuit formed by nodes 2 connected in a circular fashion by edges 3. A state in which node 2 continues to fire without external input is referred to as "network 1 running on its own." There may be multiple paths by which node 2 continues to fire. As network 1 continues to run on its own, the activity of multiple node assemblies 4 within network 1, such as the first node assembly 4 and the second node assembly 4, may change the information transmission efficiency w of edge 3, resulting in the creation of a new node assembly 4 within network 1. The concept represented by this new node assembly 4 is a new concept different from both the concept represented by the first node assembly 4 and the concept represented by the second node assembly 4. In this way, node assembly 4 generates a new concept without external input from network 1. This mechanism works similarly to how the human brain can make new discoveries and inventions while asleep.

As network 1 continues to operate independently, the information transmission efficiency w of edges 3 connecting nodes 2 may change, and the boundaries of existing node assemblies 4 may change. This situation indicates that the concepts represented by existing node assemblies 4 expand or contract. The expansion or contraction of concepts helps to change concepts and create new concepts. Therefore, concepts expand or contract without input from outside network 1, and new concepts are created.

Furthermore, if input is continuously provided to Network 1 and Network 1 continues to run on its own during periods when there is no input, it is probabilistic that Network 1 will begin to acquire the intelligence to acquire new concepts. This is because the history of evolution of life has proven that if a large number of trials are performed on Network 1, a Network 1 that has acquired intelligence can be obtained in some of the trials. In order to increase the probability that Network 1 will be intelligent, for example, the information transmission efficiency w of Edge 3 can be changed using rewards. For example, by increasing the information transmission efficiency w of Edge 3 using rewards, it becomes more likely that node assemblies 4 will be generated in a direction that increases rewards. As the probability of generating node assemblies 4 increases, the probability of concepts emerging and the probability of complex relationships between concepts emerging also increase. In other words, the probability that Network 1 will be intelligent increases.

In known reinforcement learning artificial neural networks, after the reward and input generation rules are taught to the reinforcement learning artificial neural network, it operates without any input from outside network 1. Therefore, like node assembly 4 of the present disclosure, reinforcement learning artificial neural networks can be said to operate without any input from outside network 1 on the surface, but reinforcement learning artificial neural networks can only perform operations that maximize the taught reward. Furthermore, reinforcement learning artificial neural networks cannot create new inputs that deviate from the input generation rules. In other words, reinforcement learning artificial neural networks cannot generate rewards based on different definitions, nor can they come up with new ideas that go beyond the input generation rules, i.e., discover solutions outside the expected solution space. Therefore, node assembly 4 of the present disclosure differs from known reinforcement learning artificial neural networks in its ability to define new rewards and discover solutions that are not bound by the existing solution space.

Next, an example hardware configuration of the information processing device 5 of the present disclosure will be described. Figure 4 is a block diagram showing an example hardware configuration of the information processing device 5. As shown in Figure 4, the information processing device 5 is configured using a computer 10, and includes a CPU (Central Processing Unit) 11, which is an example of a processor, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, a non-volatile memory 14, and an input/output interface (I/O) 15. The CPU 11, ROM 12, RAM 13, non-volatile memory 14, and I/O 15 are each connected via a bus 16.

Non-volatile memory 14 is an example of a storage device that maintains stored information even if the power supplied to non-volatile memory 14 is cut off. For example, semiconductor memory is used, but a hard disk may also be used. Network 1, for example, is stored in non-volatile memory 14.

For example, a communication unit 17, an input unit 18, and a display unit 19 are connected to the I/O 15.

The communication unit 17 is connected to a communication line and is equipped with a communication protocol for data communication with an external device (not shown). For data communication, a wired communication standard such as Ethernet (registered trademark) or FDDI, or a wireless communication standard such as 4G, 5G, or Wi-Fi (registered trademark) is used.

The input unit 18 is an example of a unit that accepts user operations and notifies the CPU 11, and includes, for example, buttons, touch panels, keyboards, mice, and pointing devices.

The display unit 19 is an example of a unit that visually displays information processed by the CPU 11, and includes, for example, an LCD display and an organic EL (Electro Luminescence) display.

Note that the communication unit 17, input unit 18, and display unit 19 do not necessarily need to be connected to I/O 15, but can be connected to I/O 15 as needed.

Next, we will explain the function of the node assembly 4 generated by the information processing device 5.

Figure 5 is a flowchart showing an example of the process flow for generating node assembly 4.

The node assembly generation program that defines the process for generating the node assembly 4 is pre-stored, for example, in the ROM 12 of the information processing device 5. The CPU 11 of the information processing device 5 reads the node assembly generation program stored in the ROM 12 and executes the process for generating the node assembly 4. Note that the non-volatile memory 14 stores the network 1 before the node assembly 4 is generated, as shown in Figure 1. For ease of explanation, input from outside the network 1 will be referred to as "external input."

When bit information is input from external input unit 5D to edge 3 of network 1, the bit information flows to edge 3, causing node 2 to fire.

Therefore, in step S10, the CPU 11 updates the information transmission efficiency w of each edge 3 depending on the firing order of the end nodes 2 and the magnitude of the difference between the firing times of the end nodes 2.

In this way, when both end nodes 2 connected by an edge 3 fire, the information transmission efficiency w of the edge 3 changes. Changes in the information transmission efficiency w include changes in which the information transmission efficiency w increases and changes in which the information transmission efficiency w decreases. As the number of edges 3 with increased information transmission efficiency w increases, nodes 2 that fire in sync become more likely to occur. Here, "nodes 2 firing in sync" means that multiple nodes 2 fire within a threshold time from a specific time. As already explained, nodes 2 that fire in sync constitute a node assembly 4.

Therefore, in step S20, the CPU 11 determines whether a node assembly 4 has been generated in the network 1. If a node assembly 4 has not been generated, the CPU 11 repeatedly executes the determination process of step S20 while repeatedly inputting bit information into the network 1 from within and outside the network 1, thereby monitoring the generation status of the node assembly 4. On the other hand, if a node assembly 4 has been generated, the CPU 11 proceeds to step S30.

In step S30, the CPU 11 determines whether an end instruction has been received from the user, for example, via the input unit 18. If an end instruction has been received, the process of generating the node assembly 4 shown in Figure 5 is terminated. In this case, a node assembly 4 representing the concept of input as shown in Figure 2 is obtained.

On the other hand, if the judgment process of step S30 determines that an end instruction has not been received from the user, the process proceeds to step S40.

Further bit information is input from within and outside network 1 to edges 3 connected to nodes 2 included in node assembly 4, and as network 1 progresses in learning, a node assembly 4 that constitutes a recursive circuit may be generated.

Figure 6 shows an example of node assemblies 4 that make up a recursive circuit. Each node assembly 4 is connected by an edge 3. The edge 3 connecting two node assemblies 4 does not necessarily have to be one; multiple edges are possible. There are no restrictions on the starting node 2 of one node assembly 4 and the ending node 2 of the other node assembly 4 connected by the edge 3; any node 2 within each node assembly 4 can be connected.

In this way, a network 1 that includes multiple node assemblies 4 and at least one edge 3 that connects the node assemblies 4 together by connecting any of the nodes 2 included in the node assemblies 4, and that forms at least one recursive circuit in which the multiple node assemblies 4 are connected in a circular fashion by the edges 3, is called a "concept sequencer 6."

In addition, the concept sequencer 6 may include node assemblies 4 that do not form recursive circuits.

Figure 7 shows an example of a conceptual sequencer 6 that includes a node assembly 4 that does not form a recursive circuit. In Figure 7, node assembly 4A is a node assembly 4 that does not form a recursive circuit.

In step S40 of Figure 5, the CPU 11 determines whether such a concept sequencer 6 has been generated. If a concept sequencer 6 has not been generated, the CPU 11 repeatedly executes the determination process of step S40 while repeatedly inputting bit information into the network 1 from within the network 1 and from outside the network 1, thereby monitoring the generation status of the concept sequencer 6. On the other hand, if a concept sequencer 6 has been generated, the CPU 11 proceeds to step S50.

In step S50, the CPU 11 determines whether an end instruction has been received from the user, for example, via the input unit 18. If an end instruction has been received, the process of generating the node assembly 4 shown in Figure 5 is terminated. In this case, a concept sequencer 6 is obtained that changes the concept represented by the node assembly 4 and generates a new concept.

On the other hand, if the judgment process in step S50 determines that an end instruction has not been received from the user, the process proceeds to step S60.

Naturally, not all nodes 2 in network 1 are necessarily included in any node assembly 4, so there are nodes 2 around the concept sequencer 6 that do not constitute a node assembly 4. Therefore, as bit information is repeatedly input to network 1 from within and outside network 1, and nodes 2 that were not previously included in a node assembly 4 begin to form a node assembly 4, a new recursive circuit may be generated.

Figure 8 shows an example of a conceptual sequencer 6 equipped with multiple recursive circuits. The example conceptual sequencer 6 shown in Figure 8 includes two recursive circuits: recursive circuit A and recursive circuit B.

In step S60 of Figure 5, the CPU 11 determines whether a concept sequencer 6 including multiple recursive circuits has been generated. If a concept sequencer 6 including multiple recursive circuits has not been generated, the CPU 11 repeatedly executes the determination process of step S60 while repeatedly inputting bit information into network 1 from within network 1 and from outside network 1, thereby monitoring the generation status of the concept sequencer 6 including multiple recursive circuits. On the other hand, if a concept sequencer 6 including multiple recursive circuits has been generated, the generation process of the node assembly 4 shown in Figure 5 is terminated. In this case, a concept sequencer 6 is obtained that generates a new concept different from the concept sequencer 6 including one recursive circuit shown in Figures 6 and 7.

This process of generating node assemblies 4 may result in the generation of multiple concept sequencers 6 within the network 1. The multiple generated concept sequencers 6 are connected to each other by edges 3, and exchange bit information. External inputs are also input to the concept sequencer 6 on an irregular or regular basis. Therefore, these inputs cause the information transmission efficiency w of the edges 3 included in the concept sequencer 6 to change in a complex manner. As a result, the node assembly 4 expands, contracts, or splits into multiple pieces, generating new concept sequencer 6 paths. As concepts expand and contract in the concept sequencer 6, the concept sequencer 6 grows autonomously and new concepts are created. In other words, the concept sequencer 6 can be a source of advanced intelligence.

We will explain how the concept sequencer 6 generated in this way can recall memories without external input, i.e., can recall memories.

Figure 9 shows an example of a network 1 including at least one concept sequencer 6, a node assembly 4C that accepts input from any one of the node assemblies 4 (referred to as "node assembly 4B") that constitute the concept sequencer 6, and an edge 3 that inputs external input to the node assembly 4C.

In Network 1, assume that an external input and an input from Node Assembly 4B are input to Node Assembly 4C, activating Node Assembly 4C. In this case, Node Assembly 4C memorizes the memory of the external input. After this, Network 1 operates, and the information transmission efficiency w of Edge 3 changes. Eventually, the information transmission efficiency w of Edge 3 within Node Assembly 4C is strengthened, and Node Assembly 4C becomes activated by input from Node Assembly 4B alone, without any external input. In this way, memory recall without external input is achieved in Node Assembly 4C.

Figure 10 shows an example of a conceptual sequencer 6 that recalls memories without external input for the network 1 shown in Figure 9. The conceptual sequencer 6 shown in Figure 10 includes a node assembly 4C that recalls memories using only input from a node assembly 4B.

Next, we will explain how changes in the threshold time that affect the generation of node assembly 4 change the concepts stored by node assembly 4.

For example, if a node assembly 4 (referred to as the "former node assembly 4") is generated when the threshold time is set to 10 ms, and a node assembly 4 (referred to as the "latter node assembly 4") is generated when the threshold time is set to 15 ms, the number of nodes constituting the latter node assembly 4 will be greater. While it is probabilistic that the number of nodes constituting each node assembly 4 will be the same for the former node assembly 4 and the latter node assembly 4, we will assume here that the number of nodes constituting the latter node assembly 4 is greater than the number of nodes constituting the former node assembly 4. Therefore, for example, the former node assembly 4 represents the concept of "sea fish," while the latter node assembly 4 represents the concept of "sea creatures," which is a broader concept than "sea fish."

When Network 1 is operating, there is no need to fix the threshold time that affects the generation of Node Assembly 4. There are situations where the concept of "sea fish" produces useful output in one situation, and the concept of "sea creatures" produces useful output in another situation. The Concept Sequencer 6 is not restricted to using only one concept, and can use both concepts. In this case, Network 1 itself is not aware of the switching of threshold times, and the CPU 11 virtually uses multiple threshold times, creating a state in which the Concept Sequencer 6 is simultaneously recalling multiple concepts.

Next, we will explain the growth process that encourages the growth of the node assembly 4 and concept sequencer 6 by rewarding the network 1.

Figure 11 is a flowchart showing an example of the growth process flow.

The node assembly generation program that defines the growth process is pre-stored, for example, in the ROM 12 of the information processing device 5. The CPU 11 of the information processing device 5 reads the node assembly generation program stored in the ROM 12 and executes the growth process.

It is assumed that network 1 is stored in non-volatile memory 14. Network 1 may include at least one of node assembly 4 and concept sequencer 6. External input may also be input to network 1. Specifically, if network 1 includes node assembly 4, external input may be input to edge 3 connected to node 2 included in node assembly 4.

First, in step S100, the CPU 11 generates an output bit string, which is a bit string consisting of firing bits representing the firing state of a predetermined number of nodes 2 (also called a "node group") included in the network 1.

In step S110, CPU 11 evaluates the degree of match between the contents of a predetermined expected output bit string and the contents of the output bit string generated in step S100 as a reward. In this case, CPU 11 increases the value of the reward, for example, the higher the degree of match between the contents of the output bit string and the contents of the expected output bit string. Examples of the contents of the expected output bit string include maximizing and minimizing the physical quantity represented by the output bit string, and maximizing and minimizing the amount of information represented by the output bit string.

In step S120, the CPU 11 selects an edge 3 from the network 1 that changes the information transmission efficiency w. As already explained, there are two methods for selecting an edge 3.

The first is a selection method that selects all edges 3 included in network 1. The second is a selection method that selects all edges 3 that input bit information to each node 2 selected according to a predetermined probability from nodes 2 that are in an firing state at a judgment time that is a predetermined time away from the evaluation time of the reward evaluated by the processing of step S110. The CPU 11 selects edges 3 from network 1 that change the information transmission efficiency w using the selection method selected by the user.

The second selection method will be explained in detail. Assume that CPU 11 evaluates the reward at network time t through the processing of step S110. Note that the granularity Δt, which represents the minimum time measurement capability of CPU 11, is predetermined. There are no restrictions on the time granularity Δt, but it may be 1 ms, for example. Furthermore, let variable n be a natural number, and function f(x) be any monotonically decreasing real function that takes values between 0 and 100, with natural number x as an explanatory variable. CPU 11 randomly selects f(n) percent of nodes 2 from among the nodes 2 that fired at network time t-nΔt. Then, CPU 11 selects all edges 3 that input bit information to each of the selected nodes 2. Network time t-nΔt is an example of a judgment time; for example, f(n) percent of nodes 2 may be randomly selected from the nodes 2 that fired at network time t+nΔt.

In step S130, the CPU 11 updates the information transmission efficiency w of the edge 3 selected from the network 1 by the processing of step S120, depending on the evaluation result of the reward evaluated by the processing of step S110. Specifically, the larger the reward value, the more the CPU 11 increases the information transmission efficiency w of the selected edge 3, and the smaller the reward value, the more the CPU 11 decreases the information transmission efficiency w of the selected edge 3.

This completes the growth process shown in Figure 11. Through the growth process, the node assembly 4 and concept sequencer 6 grow so as to increase the reward.

In this way, the node assembly 4 and concept sequencer 6 of the present disclosure store concepts in response to input, and change the stored concepts to generate new concepts. Furthermore, the node assembly 4 and concept sequencer 6 of the present disclosure can change the stored concepts to generate new concepts even without external input.

The above describes one embodiment of the node assembly 4 and concept sequencer 6, but the disclosed method of generating the node assembly 4 and concept sequencer 6 is merely an example and is not limited to the scope described in the embodiment. Various modifications or improvements can be made to the embodiment without departing from the spirit of this disclosure, and forms incorporating such modifications or improvements are also included in the technical scope of the disclosure. For example, the internal processing order of each process shown in Figures 5 and 11 may be changed without departing from the spirit of this disclosure.

In addition, this disclosure has described, as an example, a form in which the processes shown in Figures 5 and 11 are implemented by software. However, processes equivalent to the flowcharts of the processes shown in Figures 5 and 11 may also be implemented in, for example, an ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), or PLD (Programmable Logic Device) and processed by hardware. In this case, processing can be performed faster than when the processes are implemented by software.

In this way, the CPU 11 of the information processing device 5 may be replaced with a dedicated processor specialized for specific processing, such as an ASIC, FPGA, PLD, GPU (Graphics Processing Unit), and FPU (Floating Point Unit).

The generation process and growth process of the node assembly 4 may be performed by a single CPU 11, or by a combination of two or more processors of the same or different types, such as multiple CPUs 11, or a combination of a CPU 11 and an FPGA.

Furthermore, the generation and growth processes of the node assembly 4 may be realized through the cooperation of processors located in physically separate locations, for example connected via the Internet.

Furthermore, in the embodiment, an example has been described in which the node assembly generation program is stored in ROM 12 of the information processing device 5, but the storage location of the node assembly generation program is not limited to ROM 12. The node assembly generation program of the present disclosure can also be provided in a form recorded on a storage medium readable by the computer 10. For example, the node assembly generation program may be provided in a form recorded on an optical disc such as a CD-ROM (Compact Disk Read Only Memory) or a DVD-ROM (Digital Versatile Disk Read Only Memory). The node assembly generation program may also be provided in a form recorded on portable semiconductor memory such as a USB (Universal Serial Bus) memory or a memory card.

ROM 12, non-volatile memory 14, CD-ROM, DVD-ROM, USB, and memory cards are examples of non-transitory storage media.

Furthermore, the information processing device 5 may download a node assembly generation program from an external device via the communication unit 17 and store the downloaded node assembly generation program, for example, in non-volatile memory 14. In this case, the information processing device 5 reads the node assembly generation program downloaded from the external device and executes the generation process and growth process of the node assembly 4.

Claims (6)

A node assembly used by a computer having an external input unit, an edge information transmission efficiency change unit, an edge selection unit, and a storage unit, the node assembly including at least one or more nodes connected by at least one or more edges transmitting bit information, the node assembly being configured as a network stored in the storage unit ,
the internal state of each of the nodes is expressed by the sum of a predetermined function, which is a value that numerically represents the internal state of the node and is expressed by a potential that affects the firing state of the node and time, and the sum of input values input to each of the nodes from all of the connected edges;
The external state of each of the nodes is determined to be a firing state or a non-firing state by comparing the potential with a predetermined firing threshold;
When the external input unit inputs bit information to the network in which the edge selection unit changes the information transmission efficiency representing the transmission efficiency of bit information at each edge selected from the network by the edge information transmission efficiency change unit in accordance with the difference in firing time at each node connected to both ends of the edge, the network is configured of all nodes that are connected to other nodes other than itself by one edge among the nodes that have fired within a predetermined threshold time from a specific time.
Node assembly. a plurality of the node assemblies according to claim 1; and at least one or more of the edges connecting the node assemblies together by connecting any of the nodes included in each of the node assemblies;
A closed circuit is generated when the external input unit continues to input bit information to the edges connected to the nodes that make up the node assembly even after the node assembly is generated, and the network includes at least one recursive circuit in which a plurality of the node assemblies are connected in a circular fashion by the edges.
Concept sequencer. The computer further includes a reward evaluation unit;
the reward evaluation unit evaluates, as a reward, a degree of match between a content of a bit string generated by arranging outputs representing firing states of a predetermined number of the nodes included in the network and an expected content;
The concept sequencer according to claim 2 , wherein the edge information transmission efficiency change unit updates the information transmission efficiency of the edge pre- selected from the network by the edge selection unit according to the evaluation result of the reward. The edge selection unit selects, as the edge to be subject to change in information transmission efficiency, any of all the edges included in the network or all the edges that input bit information to each of the nodes selected according to a predetermined probability from the nodes that are in an ignition state at a judgment time that is a predetermined time away from the evaluation time at which the reward is evaluated.
4. The concept sequencer of claim 3 . In a network including at least one node connected by at least one edge carrying bit information,
The internal state of each of the nodes is represented by the sum of a predetermined function, which is a value that numerically represents the internal state of the node and is represented by potentials that affect the firing state of the node and time, and the sum of input values input to each of the nodes from all of the connected edges;
determining an external state of each of the nodes as a firing state or a non-firing state by comparing the potential with a predetermined firing threshold;
A node assembly generation program that causes a computer to execute a process of generating a node assembly that includes all nodes that are connected to other nodes other than itself by a single edge, among the nodes that have fired within a predetermined threshold time from a specific time, by changing the information transmission efficiency that represents the transmission efficiency of bit information on each edge according to the difference in firing time at each node connected to both ends of the edge. In a network including at least one node connected by at least one edge carrying bit information,
The internal state of each of the nodes is represented by the sum of a predetermined function, which is a value that numerically represents the internal state of the node and is represented by potentials that affect the firing state of the node and time, and the sum of input values input to each of the nodes from all of the connected edges;
determining an external state of each of the nodes as a firing state or a non-firing state by comparing the potential with a predetermined firing threshold;
A node assembly generation method in which a computer executes a process to generate a node assembly including all nodes that are connected to other nodes by a single edge, among the nodes that have fired within a predetermined threshold time from a specific time, by changing the information transmission efficiency, which represents the transmission efficiency of bit information on each edge, according to the difference in firing time at each node connected to both ends of the edge.