JP7794082B2 - Semiconductor Devices - Google Patents

Description

The present invention relates to a semiconductor device.

For example, Patent Document 1 discloses an in-vehicle semiconductor device that blocks current flowing in the reverse direction through a ground terminal when the battery electrodes are connected in reverse (hereinafter referred to as "reverse connection").

Japanese Patent Application Laid-Open No. 2002-95159

However, with the semiconductor device described in Patent Document 1, if the battery is connected in reverse, there is a risk that current will flow through the terminal connected to the load.

The present invention was made in consideration of the above-mentioned problems with the conventional technology, and its purpose is to provide a semiconductor device that can cut off the current that flows when a battery is connected in reverse.

The semiconductor device of the present invention, which solves the above-mentioned problems, comprises a first terminal to which a first voltage is applied, a second terminal to which a second voltage lower than the first voltage is applied, a third terminal to which a load is connected, a first diode having an anode connected to the first terminal, a first MOS transistor having a source electrode connected to the third terminal and a drain electrode connected to the cathode of the first diode, a drive circuit that controls the on/off of the first MOS transistor, a second diode having a cathode connected to the second terminal and an anode connected to the drive circuit, and a third diode having a cathode connected to a node connecting the third terminal and the source electrode of the first MOS transistor and an anode connected to the drive circuit.

The present invention provides a semiconductor device that can cut off current when a battery is connected in reverse.

FIG. 1 is a diagram illustrating a configuration of a motor control device 10. FIG. 2 is a diagram illustrating a configuration of a power supply circuit 51. 2 is a diagram for explaining a semiconductor substrate 200 on which a control IC 50 is formed. FIG. FIG. 10 is a diagram showing the configuration of a diode D3. FIG. 10 is an explanatory diagram of a comparative example in which the battery 1 is reversely connected. FIG. 6A is an explanatory diagram of a motor control device 10A and an ECU 300 of a comparative example, and FIG. 6B is an explanatory diagram of blocking of a reverse current in the comparative example. FIG. 2 is an explanatory diagram illustrating a case where the battery 1 is reversely connected in this embodiment. FIG. 10 is an explanatory diagram of a modified example (IPS31) of IPS30.

At least the following points become clear from the description in this specification and the accompanying drawings.

== ...
FIG. 1 is a diagram showing the configuration of a motor control device 10 according to an embodiment of the present invention.
The motor control device 10 of this embodiment is a device for controlling a load (here, a motor 12) provided in an automobile using power from a battery 1. The motor control device 10 includes a microcomputer 20 and an IPS (Intelligent Power Switch) 30. Although not shown, the automobile also includes an electronic control unit (ECU) and other components that control the motor control device 10 using power from the battery 1.

Battery 1 is, for example, a lithium-ion battery for use in an automobile, and outputs a voltage Vcc (e.g., 12 V). Note that voltage Vcc corresponds to the "first voltage." The voltage on the negative electrode of battery 1 is a voltage Vgnd (e.g., 0 V) lower than voltage Vcc, and corresponds to the "second voltage."

The microcomputer 20 controls the IPS 30 based on instructions (not shown) input from the outside (e.g., an ECU). Specifically, the microcomputer 20 outputs an instruction signal Sa for controlling (controlling the on/off of) the NMOS transistors M1 and M2 of the IPS 30, which will be described later.

IPS 30 is a "semiconductor device" that switches whether or not the battery 1 voltage Vcc is supplied to the motor 12, which is a load, based on an instruction signal Sa output from the microcomputer 20.

Furthermore, as will be described in detail later, the IPS 30 of this embodiment appropriately protects the motor 12 and ECU when the battery 1 is connected in reverse. Note that "reverse connection" refers to a state in which the electrodes of the battery 1 are connected in reverse. Specifically, this refers to a state in which the positive electrode of the battery 1 is connected to the ground terminal (e.g., terminals C and D) and the negative electrode of the battery 1 is connected to the power supply terminal (e.g., terminal A).

<<<Configuration of IPS30>>>
The IPS 30 includes an IC (Integrated Circuit) 40 in which a switch X1 (described later) is formed, and a control IC 50 that controls the on/off of the switch X1. The IC 40 corresponds to a "first chip," and the control IC 50 corresponds to a "second chip."

The IPS 30 of this embodiment also has terminals A to D, and is equipped with a package capable of housing the IC 40 and control IC 50. As a result, the IC 40, control IC 50, and terminals A to D are integrated into the IPS 30 (configured as a single semiconductor module). Note that the IC 40 and control IC 50 also have terminals, but in this embodiment, for simplicity, the terminals of the IC 40 and control IC 50 are not shown.

Terminal A is connected to the positive electrode of battery 1 and is supplied with the power supply voltage (voltage Vcc).

Terminal B is a signal input terminal, and in this embodiment, an instruction signal Sa is input from the microcontroller 20.

Terminal C is connected to the negative electrode of battery 1 and is connected to the ground voltage (voltage Vgnd).

Terminal D is connected to the motor 12, which serves as a load, and is also connected to the negative pole of battery 1 via motor 12. As a result, when NMOS transistors M1 and M2 are off, terminal D is grounded via the coil (not shown) of motor 12.

In the IPS 30 of this embodiment, terminal A corresponds to the "first terminal," terminal C corresponds to the "second terminal," and terminal D corresponds to the "third terminal."

<<About IC40>>
The IC 40 is an integrated circuit including two MOS transistors that constitute a switch (hereinafter referred to as a "switch X1") for switching whether or not the voltage Vcc applied to the terminal A is output from the terminal D. In this embodiment, the two MOS transistors are NMOS transistors M1 and M2.

The source electrode of NMOS transistor M1 is connected to terminal D, to which a load (here, motor 12) is connected. In this embodiment, "connection" means electrical connection. For example, an element (such as a resistor) or terminal may be provided along the wiring (line) that makes the connection. Specifically, IC40 is provided with a terminal (not shown) that is connected to the source electrode of NMOS transistor M1, and the source electrode of NMOS transistor M1 is connected to terminal D via that terminal (terminal of IC40).

The drain electrode of NMOS transistor M1 is connected to the drain electrode of NMOS transistor M2. A diode 41 (parasitic diode) is formed between the source and drain electrodes of NMOS transistor M1 as a body diode. A drive voltage Vcp is applied to the gate electrode of NMOS transistor M1 from drive circuit 52 (described below). NMOS transistor M1 corresponds to the "first MOS transistor."

The source electrode of NMOS transistor M2 is connected to terminal A, to which the power supply voltage Vcc is applied.

In addition, a diode 42 is formed as a body diode (parasitic diode) between the source electrode and drain electrode of NMOS transistor M2. A drive voltage Vcp is applied to the gate electrode of NMOS transistor M2 from drive circuit 52 (described below). Note that NMOS transistor M2 corresponds to the "third MOS transistor," and diode 42 corresponds to the "first diode."

Here, the drain electrodes of NMOS transistors M1 and M2 are connected in series, the source electrode of NMOS transistor M1 is connected to terminal D, and the source electrode of NMOS transistor M2 is connected to terminal A. Therefore, when NMOS transistors M1 and M2 are both turned on, the voltage Vcc applied to terminal A is output from terminal D via NMOS transistors M1 and M2.

The anode of diode 42 is connected to terminal A, and the cathode of diode 42 is connected to the cathode of diode 41. The anode of diode 41 is connected to terminal D. Therefore, the cathodes of diodes 41 and 42, which are provided between terminals A and D, are connected facing each other.

Therefore, when both NMOS transistors M1 and M2 are off, for example, the voltage Vcc applied to terminal A is blocked by diode 41. On the other hand, when battery 1 is connected in reverse and voltage Vcc is applied to terminal D, for example, the voltage at terminal D (here, voltage Vcc) is blocked by diode 42.

As a result, when both NMOS transistors M1 and M2 are off, switch X1 can cut off the current in the path between motor 12, terminal D, and terminal A.

<<Regarding the Control IC 50>>
The control IC 50 turns the switch X1 on and off (in other words, controls the on and off of the NMOS transistors M1 and M2) based on the instruction signal Sa. The control IC 50 includes a power supply circuit 51, a drive circuit 52, an NMOS transistor M3, and diodes D1 to D6. Of the diodes D1 to D6, the diodes D1 and D2 are parasitic diodes in the control IC 50, but are shown here for convenience.

<Power circuit 51>
The power supply circuit 51 is a circuit that generates a power supply voltage Vdd to operate circuits such as the drive circuit 52. The power supply circuit 51 generates the power supply voltage Vdd when the switch X1 (NMOS transistors M1 and M2) is turned on, and stops generating the power supply voltage Vdd when the switch X1 is turned off.

Figure 2 shows an example of the configuration of the power supply circuit 51. The power supply circuit 51 shown in Figure 2 includes a PMOS transistor M4, NMOS transistors M5 and M6, and a diode 60.

A voltage Vcc is applied to the source electrode of PMOS transistor M4, and its drain electrode is connected to the drain of NMOS transistor M5. An instruction signal Sa from microcomputer 20 is applied to the gate electrode of PMOS transistor M4. PMOS transistor M4 turns on when instruction signal Sa is a signal instructing switch X1 to turn on, and turns off when instruction signal Sa is a signal instructing switch X1 to turn off.

NMOS transistor M5 is a transistor provided for current suppression. It is a depletion-type MOS transistor whose gate electrode and source electrode are connected and which is always on.

The cathode of diode 60 is connected to the source electrode of NMOS transistor M5 and the gate electrode of NMOS transistor M6, and the anode is grounded. Diode 60 is a Zener diode, and when the voltage (reverse voltage) applied from the cathode to the anode exceeds a certain voltage, current begins to flow, controlling the voltage of the gate electrode of NMOS transistor M6 to that certain voltage.

The drain electrode of NMOS transistor M6 is connected to the source electrode of PMOS transistor M4, and the voltage at the source electrode of NMOS transistor M6 becomes the output of power supply circuit 51.

With the above configuration, when PMOS transistor M4 turns on based on instruction signal Sa, a constant voltage determined by Zener diode D7 is applied to the gate electrode of NMOS transistor M6. This turns on NMOS transistor M6, and a power supply voltage Vdd (e.g., 5 V) that is the threshold voltage lower than the constant voltage is generated and output. This power supply voltage Vdd is applied to the gate of NMOS transistor M3 and is also supplied to circuits such as drive circuit 52.

On the other hand, when PMOS transistor M4 is turned off based on instruction signal Sa, no voltage is applied to the gate electrode of NMOS transistor M6, and NMOS transistor M6 is also turned off. As a result, the power supply voltage Vdd is no longer generated.

The configuration of the power supply circuit 51 is not limited to that described above. For example, a resistor may be used instead of the depletion-type NMOS transistor M5. Furthermore, for example, the circuit may generate the power supply voltage Vdd without using the voltage Vcc.

<Drive circuit 52>
The drive circuit 52 controls the on/off of the switch X1. When an instruction signal Sa instructing the switch X1 to be on is input, the drive circuit 52 applies a drive voltage Vcp to the gate electrodes of the NMOS transistors M1 and M2, thereby turning on the switch X1. The drive circuit 70 is a charge pump circuit that receives a power supply voltage Vdd and has a ground voltage (voltage Vgnd) as its reference potential. It boosts the power supply voltage Vdd to generate a drive voltage Vcp that can turn on the NMOS transistors M1 and M2. The configuration and operation of charge pump circuits are well known, so a description thereof will be omitted here. As shown in FIG. 2, the drive circuit 52 of this embodiment includes, for example, an NMOS transistor M100 as an element constituting the drive circuit 52.

<Diodes D1 and D2>
The diodes D1 and D2 are parasitic diodes formed by the semiconductor substrate of the control IC 50 and the circuitry within the control IC 50 (for example, the NMOS transistor M100 of the drive circuit 52).

Figure 3 is a diagram illustrating the semiconductor substrate 200 on which the control IC 50 is formed.

For convenience, Figure 3 shows only a portion of the control IC 50 circuitry necessary to explain diodes D1 and D2. Specifically, Figure 3 shows terminals A and C (D), the NMOS transistor M100 included in the drive circuit 52, and diode D1 (D2).

The semiconductor substrate 200 is, for example, an n-type substrate made of silicon, and on its front side are formed a power supply electrode 214 connected to terminal A, as well as a gate electrode 210, source electrode 211, drain electrode 212, and substrate electrode 213 of the NMOS transistor M100. The source electrode 211 and substrate electrode 213 are also connected to terminal C (D).

Note that each electrode of the NMOS transistor M100 and the power supply electrode 214 are formed from a conductive material such as polysilicon or a metal electrode.

The semiconductor substrate 200 contains a semiconductor region 220 formed by the semiconductor substrate 200, a p-type well region 230, a p+ type contact region 240, an n+ type source region 250, and an n+ type drain region 251. Hereinafter, when n+ type or p+ type is used, it means that the doping concentration is higher than that of n type or p type.

A well region 230 and a contact region 260 are formed on the front surface side of the semiconductor region 220. A power electrode 214 is formed on the front surface of the contact region 260.

The well region 230 is a region containing p-type impurities, and a contact region 240, a source region 250, and a drain region 251 are formed on the front surface side of the well region 230.

The substrate electrode 213 ("Bx") of the NMOS transistor M100 is formed in the contact region 240.

In addition, a source electrode 211 ("Sx") is formed in the source region 250, and a drain electrode 212 ("Dx") is formed in the drain region 251. A gate electrode 210 ("Gx") is formed on the front surface side of the well region 230 between the source region 250 and the drain region 251.

In this embodiment, terminal A is electrically connected to the semiconductor region 220 via the power electrode 214 and the contact region 260, and the substrate electrode 213 ("Bx") is also electrically connected to the well region 230 via the contact region 240.

In such a semiconductor substrate 200, a diode D1 (D2) is formed as a parasitic diode between the n-type semiconductor region 220 and the p-type well region 230.

If battery 1 is connected in reverse, terminal A will be grounded and voltage Vcc will be applied to terminal C (in the case of terminal D, voltage Vcc will be applied via the coil (not shown) of motor 12). Therefore, voltage Vcc will be applied to terminal C (D) and terminal A will be grounded, causing a "reverse current" to flow through the path from terminal C (D), diode D1 (D2), and terminal A (see Figure 5).

Note that, although the parasitic diodes D1 and D2 have been described here as being formed in the NMOS transistor M100 of the semiconductor substrate 200, this is not limited to this. For example, if the battery 1 is reverse-connected and the voltage of the p-type region of the semiconductor substrate 200 becomes higher than the voltage of the n-type region, a reverse current will flow.

<Diodes D3 and D4>
1 is a diode that allows current to flow from the drive circuit 52 to terminal C, and diode D4 is a diode that allows current to flow from the drive circuit 52 to terminal D. Furthermore, as will be described later, when the battery 1 is reverse-connected, diodes D3 and D4 block the current that flows from terminal C to the control IC 50 and the current that flows from terminal D to the control IC 50, respectively.

The anode of diode D3 is connected to drive circuit 52, and the cathode is connected to terminal C. Diode D3 corresponds to the "second diode."

The anode of diode D4 is connected to drive circuit 52, and the cathode is connected to node N1 (the node where terminal D and the source electrode of NMOS transistor M1 are connected). Diode D4 corresponds to the "third diode."

In this embodiment, diodes D3 and D4 are polysilicon diodes formed from polysilicon. Figure 4 shows an example of the configuration of diode D3. While Figure 4 shows diode D3, diode D4 has a similar configuration.

As shown in FIG. 4 , an insulating layer 281, such as a silicon oxide (SiO ₂ ) film, is formed on a well region 280 containing p-type impurities. An n-type polysilicon layer 282 and a p-type polysilicon layer 283 are selectively formed thereon. An interlayer insulating film 284 is further formed thereon, and openings are formed in the interlayer insulating film 284 above the n-type polysilicon layer 282 and the p-type polysilicon layer 283. The n-type polysilicon layer 282 and the p-type polysilicon layer 283 are in contact with each other to form a diode D3. Reference numeral 285 denotes a conductive wiring layer. The configuration of diodes D3 and D4 is not limited to the above. For example, a trench type may be used.

Diodes formed from the diffusion layer of a semiconductor substrate may operate unintendedly (allowing current to flow) due to parasitics, etc., whereas diodes D3 and D4 formed from polysilicon are highly reliable and can prevent current from flowing through unintended paths. In particular, when an inductive load is connected to terminal D, the voltage at terminal D can change significantly. Even in such cases, diode D4 can more reliably block reverse current.

Furthermore, it is desirable that the forward voltage of diode D3 be smaller (lower) than the forward voltage of the body diode (diode D5) of NMOS transistor M3, which will be described later. This prevents electrostatic damage to NMOS transistor M3 caused by static electricity or surge voltages being applied to the gate of NMOS transistor M3 (ESD protection).

<NMOS transistor M3>
The NMOS transistor M3 is arranged in parallel with the diode D3, with its drain electrode connected to the terminal C and its source electrode connected to the drive circuit 52. As described above, the output (power supply voltage Vdd) of the power supply circuit 51 is applied to its gate electrode.

When switch X1 is on, NMOS transistor M3 is turned on by applying power supply voltage Vdd to its gate electrode, resulting in a voltage being applied between its gate and drain. When switch X1 is off, NMOS transistor M3 is turned off because power supply voltage Vdd is not applied to its gate electrode. NMOS transistor M3 corresponds to the "second MOS transistor."

In addition, diode D5 is formed as a body diode (parasitic diode) in NMOS transistor M3. Diode D5 corresponds to the "second diode." In this embodiment, NMOS transistor M3 and diode D3 are connected in parallel, but if diode D5 (body diode) of NMOS transistor M3 can block reverse current, diode D3 may be unnecessary.

In addition, a gate protection diode D6 is provided between the gate electrode and drain electrode of NMOS transistor M3. The anode of diode D6 is connected to the drain electrode of NMOS transistor M3, and the cathode is connected to the gate electrode of NMOS transistor M3. Diode D6 is a Zener diode that clamps the voltage between the gate electrode and source electrode of NMOS transistor M3 at a predetermined voltage. Note that diode D6 is not necessarily required.

<<<<When Battery 1 is connected normally>>>
When the battery 1 is properly connected as shown in Figure 1, a voltage Vcc is applied to terminal A, and a voltage Vgnd (ground) is applied to terminal C. Terminal D is also grounded via the coil (not shown) of the motor 12.

When instruction signal Sa is a signal instructing switch X1 to be on, power supply circuit 51 generates power supply voltage Vdd, and drive circuit 52 operates based on power supply voltage Vdd to output drive voltage Vcp. When switch X1 (NMOS transistors M1 and M2) is turned on, a current based on battery 1 voltage Vcc is supplied to motor 12 via terminals A and D. Furthermore, power supply voltage Vdd generated by power supply circuit 51 is applied to the gate electrode of NMOS transistor M3, turning NMOS transistor M3 on.

On the other hand, if the instruction signal Sa is a signal instructing switch X1 to be turned off, PMOS transistor M4 and NMOS transistor M6 are turned off in the power supply circuit 51, and the power supply voltage Vdd is no longer generated. This stops the operation of the drive circuit 52, and switch X1 (NMOS transistors M1 and M2) is turned off. With switch X turned off, current based on the battery 1 voltage Vcc is no longer supplied to the motor 12 (motor 12 stops). Furthermore, since the power supply voltage Vdd is no longer generated in the power supply circuit 51, NMOS transistor M3 is also turned off.

<<<<When Battery 1 is connected in reverse>>>
A case where the battery 1 is reversely connected will be described below. Before describing this embodiment, a comparative example will be described first.

<<Comparative Example>>
Fig. 5 is an explanatory diagram of a comparative example in which the battery 1 is reversely connected. Fig. 6A is an explanatory diagram of a motor control device 10A and an ECU 300 of the comparative example, and Fig. 6B is an explanatory diagram of reverse current interruption in the comparative example. In the comparative example, parts having the same configuration as in this embodiment are assigned the same reference numerals and descriptions thereof will be omitted.

The motor control device 10A of the comparative example is equipped with an IPS 30A. The IPS 30A is equipped with a control IC 50A and an IC 40.

Control IC 50A differs from control IC 50 of this embodiment in that it does not include diodes D3 to D6 and NMOS transistor M3. Control IC 50A also includes resistor RG between drive circuit 52 and terminal C. Resistor RG is a current suppression resistor.

Also, as shown in FIG. 6A, an ECU 300 that controls the operation of the motor control device 10A is provided between the positive terminal of the battery 1 and the motor control device 10A.

As shown in Figures 5 and 6B, in the comparative example, when battery 1 is connected in reverse, voltage Vcc is applied to terminals C and D, and terminal A is grounded. This could result in current flowing along the path shown by the dashed dotted line. Of these, the current along the path battery 1 → motor 12 → terminal D → switch X1 → terminal A can be blocked by diode 42.

However, in the comparative example, reverse current flows through the path battery 1 → terminal C → resistor RG → diode D1 → terminal A, and the path battery 1 → motor 12 → terminal D → node N1 → diode D2 → terminal A. For this reason, in the comparative example, a protection circuit 301 is provided in the ECU 300, as shown in Figures 6A and 6B.

Protection circuit 301 is composed of, for example, a relay or fuse, and cuts off the current (reverse current) when a current flows in the reverse direction. Note that in this example, protection circuit 301 is provided within ECU 300, but this is not limited to this; for example, protection circuit 301 may be provided between ECU 300 and motor control device 10A. In this comparative example, it is thus necessary to provide a separate protection circuit 301 (relay, fuse, etc.) to protect ECU 300.

<<Present Embodiment>>
7 is an explanatory diagram of the case where the battery 1 is reverse-connected in this embodiment. Note that the figure only shows the IPS 30 of the motor control device 10, and the current path from the positive electrode of the battery 1 is indicated by a dashed line, as in the comparative example.

As shown in Figure 7, when battery 1 is reverse-connected, voltage Vcc is applied to terminals C and D, and terminal A is grounded. Here, the current in the path from battery 1 → motor 12 → terminal D → switch X1 → terminal A can be blocked by diode 42, just like in the comparative example.

Furthermore, in this embodiment, the current in the path from battery 1 → terminal C → diode D1 → terminal A can be blocked by diode D3 and diode D5 (the body diode of NMOS transistor M3).

In addition, the current flowing through the path Battery 1 → Motor 12 → Terminal D → Node N1 → Diode D2 → Terminal A can be blocked by Diode D4.

In this way, the motor control device 10 (IPS30) of this embodiment can block the current (reverse current) flowing into the control IC 50 via terminals C and D when the battery 1 is connected in reverse. Therefore, it is possible to protect the ECU and other devices from reverse current without providing a protection circuit 301 as in the comparative example.

===Summary===
The motor control device 10 including the IPS 30 of this embodiment has been described above. The IPS 30 includes a terminal A to which a voltage Vcc is applied, a terminal C to which a voltage Vgnd lower than the voltage Vcc is applied, and a terminal D to which the motor 12 is connected. The IPS 30 also includes a diode 42 having an anode connected to terminal A, an NMOS transistor M1 having a source electrode connected to terminal D and a drain electrode connected to the cathode of the diode 42, a drive circuit 52 that controls the on/off of the NMOS transistor M1, diodes D3 and D5 having a cathode connected to terminal C and an anode connected to the drive circuit 52, and a diode D4 having a cathode connected to a node N1 at which terminal D and the source electrode of the NMOS transistor M1 are connected and an anode connected to the drive circuit 52. This allows current (reverse current) flowing into the control IC 50 via terminals C and D to be blocked if the battery 1 is reverse-connected. Therefore, a protection circuit 301 (e.g., a fuse or relay) as in the comparative example is not required.

The IPS 30 also includes an NMOS transistor M3 whose drain electrode is connected to terminal C and whose source electrode is connected to the drive circuit 52, and diode D5 is the body diode of the NMOS transistor M3. As a result, if the battery 1 is reverse-connected, diode D5 can block the current (reverse current) flowing from terminal C.

In addition, NMOS transistor M3 is arranged in parallel with diode D3. This allows diode D3 to block the current (reverse current) flowing from terminal C if battery 1 is connected in reverse.

In addition, diode D3 is made of polysilicon, which prevents current from flowing through unintended paths and improves reliability.

In addition, the forward voltage of diode D3 is smaller than the forward voltage of the body diode (diode D5) of NMOS transistor M3. This provides ESD protection for NMOS transistor M3.

The IPS 30 also includes a power supply circuit 51 that generates a power supply voltage Vdd to operate the drive circuit 52 when the NMOS transistor M1 is turned on, and stops generating the power supply voltage Vdd when the NMOS transistor M1 is turned off. The NMOS transistor M3 is then turned on based on the power supply voltage Vdd. As a result, when the NMOS transistor M1 is turned off, the NMOS transistor M3 is also turned off, thereby reducing power consumption compared to when the NMOS transistor M1 is always on.

Diode D4 is also made of polysilicon, which prevents current from flowing through unintended paths. This is also effective when an inductive load is connected to terminal D.

The IPS 30 also includes an NMOS transistor M2 whose source electrode is connected to terminal A and whose drain electrode is connected to the drain electrode of the NMOS transistor M1, and the diode 42 is the body diode of the NMOS transistor M2. This allows the body diode of the NMOS transistor M2 (diode 42) to be effectively used as a diode that blocks reverse current.

The IPS 30 also includes an IC 40 that includes NMOS transistors M1 and M2, and a control IC 50 that includes a drive circuit 52 and diodes D3 (D5) and D4. This allows reverse current flowing through the IC 40 and the control IC to be blocked. Furthermore, the IPS 30 can be made smaller than when the circuit for blocking reverse current is made up of multiple components.

The above embodiments are intended to facilitate understanding of the present invention and are not intended to limit the scope of the present invention. Furthermore, the present invention may be modified or improved without departing from its spirit, and it goes without saying that the present invention includes equivalents thereof.

For example, NMOS transistor M2 may be omitted, and instead only diode 42 may be provided. In this case, the supply and stop of voltage Vcc to motor 12 is achieved solely by turning NMOS transistor M1 on and off, and diode 42 cuts off current when battery 1 is reverse-connected. However, in this case, the heat generated by the voltage drop and loss in diode 42 when NMOS transistor M1 is on will be greater than when NMOS transistor M2 is used.

Furthermore, in the above-described embodiment, NMOS transistor M3 was configured to turn on when instruction signal Sa is a signal instructing switch X1 (NMOS transistors M1 and M2) to be on (i.e., in conjunction with switch X1), but this is not limited to this. For example, it may be always on (regardless of instruction signal Sa) when voltage Vcc is applied to terminal A. However, if it is turned on and off in response to instruction signal Sa, as in this embodiment, power consumption can be reduced, as described above.

In addition, in the above-described embodiment, for convenience, diodes D3 and D4 were each configured as a single diode, but they may also be configured as multiple (e.g., three) diodes connected in series depending on the magnitude of battery 1 voltage Vcc. This prevents the diodes from breaking down when battery 1 is reverse-connected, and more reliably prevents reverse current.

Furthermore, in the IPS 30 of the above-described embodiment, there is one terminal (terminal A) to which voltage Vcc is applied, but this is not limited to this.

Figure 8 is an explanatory diagram of a modified version of IPS30 (IPS31). In this modified version, parts with the same configuration as the previously described embodiment are designated by the same reference numerals, and their description will be omitted.

IPS 30 has terminals A1 and A2 as terminals to which voltage Vcc is applied. Terminal A1 is connected to IC 40, and terminal A2 is connected to control IC 50. In this way, terminals to which voltage Vcc is applied may be provided on both the IC 40 side and the control IC 50 side. In this case, terminals A1 and A2 correspond to "first terminals."

1 Battery 10 Motor control device 12 Motor 20 Microcomputer 30 IPS
40 IC
41, 42 Diode 50 Control IC
51 Power supply circuit 52 Drive circuit 60 Diodes D1 to D6 Diodes M1, M2, M3, M5, M6 NMOS transistor M4 PMOS transistors A, B, C, D Terminals

Claims (9)

a first terminal to which a first voltage is applied;
a second terminal to which a second voltage lower than the first voltage is applied;
a third terminal to which a load is connected;
a first diode having an anode connected to the first terminal;
a first MOS transistor having a source electrode connected to the third terminal and a drain electrode connected to the cathode of the first diode;
a drive circuit for controlling the on/off of the first MOS transistor;
a second diode having a cathode connected to the second terminal and an anode connected to the drive circuit;
a third diode having a cathode connected to a node where the third terminal and the source electrode of the first MOS transistor are connected and an anode connected to the drive circuit;
A semiconductor device comprising: 2. The semiconductor device according to claim 1,
a second MOS transistor having a drain electrode connected to the second terminal and a source electrode connected to the drive circuit;
the second diode is a body diode of the second MOS transistor;
Semiconductor device. 2. The semiconductor device according to claim 1,
a second MOS transistor having a drain electrode connected to the second terminal and a source electrode connected to the drive circuit so as to be in parallel with the second diode;
Semiconductor device. 4. The semiconductor device according to claim 3,
the second diode is formed of polysilicon;
Semiconductor device. 4. The semiconductor device according to claim 3,
a forward voltage of the second diode is smaller than a forward voltage of a body diode of the second MOS transistor;
Semiconductor device. 4. The semiconductor device according to claim 3,
When the first MOS transistor is turned on, a power supply voltage for operating the drive circuit is generated;
a power supply circuit that stops generating the power supply voltage when the first MOS transistor is turned off;
The second MOS transistor is turned on based on the power supply voltage.
Semiconductor device. 2. The semiconductor device according to claim 1,
the third diode is formed of polysilicon;
Semiconductor device. The semiconductor device according to any one of claims 1 to 7,
a third MOS transistor having a source electrode connected to the first terminal and a drain electrode connected to the drain electrode of the first MOS transistor;
the first diode is a body diode of the third MOS transistor;
Semiconductor device. 9. The semiconductor device according to claim 8,
a first chip including the first MOS transistor and the third MOS transistor;
a second chip including the driving circuit, the second diode, and the third diode;
having
Semiconductor device.