JP7794626B2 - Power conversion device and control circuit - Google Patents

Description

The present invention relates to a power conversion device and a control circuit.

Two-phase modulation is known as a method for reducing switching losses in power conversion devices. In two-phase modulation, the number of times each switching element switches is reduced by adjusting the waveform of the command signal (modulation wave). Patent Document 1 discloses an inverter device in which the command signal is fixed to an upper or lower limit for a portion of one cycle, causing the PWM signal generated from the command signal and a carrier signal (carrier wave) to remain at a low or high level for a predetermined period. In this inverter device, the switching elements do not switch during the period in which the PWM signal remains at a low or high level. Therefore, compared to when the command signal is a normal sine wave signal (which does not have a period fixed at an upper or lower limit), this inverter device can reduce the number of times the switching elements switch, thereby reducing switching losses.

JP 2013-34359 A

However, when two-phase modulation is used, the waveform of the command signal contains vertically rising or falling portions. Therefore, the phase voltage output from the power conversion device can change abruptly. In such a power conversion device, placing ground noise filters on both the DC and AC sides to reduce switching noise emissions can cause problems. Specifically, abrupt changes in phase voltage can cause large peaks of common-mode current to flow through the common-mode reactor of the ground noise filter. This can cause magnetic saturation in the core, resulting in the loss of the intended noise filtering effect. Proposed methods for suppressing magnetic saturation include setting the impedance value and carrier frequency of the ground noise filter to values based on specific mathematical formulas. However, limitations on the size of the power conversion device may prevent the desired impedance value or carrier frequency of the ground noise filter.

The present invention was conceived in light of the above circumstances, and its purpose is to provide a power conversion device that can suppress magnetic saturation of noise filters without imposing hardware restrictions.

To solve the above problems, the present invention takes the following technical measures.

A power conversion device provided by a first aspect of the present invention comprises an inverter circuit that receives DC power as input and outputs three-phase AC power, a DC-side ground noise filter arranged on the input side of the inverter circuit, an AC-side ground noise filter arranged on the output side of the inverter circuit, a command signal generation unit that generates three command signals that command the waveforms of each phase voltage output by the inverter circuit by switching between multiple reference signals, and a PWM signal generation unit that generates three PWM signals based on the three command signals and outputs them to the inverter circuit, wherein the waveforms of the three command signals do not include vertically rising or falling portions.

In a preferred embodiment of the present invention, each waveform of the three command signals includes a maximum value fixed period in which the value is fixed at a maximum value and a minimum value fixed period in which the value is fixed at a minimum value, and the maximum value fixed period and the minimum value fixed period are of the same length.

The command signal generation unit switches between the multiple reference signals over a period of time, and generates the three command signals by gradually changing the reference signal before switching to the reference signal after switching during a predetermined transition period.

The system further includes a feedback control unit that generates three feedback command signals based on the deviation between the detection signal input from the sensor and its target value, and the command signal generation unit includes, as the multiple reference signals, six line voltage command signals based on the three feedback command signals and two fixed signals.

In a preferred embodiment of the present invention, the command signal generation unit linearly changes the signal from before the switching to the signal after the switching during the transition period.

A second aspect of the present invention provides a control circuit that receives DC power as input, outputs three-phase AC power, and controls the drive of multiple switching elements in an inverter circuit having a DC-side ground noise filter on the input side and an AC-side ground noise filter on the output side, using PWM signals. The control circuit includes a command signal generator that generates three command signals that command the waveforms of the phase voltages output by the inverter circuit by switching between multiple reference signals, and a PWM signal generator that generates three PWM signals based on the three command signals and outputs them to the inverter circuit, and the waveforms of the three command signals do not include vertically rising or falling portions.

According to the present invention, the command signal generation unit generates a signal with a waveform that does not include vertically rising or falling portions as a command signal for each phase voltage. Because the phase voltages output by the power conversion device do not change sharply, large common-mode currents do not flow. This suppresses peaks in common-mode currents and reduces magnetic saturation in each noise filter. Furthermore, because the command signal waveform is the only adjustment required, this can be implemented using software alone, eliminating the need to impose restrictions on the power conversion device's hardware.

Other features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

1A and 1B are block diagrams for explaining a power conversion device according to a first embodiment, in which (a) shows the overall configuration of the power conversion device, (b) shows the internal configuration of an inverter circuit, and (c) shows the internal configuration of a control circuit. FIG. 4 is a diagram for explaining a waveform of a command signal. FIG. 4 is a diagram for explaining a waveform of a command signal. 10 is a flowchart illustrating an example of a command signal generation process. 10 is a flowchart illustrating an example of a command signal generation process. 10 is a diagram for explaining a method of generating a PWM signal from a command signal and a carrier signal. FIG. FIG. 10 is a diagram illustrating a simulation result of the power conversion device. FIG. 10 is a diagram showing a modified example of a command signal.

The following describes in detail the embodiments of the present invention with reference to the drawings.

First Embodiment
FIG. 1 is a block diagram for explaining a power conversion device A1 according to the first embodiment.
1A shows the overall configuration of the power conversion device A1, FIG. 1B shows the internal configuration of the inverter circuit 1, and FIG. 1C shows the internal configuration of the control circuit 2.

As shown in FIG. 1(a), the power conversion device A1 includes an inverter circuit 1, a control circuit 2, a DC-side ground noise filter 3, and an AC-side ground noise filter 4. A DC power source B is connected to the input side of the inverter circuit 1 via the DC-side ground noise filter 3. The inverter circuit 1 is a three-phase inverter, and output lines for U-phase, V-phase, and W-phase output voltages are connected to the inverter circuit 1. The output lines are connected to a three-phase power grid C via the AC-side ground noise filter 4. The power conversion device A1 is a so-called power conditioner that is connected to the power grid C. The inverter circuit 1 converts DC power output by the DC power source B into AC power and supplies it to the power grid C. The power conversion device A1 is equipped with various sensors (not shown), and the control circuit 2 performs control based on the values detected by the sensors. Components such as a transformer circuit, a DC/DC converter circuit, and switches are omitted from FIG. 1. The configuration of the power conversion device A1 is not limited to this.

DC power supply B outputs DC power and includes, for example, a solar cell. The solar cell generates DC power by converting solar energy into electrical energy. DC power supply B outputs the generated DC power to power conversion device A1. Note that DC power supply B is not limited to generating DC power using a solar cell. For example, DC power supply B may be a fuel cell, a storage battery, an electric double-layer capacitor, or a lithium-ion battery. It may also be a device that converts AC power generated by a diesel engine generator, a micro gas turbine generator, a wind turbine generator, or the like into DC power and outputs it.

Inverter circuit 1 converts DC power input from DC power source B into AC power and outputs it to power grid C. Inverter circuit 1 is a three-phase PWM-controlled inverter equipped with switching elements. Inverter circuit 1 converts DC power input from DC power source B into three-phase AC power by switching each switching element on and off based on PWM signal P input from control circuit 2.

As shown in FIG. 1(b), the inverter circuit 1 is a three-phase full-bridge type and includes six switching elements S1 to S6. Each switching element may be an IGBT (insulated gate bipolar transistor) or other switching elements such as a MOSFET (metal-oxide-semiconductor field-effect transistor), bipolar transistor, or reverse-blocking thyristor. Freewheeling diodes D1 to D6 are connected in anti-parallel to the switching elements S1 to S6, respectively. The switching elements S1 and S3, S2 and S5, and S3 and S6 are connected in series to form a bridge structure. The U-phase output line is connected to the connection point between the switching elements S1 and S3. The V-phase output line is connected to the connection point between the switching elements S2 and S4. The W-phase output line is connected to the connection point between the switching elements S3 and S6. The specific circuit configuration of the inverter circuit 1 is not limited. Each switching element S1 to S6 receives a PWM signal P (P1 to P6) output from the control circuit 2. Details of each PWM signal will be described later.

The control circuit 2 generates a PWM signal P that controls the switching of the switching elements of the inverter circuit 1. The control circuit 2 is implemented, for example, by a microcomputer. Detection signals are input to the control circuit 2 from various sensors (not shown) and the control circuit 2 outputs the PWM signal P to the inverter circuit 1. Based on the detection signals input from the various sensors, the control circuit 2 generates command signals Xu1, Xv1, and Xw1, similar to a so-called two-phase modulation method, to actually control the waveform of the phase voltages output by the power conversion device A1. The control circuit 2 then generates the PWM signal P based on the command signals Xu1, Xv1, and Xw1. The inverter circuit 1 outputs phase voltages corresponding to the command signals Xu1, Xv1, and Xw1 by switching each switching element on and off based on the input PWM signal P. The control circuit 2 controls the output current by changing the waveforms of the command signals Xu1, Xv1, and Xw1 to change the phase voltages output by the inverter circuit 1. This allows the control circuit 2 to perform various feedback controls. A detailed description of the control circuit 2 will be provided later.

The DC-side ground noise filter 3 is located on the input side of the inverter circuit 1 and reduces switching noise output to the DC power supply B. The DC-side ground noise filter 3 includes a reactor located on each of the two input lines and a capacitor located on each of the lines connecting each input line to ground. The two reactors form a common mode reactor.

The AC-side ground noise filter 4 is located on the output side of the inverter circuit 1 and reduces switching noise output to the power system C. The AC-side ground noise filter 4 includes a reactor located on each of the three output lines and a capacitor located on each of the lines connecting each output line to ground. The three reactors form a common mode reactor.

Since both the DC side ground noise filter 3 and the AC side ground noise filter 4 are connected to ground, a common mode current (indicated by the arrows in Figure 1(a)) circulates via the ground. If a large common mode current flows, the core of the common mode reactor (not shown) may become magnetically saturated, causing the intended noise filtering effect to be lost. The power conversion device A1 prevents the core of the common mode reactor from becoming magnetically saturated by adjusting the command signals Xu1, Xv1, and Xw1 generated inside the control circuit 2.

Next, the internal configuration and detailed description of the control circuit 2 will be provided with reference to Figures 1(c) and 2 to 6.

As shown in Figure 1(c), the control circuit 2 includes a feedback control unit 21, a command signal generation unit 22, and a PWM signal generation unit 23. The control circuit 2 also includes components for detecting overcurrent, ground fault, short circuit, islanding, etc. and stopping operation of the inverter circuit 1, as well as components for maximum power point tracking; however, these components are not relevant to the explanation of the present invention and therefore are not shown or described in Figure 1(c).

The feedback control unit 21 performs feedback control based on the deviation between the detection signals input from various sensors and preset target values, generates feedback command signals Xu, Xv, and Xw for commanding the waveform of the output phase voltage of the power conversion device A1, and outputs these to the command signal generation unit 22. Details of the feedback control performed by the feedback control unit 21 are omitted. The feedback control performed by the feedback control unit 21 may control the output current, output voltage, output active power, and output reactive power output by the power conversion device A1, or may control the DC voltage input from the DC power source B.

The command signal generation unit 22 generates command signals Xu1, Xv1, and Xw1 based on the feedback command signals Xu, Xv, and Xw input from the feedback control unit 21 and outputs them to the PWM signal generation unit 23. The command signals Xu1, Xv1, and Xw1 are signals that actually command the waveforms of the phase voltages output by the inverter circuit 1. In other words, the command signal generation unit 22 converts the feedback command signals Xu, Xv, and Xw into command signals Xu1, Xv1, and Xw1. The waveforms of the command signals Xu1, Xv1, and Xw1 have special shapes like the waveforms Xu1, Xv1, and Xw1 shown in Figure 2(d), which will be described later.

The command signal generation unit 22 generates line voltage command signals Xuv, Xvw, and Xwu from the feedback command signals Xu, Xv, and Xw. The line voltage command signal Xuv is a signal for commanding the waveform of the line voltage of the U phase relative to the V phase. The command signal generation unit 22 generates the line voltage command signal Xuv based on the difference between the feedback command signal Xu and the feedback command signal Xv. The line voltage command signal Xvw is a signal for commanding the waveform of the line voltage of the V phase relative to the W phase. The command signal generation unit 22 generates the line voltage command signal Xvw based on the difference between the feedback command signal Xv and the feedback command signal Xw. The line voltage command signal Xwu is a signal for commanding the waveform of the line voltage of the W phase relative to the U phase. The command signal generation unit 22 generates the line voltage command signal Xwu based on the difference between the feedback command signal Xw and the feedback command signal Xu. In this embodiment, the amplitude of the feedback command signals Xu, Xv, and Xw is set to "1" for normalization (see Figure 2(a)), so the amplitude of the line voltage command signals Xuv, Xvw, and Xwu is √(3) (see Figure 2(b)).

The command signal generation unit 22 also generates line voltage command signals Xvu, Xwv, and Xuw by inverting the polarity of the line voltage command signals Xuv, Xvw, and Xwu. Instead of inverting the polarity, the command signal generation unit 22 may generate the line voltage command signal Xvu from the difference between the feedback command signal Xv and the feedback command signal Xu, generate the line voltage command signal Xwv from the difference between the feedback command signal Xw and the feedback command signal Xv, and generate the line voltage command signal Xuw from the difference between the feedback command signal Xu and the feedback command signal Xw.

The command signal generation unit 22 generates command signals Xu1, Xv1, and Xw1 using line voltage command signals Xuv, Xvw, and Xwu, line voltage command signals Xvu, Xwv, and Xuw, a first fixed signal whose value is fixed at "0," and a second fixed signal whose value is fixed at "2" (these may be collectively referred to as "reference signals"). The upper limit values of command signals Xu1, Xv1, and Xw1 must be equal to or greater than the amplitude of line voltage command signals Xuv, Xvw, and Xwu. Therefore, in this embodiment, the second fixed signal whose value is fixed at "2" is used to set the upper limit value to "2." Note that the upper limit value only needs to be equal to or greater than the amplitude of line voltage command signals Xuv, Xvw, and Xwu, so a predetermined value equal to or greater than √(3) is set as the upper limit value depending on the modulation index to be set.

The command signal generation unit 22 generates command signals Xu1, Xv1, and Xw1 by switching between line voltage command signals Xuv, Xvw, and Xwu, line voltage command signals Xvu, Xwv, and Xuw, the first fixed signal, and the second fixed signal over a period of time. When switching between signals, the command signal generation unit 22 gradually changes the pre-switching reference signal to the post-switching reference signal over a predetermined transition period Tx, thereby generating command signals Xu1, Xv1, and Xw1 as signals that do not change abruptly. In this embodiment, the command signal generation unit 22 linearly changes the pre-switching reference signal to the post-switching reference signal during the transition period Tx. Note that the transition period Tx is not limited and can be set as appropriate. When changing linearly, the slope of the command signals Xu1, Xv1, and Xw1 during the transition period Tx can be made smaller as the transition period Tx is made longer.

Figures 2 and 3 are diagrams illustrating the waveforms of the command signals Xu1, Xv1, and Xw1 generated by the command signal generation unit 22.

The waveforms Xu, Xv, and Xw shown in Figure 2(a) represent the waveforms of the feedback command signals Xu, Xv, and Xw, respectively. The waveforms Xuv, Xvw, and Xwu shown in Figure 2(b) represent the waveforms of the line voltage command signals Xuv, Xvw, and Xwu, respectively. The waveforms Xvu, Xwv, and Xuw shown in Figure 2(c) represent the waveforms of the line voltage command signals Xvu, Xwv, and Xuw, respectively. In Figure 2, the phase of the U-phase feedback command signal Xu is used as the reference.

The waveform Xu1 shown in Figure 2(d) is the waveform of the U-phase command signal Xu1. Figure 3 shows an enlarged portion of the waveform Xu1. The command signal Xu1 is generated for modes 1 to 6. The waveform Xu1 is the waveform Xuv in mode 1 (0≦θ≦π/3), a waveform fixed at "2" in mode 2 (π/3≦θ≦2π/3), the waveform Xuw in mode 3 (2π/3≦θ≦π), a waveform obtained by shifting the waveform Xuv upward by "2" in mode 4 (π≦θ≦4π/3), a waveform fixed at "0" in mode 5 (4π/3≦θ≦5π/3), and a waveform obtained by shifting the waveform Xuw upward by "2" in mode 6 (5π/3≦θ≦2π). However, the waveform Xu1 is not a waveform obtained by simply switching the reference signal when switching between modes. If the reference signal is switched as is when switching between modes, the waveforms shown by the dashed lines in Figures 2(d) and 3 will include vertically rising and falling portions. As shown in Figure 3, waveform Xu1 is a waveform that gradually changes from the reference signal before switching to the reference signal after switching during a predetermined transition period Tx from when the mode switches. As a result, waveform Xu1 does not include vertically rising or falling portions.

For example, as shown in Figure 3, the waveform Xuv is √(3) at the end of mode 1, so if it is changed to "2" at the start of mode 2, it will result in a waveform that rises vertically, as shown by the dashed line. However, waveform Xu1 changes linearly from √(3) to "2" during the transition period Tx, so it does not rise vertically. Similarly, if the waveform Xuv is shifted upward by "2" at the end of mode 4, it will be "2 - √(3)", so if it is changed to "0" at the start of mode 5, it will result in a waveform that falls vertically, as shown by the dashed line. However, waveform Xu1 changes linearly from "2 - √(3)" to "0" during the transition period Tx, so it does not fall vertically.

Similarly, waveform Xv1 shown in Figure 2(d) is a waveform fixed at "0" in mode 1, a waveform obtained by shifting waveform Xvu upward by "2" in mode 2, waveform Xvw in mode 3, a waveform fixed at "2" in mode 4, waveform Xvu in mode 5, and waveform Xvw in mode 6 shifted upward by "2". However, waveform Xv1 is also a waveform that gradually changes from the reference signal before the mode change to the reference signal after the mode change during a predetermined transition period Tx from when the mode changes. As a result, waveform Xv1 does not include vertically rising or falling portions.

Furthermore, waveform Xw1 shown in Figure 2(d) is a waveform obtained by shifting waveform Xwv upward by "2" in mode 1, waveform Xwu upward by "2" in mode 2, a waveform fixed at "0" in mode 3, a waveform obtained by shifting waveform Xwv upward by "2" in mode 4, waveform Xwu upward by "2" in mode 5, and a waveform fixed at "2" in mode 6. However, waveform Xw1 is also a waveform that gradually changes from the reference signal before the mode change to the reference signal after the mode change during a predetermined transition period Tx from when the mode changes. As a result, waveform Xw1 does not include vertically rising or falling portions.

Figures 4 and 5 are flowcharts showing an example of the process performed by the command signal generator 22 to generate command signals Xu1, Xv1, and Xw1 (hereinafter referred to as the "command signal generation process"). The command signal generation process is performed at a predetermined timing.

First, the feedback command signals Xu, Xv, and Xw, the line voltage command signals Xuv, Xvw, and Xwu, and the line voltage command signals Xvu, Xwv, and Xuw are acquired (S1). Next, it is determined whether the absolute value of Xu is greater than the absolute value of Xv (S2). If the absolute value of Xu is greater (S2: YES), it is determined whether the absolute value of Xu is greater than the absolute value of Xw (S3). If the absolute value of Xu is greater (S3: YES), i.e., if the absolute value of Xu is maximum, proceed to step S5. On the other hand, if the absolute value of Xu is less than or equal to the absolute value of Xw (S3: NO), i.e., if the absolute value of Xw is maximum, proceed to step S6. If the absolute value of Xu is less than or equal to the absolute value of Xv (S2: NO) in step S2, it is determined whether the absolute value of Xv is greater than the absolute value of Xw (S4). If the absolute value of Xv is greater (S4: YES), i.e., if the absolute value of Xv is the largest, proceed to step S7. On the other hand, if the absolute value of Xv is less than or equal to the absolute value of Xw (S4: NO), i.e., if the absolute value of Xw is the largest, proceed to step S6. In steps S2 to S4, it is determined which of Xu, Xv, and Xw has the largest absolute value.

If the absolute value of Xu is determined to be maximum and processing proceeds to step S5, it is determined whether Xu is a positive value (S5). If Xu is a positive value (S5: YES), the first process is performed (S8). On the other hand, if Xu is equal to or less than 0 (S5: NO), the second process is performed (S9).

If the absolute value of Xw is determined to be maximum and processing proceeds to step S6, it is determined whether Xw is a positive value (S6). If Xw is a positive value (S6: YES), the third process is performed (S10). On the other hand, if Xw is equal to or less than 0 (S6: NO), the fourth process is performed (S11).

If the absolute value of Xv is determined to be maximum and processing proceeds to step S7, it is determined whether Xv is a positive value (S7). If Xv is a positive value (S7: YES), the fifth process is performed (S12). On the other hand, if Xv is equal to or less than 0 (S7: NO), the sixth process is performed (S13).

In other words, the command signal generation process determines which of the feedback command signals Xu, Xv, and Xw has the largest absolute value, and determines whether the feedback command signal with the largest absolute value is positive or negative. This determines which of modes 1 to 6 it is in. The command signal generation process then performs different processing depending on the result of this determination.

Figure 5(a) is a flowchart showing an example of the first process (S8).

In the first process, it is first determined whether the variable c is "0" (S21). The variable c is a variable for counting the transition period Tx and is initialized to "0" when each mode is switched. For example, the variable c is initialized when the determination result changes in steps S2 to S7 of the flowchart shown in Figure 4. If the variable c is "0" (S21: YES), it is determined that mode 1 has been switched to mode 2, and the command signal Xu1 is set to the line voltage command signal Xuv of the previous mode 1 (S22). Next, the line voltage command signal Xuv is input to the variable tmp (S23). As shown in Figure 2, the phase θ when switching from mode 1 to mode 2 is "π/3" and the line voltage command signal Xuv is "√(3)", so "√(3)" is input to the variable tmp. Next, the command signal Xv1 is set to the value obtained by adding the line voltage command signal Xvu to the command signal Xu1, and the command signal Xw1 is set to the value obtained by adding the line voltage command signal Xwu to the command signal Xu1 (S27). Next, the variable c is incremented by "1" (S28), and the first process ends.

In step S21, if the variable c is not "0" (S21: NO), it is determined whether the variable c is equal to or less than the transition period Tx (S24). If the variable c is equal to or less than the transition period Tx (S24: YES), it is determined that the transition period Tx is in progress, and the command signal Xu1 is set to the result of calculation of the following equation (1). The following equation (1) is an equation for linearly changing the command signal Xu1 from the variable tmp to "2" during the transition period Tx. Next, the command signal Xv1 is set to a value obtained by adding the line voltage command signal Xvu to the command signal Xu1, and the command signal Xw1 is set to a value obtained by adding the line voltage command signal Xwu to the command signal Xu1 (S27). Next, the variable c is incremented by "1" (S28), and the first processing ends.

In step S24, if the variable c exceeds the transition period Tx (S24: NO), it is determined that the transition period Tx has ended, and the command signal Xu1 is set to "2." Next, the command signal Xv1 is set to the value obtained by adding the line voltage command signal Xvu to the command signal Xu1, and the command signal Xw1 is set to the value obtained by adding the line voltage command signal Xwu to the command signal Xu1 (S27). Next, the variable c is incremented by "1" (S28), and the first process ends.

Figure 5(b) is a flowchart showing an example of the second process (S9).

In the second process, it is first determined whether the variable c is "0" (S31). If the variable c is "0" (S31: YES), it is determined that mode 4 has been switched to mode 5, and the command signal Xu1 is set to a signal obtained by adding "2" to the line voltage command signal Xuv of the previous mode 4 (S32). Next, the signal obtained by adding "2" to the line voltage command signal Xuv is input to the variable tmp (S33). As shown in FIG. 2, the phase θ when switching from mode 4 to mode 5 is "(4/3)π" and the line voltage command signal Xuv is "-√(3)", so "2-√(3)" is input to the variable tmp. Next, the command signal Xv1 is set to the value obtained by adding the line voltage command signal Xvu to the command signal Xu1, and the command signal Xw1 is set to the value obtained by adding the line voltage command signal Xwu to the command signal Xu1 (S37). Next, the variable c is incremented by "1" (328), and the second process ends.

In step S31, if the variable c is not "0" (S31: NO), it is determined whether the variable c is equal to or less than the transition period Tx (S34). If the variable c is equal to or less than the transition period Tx (S34: YES), it is determined that the transition period Tx is in progress, and the command signal Xu1 is set to the result of calculation of the following equation (2). The following equation (2) is an equation for linearly changing the command signal Xu1 from the variable tmp to "0" during the transition period Tx. Next, the command signal Xv1 is set to a value obtained by adding the line voltage command signal Xvu to the command signal Xu1, and the command signal Xw1 is set to a value obtained by adding the line voltage command signal Xwu to the command signal Xu1 (S37). Next, the variable c is incremented by "1" (S38), and the second process ends.

In step S34, if the variable c exceeds the transition period Tx (S34: NO), it is determined that the transition period Tx has ended, and the command signal Xu1 is set to "0." Next, the command signal Xv1 is set to the value obtained by adding the line voltage command signal Xvu to the command signal Xu1, and the command signal Xw1 is set to the value obtained by adding the line voltage command signal Xwu to the command signal Xu1 (S37). Next, the variable c is incremented by "1" (S38), and the second process ends.

The third process (S10), fourth process (S11), fifth process (S12), and sixth process (S13) are also performed in the same manner, and detailed explanations will be omitted. Note that the processes shown in the flowcharts of Figures 4 and 5 are merely examples, and the command signal generation process performed by the command signal generation unit 22 is not limited to the above.

The waveforms of the command signals Xu1, Xv1, and Xw1 generated by the command signal generation process are shown in Figure 2(d). That is, in mode 2, the process proceeds to step S8 in the flowchart of Figure 4 and the first process (see Figure 5(a)) is performed, so that waveform Xu1 is fixed at "2," waveform Xv1 is waveform Xvu shifted upward by "2," and waveform Xw1 is waveform Xwu shifted upward by "2." However, during the transition period Tx after switching to mode 2, the calculation in step S25 of Figure 5(a) (see equation (1) above) causes the waveforms to rise linearly at a predetermined slope from the signal at the end of mode 1 to "2." In mode 5, the flow proceeds to step S9 in the flowchart of FIG. 4 and the second process (see FIG. 5(b)) is performed, so waveform Xu1 becomes a waveform fixed at "0", waveform Xv1 becomes waveform Xvu, and waveform Xw1 becomes waveform Xwu. However, during the transition period Tx after switching to mode 5, the calculation in step S35 of FIG. 5(b) (see equation (2) above) causes the waveform to linearly descend at a predetermined slope from the signal at the end of mode 4 to "0".

Similarly, in mode 1, the process proceeds to step S13, where a sixth process is performed, where waveform Xu1 becomes waveform Xuv, waveform Xv1 becomes a waveform fixed at "0", and waveform Xw1 becomes waveform Xwv. Also, in mode 3, the process proceeds to step S11, where a fourth process is performed, where waveform Xu1 becomes waveform Xuw, waveform Xv1 becomes waveform Xvw, and waveform Xw1 becomes a waveform fixed at "0". In mode 4, the process proceeds to step S12, where a fifth process is performed, where waveform Xu1 becomes a waveform obtained by shifting waveform Xuv upward by "2", waveform Xv1 becomes a waveform fixed at "2", and waveform Xw1 becomes a waveform obtained by shifting waveform Xwv upward by "2". In mode 6, the process proceeds to step S10, where the third process is performed, where waveform Xu1 becomes waveform Xuw shifted upward by "2", waveform Xv1 becomes waveform Xvw shifted upward by "2", and waveform Xw1 becomes a waveform fixed at "2". In modes 1, 3, 4, and 6, as in modes 2 and 5, during the transition period Tx after switching to the mode, the waveform linearly rises or falls at a predetermined slope from the signal at the end of the previous mode.

Returning to Figure 1(c), the PWM signal generation unit 23 generates a PWM signal P based on a carrier signal (e.g., a triangular wave signal) of a predetermined frequency (e.g., 4 kHz) generated internally and the command signals Xu1, Xv1, and Xw1 input from the command signal generation unit 22, and outputs the PWM signal P to the inverter circuit 1.

Command signals Xu1, Xv1, and Xw1 vary between an upper limit of "2" and a lower limit of "0" (see Figure 2(d)). The PWM signal generation unit 23 generates a carrier signal that varies between the upper limit of "2" for command signals Xu1, Xv1, and Xw1 and the lower limit of "0" for command signals Xu1, Xv1, and Xw1. Based on the carrier signal and command signals Xu1, Xv1, and Xw1, the PWM signal generation unit 23 generates PWM signals P1, P2, and P3 to be input to switching elements S1, S2, and S3, respectively. The PWM signal generation unit 23 also inverts the polarity of PWM signals P1, P2, and P3 to generate PWM signals P4, P5, and P6 to be input to switching elements S4, S5, and S6, respectively.

Figure 6 is a diagram illustrating a method for generating PWM signals P1 and P4 from a command signal Xu1 and a carrier signal. In the figure, the command signal Xu1 is represented by waveform X, the carrier signal by waveform C, and the PWM signals P1 and P4 by waveforms P1 and P4. As shown in Figure 6, the carrier signal waveform C is a triangular wave that changes between "2" and "0." The PWM signal generator 23 generates the PWM signal P1 as a pulse signal that is high when the command signal Xu1 is equal to or greater than the carrier signal and low when the command signal Xu1 is smaller than the carrier signal. Therefore, in Figure 4, waveform P1 is high when waveform X is equal to or greater than waveform C, and low when waveform X is smaller than waveform C. Note that Figure 6 illustrates a case where the frequency of each carrier signal (waveform C) is low, for the purpose of conceptual explanation; however, the frequency of each carrier signal is actually much higher. Furthermore, the carrier signal is not limited to a triangular wave signal.

During period t1 (maximum value fixed period) in Figure 6, PWM signal P1 (waveform P1) is fixed at high level, and PWM signal P4 (waveform P4) is fixed at low level. In this case, switching elements S1 and S4, to which PWM signals P1 and P4 are respectively input, stop switching. During period t2 (minimum value fixed period), PWM signal P1 (waveform P1) is fixed at low level, and PWM signal P4 (waveform P4) is fixed at high level. In this case, switching elements S1 and S4 also stop switching.

Note that the configuration of the PWM signal generator 23 is not limited to the one described above. Any other method may be used as long as it can generate PWM signals P1 to P6 for driving the switching elements S1 to S6 from the command signals Xu1, Xv1, and Xw1. For example, a configuration that applies an instantaneous space vector selection method may be used.

The control circuit 2 may be implemented as a digital circuit or an analog circuit. The processing performed by each component may be designed as a program, and the computer may function as the control circuit 2 by executing the program. The program may also be recorded on a recording medium and read by the computer.

In this embodiment, the command signal generation unit 22 of the control circuit 2 outputs command signals Xu1, Xv1, and Xw1 having the waveforms shown in Figure 2(d), and the PWM signal generation unit 23 generates PWM signals P1 to P6 based on the command signals Xu1, Xv1, and Xw1 and outputs them to the inverter circuit 1. The inverter circuit 1 switches the switching elements S1 to S6 based on the PWM signals P1 to P6. As a result, the DC power output by the DC power supply B is converted to AC power and output.

The waveforms of the phase voltage signals Vu1, Vv1, and Vw1 output by the power conversion device A1 are similar to the waveforms of the command signals Xu1, Xv1, and Xw1 shown in Figure 2(d). As can be seen from Figure 2, the difference signal between the command signals Xu1 and Xv1 is equal to the line voltage command signal Xuv. Similarly, the difference signal between the command signals Xv1 and Xw1 is equal to the line voltage command signal Xvw, and the difference signal between the command signals Xw1 and Xu1 is equal to the line voltage command signal Xwu. Therefore, the waveforms of the line voltage signals Vuv, Vvw, and Vwu, which are the difference signals between the phase voltage signals Vu1, Vv1, and Vw1, are the same as the waveforms Xuv, Xvw, and Xwu of the line voltage command signals Xuv, Xvw, and Xwu shown in Figure 2(b). Therefore, the line voltage signals Vuv, Vvw, and Vwu become three-phase balanced sine wave signals, and can be synchronized with the system voltage of power system C. Therefore, the AC power output by power conversion device A1 can be supplied to power system C. In addition, the waveform of the output current of power conversion device A1 also becomes a sine wave.

Next, a simulation of power conversion device A1 will be described with reference to Figure 7. Figure 7(b) shows the simulation results for power conversion device A1. On the other hand, Figure 7(a) shows the simulation results when the transition period Tx is not set in the command signal generation process. In Figures 7(a) and 7(b), the top row shows the waveforms of the line voltage signals Vuv, Vvw, and Vwu output by power conversion device A1, the second row shows the waveforms of the AC side ground voltages Vg_u, Vg_v, and Vg_w, and the third row shows the waveforms of the DC side ground voltages Vg_p and Vg_n. The fourth row shows the waveform of the common mode current, and the bottom row shows the waveform of U-phase command signal Xu1. Note that the waveforms of V-phase command signal Xv1 and W-phase command signal Xw1 are not shown, but have waveforms similar to command signal Xu1 but shifted in phase.

As shown in the bottom row of Figure 7(a), if the transition period Tx is not set in the command signal generation process, the waveform of the command signal Xu1 will have a waveform that rises or falls vertically when the mode is switched. Even in this case, the waveforms of the line voltage signals Vuv, Vvw, and Vwu are sinusoidal. However, the waveforms of the AC side voltages to ground Vg_u, Vg_v, and Vg_w and the DC side voltages to ground Vg_p and Vg_n are significantly distorted when the mode is switched. In addition, the common mode current increases when the mode is switched.

On the other hand, as shown in the bottom row of Figure 7(b), in the case of power conversion device A1, the waveform of command signal Xu1 is a waveform that does not include vertically rising or falling portions. In this case, the waveforms of each line voltage signal Vuv, Vvw, Vwu are sinusoidal, and the waveforms of each AC side ground voltage Vg_u, Vg_v, Vg_w and each DC side ground voltage Vg_p, Vg_n are waveforms with little disturbance. Furthermore, no large common mode current flows when switching modes.

As described above, by setting the transition period Tx in the command signal generation process and making the waveform of the command signal Xu1 (Xv1, Xw1) a waveform that does not include vertically changing portions, it can be seen that the common mode current is suppressed.

Next, we will explain the operation and effects of the power conversion device A1 according to this embodiment.

In this embodiment, the command signal generator 22 generates command signals Xu1, Xv1, and Xw1 with waveforms that do not include vertical rising or falling portions. The waveforms of the phase voltage signals Vu1, Vv1, and Vw1 output by the power conversion device A1 are similar to those of the command signals Xu1, Xv1, and Xw1 and do not change sharply, preventing large common-mode currents from flowing. This suppresses common-mode current peaks and reduces magnetic saturation in the common-mode reactors of the DC-side ground noise filter 3 and the AC-side ground noise filter 4. Furthermore, because the waveforms of the command signals Xu1, Xv1, and Xw1 are adjusted, this can be achieved solely through software, eliminating the need for hardware limitations in the power conversion device A1. This broadens the tolerance range for the magnetic saturation characteristics of the cores of each common-mode reactor, simplifying common-mode reactor selection. Furthermore, by suppressing intermittent peaks in the common mode current, the power conversion device A1 can reduce noise caused by the common mode current.

Furthermore, according to this embodiment, when generating the command signals Xu1, Xv1, and Xw1, the command signal generation unit 22 gradually changes the pre-switching reference signal to the post-switching reference signal during a predetermined transition period Tx from when each mode is switched. This allows the command signal generation unit 22 to generate the command signals Xu1, Xv1, and Xw1 as signals with waveforms that do not include vertically rising or falling portions. Furthermore, according to this embodiment, the command signal generation unit 22 linearly changes the pre-switching reference signal to the post-switching reference signal during the transition period Tx. This allows the command signal generation unit 22 to make a gradual change during the transition period Tx.

In this embodiment, the waveform of the command signal Xu1 includes a maximum value fixed period in which the signal is fixed at the maximum value "2" and a minimum value fixed period in which the signal is fixed at the minimum value "0," as shown in Figures 3(d) and 4. The PWM signal P1 is fixed at a high level during the maximum value fixed period and at a low level during the minimum value fixed period, thereby stopping the switching of the switching element S1 during these periods. The PWM signal P4 is fixed at a low level during the maximum value fixed period and at a high level during the minimum value fixed period, thereby stopping the switching of the switching element S4 during these periods. This reduces the number of times the switching elements S1 and S4 switch, thereby reducing switching loss. Furthermore, the maximum value fixed period and the minimum value fixed period in the command signal Xu1 are the same length. Therefore, the time that the switching element S1 is in the on state is equivalent to the time that the switching element S4 is in the on state. As a result, the degradation of the switching elements S1 and S4 progresses in the same manner, resulting in equivalent lifespans for both elements. Additionally, the amount of heat generated by both is the same, making it easier to design the cooling components. The same applies to the waveforms of the command signals Xv1 and Xw1.

Furthermore, according to this embodiment, the command signal generation unit 22 generates the command signals Xu1, Xv1, and Xw1 using the line voltage command signals Xuv, Xvw, and Xwu, the line voltage command signals Xvu, Xwv, and Xuw, a first fixed signal whose value is fixed at "0," and a second fixed signal whose value is fixed at "2." Therefore, the command signal generation unit 22 can appropriately generate the command signals Xu1, Xv1, and Xw1 that can make the line voltage waveform a sine wave while stopping each switching element for a portion of the period.

In this embodiment, the upper limit value of the command signals Xu1, Xv1, and Xw1 is described as "2" and the lower limit value as "0," but this is not limited to this. For example, the command signals Xu1, Xv1, and Xw1 may be generated so that the upper limit value is "1" and the lower limit value is "-1." In this case, the upper limit value of the carrier signal should be set to "1" and the lower limit value to "-1."

In this embodiment, the command signal generation unit 22 linearly changes the reference signal before switching to the reference signal after switching, but this is not limited to this. The change from the reference signal before switching to the reference signal after switching may also be a curved change, such as a quadratic curve. By changing the calculation formulas such as the above formulas (1) and (2), the way in which the reference signal before switching changes to the reference signal after switching can be changed.

In this embodiment, the command signal generation unit 22 generates the command signals Xu1, Xv1, and Xw1 by gradually changing them during a predetermined transition period Tx from when the mode is switched, but this is not limited to this. For example, as shown in the waveform in FIG. 8, the command signal generation unit 22 may generate the command signal Xu1 (Xv1, Xw1) by gradually changing them during the transition period Tx before the mode is switched. Alternatively, the command signal generation unit 22 may generate the command signal Xu1 (Xv1, Xw1) by gradually changing them during the transition period Tx, which includes when the mode is switched.

In this embodiment, the command signal generating unit 22 generates the command signals Xu1, Xv1, and Xw1 with the waveforms shown in Figure 2(d), but this is not limited to this. The waveforms of the command signals Xu1, Xv1, and Xw1 are not limited. The command signals Xu1, Xv1, and Xw1 do not necessarily have waveforms that simply switch the reference signal when switching modes, but rather have waveforms that gradually change from the reference signal before switching to the reference signal after switching, and they may have waveforms that do not include vertically rising or falling portions.

In this embodiment, the power conversion device A1 is used as a power conditioner, but this is not limited to this. The present invention can also be applied to power conversion devices in other systems.

The power conversion device and control circuit according to the present invention are not limited to the above-described embodiment. The specific configuration of each part of the power conversion device and control circuit according to the present invention can be freely designed and modified in various ways.

A1: Power conversion device, 1: Inverter circuit, 2: Control circuit, 21: Feedback control unit, 22: Command signal generation unit, 23: PWM signal generation unit, 3: DC side ground noise filter, 4: AC side ground noise filter

Claims (6)

an inverter circuit that receives DC power and outputs three-phase AC power;
a DC-side ground noise filter disposed on the input side of the inverter circuit;
an AC-side ground noise filter disposed on the output side of the inverter circuit;
a command signal generating unit that generates three command signals for commanding waveforms of the phase voltages output by the inverter circuit by switching between a plurality of reference signals;
a PWM signal generating unit that generates three PWM signals based on the three command signals and outputs the PWM signals to the inverter circuit;
Equipped with
each waveform of the three command signals does not include a vertical rising portion or a vertical falling portion , but includes a maximum value fixed period in which the waveform is fixed at a maximum value and a minimum value fixed period in which the waveform is fixed at a minimum value;
the maximum value fixing period and the minimum value fixing period have the same length;
Power conversion device. an inverter circuit that receives DC power and outputs three-phase AC power;
a DC-side ground noise filter disposed on the input side of the inverter circuit;
an AC-side ground noise filter disposed on the output side of the inverter circuit;
a command signal generating unit that generates three command signals for commanding waveforms of the phase voltages output by the inverter circuit by switching between a plurality of reference signals;
a PWM signal generating unit that generates three PWM signals based on the three command signals and outputs the PWM signals to the inverter circuit;
Equipped with
The waveforms of the three command signals do not include a vertical rising portion or a vertical falling portion,
the command signal generation unit switches the plurality of reference signals according to periods, and gradually changes the reference signal from before the switching to the reference signal after the switching during a predetermined transition period, thereby generating the three command signals.
Power conversion device. a feedback control unit that generates three feedback command signals based on a deviation between a detection signal input from the sensor and a target value thereof;
the command signal generation unit includes, as the plurality of reference signals, six line voltage command signals based on the three feedback command signals and two fixed signals;
The power conversion device according to claim 2 . the command signal generation unit linearly changes the signal from the pre-switching signal to the post-switching signal during the transition period;
The power conversion device according to claim 2 or 3 . A control circuit that receives DC power as input and outputs three-phase AC power, and that controls, by a PWM signal, driving of a plurality of switching elements in an inverter circuit having a DC-side ground noise filter disposed on the input side and an AC-side ground noise filter disposed on the output side,
a command signal generating unit that generates three command signals for commanding waveforms of the phase voltages output by the inverter circuit by switching between a plurality of reference signals;
a PWM signal generating unit that generates three PWM signals based on the three command signals and outputs the PWM signals to the inverter circuit;
Equipped with
each waveform of the three command signals does not include a vertical rising portion or a vertical falling portion , but includes a maximum value fixed period in which the waveform is fixed at a maximum value and a minimum value fixed period in which the waveform is fixed at a minimum value;
the maximum value fixing period and the minimum value fixing period have the same length;
Control circuit. A control circuit that receives DC power as input and outputs three-phase AC power, and that controls, by a PWM signal, driving of a plurality of switching elements in an inverter circuit having a DC-side ground noise filter disposed on the input side and an AC-side ground noise filter disposed on the output side,
a command signal generating unit that generates three command signals for commanding waveforms of the phase voltages output by the inverter circuit by switching between a plurality of reference signals;
a PWM signal generating unit that generates three PWM signals based on the three command signals and outputs the PWM signals to the inverter circuit;
Equipped with
The waveforms of the three command signals do not include a vertical rising portion or a vertical falling portion,
the command signal generation unit switches the plurality of reference signals according to periods, and gradually changes the reference signal from before the switching to the reference signal after the switching during a predetermined transition period, thereby generating the three command signals.
Control circuit.