JP7794725B2 - Semiconductor device manufacturing method - Google Patents

Description

The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

Patent Document 1 discloses a technique for forming a diffusion layer at the bottom of a trench by ion-implanting dopants into the bottom surface of the trench. In this technique, an oxide film is formed on the inner surface of the trench before ion implantation. Next, the oxide film covering the bottom surface of the trench is removed by etching, leaving oxide films on both side surfaces of the trench. Next, a diffusion layer is formed at the bottom of the trench by ion-implanting dopants into the bottom surface of the trench. Because both side surfaces of the trench are covered with oxide films, implantation of dopants into both side surfaces of the trench is prevented.

Japanese Patent Application Laid-Open No. 2018-207061

In the technology of Patent Document 1, the oxide film covering both sides of the trench prevents dopants from being injected into the edges of the trench bottom. As a result, dopants can only be injected into the center of the trench bottom. For example, if the width of the trench bottom is 0.5 μm and the oxide film covering both sides is 0.1 μm thick, dopants can only be injected into a 0.3 μm-wide area in the center of the trench bottom. As a result, this technology can only form a diffusion region that is narrower than the trench bottom. This specification proposes a technology that prevents dopants from being injected into the trench side, while injecting dopants into a wide area of the trench bottom.

The method for manufacturing a semiconductor device disclosed herein includes a wafer preparation process, a first inert ion implantation process, a second inert ion implantation process, an oxide film growth process, and a dopant implantation process. In the wafer preparation process, a wafer including a semiconductor substrate is prepared. A trench is provided on the surface of the wafer. The trench has a first side surface, a second side surface, and a bottom surface disposed between the first side surface and the second side surface. The bottom surface is located within the semiconductor substrate. In the first inert ion implantation process, inert ions are implanted into the first side surface. In the first inert ion implantation process, inert ions are implanted into the first side surface such that, in a cross section along the width direction of the trench, the inclination angle of the inert ion implantation direction relative to the surface of the wafer is greater than the inclination angle of a straight line connecting the upper end of the second side surface and the lower end of the first side surface relative to the surface of the wafer. In the second inert ion implantation process, inert ions are implanted into the second side surface. In the second inert ion implantation process, inert ions are implanted into the second side surface such that the inclination angle of the inert ion implantation direction relative to the surface of the wafer in the cross section along the width direction of the trench is greater than the inclination angle of a line connecting the upper end of the first side surface and the lower end of the second side surface relative to the surface of the wafer. In the oxide film growth process, an oxide film is grown on the first side surface and the second side surface by heating the semiconductor substrate. In the dopant implantation process, dopants are implanted into the bottom surface.

The wafer may consist solely of a semiconductor substrate, or may include a semiconductor substrate and other layers (e.g., insulating layers, conductor layers, mask layers, etc.) disposed on its surface. The trench may be disposed on the surface of the semiconductor substrate, or on the surface of the other layer disposed on the surface of the semiconductor substrate. If the trench is disposed on the surface of the other layer, the trench penetrates the other layer and reaches the semiconductor substrate, so that the bottom of the trench is located within the semiconductor substrate. If the side and bottom of the trench are connected by a curved surface, the lower end of the side of the trench is the position where the tangent to the curved surface with respect to the surface of the semiconductor substrate forms a 45-degree inclination angle. The inert ions refer to ions that do not function as either acceptors or donors in the semiconductor substrate (i.e., nonpolar ions). Examples of inert ions include argon ions and neon ions. In this specification, the inclination angle with respect to the wafer surface refers to the angle between a perpendicular to the wafer surface and an object (e.g., an implantation direction or a straight line). Therefore, a tilt angle of 0 degrees means that the object is parallel to the normal (i.e., perpendicular to the surface of the wafer).

In this manufacturing method, inert ions are implanted into the first and second side surfaces in the first and second inert ion implantation processes, generating crystal defects on these side surfaces. In the first inert ion implantation process, the tilt angle of the inert ion implantation direction is set as described above, thereby preventing inert ions from being implanted near the bottom of the first side surface. Furthermore, in the second inert ion implantation process, the tilt angle of the inert ion implantation direction is set as described above, thereby preventing inert ions from being implanted near the bottom of the second side surface. Next, in the oxide film growth process, the semiconductor substrate is heated. Because the density of crystal defects is high in the inert ion implantation area, the oxide film grows faster. Therefore, the oxide film grows faster in the inert ion implantation area of the first and second side surfaces than on the trench bottom. Furthermore, because inert ions are not implanted in the areas near the bottom of the first and second side surfaces, the oxide film grows more slowly in the areas near the bottom of the first and second side surfaces. Therefore, in the oxide film growth process, a sufficiently thick oxide film can be formed in the inert ion implantation area of the first and second side surfaces without growing a thick oxide film in the areas near the bottom ends of the first and second side surfaces or on the bottom surface of the trench. Next, in the dopant implantation process, dopants are implanted into the bottom surface of the trench. Because a thick oxide film is not present in the areas near the bottom ends of the first and second side surfaces, dopants can be implanted over a wide area of the bottom surface of the trench. Furthermore, implantation of dopants into the first and second side surfaces is prevented in the areas covered by the oxide film. Thus, this manufacturing method allows dopants to be implanted over a wide area of the bottom surface of the trench while preventing implantation of dopants into the side surfaces of the trench.

FIG. 1 is a cross-sectional view of a semiconductor device 10. FIG. 2 is an explanatory diagram of a manufacturing method according to the first embodiment. FIG. 2 is an explanatory diagram of a manufacturing method according to the first embodiment. FIG. 2 is an explanatory diagram of a manufacturing method according to the first embodiment. FIG. 2 is an explanatory diagram of a manufacturing method according to the first embodiment. FIG. 2 is an explanatory diagram of a manufacturing method according to the first embodiment. FIG. 2 is an explanatory diagram of a manufacturing method according to the first embodiment. FIG. 10 is an explanatory diagram of a manufacturing method according to a second embodiment. FIG. 10 is an explanatory diagram of a manufacturing method according to a second embodiment. FIG. 10 is an explanatory diagram of a manufacturing method according to a second embodiment. FIG. 10 is an explanatory diagram of a manufacturing method according to a second embodiment.

In one example of a manufacturing method disclosed herein, the wafer preparation step may include the steps of forming a mask layer on the surface of the semiconductor substrate and forming the trench through the mask layer to reach the semiconductor substrate. With the mask layer in place, the steps of implanting inert ions into the first side surface, implanting inert ions into the second side surface, growing the oxide film, and implanting a dopant may be performed.

In another example of a manufacturing method disclosed herein, the step of preparing the wafer may include the steps of forming a mask layer on the surface of the semiconductor substrate, forming the trench through the mask layer to reach the semiconductor substrate, and removing the mask layer. In the steps of implanting inert ions into the first side surface and implanting inert ions into the second side surface, the inert ions may be implanted into the surface of the semiconductor substrate. In the step of growing an oxide film, the oxide film may be grown on the first side surface, the second side surface, and the surface of the semiconductor substrate. The step of implanting a dopant may be performed with the oxide film present on the surface of the semiconductor substrate.

Either of these configurations can prevent dopants from being implanted into the surface of the semiconductor substrate.

In one example manufacturing method disclosed herein, the semiconductor substrate may have a p-type body layer. The trench may penetrate the body layer. In the step of implanting inert ions into the first side surface, the inert ions may be implanted into the first side surface such that, in the cross section along the width direction of the trench, the inclination angle of the inert ion implantation direction relative to the surface of the wafer is smaller than the inclination angle of a straight line connecting an upper end of the second side surface and a lower end of the body layer at the first side surface relative to the surface of the wafer in the cross section. In the step of implanting inert ions into the second side surface, the inert ions may be implanted into the second side surface such that, in the cross section along the width direction of the trench, the inclination angle of the inert ion implantation direction relative to the surface of the wafer is smaller than the inclination angle of a straight line connecting an upper end of the first side surface and a lower end of the body layer at the second side surface relative to the surface of the wafer in the cross section.

This manufacturing method allows the diffusion layer to be formed at the bottom of the trench while being separated from the body layer.

The semiconductor device 10 shown in FIG. 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x-direction, a direction parallel to the upper surface 12a and perpendicular to the x-direction is referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z-direction. FIG. 1 shows a cross section along the x-direction and z-direction. The upper surface 12a of the semiconductor substrate 12 has multiple trenches 14. Each trench 14 extends linearly in the y-direction on the upper surface 12a. That is, the x-direction is a direction perpendicular to the trench 14 and corresponds to the width direction of the trench 14. The trenches 14 are spaced apart in the x-direction on the upper surface 12a. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed within each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. A source electrode 22 is disposed on the upper part of the semiconductor substrate 12. The source electrode 22 is insulated from the gate electrode 18 by an interlayer insulating film 20. A drain electrode 24 is provided on the lower surface 12b of the semiconductor substrate 12.

The semiconductor substrate 12 has a source region 40, a contact region 42, a body region 44, a drift region 46, a drain region 48, and a deep region 50.

The source region 40 is an n-type region with a high n-type impurity concentration. The source region 40 is in contact with the source electrode 22 and the gate insulating film 16. The contact region 42 is a p-type region with a high p-type impurity concentration. The contact region 42 is in contact with the source electrode 22. The body region 44 is a p-type region with a lower p-type impurity concentration than the contact region 42. The body region 44 is in contact with the source region 40 and the contact region 42 from below. The body region 44 is in contact with the gate insulating film 16 below the source region 40. The drift region 46 is an n-type region with a lower n-type impurity concentration than the source region 40. The drift region 46 is in contact with the body region 44 from below. The drift region 46 is in contact with the gate insulating film 16 below the body region 44. The drain region 48 is an n-type region with a higher n-type impurity concentration than the drift region 46. The drain region 48 contacts the drift region 46 from below. The drain region 48 contacts the drain electrode 24. Each deep region 50 is located at the bottom of each trench 14. The deep region 50 contacts the gate insulating film 16 at the bottom of the trench 14. The width of the deep region 50 is approximately equal to the width of the bottom of the trench 14. The deep region 50 is surrounded by the drift region 46.

The source region 40, contact region 42, body region 44, drift region 46, drain region 48, deep region 50, gate electrode 18, and gate insulating film 16 constitute a metal-oxide-semiconductor field effect transistor (MOSFET). When a potential equal to or greater than the gate threshold is applied to the gate electrode 18, a channel is formed in the body region 44, turning the MOSFET on. When the potential of the gate electrode 18 is reduced to a potential below the gate threshold, the channel disappears, turning the MOSFET off. When the MOSFET is turned off, a depletion layer extends from the body region 44 to the drift region 46. At the same time, the depletion layer also extends from the deep region 50 to the drift region 46. The depletion layer extending from the deep region 50 to the drift region 46 prevents a high electric field from being applied to the gate insulating film 16 covering the bottom end of the trench 14. In particular, because the width of the deep region 50 is approximately equal to the width of the bottom of the trench 14, the deep region 50 contacts the gate insulating film 16 over almost the entire bottom of the trench 14. Therefore, the gate insulating film 16 at the bottom end of the trench 14 can be effectively protected.

Next, we will explain the manufacturing method of the semiconductor device 10. Note that the manufacturing methods of Examples 1 and 2 are characterized by the process of forming the deep region 50, so the process of forming the deep region 50 will be explained below.

The manufacturing method of Example 1 includes a wafer preparation process, a first inert ion implantation process, a second inert ion implantation process, an oxide film growth process, and a dopant implantation process.

In the wafer preparation process, as shown in FIG. 2, a mask layer 60 is formed on the upper surface 12a of the semiconductor substrate 12, on which the source region 40, contact region 42, body region 44, and drift region 46 are provided. Hereinafter, the semiconductor substrate 12 and mask layer 60 may be collectively referred to as the wafer. Next, an opening 60a is formed in the mask layer 60. Next, as shown in FIG. 3, the semiconductor substrate 12 is etched through the mask layer 60 to form a trench 14 in the semiconductor substrate 12. Hereinafter, the opening 60a in the mask layer 60 and the trench 14 in the semiconductor substrate 12 are collectively referred to as the trench 62. The trench 62 is provided on the upper surface of the mask layer 60 (i.e., the upper surface of the wafer) and penetrates the mask layer 60 to reach the semiconductor substrate 12. Therefore, the bottom surface of the trench 62 (i.e., the bottom surface 14c of the trench 14) is located within the semiconductor substrate 12. Hereinafter, one side of the trench 62 will be referred to as the first side 62a, and the other side of the trench 62 will be referred to as the second side 62b. The first side 62a faces the second side 62b.

Next, the first inert ion implantation process is performed. In the first inert ion implantation process, argon ions are implanted into the first side surface 62a of the trench 62, as shown in FIG. 4. Argon ions are inert ions. Here, the argon ions are implanted into the first side surface 62a with the argon ion implantation direction 92 tilted relative to the top surface of the wafer.

Angle θ92 in Figure 4 is the angle between a perpendicular line 90 erected on the top surface of the wafer (i.e., the top surface of the mask layer 60) and the argon ion implantation direction 92. Angle θ92 is the inclination angle of the argon ion implantation direction 92 with respect to the top surface of the wafer.

The straight line 94 in Figure 4 is a line connecting the upper end of the second side surface 62b and the lower end of the first side surface 62a. Also, the angle θ94 in Figure 4 is the inclination angle of the straight line 94 with respect to the upper surface of the wafer.

The straight line 96 in Figure 4 is a line connecting the upper end of the second side surface 62b and the lower end of the body region 44 on the first side surface 62a. Also, the angle θ96 in Figure 4 is the inclination angle of the straight line 96 with respect to the upper surface of the wafer.

As shown in FIG. 4, the inclination angle θ92 of the argon ion implantation direction 92 is greater than the inclination angle θ94 of the straight line 94. Therefore, due to the shadow of the second side surface 62b, argon ions are not implanted into the range 62aL near the lower end of the first side surface 62a. Furthermore, argon ions are not implanted into the bottom surface 14c of the trench 62. Also, as shown in FIG. 4, the inclination angle θ92 of the argon ion implantation direction 92 is smaller than the inclination angle θ96 of the straight line 96. Therefore, argon ions are implanted into the range 62aU from the upper end of the first side surface 62a to the portion below the lower end of the body region 44 (i.e., the surface portion of the drift region 46). Therefore, crystal defects are formed on the first side surface 62a within the range 62aU.

Next, a second inert ion implantation process is performed. In the second inert ion implantation process, argon ions are implanted into the second side surface 62b of the trench 62, as shown in FIG. 5. Here, the argon ions are implanted into the second side surface 62b with the argon ion implantation direction 82 tilted relative to the top surface 12a of the semiconductor substrate 12.

Perpendicular line 80 in Figure 5 is a perpendicular line erected on the top surface of the wafer. Angle θ82 in Figure 5 is the inclination angle of argon ion implantation direction 82 with respect to the top surface of the wafer. Line 84 in Figure 5 is a line connecting the upper end of first side surface 62a and the lower end of second side surface 62b. Also, angle θ84 in Figure 5 is the inclination angle of line 84 with respect to the top surface of the wafer. Line 86 in Figure 5 is a line connecting the upper end of first side surface 62a and the lower end of body region 44 on second side surface 62b. Also, angle θ86 in Figure 5 is the inclination angle of line 86 with respect to the top surface of the wafer.

As shown in FIG. 5, the inclination angle θ82 of the argon ion implantation direction 82 is greater than the inclination angle θ84 of the straight line 84. Therefore, argon ions are not implanted into a range 62bL near the lower end of the second side surface 62b. Furthermore, argon ions are not implanted into the bottom surface 14c of the trench 62. Also, as shown in FIG. 5, the inclination angle θ82 of the argon ion implantation direction 82 is smaller than the inclination angle θ86 of the straight line 86. Therefore, argon ions are implanted into a range 62bU from the upper end of the second side surface 62b to a portion below the lower end of the body region 44 (i.e., the surface portion of the drift region 46). Therefore, crystal defects are formed on the second side surface 62b within the range 62bU.

Next, the oxide film growth process is performed. In this process, the wafer is heated to oxidize the inner surface of the trench 14. As a result, an oxide film 64 grows within the trench 14, as shown in FIG. 6. In the areas 62aU and 62bU where argon ions are implanted, the oxide film 64 grows faster than in the areas 62aL, 62bL and bottom surface 14c where argon ions are not implanted. Therefore, an oxide film 64 that is much thicker in the areas 62aU and 62bU than in the areas 62aL, 62bL and bottom surface 14c is formed. Note that because the oxide film formed in the areas 62aL, 62bL and bottom surface 14c is extremely thin, the oxide film formed in the areas 62aL, 62bL and bottom surface 14c is not shown in FIG. 6. In this way, a thick oxide film 64 is formed in the ranges 62aU and 62bU on each side surface 62a and 62b, while almost no oxide film is formed in the ranges 62aL and 62bL on each side surface 62a and 62b near the bottom surface 14c.

Next, the dopant implantation process is performed. In this dopant implantation process, as shown in FIG. 7, p-type dopants are ion-implanted into the bottom surface 14c of the trench 62. Here, the dopant is implanted without tilting the dopant implantation direction relative to the upper surface of the wafer. After the dopant implantation, the wafer is heat-treated. This activates the dopants implanted into the bottom surface 14c, forming deep regions 50. Because no thick oxide film is formed in the areas 62aL, 62bL near the bottom surface 14c on each side surface 62a, 62b, the dopant is implanted into almost the entire bottom surface 14c during the dopant implantation process. Therefore, a deep region 50 with approximately the same width as the bottom surface 14c can be formed. Furthermore, in the areas 62aU, 62bU covered by the thick oxide film 64, the oxide film 64 prevents dopant implantation into the side surfaces 62a, 62b. Therefore, no deep region 50 is formed within the areas 62aU, 62bU. Since the deep region 50 is not formed in the surface layer portion of the drift region 46 on the side surfaces 62a, 62b, the deep region 50 can be prevented from connecting with the body region 44.

Furthermore, in the dopant implantation process, the mask layer 60 prevents the dopant from being implanted into the upper surface 12a of the semiconductor substrate 12. In other words, according to Example 1, the etching mask used to form the trench 14 can be used as a mask in the dopant implantation process.

After the dopant implantation process, the mask layer 60 and oxide film 64 are removed. The semiconductor device 10 is then completed by forming the gate insulating film 16, gate electrode 18, interlayer insulating film 20, source electrode 22, drain electrode 24, etc.

The manufacturing method of Example 2 includes a wafer preparation process, a first inert ion implantation process, a second inert ion implantation process, an oxide film growth process, and a dopant implantation process.

In Example 2, the wafer preparation process is performed in the same manner as in Example 1. That is, as shown in Figures 2 and 3, trenches 62 are formed in the wafer. Unlike Example 1, in Example 2, the mask layer 60 is removed after the trenches 62 are formed. Therefore, after the mask layer 60 is removed, the wafer consists of the semiconductor substrate 12 alone. Hereinafter, one side of the trench 14 is referred to as the first side 14a, and the other side of the trench 14 is referred to as the second side 14b. The first side 14a faces the second side 14b.

Next, the first inert ion implantation process is carried out. In the first inert ion implantation process, argon ions are implanted into the first side surface 14a of the trench 14, as shown in FIG. 8. Here, the argon ions are implanted into the first side surface 14a with the argon ion implantation direction 192 tilted relative to the upper surface 12a of the semiconductor substrate 12 (i.e., the upper surface of the wafer).

Perpendicular line 190 in FIG. 8 is a perpendicular line erected on top surface 12a. Angle θ192 in FIG. 8 is the inclination angle of argon ion implantation direction 192 with respect to top surface 12a. Line 194 in FIG. 8 is a line connecting the upper end of second side surface 14b and the lower end of first side surface 14a. Also, angle θ194 in FIG. 8 is the inclination angle of line 194 with respect to top surface 12a. Line 196 in FIG. 8 is a line connecting the upper end of second side surface 14b and the lower end of body region 44 on first side surface 14a. Also, angle θ196 in FIG. 8 is the inclination angle of line 196 with respect to top surface 12a.

As shown in FIG. 8, the inclination angle θ192 of the argon ion implantation direction 192 is larger than the inclination angle θ194 of the straight line 194. Therefore, argon ions are not implanted into the range 14aL near the lower end of the first side surface 14a. Furthermore, argon ions are not implanted into the bottom surface 14c of the trench 14. Also, as shown in FIG. 8, the inclination angle θ192 of the argon ion implantation direction 192 is smaller than the inclination angle θ196 of the straight line 196. Therefore, argon ions are implanted into the range 14aU from the upper end of the first side surface 14a to the portion below the lower end of the body region 44 (i.e., the surface portion of the drift region 46). Therefore, crystal defects are formed on the first side surface 14a within the range 14aU.

In addition, in the first inert ion implantation process of Example 2, argon ions are also implanted into the upper surface 12a of the semiconductor substrate 12 to form crystal defects.

Next, a second inert ion implantation process is performed. In the second inert ion implantation process, argon ions are implanted into the second side surface 14b of the trench 14, as shown in FIG. 9. Here, the argon ions are implanted into the second side surface 14b with the argon ion implantation direction 182 tilted relative to the top surface 12a of the semiconductor substrate 12.

Perpendicular line 180 in FIG. 9 is a perpendicular line erected on top surface 12a. Angle θ182 in FIG. 9 is the inclination angle of argon ion implantation direction 182 with respect to top surface 12a. Line 184 in FIG. 9 is a line connecting the upper end of first side surface 14a and the lower end of second side surface 14b. Also, angle θ184 in FIG. 9 is the inclination angle of line 184 with respect to top surface 12a. Line 186 in FIG. 9 is a line connecting the upper end of first side surface 14a and the lower end of body region 44 on second side surface 14b. Also, angle θ186 in FIG. 9 is the inclination angle of line 186 with respect to top surface 12a.

As shown in FIG. 9, the inclination angle θ182 of the argon ion implantation direction 182 is greater than the inclination angle θ184 of the straight line 184. Therefore, argon ions are not implanted into the range 14bL near the lower end of the second side surface 14b. Furthermore, argon ions are not implanted into the bottom surface 14c of the trench 14. Also, as shown in FIG. 9, the inclination angle θ182 of the argon ion implantation direction 182 is smaller than the inclination angle θ186 of the straight line 186. Therefore, argon ions are implanted into the range 14bU from the upper end of the second side surface 14b to the portion below the lower end of the body region 44 (i.e., the surface portion of the drift region 46). Therefore, crystal defects are formed on the second side surface 14b within the range 14bU.

In addition, in the second inert ion implantation process of Example 2, argon ions are also implanted into the upper surface 12a of the semiconductor substrate 12 to form crystal defects.

Next, the oxide film growth process is performed. In this process, the wafer is heated to oxidize the inner surface of the trench 14. As a result, an oxide film 64 is grown within the trench 14, as shown in FIG. 10. An oxide film 64 is formed in the areas 14aU and 14bU that is much thicker than the areas 14aL, 14bL and the bottom surface 14c. Note that because the oxide film formed in the areas 14aL, 14bL and the bottom surface 14c is extremely thin, the oxide film formed in the areas 14aL, 14bL and the bottom surface 14c is not shown in FIG. 10. In this way, a thick oxide film 64 is formed in the areas 14aU and 14bU on each side surface 14a and 14b, from the upper end to below the lower end of the body region 44, while almost no oxide film is formed in the areas 14aL and 14bL on each side surface 14a and 14b near the bottom surface 14c.

In addition, in the oxide film growth process of Example 2, a hot oxide film 64 also grows on the upper surface 12a of the semiconductor substrate 12.

Next, the dopant implantation process is performed. In this dopant implantation process, as shown in FIG. 11, p-type dopants are ion-implanted into the bottom surface 14c of the trench 14. Here, the dopant is implanted without tilting the dopant implantation direction relative to the upper surface of the wafer. After the dopant implantation, the wafer is heat-treated. This activates the dopant implanted into the bottom surface 14c, forming a deep region 50. Because no thick oxide film is formed in the areas 14aL and 14bL near the bottom surface 14c on each side surface 14a and 14b, the dopant is implanted into almost the entire bottom surface 14c during the dopant implantation process. Therefore, a deep region 50 with approximately the same width as the bottom surface 14c can be formed. Furthermore, in the areas 14aU and 14bU covered by the thick oxide film 64, the oxide film 64 prevents dopant implantation into the side surfaces 14a and 14b. Therefore, a deep region 50 is not formed within the areas 14aU and 14bU. Since the deep region 50 is not formed in the surface layer of the drift region 46 on the side surfaces 14a and 14b, the deep region 50 can be prevented from connecting with the body region 44.

In addition, during the dopant implantation process, the oxide film 64 prevents the dopant from being implanted into the upper surface 12a of the semiconductor substrate 12.

After the dopant implantation process, the oxide film 64 is removed. The semiconductor device 10 is then completed by forming the gate insulating film 16, gate electrode 18, interlayer insulating film 20, source electrode 22, drain electrode 24, etc.

In the above-described embodiment, the semiconductor substrate 12 was made of SiC, but the semiconductor substrate 12 may also be made of other semiconductors such as Si.

Furthermore, while the above-described embodiments have described methods for manufacturing MOSFETs, the techniques disclosed in this specification may also be applied to methods for manufacturing other semiconductor devices. In this case, the dopant implanted into the bottom surface of the trench may be either n-type or p-type.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings demonstrate technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of those objectives itself has technical utility.

12: semiconductor substrate, 14: trench, 14a: first side surface, 14b: second side surface, 60: mask layer, 62: trench, 62a: first side surface, 62b: second side surface

Claims (4)

A method for manufacturing a semiconductor device, comprising:
providing a wafer including a semiconductor substrate (12), the wafer having a trench (14, 62) in a surface thereof, the trench having a first side (14a, 62a), a second side (14b, 62b), and a bottom surface (14c) disposed between the first side and the second side, the bottom surface being located within the semiconductor substrate;
a step of implanting inert ions into the first side surface, wherein an inclination angle (θ92, θ192) of the implantation direction of the inert ions relative to the surface of the wafer is greater than an inclination angle (θ94, θ194) of a line connecting an upper end of the second side surface and a lower end of the first side surface relative to the surface of the wafer in a cross section along the width direction of the trench;
a step of implanting inert ions into the second side surface, wherein an inclination angle (θ82, θ182) of the implantation direction of the inert ions relative to the surface of the wafer is greater than an inclination angle (θ84, θ184) of a line connecting the upper end of the first side surface and the lower end of the second side surface relative to the surface of the wafer in the cross section along the width direction of the trench;
growing an oxide film (64) on the first side and the second side by heating the semiconductor substrate;
implanting dopants into the bottom surface;
A manufacturing method comprising the steps of: the step of preparing the wafer comprises:
forming a mask layer (60) on the surface of the semiconductor substrate;
forming the trench through the mask layer to reach the semiconductor substrate;
and
In a state where the mask layer exists, the step of implanting inert ions into the first side surface, the step of implanting inert ions into the second side surface, the step of growing the oxide film, and the step of implanting a dopant are performed.
The method of claim 1. the step of preparing the wafer comprises:
forming a mask layer on a surface of the semiconductor substrate;
forming the trench through the mask layer to the semiconductor substrate;
removing the mask layer;
and
In the step of implanting inert ions into the first side surface and the step of implanting inert ions into the second side surface, inert ions are implanted into the surface of the semiconductor substrate;
In the step of growing the oxide film, the oxide film is grown on the first side surface, the second side surface, and the surface of the semiconductor substrate;
The step of implanting dopants is carried out in a state where the oxide film is present on the surface of the semiconductor substrate.
The method of claim 1. the semiconductor substrate has a p-type body layer (44);
the trench penetrates the body layer;
In the step of implanting inert ions into the first side surface, inert ions are implanted into the first side surface in a state in which the inclination angle of the implantation direction of the inert ions relative to the surface of the wafer in the cross section along the width direction of the trench is smaller than the inclination angle (θ96, θ196) of a straight line connecting an upper end of the second side surface and a lower end of the body layer on the first side surface in the cross section relative to the surface of the wafer;
In the step of implanting inert ions into the second side surface, the inert ions are implanted into the second side surface in a state in which the inclination angle of the implantation direction of the inert ions with respect to the surface of the wafer in the cross section along the width direction of the trench is smaller than the inclination angle (θ86, θ186) of the straight line connecting the upper end of the first side surface and the lower end of the body layer on the second side surface with respect to the surface of the wafer in the cross section.
The method according to any one of claims 1 to 3.