JP7796567B2 - Exposure apparatus and method for creating wiring patterns - Google Patents

Description

The present invention relates to wiring patterning in the manufacturing process of semiconductor packages, and in particular to wiring patterning in wafer-level semiconductor packaging technology (Wafer-Level-Package, hereafter referred to as WLP).

In WLP, electronic components such as semiconductor chips (hereafter referred to as ICs or dies) and passive components are placed on a temporary support substrate, which is then sealed with resin and then RDL (Redistribution Layer) wiring is applied. The semiconductor package is then obtained by dicing (this process is called mold-first (chip-first) WLP).

For example, FI (Fan-In)-WLP, which routes the die's I/O terminals to the BGA (Ball Grid Array) placement location that can be mounted on a motherboard, is known, while FO (Fan-Out)-WLP, which virtually expands the area around the die with resin for RDL routing, is known. FO-WLP packages multiple semiconductor chips (Multi Chip FO-WLP), enabling the realization of a SiP (System in Package) that integrates and modularizes various electronic devices such as semiconductor chips and passive components.

In mold-first WLP, random misalignment occurs in individual semiconductor chips relative to their reference design positions. Therefore, the wiring pattern data created in CAD/CAM format must be corrected accordingly.

For example, the wiring pattern to connect to external electrodes in accordance with a misaligned semiconductor chip is determined based on a netlist included in the design information, and wiring pattern data is generated (see Patent Document 1). Furthermore, the wiring pattern defined for a region (zone) determined according to the semiconductor chip size, etc., is reconverted (resampled) (see Patent Document 2).

Patent No. 5779145 Patent No. 5767255

The misalignment of individual semiconductor chips must be measured by taking photos with a camera before exposure. Therefore, the task of redesigning the wiring pattern after measurement takes time. In particular, with the increasing demand for multi-layered substrates and SiP using FO-WLP, the data correction process for wiring patterns takes a significant amount of time, affecting throughput.

Therefore, there is a need for wiring patterning that can minimize throughput degradation in semiconductor package manufacturing processes, etc.

The exposure apparatus of the present invention can pattern wiring such as RDL wiring in semiconductor package manufacturing processes such as WLP. For example, it can be applied to exposure processes in SiP using FI-WLP, FO-WLP, multi-chip FO-WLP, etc. RDL wiring patterning can also be performed on single-layer or multi-layer RDL.

The exposure apparatus of the present invention can perform wiring patterning based on an intra-area wiring pattern formed in a wiring area that is the size of a die (semiconductor chip) placed on a support substrate or is larger than the die, and an extra-area wiring pattern that is connected by design to the intra-area wiring pattern and connects to adjacent dies or electronic components. The wiring pattern is created in advance as vector data in, for example, CAD/CAM format and input into the exposure apparatus.

The support substrate may be any substrate that can be configured as a temporary substrate, and its shape is not limited to wafer-like (including rectangular panels), as long as it can accommodate the arrangement of dies. For example, a pseudo-wafer with dies sealed in a mold can be configured as the temporary support substrate. Furthermore, a wiring area larger than the die size can be defined as a rectangular area scaled (enlarged) to match the rectangular shape of the die, or it can be of any other shape, as long as it is configured as an area that encompasses the die. Electronic components include external electrodes, passive components, etc., and can be defined as elements that can be electrically connected to the die.

Intra-area wiring patterns include, for example, RDL wiring in areas expanded by resin or the like in FO-WLP, and RDL wiring in FI-WLP. Out-of-area wiring patterns include, for example, in the case of FO-WLP, wiring patterns that connect intra-area wiring patterns formed in the expanded areas of adjacent dies. They also include wiring patterns that connect intra-area wiring patterns formed in the expanded areas to electronic components such as external electrodes. Meanwhile, wiring patterns can be configured as either a single wire or a pattern consisting of multiple wires. For example, in the case of FO-WLP, the intra-area wiring pattern and extra-area wiring pattern that connect adjacent dies can be configured as a wiring group consisting of multiple wires.

The exposure apparatus of the present invention includes an exposure data generation unit that converts these intra-area wiring patterns and extra-area wiring patterns into raster data and generates exposure data. The exposure data can be configured as data capable of driving the light modulation elements of the exposure apparatus. For example, in the case of an exposure apparatus equipped with a light modulation element array such as a DMD, it is possible to generate exposure data that controls the ON/OFF of light modulation elements such as micromirrors. The exposure data generation unit can convert overall pattern data, including the intra-area wiring pattern and extra-area wiring pattern along with other patterns (other wiring patterns, patterns other than wiring, etc.), into raster data and generate it as exposure data. Alternatively, the exposure data generation unit can distinguish the intra-area wiring pattern and extra-area wiring pattern from other patterns and perform raster conversion to generate exposure data. It is also possible to include the intra-area wiring pattern in other patterns while converting the extra-area wiring pattern into raster data as separate data.

The exposure apparatus of the present invention also includes a positional deviation measurement unit that measures the positional deviation of the die relative to a reference position. The reference position can be set, for example, to a representative position of the die determined by design (e.g., the center position). The measurement unit can measure, for example, the degree of positional deviation (positional deviation amount). The positional deviation amount can be measured as the deviation between the coordinates measured when the support substrate is placed on a stage or the like and the designed coordinates. It is also possible to measure rotational deviation relative to the center position of the die as a positional deviation.

In the present invention, the exposure data generation unit generates a supplemental wiring pattern that connects the intra-area wiring pattern and the out-of-area wiring pattern, whose ends are separated due to the correction of the formation position of the intra-area wiring pattern in accordance with the die misalignment. The formation position, wiring shape, etc. of the out-of-area wiring pattern may be corrected in accordance with the die misalignment, or the formation position may not be corrected. The shape, length, line width, etc. of the supplemental wiring pattern can be determined in accordance with the corrected formation position of the intra-area wiring pattern.

The exposure data generation unit can be configured as a circuit including, for example, a raster conversion circuit, and may also include circuits that perform misalignment correction processing, circuits that perform data synthesis processing, and the like. Furthermore, the exposure data generation unit is not limited to specifications or configurations such as hardware, software, or firmware. There are various ways to generate the intra-area wiring pattern, extra-area wiring pattern, and supplementary wiring pattern. For example, the exposure data generation unit can separately convert the intra-area wiring pattern and extra-area wiring pattern, whose formation positions have been corrected, from CAD/CAM format data (vector data) to raster data, while generating the supplementary wiring pattern as raster data. Alternatively, the supplementary wiring pattern may be generated as vector data and then converted to raster data.

Correction of the formation position of the intra-area wiring pattern, conversion of the corrected intra-area wiring pattern and the out-of-area wiring pattern to raster data, and generation of the supplementary wiring pattern can be performed according to the measurement of the die misalignment. Furthermore, the raster data conversion process for the intra-area wiring pattern can be performed in advance by creating standard exposure raster data before the start of exposure, and then performing raster conversion along with the correction process. For example, the exposure data generation unit can determine the block that contains the intra-area wiring pattern and create standard exposure raster data based on the position coordinate data of the input block.

Raster conversion processing can also be performed on the outside-area wiring patterns in a similar manner. For example, the exposure data generation unit can correct the pattern formation position and perform scaling correction on the outside-area wiring patterns in accordance with the inside-area wiring patterns whose formation positions have been corrected. Scaling correction here includes scaling (reduction or enlargement) along the wiring length direction. Then, in accordance with the generation of the supplementary wiring patterns, the exposure device performs exposure operations based on exposure data that combines the inside-area wiring patterns, outside-area wiring patterns, and supplementary wiring patterns.

The wiring width and shape of the supplementary wiring pattern vary. For example, the exposure data generation unit can form an arc-shaped pattern as the supplementary wiring pattern. Here, arc-shaped patterns include not only arcs with a strictly constant radius of curvature, but also patterns that are roughly arc-shaped. For example, if the intra-area wiring pattern and the extra-area wiring pattern are configured as a wiring group consisting of multiple wires, the exposure data generation unit can generate an arc-shaped pattern, taking into consideration that the wiring width, wiring spacing, overall wiring width, etc. will be maintained unchanged overall.

The exposure data generation unit can generate an arc-shaped filler wiring pattern by extracting a portion of the circular pattern. For example, the circular pattern data can be saved to memory at times such as when a lot changes, and the exposure data generation unit can generate an arc-shaped filler wiring pattern from the circular pattern through masking processing. For example, if the intra-area wiring pattern and the extra-area wiring pattern, which are used to connect adjacent dies, are configured as a wiring group consisting of multiple wires, a concentric wiring pattern with the same wiring width and spacing as the intra-area wiring pattern and the extra-area wiring pattern can be created in advance and saved in memory before exposure begins.

Another aspect of the present invention, a wiring pattern creation method, converts into raster data an intra-area wiring pattern formed in a wiring area the size of a die placed on a support substrate or larger than the die, and an out-area wiring pattern that is connected to the intra-area wiring pattern by design and connects to an adjacent die or electronic component. This method generates exposure data, measures the die misalignment with a reference position, and generates a supplemental wiring pattern that connects the intra-area wiring pattern and the out-area wiring pattern, the ends of which are separated due to the intra-area wiring pattern's formation position being corrected in accordance with the die misalignment. The die misalignment with a reference position can be measured using an exposure device. Furthermore, the supplemental wiring pattern can be generated as vector data or raster data. For example, in the exposure process for fan-out (FO)-wafer-level packaging (WLP), an exposure device can perform an exposure operation based on the wiring pattern created by the wiring pattern creation method of the present invention. As described above, various data processing techniques can be applied to the conversion to raster data and the generation of exposure data.

This invention enables wiring patterning that minimizes throughput degradation in semiconductor package manufacturing processes, etc.

1 is a block diagram of an exposure apparatus according to an embodiment of the present invention. FIG. 1 is a diagram showing a part of a semiconductor chip mounted on a support substrate (temporary substrate) in mold-first type FO-WLP. 10A and 10B are diagrams illustrating the formation of wiring patterns based on misalignment of semiconductor chips; FIG. 10 is a diagram showing a flow of data processing of a wiring pattern accompanied by alignment adjustment in a wafer-level exposure process. 1A and 1B are diagrams showing an intra-area wiring pattern, an extra-area wiring pattern, a supplementary wiring pattern, and a template pattern. FIG. 1 is a diagram showing pattern formation positions of intra-region wiring patterns on a substrate; 10A and 10B are diagrams showing a part of a method for generating a supplementary wiring pattern CD. 10A and 10B are diagrams showing a part of a method for generating a supplementary wiring pattern CD. 10A and 10B are diagrams showing correction of the pattern formation position and scaling correction for the outside-area wiring pattern BD; FIG. 10 is a diagram showing a wiring pattern obtained by combining an in-area wiring pattern, an out-of-area wiring pattern, and a supplementary wiring pattern.

The following describes an embodiment of the present invention with reference to the drawings.

Figure 1 is a block diagram of the exposure apparatus of this embodiment.

The exposure device 10 is capable of forming a circuit pattern by irradiating light onto a substrate B, and is configured here as a maskless exposure device equipped with multiple exposure heads 15 (only one exposure head is shown in Figure 1). The substrate B is mounted on a drawing table 12, and can be moved in the main scanning direction (X direction) and sub-scanning direction (Y direction) by a table drive mechanism 13. An X-Y coordinate system is defined on the drawing table 12.

The exposure head 15 includes a DMD (Digital Micro-mirror Device) 16 as well as an illumination optical system and an imaging optical system (not shown). Light emitted from a light source 20 (laser, discharge lamp, etc.) provided in the exposure device 10 is guided to the DMD 16 via the illumination optical system.

The DMD 16 is a light modulation element array in which tiny rectangular micromirrors (here, a few μm to a few tens of μm) are arranged two-dimensionally in a matrix. Depending on the exposure data, each micromirror is selectively positioned in either a first position (ON state) that reflects the beam from the light source 20 toward the substrate B, or a second position (OFF state) that reflects the beam toward a direction outside the exposure surface.

The rectangular projection area (hereinafter referred to as the exposure area) defined when all micromirrors are in the ON state moves relative to the substrate B as the imaging table 12 moves along the main scanning direction (X direction). However, in this case, the exposure head 15 is installed so that the exposure area is tilted at a predetermined small angle relative to the main scanning direction (X direction).

Light reflected by the micromirrors in the ON state is imaged on the exposure surface of substrate B as a pattern of light that corresponds to the relative position of the exposure area on substrate B. The entire substrate B is imaged by performing an exposure operation in which the pattern of light is projected while the imaging table 12 moves at a constant speed. Here, multiple exposures (overlapping exposures) are performed at a predetermined pitch.

The controller 30, which is connected to an external workstation or server (not shown), controls the operation of the exposure apparatus 10 and outputs control signals to each circuit, such as the light source driver 21. The program that controls the operation of the exposure apparatus 10 is stored in advance in ROM (not shown) within the controller 30. The drawing data (pattern data) input to the exposure apparatus 10 from a workstation or the like is vector data (coordinate data) configured in CAD/CAM format, and is input to the vector data processing circuit 31.

In the exposure device 10, raster data (hereinafter referred to as standard raster data for exposure) is created for some standard patterns of the drawing data input to the vector data processing circuit 31, and stored in memory 39 before exposure begins. Other drawing data (vector data) is converted to raster data by the raster conversion circuit 26 and then sent to the composition circuit 40.

The correction circuit 33 is a raster data conversion processing circuit that processes standard pattern data that requires alignment adjustment and conversion to raster data, and outputs raster data based on the standard raster data for exposure stored in memory 39 to the composition circuit 40. As described below, the mask processing circuit 34 performs mask processing on the template data stored in memory 41, and then outputs the raster data (hereinafter referred to as filler raster data) to the composition circuit 40.

The combining circuit 40 combines the raster data output from the correction circuit 33 with the raster data output from the raster conversion circuit 26, and also combines it with the fill raster data output from the mask processing circuit 34. The standard raster data and fill raster data are combined according to the position of the exposure area during the exposure operation. The DMD driving circuit 35 drives and controls the DMD 16 based on the exposure data obtained by the combination, thereby performing the multiple exposure operation.

The camera 38 is installed so that it can capture an image of the substrate B placed on the drawing table 12, and is used during alignment adjustment. Exposure control such as image magnification, AF processing, and aperture adjustment for the camera 38 is performed by the camera control unit 36. The measurement circuit 37 detects the positions of feature points such as alignment marks based on the image data captured by the camera 38. The controller 30 performs alignment adjustment for the drawing data based on the amount of positional deviation, which is the difference between the position of the detected feature point and its reference position in the design.

Figure 2 shows a portion of a semiconductor chip mounted on a support substrate (temporary substrate) B in a mold-first FO-WLP. Figure 2 compares the design arrangement of the semiconductor chips SC (four in this case) with the semiconductor chips SC placed on the support substrate B while embedded in resin.

FO-WLP defines a wiring area D that is larger than the chip size of the semiconductor chip SC, and it is possible to form wiring patterns that connect to the chip terminals in a chip area (hereinafter referred to as the extended area) MD that is pseudo-extended by resin around the semiconductor chip SC. This makes it possible to achieve a pitch similar to the I/O terminal pitch of a BGA even for miniaturized semiconductor chips SC. It also makes it possible to form high-density wiring patterns between semiconductor chips SC that are not limited by wiring design rules, enabling the realization of even smaller SiPs with multi-chip mounting.

Due to the malleability of the resin, each semiconductor chip SC has a random amount of positional deviation from the design reference position. Therefore, if the design wiring pattern data is not corrected for the resin portion M, disconnections or short circuits will occur between adjacent semiconductor chips SC. For this reason, alignment adjustments are made before the exposure operation to correct the drawing data.

Figure 3 shows the formation of wiring patterns based on misalignment of semiconductor chips. In this embodiment, in wafer-level RDL wiring in the FO-WLP process, the wiring patterns connecting adjacent semiconductor chips are divided into two groups: wiring patterns AD (also called fan-out wiring patterns; hereafter referred to as intra-area wiring patterns) formed within the semiconductor chip SC and expansion region MD, and wiring patterns BD (hereafter referred to as extra-area wiring patterns) formed outside the wiring region D.

For the intra-region wiring patterns AD within the extension region MD, the pattern formation positions are corrected in accordance with the misalignment of the semiconductor chip SC (see symbol P'). Then, for the extra-region wiring patterns BD, the formation positions are corrected based on the corrected formation positions of the intra-region wiring patterns AD (see symbol P").

Furthermore, a wiring pattern (hereafter referred to as a supplementary wiring pattern) CD is generated to connect the ends of the intra-area wiring pattern AD and the extra-area wiring pattern BD, whose ends have become separated from each other due to the formation position correction, to compensate for this. This type of wiring pattern synthesis is also performed for connections between semiconductor chips and electronic components such as external electrodes and passive components. This is described in detail below using Figures 4 to 10.

Figure 4 shows the flow of data processing for wiring patterns involving alignment adjustment during a wafer-level exposure process. Figure 5 shows the intra-area wiring pattern AD, the extra-area wiring pattern BD, the supplementary wiring pattern CD, and the template pattern CO. For ease of explanation, the following will mainly describe data processing for wiring patterns that connect specific semiconductor chips.

When drawing data in CAD/CAM format is input to the exposure apparatus 10 from a workstation or the like, data for the intra-area wiring pattern AD and data for the extra-area wiring pattern BD are identified and extracted (S101). The intra-area wiring pattern AD is configured as design data, consisting of a group of wires extending from terminals and arranged in parallel at equal intervals, with each wire having the same line width W and the same distance (pitch) M between adjacent wires. In this example, it is configured as a five-wire pattern.

The outside-area wiring pattern BD is configured as a wiring group with the same line width W, wiring distance M, overall wiring width L, and the same number of wires (5) as the inside-area wiring pattern AD in design data. The inside-area wiring pattern AD and the outside-area wiring pattern BD are configured as wiring groups that extend in a straight line across the wiring area D defined by the FO-WLP (see Figure 3).

Here, blocks BL1 and BL2 are defined that surround the intra-area wiring pattern AD and the extra-area wiring pattern BD, respectively. The drawing data for the entire substrate input to the exposure apparatus 10 during the exposure process includes pattern data for block BL1 that surrounds the intra-area wiring pattern AD. Meanwhile, pattern data for block B2 that surrounds the extra-area wiring pattern BD is input separately from the drawing data. In addition, coordinate data for blocks BL1 and BL2 (here, position coordinate data for the block endpoints) is input separately.

Meanwhile, in the memory 41 of the exposure apparatus 10, a template pattern C0, which serves as a prototype for forming the above-mentioned supplementary wiring pattern (see Figure 3), is stored and registered as raster data in the memory 39. Template pattern C0 is configured as five concentric wiring patterns, matching the number of wires (five) in the intra-area wiring pattern AD and the extra-area wiring pattern BD.

The overall wiring width l, individual wiring width w, and wiring distance interval m of template pattern C0 are equal to the overall wiring width L, individual wiring width W, and wiring distance interval M determined for the intra-area wiring pattern AD and the extra-area wiring pattern BD. Data for template pattern C0 is input and saved in exposure tool 10, for example, for each lot.

Figure 5 shows a mask pattern MD used to extract a portion of the template pattern C0 and generate a fill wiring pattern CD. The mask pattern MD has a size that covers the entire template pattern C0 when its center D is aligned with the center C of the template pattern C0, and is configured as raster data that masks the area MA outside the area surrounded by a predetermined angle α from the center D, i.e., invalidates the data.

In the exposure apparatus 10, alignment measurement is performed by camera scanning in parallel with the data processing of the input drawing data described above. This measures the amount of positional deviation of each semiconductor chip on substrate B from its reference position (based on the design) (S102).

One method for calculating the amount of misalignment is to use image processing to extract the terminals (connection pads) of the semiconductor chip as feature points and then use template matching. Alternatively, alignment marks on the semiconductor chip can be measured. The amount of misalignment of the semiconductor chip can be calculated as the amount of misalignment from a reference position in the main scanning direction (X direction) and sub-scanning direction (Y direction), as well as the amount of rotational misalignment (angle (θ)) from the center position of the chip.

Figure 6 shows the pattern formation position of the intra-area wiring pattern AD on substrate B. As shown in Figure 6, the pattern formation position of the intra-area wiring pattern AD is corrected based on the detected positional deviation amount of each semiconductor chip SC. Because the semiconductor chip SC itself does not deform, when a boundary line D'L of the wiring area D is defined on substrate B, a process is executed to correct the X and Y positions and rotation angle so that the wiring group of the intra-area wiring pattern AD remains perpendicular to the boundary line D'L (S104).

Here, the pattern data of block BL1 surrounding the intra-region wiring pattern AD is treated as a standard pattern to be used for repeated exposure, and corrected standard raster data for exposure is output to the synthesis circuit 40 based on the amount of positional misalignment of each semiconductor chip SC described above.

The line width W, overall wiring width L, and wiring distance interval M are equal between the outside-area wiring pattern BD included in block BL2 and the inside-area wiring pattern AD included in block BL1. Furthermore, the overall wiring width l, individual wiring width w, and wiring distance interval m of template pattern C0 are also equal to the overall wiring width L, individual wiring width W, and wiring distance interval M.

Therefore, by extracting a portion of the template pattern C0 shown in Figure 5, an arc-shaped supplementary wiring pattern CD (see Figure 3) is generated, and the formation position of the outside-area wiring pattern BD of block BL2 is corrected and scaled along the length. This forms a wiring pattern that connects semiconductor chips that are misaligned.

First, a method for generating a supplemental wiring pattern CD will be explained using Figures 7 and 8. If the endpoints of the connection block B1 of one semiconductor chip SC are A1 and B1, and the endpoints of the connection block B1 of the adjacent semiconductor chip are A2 and B2, the two points that form the shortest distance between the block endpoints are found. In Figure 7, endpoints A1 and A2 are identified as the endpoints that create the shortest distance K. These endpoints A1 and A2 are used as placement reference points.

Then, a circle (arc) CA centered at the midpoint A0 between the placement reference points A1 and A2, and circles (arcs) CB1 and CB2 centered at the placement reference points A1 and A2 and passing through the block end points B1 and B2, respectively, are defined, and intersections C1 and C2 are found. A rectangular area G defined by connecting the block end point A1, intersection C1, block end point A2, and intersection C2 is given as the area for forming the outside-area wiring pattern BD. Rectangular area G is an area that touches the wiring areas of adjacent semiconductor chips at a single point.

Figure 8 shows the template pattern C0 and mask data MD superimposed on placement reference points (A1, A2). When the center D of the mask data MD is superimposed on the block end point A1, the area MA outside the area MG of the included angle α, surrounded by the line G1 connecting the block end point A1 and the block end point B1 and the line G2 connecting the block end point A1 and the intersection point C1, is defined as the masking area MA.

Then, by performing a masking process, a fill wiring pattern CD that fits within the area MG of the included angle α is generated (S104). Specifically, the data for area MA of the template pattern C0, which is raster data, is invalidated, and the raster data for the fill wiring pattern CD is output to the synthesis circuit 40.

The supplementary wiring pattern CD is formed at a position that is continuously connected to the corrected formation position of the intra-area wiring pattern AD. The radial distance t (see Figure 5) to the innermost wiring of the template pattern C0 is determined so that the connection from the intra-area wiring pattern AD to the supplementary wiring pattern CD is a continuous connection from a straight line to a circle.

For the other semiconductor chip SC, the block end point A2 is used as the placement reference point, and a similar masking process is performed to extract a supplementary wiring pattern CD. The shape of the supplementary wiring pattern CD follows the range of the non-masking area MG, i.e., the positions of the placement reference positions A1 and A2.

Figure 9 shows the correction of the pattern formation position and scaling correction for the outside-area wiring pattern BD. The formation position of the pattern data for block BL2 (see Figure 5) is corrected and scaling correction is performed to fit the rectangular area G defined by connecting block end point A1, intersection point C1, block end point A2, and intersection point C2 (S105).

Specifically, the pattern formation position is rotated so that the two endpoints b1 and b3 of block BL2 shown in Figure 5 coincide with the endpoints A1 and A2 of blocks BL1 and BL1', and a scaling correction is performed to change the block length E to E'. These correction processes are performed using vector data. The above corrections to the intra-area wiring pattern AD and extra-area wiring pattern BD, and the generation of the supplementary wiring pattern CD, are performed for each wiring pattern that connects semiconductor chips together.

The intra-area wiring pattern AD and the extra-area wiring pattern BD are converted into raster data through their respective correction processes, and then combined with the drawing data for the entire board, which has also been converted into raster data. The raster data for the supplementary wiring pattern generated by the masking process is then combined with the drawing data (S106). An exposure operation is performed using the exposure data obtained by the data combination (S107).

Figure 10 shows a wiring pattern that combines an intra-area wiring pattern AD, an extra-area wiring pattern BD, and a supplementary wiring pattern CD. As shown in Figure 10, a wiring pattern DD is formed across adjacent semiconductor chips SC, with the line width W, overall wiring width L, and wiring distance M remaining constant.

As described above, according to this embodiment, the amount of misalignment between semiconductor chips SC placed on a temporary substrate B and a reference position is measured during the FO-WLP exposure process. Based on the input drawing data, the wiring area D, which is larger than the chip size, is classified into an in-area wiring pattern AD of fan-out wiring formed in the expansion area MD around the chip, and an out-area wiring pattern BD formed in the resin between the wiring area D.

In response to the correction of the formation position of the in-area wiring pattern AD, the formation position and scaling correction for the outside-area wiring pattern BD are performed, and an arc-shaped filler wiring pattern CD is generated. The corrected inside-area wiring pattern AD, outside-area wiring pattern BD, and the generated arc-shaped filler wiring pattern CD are then combined as raster data.

In this embodiment, the RDL wiring pattern is corrected along the entire exposure process, from inputting the drawing data (vector data) to converting it to raster data, and then performing the exposure operation. Because the wiring pattern is not redesigned in the vector data, the impact on throughput can be minimized.

In particular, by generating an arc-shaped supplementary wiring pattern CD, it is possible to continuously connect the in-area wiring pattern AD and the out-of-area wiring pattern BD, which would otherwise become separated due to correction of the pattern formation position. In particular, since the two chips are connected without changing the line width W, overall wiring width L, or wiring distance M, changes in electrical characteristics such as impedance can be suppressed.

Because the supplementary wiring pattern CD is created based on the concentric template pattern C0, it is possible to generate an appropriate supplementary wiring pattern CD for semiconductor chips SC with individually different amounts of misalignment. Furthermore, in the FO-WLP exposure process, the wiring patterns connecting semiconductor chips are typically a group of multiple wiring patterns, but masking alone can smoothly connect and compensate for both ends of the wiring. Furthermore, because the masking process itself is fast, it does not significantly reduce throughput.

It is also possible to configure the system to generate filler wiring patterns other than arc-shaped ones, or to prepare and store filler wiring patterns of various shapes in advance, and apply a filler wiring pattern of an appropriate shape to connect wire ends that would otherwise be separated. Furthermore, for the out-of-area wiring pattern BD, the formation position may not be rotated, and only scaling correction may be performed. This method may be applied not only to the FO-WLP exposure process, but also to the FI-WLP exposure process. Furthermore, the above-mentioned exposure process may be applied to a laser scanning exposure device.

10 Exposure device 26 Raster conversion circuit 33 Correction circuit 37 Measurement circuit 38 Camera 40 Composition circuit AD In-area wiring pattern BD Out-area wiring pattern CD Complementary wiring pattern

Claims (8)

an exposure data generation unit that converts a linear intra-area wiring pattern formed in a wiring area that is the size of a die placed on a support substrate or is larger than the die, and a linear out-of-area wiring pattern that is connected to the intra-area wiring pattern in terms of design and connects to a die or electronic component adjacent to the die, into raster data and generates exposure data;
a positional deviation measurement unit that measures a positional deviation of the die relative to a reference position,
the exposure data generation unit corrects a formation position of the in-region wiring pattern with respect to the outside-region wiring pattern in accordance with the positional deviation of the die, and also performs a pattern formation position correction involving rotation and a scaling correction along the wiring length direction with respect to the outside-region wiring pattern in accordance with the positional deviation of the die;
the exposure data generating unit generates an arc-shaped supplementary wiring pattern that connects the corrected intra-region wiring pattern and the corrected outer-region wiring pattern, the ends of which are separated from each other, and then synthesizes the corrected intra-region wiring pattern, the corrected outer-region wiring pattern, and the generated supplementary wiring pattern to generate exposure data;
An exposure apparatus that performs an exposure operation based on the exposure data. 2. The exposure apparatus according to claim 1 , wherein the exposure data generation unit performs a correction process on the intra-area wiring pattern and the extra-area wiring pattern, which are vector data, and converts the data into raster data after the correction process . 3. The exposure apparatus according to claim 1, wherein the exposure data generating unit generates the supplementary wiring pattern by extracting a part of a circular pattern. 4. An exposure apparatus according to claim 3, wherein the exposure data generating unit generates the supplementary wiring pattern by a masking process. 5. An exposure apparatus according to claim 1, wherein the exposure data generating unit generates the supplementary wiring pattern as raster data . 6. An exposure apparatus according to claim 1, wherein the intra- area wiring pattern and the extra- area wiring pattern are configured as a wiring group in which a plurality of wirings are arranged. An exposure apparatus according to any one of claims 1 to 6, characterized in that it is used in an exposure process for FO (Fan-Out)-WLP (Wafer-Level Package). converting into raster data a linear intra-area wiring pattern formed in a wiring area having a size equal to or larger than the die to be placed on a support substrate, and a linear out-of-area wiring pattern that is connected to the intra-area wiring pattern in terms of design and connects to a die or electronic component adjacent to the die, and generating exposure data;
A method for creating a wiring pattern that measures a positional deviation of the die relative to a reference position, comprising:
correcting a formation position of the intra-region wiring pattern for the outside-region wiring pattern in accordance with the positional deviation of the die, and performing a pattern formation position correction involving rotation and a scaling correction along the wiring length direction for the outside-region wiring pattern in accordance with the positional deviation of the die;
a wiring pattern creating method comprising: generating an arc-shaped supplementary wiring pattern that connects the corrected intra -region wiring pattern and the corrected outside -region wiring pattern, the ends of which are separated from each other; and generating exposure data by combining the corrected intra-region wiring pattern, the corrected outside-region wiring pattern, and the generated supplementary wiring pattern.