JP7798538B2 - Display driver and display device - Google Patents

Description

The present invention relates to a display driver that drives a display panel in response to a video signal, and a display device that includes the display driver.

In recent years, vehicles have begun to appear that are equipped with display panels such as liquid crystal display panels and organic EL (Electro Luminescence) display panels, not only for car navigation but also for various electronic instruments.

However, if the display panel malfunctions while the vehicle is in motion and displays an incorrect message, this could cause problems while driving.

In response, a liquid crystal display device has been proposed that includes a fault detection circuit that checks whether a fault has occurred in the display panel during normal use and, if a fault is detected, warns the vehicle occupants of the fault (see, for example, Patent Document 1).

The fault inspection circuit supplies a monitor input signal to one end of each of the multiple source lines of the liquid crystal display panel and compares the monitor output signal output from the other end with a predetermined expected value to detect short and open abnormalities in the source lines. Therefore, the fault inspection circuit includes a monitor signal line connected individually to one end of each source line for inputting a monitor input signal for fault inspection, and a comparison circuit that compares the monitor output signal output from the other end of each source line with a predetermined expected value.

WO2018/079636 publication

However, the fault testing described in Patent Document 1 determines whether a short circuit or open circuit has occurred in the source line of a display panel by comparing the magnitude of an expected value as a threshold value, making it difficult to accurately detect faults such as minute current leaks. Furthermore, the fault testing circuit described in Patent Document 1 has a switch connected to the other end of the source line for extracting the monitor output signal described above, which creates the problem of an increased output load on the amplifier that outputs a drive voltage to the source line due to the amount of this switch element.

The present invention aims to provide a display driver and display device that can accurately detect faults occurring in the display panel without increasing the output load.

The display driver of the present invention comprises an amplifier circuit that receives a grayscale voltage having a voltage value corresponding to the brightness level indicated by a video signal and outputs an output current based on the grayscale voltage to a source line of a display panel, thereby supplying an output voltage having a voltage value corresponding to the grayscale voltage to the source line; an output current detection circuit that generates a mirror current that copies the output current and outputs an output current detection signal having a level corresponding to the current amount of the mirror current; and a circuit that determines whether a short circuit fault or current leak fault has occurred in the source line by comparing the level of the output current detection signal output from the output current detection circuit with a predetermined threshold. and a fault determination circuit for detecting the difference between the gradation voltage and the output voltage, wherein the amplifier circuit includes a differential section that generates a differential signal representing the difference between the gradation voltage and the output voltage, and a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected, and the output current detection circuit includes a second transistor that receives the differential signal at its gate and outputs the mirror current from a second output node to which its drain is connected, and a variable resistor that is connected to the second output node and generates the output current detection signal at the second output node when the mirror current flows into it.

The display driver according to the present invention also includes first to nth amplifier circuits that receive first to nth (n is an integer of 2 or greater) grayscale voltages, each having a voltage value corresponding to the brightness level of each pixel indicated by a video signal, generate first to nth output currents corresponding to the amount of change in the voltage value of each of the first to nth grayscale voltages, and output the generated first to nth output currents to first to nth source lines of the display panel, respectively, thereby supplying first to nth output voltages having voltage values corresponding to the first to nth grayscale voltages, respectively, to the first to nth source lines; first to nth output current detection circuits that generate first to nth mirror currents that are copies of the first to nth output currents, respectively, and output first to nth output current detection signals having levels corresponding to the current amounts of the first to nth mirror currents; and a fault determination circuit that determines whether the first to nth source lines have a short-circuit fault or a current leakage fault based on the first to nth output current detection signals output from the output current detection circuits, wherein each of the first to nth amplifier circuits includes a differential section that generates a differential signal representing the difference between the gradation voltage and the output voltage, and a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected, and each of the first to nth output current detection circuits includes a second transistor that receives the differential signal at its gate and outputs the mirror current from a second output node to which its drain is connected, and a variable resistor that is connected to the second output node and receives the mirror current flowing into it to generate the output current detection signal at the second output node.

The display device according to the present invention comprises a display panel in which display cells are arranged at each intersection of first to nth (n is an integer of 2 or greater) source lines and a plurality of gate lines, and a display driver that drives the display panel in response to a video signal. The display driver receives first to nth gradation voltages, each having a voltage value corresponding to the brightness level of each pixel indicated by the video signal, and generates first to nth output currents corresponding to the amount of change in the voltage value of the gradation voltage for each of the first to nth gradation voltages, and supplies the generated first to nth output voltages to the first to nth source lines. The display driver also comprises first to nth output current detection circuits that generate first to nth mirror currents by copying the first to nth output currents, respectively, and output first to nth output current detection signals having levels corresponding to the current amounts of the first to nth mirror currents. and a fault determination circuit that individually determines whether a short-circuit fault or a current leak fault has occurred in the first to nth source lines by comparing the levels of the first to nth output current detection signals output from the output current detection circuit with respective predetermined thresholds. Each of the first to nth amplifier circuits includes a differential section that generates a differential signal representing the difference between the gradation voltage and the output voltage, and a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected. Each of the first to nth output current detection circuits includes a second transistor that receives the differential signal at its gate and outputs the mirror current from a second output node to which its drain is connected, and a variable resistor that is connected to the second output node and receives the mirror current flowing into it to generate the output current detection signal at the second output node.

The display driver according to the present invention also includes first to nth amplifier circuits that receive first to nth (n is an integer of 2 or greater) grayscale voltages, each having a voltage value corresponding to the brightness level of each pixel indicated by a video signal, generate first to nth output currents corresponding to the amount of change in the voltage value of each of the first to nth grayscale voltages, and output the generated first to nth output currents to first to nth source lines of a display panel, respectively, thereby supplying first to nth output voltages having voltage values corresponding to the first to nth grayscale voltages, respectively, to the first to nth source lines; a failure determination circuit that determines whether the first to nth source lines have a short-circuit failure or a current leakage failure; and common wiring connected to each of the first to nth amplifier circuits, and each of the first to nth amplifier circuits determines whether the first to nth amplifier circuits are short-circuited or short-circuited. a differential section that generates a differential signal representing the difference between the first and nth source lines; a first transistor that receives the differential signal at its gate and outputs the output current from its drain; and a second transistor that receives the differential signal at its gate and outputs a mirror current that is a copy of the output current output from the first transistor to the common wiring. The fault determination circuit includes a variable resistor connected to the common wiring and that generates an output current detection signal on the common wiring when a current that is a combination of the mirror currents output from the second transistors of the first to nth amplifier circuits flows through the common wiring; and a comparator that compares the level of the output current detection signal with a predetermined threshold to determine whether a short circuit or current leak failure has occurred in the first to nth source lines.

The display driver according to the present invention receives first to nth (n is an integer of 2 or more) grayscale voltages, each having a voltage value corresponding to the brightness level of each pixel indicated by a video signal, generates first to nth output currents corresponding to the amount of change in the voltage value of each of the first to nth grayscale voltages, and outputs the generated first to nth output currents to first to nth source lines of the display panel, respectively, thereby generating first to nth output voltages having voltage values corresponding to the first to nth grayscale voltages. a fault determination circuit that determines whether the first to n-th source lines have a short-circuit fault or a current leakage fault; and first to k-th common wirings that are individually connected to the first to k-th amplifier circuit groups, where the first to n-th amplifier circuits are divided into first to k-th amplifier circuit groups (k is an integer equal to or greater than 2 and less than n), each of which includes at least one amplifier circuit, and each of the first to n-th amplifier circuits generates a differential signal that represents a difference between the grayscale voltage and the output voltage. a differential section having a first transistor receiving the differential signal at its gate and outputting the output current from its drain; and a second transistor receiving the differential signal at its gate and outputting a mirror current, which is a copy of the output current output from the first transistor, to one of the first to kth common wirings to which the amplifier circuit group to which it belongs is connected. The fault determination circuit includes a multiplexer that selects the first to kth common wirings one by one and connects the selected common wiring to an output node, a variable resistor connected to the output node and that generates an output current detection signal at the output node when a current composed of the mirror currents output from the second transistors of each of the amplifier circuits flows via the one common wiring, the multiplexer, and the output node, and a comparator that compares the level of the output current detection signal with a predetermined threshold to determine whether a short circuit fault or a current leak fault has occurred in the first to nth source lines.

The present invention provides a display driver that includes an amplifier circuit that supplies an output voltage to a source line of a display panel by outputting an output current based on a gradation voltage corresponding to the brightness level indicated by a video signal to the source line, and includes the following output current detection circuit and failure determination circuit that detect short-circuit or current leakage failures in the source line of the display panel.

The output current detection circuit generates a mirror current that is a copy of the output current output by the amplifier circuit to the source line, and obtains an output current detection signal that represents this mirror current. The fault determination circuit compares the level of the output current detection signal with a predetermined threshold to determine whether a short circuit fault or current leakage fault has occurred in the source line.

Here, the output current detection circuit includes a transistor that generates the above-mentioned mirror current by receiving at its gate a differential signal that represents the difference between the gradation voltage and the output voltage, which is generated in the differential section of the amplifier circuit, and a variable resistor that generates the above-mentioned output current detection signal by the flow of this mirror current and adjusts the level of this output current detection signal.

Therefore, by adjusting the level of the output current detection signal using the variable resistor to match the amount of current leakage expected due to the size of the display panel, the length and material of each source line, etc., it is possible to perform highly accurate fault detection using a specified threshold value regardless of the amount of current leakage.

As a result, even if the amount of current leakage occurring in the source line of the display panel is minute, it is possible to accurately detect this as a fault.

Furthermore, the output current detection circuit generates a mirror current that copies the output current output by the amplifier circuit based on the differential signal generated by the differential section of the amplifier circuit, and generates an output current detection signal that indicates the change in the amount of output current based on this mirror current.

This eliminates the need to connect current detection switches, resistors, or other elements to the amplifier circuit's output node, making it possible to detect short circuit or current leakage faults in the display panel's source lines without increasing the output load.

FIG. 1 is a block diagram showing a configuration of a display device 100. 4A and 4B are waveform diagrams showing examples of waveforms of a data capture signal LOAD and a strobe signal STB. 2 is a block diagram showing an example of the internal configuration of a source driver 13. FIG. FIG. 2 is a circuit diagram showing the internal configuration of an amplifier AMI. 10A and 10B are diagrams showing operational waveforms in an amplifier AM1 when a short circuit fault or a current leakage fault occurs in a source line S1 of a display panel 20 and when no such fault occurs. FIG. 13 is a circuit diagram showing an example of the internal configuration of a failure determination circuit 1330. FIG. 10 is a block diagram showing another example of the internal configuration of the source driver 13. FIG. 2 is a circuit diagram showing the internal configuration of an amplifier AXI. FIG. 13 is a circuit diagram showing an example of the internal configuration of a failure determination circuit 1330A. FIG. 10 is a block diagram showing yet another example of the internal configuration of the source driver 10. FIG. 13 is a circuit diagram showing an example of the internal configuration of a failure determination circuit 1330B.

Embodiments of the present invention will be described in detail below with reference to the drawings.

Figure 1 is a block diagram showing the configuration of a display device 100 including a display driver according to the present invention.

The display device 100 has a drive control unit 11, a gate driver 12, a source driver 13, and a display panel 20.

The display panel 20 is, for example, a liquid crystal or organic electroluminescence (EL) panel. The display panel 20 has gate lines G1 to Gm (m is an integer of 2 or greater) that extend horizontally on the two-dimensional screen and source lines S1 to Sn (n is an integer of 2 or greater) that extend vertically on the two-dimensional screen, arranged to intersect with each other. Display cells PC, made of liquid crystal or organic EL elements, are formed at the intersections of the gate lines and source lines.

The drive control unit 11 receives the video signal VS, generates a scanning signal in accordance with the horizontal synchronization signal contained in the video signal VS, and supplies this to the gate driver 12.

In addition, the drive control unit 11 generates a video data signal VPD containing a series of display data fragments representing the brightness level of each pixel, for example in 8 bits, based on the video signal VS, and various control signals including a data load signal LOAD, and supplies these to the source driver 13.

As shown in Figure 2, the data load signal LOAD is a binary (logical levels 0 and 1) pulse signal with the same period (1H) as the horizontal synchronization signal.

Furthermore, the drive control unit 11 takes in the fault location data signal FLD supplied from the source driver 13 at predetermined intervals. The fault location data signal FLD is a signal that indicates the fault location when a fault occurs in the display panel 20. When the fault location data signal FLD indicates the fault location, the drive control unit 11 executes display control or audio output control to notify the user that a fault has occurred in that fault location.

The gate driver 12 generates scanning pulses in response to the scanning signals supplied from the drive control unit 11 and applies them sequentially to the gate lines G1 to Gn of the display panel 20.

The source driver 13 captures a series of display data fragments contained in the video data signal VPD in response to the data capture signal LOAD. Here, each time the source driver 13 captures one horizontal scan line, i.e., n display data fragments, it generates output voltages GV1 to GVn, each having a voltage value corresponding to the brightness level represented by each display data fragment. The source driver 13 then supplies the output voltages GV1 to GVn to the source lines S1 to Sn of the display panel 20.

Furthermore, the source driver 13 detects any faults occurring in the source lines S1 to Sn of the display panel 20 and supplies a signal indicating the fault location to the drive control unit 11 as the above-mentioned fault location data signal FLD.

Figure 3 is a block diagram showing an example of the internal configuration of the source driver 13.

As shown in Figure 3, the source driver 13 includes a data latch unit 131, a decoder unit 132, and an output amplifier unit 133.

The data latch unit 131 captures a series of display data fragments corresponding to each pixel contained in the video data signal VPD, for example, at the timing of the front edge of the data capture signal LOAD.

Then, each time the data latch unit 131 captures n pieces of display data for one horizontal scanning period, it supplies them as display data J1 to Jn to the decoder unit 132, timing them, for example, at the front edge of the data capture signal LOAD.

For each piece of display data J1 to Jn, the decoder unit 132 selects a gradation voltage corresponding to the brightness level indicated by that display data Jq (q is an integer from 1 to n) from, for example, 256 gradation voltages having mutually different voltage values. The decoder unit 132 then supplies the n gradation voltages selected as described above based on the display data J1 to Jn to the output amplifier unit 133 as gradation voltages V1 to Vn.

The output amplifier section 133 includes amplifiers AM1 to AMn provided corresponding to the source lines S1 to Sn of the display panel 20, respectively, and a fault determination circuit 1330.

Amplifiers AM1 to AMn receive grayscale voltages V1 to Vn and amplify each individually to generate output voltages GV1 to GVn having voltage values corresponding to the voltage values of each grayscale voltage. Source lines S1 to Sn of the display panel 20 are connected to external terminals TM1 to TMn, respectively. Amplifiers AM1 to AMn supply the generated output voltages GV1 to GVn to the source lines S1 to Sn via external terminals TM1 to TMn.

Furthermore, amplifiers AM1 to AMn detect the output current sent to each of source lines S1 to Sn, and supply output current detection signals f1 to fn representing the amount of output current for each of source lines S1 to Sn to the fault determination circuit 1330.

Note that amplifiers AM1 to AMn have the same internal configuration. Therefore, the following describes the internal configuration of amplifier AM1, selected from amplifiers AM1 to AMn.

Figure 4 is a circuit diagram showing an example of the internal configuration of amplifier AM1.

As shown in Figure 4, amplifier AM1 includes an amplifier circuit 1331 and an output current detection circuit 1332.

The amplifier circuit 1331 is, for example, a voltage follower operational amplifier, and has a differential section DC, a P-channel MOS output transistor Q1, and an N-channel MOS output transistor Q2.

The differential unit DC receives the output voltage GV1 output from the amplifier circuit 1331 and the above-mentioned gradation voltage V1, and generates a differential signal PG having a level corresponding to the difference between the two voltage values. The differential unit DC supplies the generated differential signal PG via node nd0 to the gate of transistor Q1, which serves as the positive output transistor, and to the output current detection circuit 1332. Furthermore, the differential unit DC inverts the phase of the differential signal PG to generate an inverted differential signal NG, which is supplied to the gate of transistor Q2, which serves as the negative output transistor.

That is, when the grayscale voltage V1 is higher than the output voltage GV1, i.e., when the output voltage rises, the differential unit DC generates a differential signal PG whose level increases as the difference between the two increases. Furthermore, when the grayscale voltage V1 is lower than the output voltage GV1, i.e., when the output voltage falls, the differential unit DC generates an inverted differential signal NG whose level increases as the difference between the two increases.

The power supply potential is applied to the source of transistor Q1, and the drain is connected to the drain of transistor Q2 and external terminal TM1 via output node nd1. The ground potential is applied to the source of transistor Q2.

Transistor Q1 generates an output current Iout corresponding to the differential signal PG received at its gate and sends this to external terminal TM1 via output node nd1. Transistor Q2 extracts a current (called the extraction current) corresponding to the inverted differential signal NG received at its gate from output node nd1. As a result of this operation, an output voltage GV1 having a voltage value corresponding to the input gradation voltage V1 is generated at output node nd1 and external terminal TM1.

For example, as shown in FIG. 4, the external terminal TM1 connected to the amplifier circuit 1331 included in amplifier AM1 is connected to the source line S1 of the display panel 20. Therefore, amplifier AM1 supplies the output voltage GV1 generated as described above to the source line S1 of the display panel 20. Similarly, the external terminal TMj connected to the amplifier circuit 1331 included in amplifier AMj (j is an integer from 2 to n) is connected to the source line Sj of the display panel 20, and supplies the output voltage GVj generated by each to the source line Sj.

The output current detection circuit 1332 detects the output current output to the source line connected to the amplifier circuit 1331 and generates an output current detection signal that represents the amount of that output current as a voltage value level. For example, the output current detection circuit 1332 included in amplifier AM1 detects the output current Iout that the amplifier circuit 1331 sends to the source line S1 and generates an output current detection signal f1 that represents the amount of that current as a voltage value level. Similarly, the output current detection circuit 1332 included in amplifier AMj (j is an integer from 2 to n) detects the output current that the amplifier circuit 1331 sends to the source line Sj and generates an output current detection signal fj that represents the amount of that current as a voltage value level.

As shown in Figure 4, the output current detection circuit 1332 includes a P-channel MOS transistor QS, a resistor RG1, and a variable resistor R1.

The power supply potential is applied to the source of transistor QS, and the differential signal PG is supplied to its gate via node nd0. In other words, like transistor Q1, transistor QS receives the differential signal PG generated by the differential section DC at its gate. The drain of transistor QS is connected to one end of variable resistor R1 via output node nd2. The ground potential is applied to the other end of variable resistor R1, and its resistance value can be changed using the adjustment value held in register RG1.

With this configuration, transistor QS generates a current corresponding to the differential signal PG received at its gate - in other words, a mirror current corresponding to the output current output by transistor Q1 of amplifier circuit 1331 - and sends this to variable resistor R1 via output node nd2. As a result, the mirror current flows into variable resistor R1, generating a voltage signal at output node nd2, which is generated as output current detection signal f, whose voltage level indicates the change in the amount of output current sent to the source line. In other words, the mirror current flows into variable resistor R1, and an output current detection signal that changes depending on the amount of this flow is provided to output node nd2.

As a result, the output current detection circuits 1332 included in each of the amplifiers AM1 to AMn supply the fault determination circuit 1330 with output current detection signals f1 to fn, which individually represent the amount of output current sent to each of the source lines S1 to Sn.

The level of each of the output current detection signals f1 to fn can be adjusted by the variable resistor R1 using the adjustment value stored in register RG1. For example, taking into account the increase in output current due to current leakage that is expected when the source line of the display panel 20 is short-circuited with the gate line, the adjustment value is stored in advance in register RG1 so that the fault determination circuit 1330 can determine this current increase as a fault.

The fault determination circuit 1330 determines whether a short circuit fault or current leakage fault has occurred in the source lines S1 to Sn of the display panel 20 based on the output current detection signals f1 to fn, and generates a fault location data signal FLD that indicates the source line in which the fault has occurred.

Specifically, as shown in FIG. 2, at time t1, a predetermined period DL has elapsed since time t0 of the front edge of the data capture signal LOAD, the fault determination circuit 1330 compares the level of the output current detection signal with a predetermined threshold value Vth for fault determination. If the level of the output current detection signal is greater than threshold value Vth, the fault determination circuit 1330 determines that a short-circuit fault or current leakage fault has occurred in the source line corresponding to this output current detection signal. On the other hand, if the level of the output current detection signal is equal to or less than threshold value Vth, the fault determination circuit 1330 determines that a short-circuit fault or current leakage fault has not occurred in the source line corresponding to this output current detection signal. The fault determination circuit 1330 then generates a fault location data signal FLD that individually indicates the determination results obtained by performing the above-mentioned determination process for each output current detection signal.

The fault detection operations of the amplifier circuit 1331, output current detection circuit 1332, and fault detection circuit 1330 described above will be explained below with reference to Figures 4 and 5.

Note that Figure 5 is a diagram showing the operating waveforms within amplifier AM1 shown in Figure 4, divided into cases where a short circuit or current leakage failure occurs in source line S1 of display panel 20 and where it does not. Figure 5 also shows the operating waveforms when the grayscale voltage V1 received by amplifier AM1 transitions from a voltage value of 0 to a voltage value Va at the timing of the leading edge of data capture signal LOAD (time t0).

[If there is no malfunction]
As shown in FIG. 5 , when the gradation voltage V1 transitions from zero to Va (Va > 0) at time t0, the differential section DC of the amplifier circuit 1331 sends a differential signal PG having a difference (0-Va) between the output voltage GV1 and the gradation voltage V1 to node nd0. In response to this differential signal PG, the transistor Q1 turns on and sends an output current Iout corresponding to the difference (0-Va) to the source line S1. This causes the voltage on the source line S1, i.e., the voltage value of the output voltage GV1, to gradually increase. As a result, the difference between the gradation voltage V1 and the output voltage GV1 gradually decreases, and the voltage value of the differential signal PG gradually returns to Vb, thereby decreasing the output current Iout. After that, when the voltage value of the output voltage GV1 reaches Va, the voltage value of the gradation voltage V1, the voltage value of the differential signal PG becomes Vb, which transitions the transistor Q1 to the off state. Therefore, when the transistor Q1 is turned off, the output current Iout also becomes zero.

During this time, transistor QS of output current detection circuit 1332 sends a mirror current Imr, which is a copy of output current Iout, to variable resistor R1 via output node nd2 as shown in Figure 5. As a result, a signal representing the change in the amount of current in mirror current Imr as a change in voltage value is generated on output node nd2, i.e., an output current detection signal f1 representing the change in the amount of current in output current Iout shown in Figure 5 is generated.

Here, if there is no short circuit or current leakage failure in the source line S1 of the display panel 20, the output current Iout will be zero at time t1, a predetermined period DL after time t0, as shown in Figure 5. At this time, the mirror current Imr, which is a copy of the output current Iout, will also be zero at time t1, and the level of the output current detection signal f1 corresponding to the mirror current Imr at time t1 will be a voltage value Vx, which indicates a current of zero, as shown in Figure 5.

As shown in FIG. 5, since the level of the output current detection signal f1 at time t1 is equal to or lower than the predetermined threshold Vth (shown by the dashed line in FIG. 5), the fault determination circuit 1330 generates a fault location data signal FLD indicating that there is no short-circuit fault or current leakage fault for the source line S1.

[If there is a malfunction]
Even if a short circuit or current leakage fault occurs in the source line S1, when the grayscale voltage V1 transitions from a voltage value of zero to a voltage value Va at time t0, the differential section DC of the amplifier circuit 1331 sends a differential signal PG having a difference value (0-Va) between the output voltage GV1 and the grayscale voltage V1 to node nd0. In response to this differential signal PG, the transistor Q1 turns on and sends an output current Iout corresponding to this difference value (0-Va) to the source line S1. This causes the voltage on the source line S1, i.e., the voltage value of the output voltage GV1, to gradually increase. As a result, the difference value gradually increases, and the voltage value of the differential signal PG also gradually increases, and as the voltage value of the differential signal PG increases, the output current Iout decreases.

In this case, if the source line S1 is shorted to at least one of the gate lines G1-Gn, such as gate line G2 as shown in Figure 4, the output current Iout flows not only through the source line S1 but also through the gate line G2. In other words, a portion of the output current Iout leaks into gate line G2 as a leakage current. Therefore, because both the source line S1 and the gate line G2 are charged by the output current Iout, the increase in the output voltage GV1 is slower than when there is no short-circuit fault in the source line S1. As a result, as shown in Figure 5, at time t1, the voltage value of the output voltage GV1 does not reach Va, the voltage value of the gradation voltage V1, but remains at Vc, which is lower than Va. Therefore, the difference between the output voltage GV1 and the gradation voltage V1 (Vc - Va) does not become zero. Therefore, as shown in Figure 5, the voltage value of the differential signal PG corresponding to this difference does not reach Vb, which is the voltage value that can transition transistor Q1 to the off state. Therefore, transistor Q1 remains on even at time t1, and outputs output current Iout having a current amount Ib corresponding to the difference value (Vc - Va) represented by differential signal PG, as shown in Figure 5. As a result, the level of output current detection signal f1 at time t1, which corresponds to mirror current Imr, a copy of output current Iout, becomes current amount Vy, which is higher than voltage value Vx representing zero current amount, as shown in Figure 5.

As shown in FIG. 5, because the level of the output current detection signal f1 at time t1 is higher than the predetermined threshold Vth, the fault determination circuit 1330 generates a fault location data signal FLD indicating the presence of a short circuit fault or current leakage fault for the source line S1.

As described above in detail, the display device 100 includes an output current detection circuit 1332 and a fault determination circuit 1330 in the source driver 13 as fault detection devices that detect short-circuit faults or current leakage faults in the source lines (S1 to Sn) of the display panel 20.

The output current detection circuit 1332 is provided within each of the amplifiers AM1 to AMn, and for each amplifier AM, it generates a mirror current Imr that is a copy of the output current Iout that the amplifier outputs to the source line, and sends this to the variable resistor R1 via the output node nd2. When this happens, the mirror current Imr flows through the variable resistor R1, and an output current detection signal f is generated at the output node nd2, which is a signal that has undergone current-voltage conversion on the mirror current Imr, i.e., an output current detection signal f that represents the change in the current amount of the mirror current Imr as a change in voltage value.

As shown in Figure 5, at time t1, a predetermined period DL has elapsed since time t0 when the voltage value of the input gradation voltage changed, if the level of the output current detection signal f is greater than a predetermined threshold value Vth, the fault determination circuit 1330 determines that a fault exists; if it is equal to or less than the threshold value Vth, the fault determination circuit 1330 determines that no fault exists.

In this way, when a voltage follower operational amplifier (1331) is used as the output amplifier of the source driver, the fault detection device (1332, 1330) performs fault detection using the threshold value Vth, focusing on the fact that if a fault such as a short circuit or current leakage occurs in the source line, the mirror current Imr (= Iout) becomes higher than when no fault occurs.

Here, the output current detection circuit 1332 uses a variable resistor R1 as the resistor used to obtain the output current detection signal from the mirror current Imr, making it possible to adjust the level of the output current detection signal.

This allows the level of the output current detection signal to be adjusted according to the amount of current leakage expected due to the size of the display panel, the length and material of each source line, etc., making it possible to perform highly accurate fault detection using a fixed threshold Vth regardless of the amount of current leakage.

Therefore, the fault detection device (1332, 1330) can accurately determine that a fault has occurred even if the amount of current leakage occurring in the source line of the display panel 20 is minute.

Furthermore, in the output current detection circuit 1332, in order to detect the output current Iout output to the source line, a transistor QS is provided whose gate receives the differential signal PG generated by the differential section DC of the amplifier circuit 1331, in the same manner as the output transistor (Q1).

In other words, the output current detection circuit 1332 copies the output current Iout using transistor QS, and detects the output current by sending the mirror current Imr obtained by this copy to resistor (R1). This eliminates the need to connect elements such as switches and resistors to the output node nd1 of the amplifier circuit 1331 to detect faults (short circuits, current leaks). Therefore, it is possible to detect short circuit faults or current leak faults in the source lines of the display panel 20 without increasing the output load of the amplifier.

In addition, the above-mentioned fault determination circuit 1330 may divide all source lines into multiple source line groups and perform fault determination on one representative source line for each source line group, rather than individually determining faults for all source lines S1 to Sn as described above.

Figure 6 is a block diagram showing an example of the internal configuration of the fault determination circuit 1330, which was created with this in mind. In the configuration shown in Figure 6, the source lines S1 to Sn are divided into first to r-th source line groups (r is an integer greater than or equal to 2), each consisting of, for example, 20 adjacent source lines, and fault determination is performed on any one representative source line for each of the first to r-th source line groups.

The fault determination circuit 1330 shown in FIG. 6 includes selectors SL1 to SLr (r is an integer greater than or equal to 2), comparators CM1 to CMr, a delay circuit DD1, and a register RG2.

Each of the selectors SL1 to SLr receives 20 of the output current detection signals f1 to fn. Each of the selectors SL1 to SLr selects one of the 20 output current detection signals indicated by the representative source line designation signal TS and outputs it as the representative output current detection signal Sf. In other words, the selectors SL1 to SLr supply the representative output current detection signals Sf1 to SFr selected by them in response to the representative source line designation signal TS to the corresponding comparators CM1 to CMr.

Each of the comparators CM1 to CMr compares the level of the representative output current detection signal Sf it receives with a predetermined threshold value Vth for fault detection. At this time, each of the comparators CM1 to CMr generates a pre-fault detection signal that indicates the presence of a fault if the level of the representative output current detection signal Sf is greater than the threshold value Vth, and indicates the absence of a fault if the level is equal to or less than the threshold value Vth. Therefore, the comparators CM1 to CMr supply the pre-fault detection signals they have generated to register RG2 as pre-fault detection signals e1 to er.

Delay circuit DD1 receives the data capture signal LOAD and delays it by a predetermined period DL as shown in Figure 2, before supplying the resulting signal to register RG2 as a strobe signal STB.

Register RG2 captures the pre-fault determination signals e1-er supplied from comparators CM1-CMr at the timing of the leading edge of the strobe signal STB shown in Figure 2. Register RG2 outputs a fault location data signal FLD that includes the captured pre-fault determination signals e1-er as fault determination signals b1-br.

Here, for example, if the failure determination signal b1 indicates the presence of a failure, it can be confirmed that a short-circuit failure or current leakage failure has occurred in the first source line group (S1-S20) corresponding to the output current detection signal group (e.g., f1-f20) to which the representative output current detection signal Sf1 corresponding to the failure determination signal b1 belongs. Furthermore, for example, if the failure determination signal b2 indicates the presence of a failure, it can be confirmed that a short-circuit failure or current leakage failure has occurred in the second source line group (S21-S40) corresponding to the output current detection signal group (e.g., f21-f40) to which the representative output current detection signal Sf2 corresponding to the failure determination signal b2 belongs.

As such, in the configuration shown in FIG. 6, the output current detection signals f1 to fn corresponding to the source lines S1 to Sn are first divided into first to rth output current detection signal groups, each consisting of, for example, 20 output current detection signals. Then, for each of these first to rth output current detection signal groups, a representative output current detection signal is selected, and the level of the selected output current detection signal is compared with the threshold value Vth. This determines whether a short-circuit fault or current leakage fault has occurred in each source line group corresponding to the output current detection signal group to which the selected output current detection signal belongs.

In the above embodiment, the output current detection circuit 1332 provided in each of the amplifiers AM1 to AMn converts the mirror current Imr, which is a copy of the output current Iout, into a voltage level using the variable resistor R1, thereby generating the output current detection signal f that indicates the amount of the output current Iout.

However, it is also possible to provide only one system of variable resistor R1 and resistor RG1 included in the output current detection circuit 1332 within the source driver 13, and to commonly connect the drain of the transistor QS included in each of the amplifiers AM1 to AMn to one end of the variable resistor R1 via a single wiring.

Figure 7 is a block diagram showing another example of the internal configuration of the source driver 13, designed with this in mind.

In the configuration shown in Figure 7, except for the use of output amplifier section 133A instead of output amplifier section 133, the other configuration, i.e., the data latch section 131 and decoder section 132, are the same as those shown in Figure 3, so their explanation will be omitted.

The output amplifier section 133A uses amplifiers AX1 to AXn instead of the amplifiers AM1 to AMn shown in FIG. 3, and uses a failure determination circuit 1330A instead of the failure determination circuit 1330 shown in FIG. 3.

Like amplifiers AM1-AMn, amplifiers AX1-AXn receive grayscale voltages V1-Vn and amplify them individually to generate output voltages GV1-GVn, which are then supplied to source lines S1-Sn via external terminals TM1-TMn.

Note that amplifiers AX1 to AXn have the same internal configuration. Therefore, the following describes the internal configuration of amplifier AX1, selected from amplifiers AX1 to AXn.

Figure 8 is a circuit diagram showing an example of the internal configuration of amplifier AX1.

As shown in FIG. 8, amplifier AX1 includes an amplifier circuit 1331, similar to amplifier AM1. However, amplifier AX1 employs a mirror current generation circuit 1333 instead of the output current detection circuit 1332 shown in FIG. 4.

Note that the amplifier circuit 1331 shown in Figure 8 has the same configuration and operation as the amplifier circuit 1331 shown in Figure 4, so a description of it will be omitted.

The mirror current generation circuit 1333 includes a P-channel MOS transistor QS, whose source is connected to the power supply potential. The gate of transistor QS is connected to the gate of transistor Q1 of amplifier circuit 1331 via node nd0, and receives the differential signal PG output from the differential section DC at that gate. The drain of transistor QS is connected to common wiring LB. The drains of transistors QS included in each of amplifiers AX2 to AXn are also commonly connected to common wiring LB.

With this configuration, transistor QS generates a current corresponding to the differential signal PG received at its gate, i.e., a mirror current Imr corresponding to the output current output by transistor Q1 of amplifier circuit 1331, and sends this to common wiring LB.

The fault determination circuit 1330A determines whether a short circuit fault or current leakage fault has occurred in the source lines S1 to Sn of the display panel 20, based on the current sent to the common line LB, at a timing corresponding to the data capture signal LOAD. The fault determination circuit 1330A then outputs a fault detection signal FLX indicating whether a fault has occurred as a result of the determination.

Figure 9 is a circuit diagram showing an example of the internal configuration of the fault determination circuit 1330A.

As shown in FIG. 9, the fault determination circuit 1330A includes a resistor RG1, a variable resistor R1, a comparator CM1, a resistor RG3, and a delay circuit DD1.

One end of the variable resistor R1 is connected to the common line LB, and the other end is connected to ground potential. Therefore, a combined current, which is the mirror current Imr output from the transistors QS included in each of the amplifiers AX1 to AXn, flows into the variable resistor R1 via the common line LB. As a result, the variable resistor R1 converts the combined current flowing into itself via the common line LB into a voltage level corresponding to the amount of that current, and generates a signal having this voltage level on the common line LB as an output current detection signal.

Register RG1 holds an adjustment value that indicates the resistance value of variable resistor R1. Register RG1 sets the resistance value of variable resistor R1 based on the adjustment value it holds.

Comparator CM1 compares the voltage of the common line LB, i.e., the output current detection signal described above, with a predetermined threshold Vth for fault determination, and generates a fault determination signal eX indicating the presence of a fault if the voltage level of the output current detection signal is greater than threshold Vth, and indicating the absence of a fault if the voltage level is equal to or less than threshold Vth. Comparator CM1 supplies the generated fault determination signal eX to register RG3.

Delay circuit DD1 receives the data capture signal LOAD and delays it by a predetermined period DL as shown in Figure 2, before supplying the resulting signal to register RG3 as a strobe signal STB.

Register RG3 captures the fault determination signal eX supplied from comparator CM1 at the timing of the leading edge of strobe signal STB shown in Figure 2. Register RG3 holds a signal indicating the level of the captured fault determination signal eX and supplies this to drive control unit 11 as fault detection signal FLX, which indicates whether a short circuit fault or current leakage fault has occurred in the source line group (S1 to Sn).

In other words, a combined current flows through the common wiring LB, which is a combination of the output current Iout output from the transistor QS of each of the amplifiers AX1 to AXn and the same mirror current Imr. In this case, if a short-circuit fault or current leakage fault has occurred in at least one of the source lines S1 to Sn, the mirror current Imr (= Iout) at time t1 shown in Figure 5 will be higher than when no short-circuit fault or current leakage fault has occurred in the source lines S1 to Sn.

Therefore, an adjustment value for adjusting the resistance value of variable resistor R1 is stored in register RG1 so that the above-mentioned threshold Vth can be used to distinguish between when a short circuit or current leakage failure has occurred in one of source lines S1 to Sn and when no short circuit or current leakage failure has occurred in source lines S1 to Sn.

Thus, the configurations shown in Figures 7 to 9 make it possible to detect a short circuit or current leakage failure that has occurred in at least one of the source lines S1 to Sn. While the configurations shown in Figures 7 to 9 do not allow for the identification of the source line in which such a failure has occurred, they do enable a reduction in device scale compared to the configurations shown in Figures 3, 4, and 6.

In addition, by using multiple common lines LB in the configurations shown in Figures 7 to 9, it is possible to identify the fault location in units of source line groups.

Figure 10 is a block diagram showing an example of the internal configuration of a source driver 10, which was developed with this in mind and is an application example of the configuration shown in Figures 7 to 9.

In the configuration shown in Figure 10, except for the use of output amplifier unit 133B instead of output amplifier unit 133, the other components, i.e., the data latch unit 131 and decoder unit 132, are the same as those shown in Figure 3, so their description will be omitted.

The output amplifier section 133B includes amplifiers AX1 to AXn, common wiring LB1 to LB3, and a fault determination circuit 1330B, similar to those shown in Figure 7. Note that amplifiers AX1 to AXn are the same as those shown in Figure 7, so their description is omitted.

However, the drain of the transistor QS of each of amplifiers AX1 to AXp (p is an integer greater than or equal to 2) among amplifiers AX1 to AXn is connected to common wiring LB1. Furthermore, the drain of the transistor QS of each of amplifiers AX(p+1) to AXt (t is an integer greater than p) is connected to common wiring LB2, and the drain of the transistor QS of each of amplifiers AX(t+1) to AXn is connected to common wiring LB3.

The fault determination circuit 1330B determines whether a short circuit fault or current leakage fault has occurred in the source lines S1 to Sn of the display panel 20, based on the currents sent to the common lines LB1 to LB3, at a timing corresponding to the data capture signal LOAD. The fault determination circuit 1330B outputs a fault location data signal FLD that individually indicates whether a fault has occurred in each of the following source line groups: a first source line group consisting of source lines S1 to Sp, a second source line group consisting of source lines S(p+1) to St, and a third source line group consisting of source lines S(t+1) to Sn.

Figure 11 is a circuit diagram showing an example of the internal configuration of the fault determination circuit 1330B.

As shown in FIG. 11, the fault determination circuit 1330B includes a multiplexer MX, resistors RG1 and RG4, a variable resistor R1, a comparator CM1, and a delay circuit DD1.

The multiplexer MX selects the common lines LB1 to LB3 one by one based on the representative source line designation signal TS, and connects the selected common line to the output node nd2.

One end of variable resistor R1 is connected to output node nd2, and the other end is connected to ground potential. Register RG1 holds an adjustment value that indicates the resistance value of variable resistor R1. Register RG1 sets the resistance value of variable resistor R1 using the adjustment value it holds.

Comparator CM1 compares the voltage of output node nd2, i.e., the voltage of one common line (LB1, LB2, or LB3) selected by multiplexer MX, with a predetermined threshold value Vth for fault detection. Comparator CM1 generates a fault detection signal eX indicating the presence of a fault if the voltage of the one common line is greater than threshold value Vth, and indicating the absence of a fault if the voltage is equal to or less than threshold value Vth. Comparator CM1 then supplies the generated fault detection signal eX to register RG4.

Delay circuit DD1 receives the data capture signal LOAD and delays it by a predetermined period DL as shown in Figure 2, before supplying the resulting signal to register RG4 as a strobe signal STB.

Register RG4 captures the fault determination signal eX supplied from comparator CM1 at the timing of the leading edge of strobe signal STB shown in FIG. 2. Register RG4 holds a signal representing the level of the captured fault determination signal eX. That is, register RG4 holds a signal representing the level of the fault determination signal eX obtained when common wiring LB1 is connected to comparator CM1 by multiplexer MX as a first fault determination signal representing whether a short-circuit fault or current leakage fault has occurred in the first group of source lines (S1 to Sp). Register RG4 also holds a signal representing the level of the fault determination signal eX obtained when common wiring LB2 is connected to comparator CM1 by multiplexer MX as a second fault determination signal representing whether a short-circuit fault or current leakage fault has occurred in the second group of source lines [S(p+1) to St]. Furthermore, register RG4 holds a signal indicating the level of the failure determination signal eX obtained when the common line LB3 is connected to the comparator CM1 by the multiplexer MX, as a third failure determination signal indicating whether a short circuit failure or current leakage failure has occurred in the third source line group [S(t+1) to Sn].

Then, register RG4 supplies to the drive control unit 11 a failure location data signal FLD that individually indicates whether or not a failure has occurred in each of the first to third source line groups.

In the example shown in Figures 10 and 11, amplifiers AX1 to AXn are divided into three amplifier groups, namely [AX1 to AXp], [AX(p+1) to AXt], and [AX(t+1) to AXn], and three common wirings LB1 to LB3 are used for each amplifier group to connect the drains of the transistors QS included in that amplifier group, but the number is not limited to three. In short, it is sufficient to divide the first to n-th amplifier circuits (AX1 to AXn) into first to k-th amplifier circuit groups (k is an integer greater than or equal to 2 and less than n), each including at least one amplifier, and to connect the first to k-th common wirings individually to the first to k-th amplifier circuit groups, respectively.

Furthermore, in the above embodiment, the delay circuit DD1 generates the strobe signal STB from the data capture signal LOAD, but the drive control unit 11 may also generate the strobe signal STB directly.

11 Drive control unit 13 Source driver 20 Display panel 100 Display device 1330 Failure determination circuit 1331 Amplifier circuit
1332 Output current detection circuit AM1 to AMn Amplifier DC Differential section QS Transistor R1 Variable resistor RG1 Resistors S1 to Sn Source line

Claims (13)

an amplifier circuit that receives a grayscale voltage having a voltage value corresponding to a luminance level indicated by a video signal, and outputs an output current based on the grayscale voltage to a source line of a display panel, thereby supplying an output voltage having a voltage value corresponding to the grayscale voltage to the source line;
an output current detection circuit that generates a mirror current that is a copy of the output current and outputs an output current detection signal having a level corresponding to the amount of the mirror current;
a failure determination circuit that determines whether a short-circuit failure or a current leakage failure has occurred in the source line by comparing the level of the output current detection signal output from the output current detection circuit with a predetermined threshold value,
The amplifier circuit
a differential section that generates a differential signal representing a difference between the grayscale voltage and the output voltage;
a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected;
The output current detection circuit
a second transistor receiving the differential signal at its gate and sending out the mirror current from a second output node connected to its drain;
a variable resistor connected to the second output node, the variable resistor receiving the mirror current and generating the output current detection signal at the second output node. a register for holding an adjustment value;
2. The display driver according to claim 1, wherein the variable resistor adjusts the level of the output current detection signal in accordance with the adjustment value held in the register. a data latch unit that captures and outputs display data pieces that represent the luminance levels of the pixels based on the video signal at predetermined timings;
a decoder unit that converts the display data fragment output from the data latch unit into a voltage having a voltage value corresponding to a luminance level indicated by the display data fragment, and supplies the voltage to the amplifier circuit as the gradation voltage,
The display driver according to claim 1 or 2, characterized in that the fault judgment circuit judges whether a short circuit fault or a current leakage fault has occurred in the source line based on the result of comparing the level of the output current detection signal with the predetermined threshold value at a time when a predetermined period has elapsed from the predetermined timing. The display driver described in claim 3, characterized in that the failure determination circuit determines that a short circuit failure or a current leakage failure has occurred in the source line when the level of the output current detection signal is greater than the predetermined threshold. first to n-th amplifier circuits that receive first to n-th (n is an integer of 2 or more) grayscale voltages, each having a voltage value corresponding to a luminance level of each pixel indicated by a video signal, generate first to n-th output currents corresponding to an amount of change in the voltage value of each of the first to n-th grayscale voltages, and output the generated first to n-th output currents to first to n-th source lines of a display panel, respectively, thereby supplying first to n-th output voltages having voltage values corresponding to the first to n-th grayscale voltages, respectively, to the first to n-th source lines;
first to n-th output current detection circuits that generate first to n-th mirror currents by copying the first to n-th output currents, respectively, and output first to n-th output current detection signals having levels that respectively correspond to the amounts of the first to n-th mirror currents;
a failure determination circuit that determines whether a short-circuit failure or a current leakage failure has occurred in the first to n-th source lines based on the first to n-th output current detection signals output from the first to n-th output current detection circuits,
Each of the first to n-th amplifier circuits
a differential section that generates a differential signal representing a difference between the grayscale voltage and the output voltage;
a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected;
Each of the first to nth output current detection circuits comprises:
a second transistor receiving the differential signal at its gate and sending out the mirror current from a second output node connected to its drain;
a variable resistor connected to the second output node, the variable resistor receiving the mirror current and generating the output current detection signal at the second output node. The display driver described in claim 5, characterized in that the failure determination circuit individually determines whether a short circuit failure or a current leakage failure has occurred in the first to nth source lines by comparing the levels of the first to nth output current detection signals output from the first to nth output current detection circuits with respective predetermined thresholds. The display driver of claim 5, wherein the failure determination circuit divides the first to nth output current detection signals output from the first to nth output current detection circuits into first to rth (r is an integer equal to or greater than 2) output current detection signal groups, each consisting of a plurality of output current detection signals, selects one representative output current detection signal from the output current detection signal group for each of the first to rth output current detection signal groups, and compares the level of the selected one output current detection signal with a predetermined threshold value to determine whether a short-circuit failure or a current leakage failure has occurred in units of source line groups corresponding to the output current detection signal group belonging to the one output current detection signal. a display panel in which display cells are arranged at each intersection of first to n-th (n is an integer of 2 or more) source lines and a plurality of gate lines;
a display driver that drives the display panel in response to a video signal,
The display driver
first to n-th amplifier circuits that receive first to n-th gradation voltages, each having a voltage value corresponding to a luminance level of each pixel indicated by the video signal, generate currents corresponding to an amount of change in voltage value of the gradation voltage for each of the first to n-th gradation voltages as first to n-th output currents, and output the generated first to n-th output currents to the first to n-th source lines, respectively, thereby supplying first to n-th output voltages having voltage values corresponding to the first to n-th gradation voltages, respectively, to the first to n-th source lines;
first to n-th output current detection circuits that generate first to n-th mirror currents by copying the first to n-th output currents, respectively, and output first to n-th output current detection signals having levels that respectively correspond to the amounts of the first to n-th mirror currents;
a failure determination circuit that individually determines whether or not a short-circuit failure or a current leakage failure has occurred in the first to n-th source lines by comparing the levels of the first to n-th output current detection signals output from the first to n-th output current detection circuits with predetermined threshold values,
Each of the first to n-th amplifier circuits
a differential section that generates a differential signal representing a difference between the grayscale voltage and the output voltage;
a first transistor that receives the differential signal at its gate and outputs the output current from a first output node to which its drain is connected;
Each of the first to nth output current detection circuits comprises:
a second transistor receiving the differential signal at its gate and sending out the mirror current from a second output node connected to its drain;
a variable resistor connected to the second output node, the variable resistor generating the output current detection signal at the second output node when the mirror current flows into the variable resistor. first to n-th amplifier circuits that receive first to n-th (n is an integer of 2 or more) grayscale voltages, each having a voltage value corresponding to a luminance level of each pixel indicated by a video signal, generate first to n-th output currents corresponding to an amount of change in the voltage value of each of the first to n-th grayscale voltages, and output the generated first to n-th output currents to first to n-th source lines of a display panel, respectively, thereby supplying first to n-th output voltages having voltage values corresponding to the first to n-th grayscale voltages, respectively, to the first to n-th source lines;
a fault determination circuit for determining whether a short circuit fault or a current leakage fault occurs in the first to n-th source lines;
a common wiring connected to each of the first to n-th amplifier circuits;
and
Each of the first to n-th amplifier circuits
a differential section that generates a differential signal representing a difference between the grayscale voltage and the output voltage;
a first transistor receiving the differential signal at its gate and sending the output current from its drain;
a second transistor that receives the differential signal at its gate and sends a mirror current that is a copy of the output current sent from the first transistor to the common wiring;
The failure determination circuit
a variable resistor connected to the common wiring, the variable resistor generating an output current detection signal on the common wiring when a current obtained by combining the mirror currents sent from the second transistors of the first to nth amplifier circuits flows through the common wiring;
a comparator that determines whether a short circuit failure or a current leakage failure has occurred in the first to nth source lines by comparing the level of the output current detection signal with a predetermined threshold. a register for holding an adjustment value;
10. The display driver according to claim 9, wherein the variable resistor adjusts the level of the output current detection signal in accordance with the adjustment value held in the register. a data latch unit that captures and outputs first to nth display data pieces that represent the luminance levels of the pixels based on the video signal at predetermined timings;
a decoder section that converts the first to n-th display data pieces output from the data latch section into n voltages each having a voltage value corresponding to a luminance level indicated by the display data piece, and supplies the n voltages to the first to n-th amplifier circuits as the first to n-th gradation voltages,
The display driver according to claim 9 or 10, characterized in that the fault judgment circuit judges whether a short circuit fault or a current leakage fault has occurred in the source line based on the result of comparing the level of the output current detection signal with the predetermined threshold value at a time when a predetermined period has elapsed from the predetermined timing. The display driver described in claim 11, characterized in that the failure determination circuit determines that a short circuit failure or a current leakage failure has occurred in at least one of the first to nth source lines when the level of the output current detection signal is greater than the predetermined threshold. first to n-th amplifier circuits that receive first to n-th (n is an integer of 2 or more) grayscale voltages, each having a voltage value corresponding to a luminance level of each pixel indicated by a video signal, generate first to n-th output currents corresponding to an amount of change in the voltage value of each of the first to n-th grayscale voltages, and output the generated first to n-th output currents to first to n-th source lines of a display panel, respectively, thereby supplying first to n-th output voltages having voltage values corresponding to the first to n-th grayscale voltages, respectively, to the first to n-th source lines;
a fault determination circuit for determining whether a short circuit fault or a current leakage fault occurs in the first to n-th source lines;
the first to n-th amplifier circuits are divided into first to k-th amplifier circuit groups (k is an integer equal to or greater than 2 and less than n), each of which includes at least one amplifier circuit; and first to k-th common wirings individually connected to the first to k-th amplifier circuit groups,
Each of the first to n-th amplifier circuits
a differential section that generates a differential signal representing a difference between the grayscale voltage and the output voltage;
a first transistor receiving the differential signal at its gate and sending the output current from its drain;
a second transistor that receives the differential signal at its gate, and sends a mirror current that is a copy of the output current sent from the first transistor to a common wiring to which the amplifier circuit group to which the second transistor belongs is connected, among the first to kth common wirings;
The failure determination circuit
a multiplexer that selects one of the first to kth common wirings and connects the selected common wiring to an output node;
a variable resistor connected to the output node, which generates an output current detection signal at the output node when a current obtained by combining the mirror currents sent from the second transistors of the amplifier circuits flows into the variable resistor via the first common wiring, the multiplexer, and the output node;
a comparator that determines whether a short circuit failure or a current leakage failure has occurred in the first to nth source lines by comparing the level of the output current detection signal with a predetermined threshold.