JP7798607B2 - Image inspection method for semiconductor devices and manufacturing method for semiconductor devices - Google Patents

Description

The technology disclosed in this specification relates to an image inspection method for semiconductor elements and a manufacturing method for semiconductor elements.

Patent Document 1 discloses technology for detecting the relative positions of marks on the front and back surfaces of a semiconductor substrate with high precision.

JP 2015-084437 A

There is a technology that detects defects on the surface of a semiconductor element by dividing the surface of the semiconductor element into multiple inspection areas, capturing images of each inspection area, and comparing the captured images with a normal image. With this type of technology, it is difficult to determine the relative positional relationship between the inspection area image and the normal image in inspection areas that do not have feature points, making it impossible to accurately detect defects. For example, if the corners of the element pattern are present in the inspection area, defects can be accurately detected by comparing the inspection area image and the normal image after aligning them so that the corners of the element pattern match. In contrast, if feature points (e.g., corners of the element pattern) are not present in the inspection area, it is not possible to align the inspection area image with the normal image, making it impossible to accurately detect defects. This specification proposes an image inspection method that can accurately detect defects even when feature points are not present in the inspection area.

In the image inspection method for a semiconductor element (14) disclosed herein, the semiconductor element has a plurality of inspection areas (50). The image inspection method includes the steps of forming an alignment mark (20) within each inspection area on the underside (10b) of the semiconductor element, capturing an upper surface inspection image that is an image of the upper surface of the semiconductor element and a lower surface inspection image that is an image of the lower surface of the semiconductor element for each inspection area of the semiconductor element, and performing image inspection using an image inspection device. The image inspection device stores a normal upper surface image that is a normal image of the upper surface of the semiconductor element and a normal lower surface image that is a normal image of the lower surface of the semiconductor element for each inspection area of the semiconductor element. Each normal lower surface image is an image that includes the alignment mark. During the image inspection, the image inspection device compares the top surface inspection image with the top surface normal image for each inspection range, using the positions of the alignment marks included in the bottom surface inspection image and the positions of the alignment marks included in the bottom surface normal image as references, to determine whether the top surface inspection image contains any defects.

In this image inspection method, a top surface inspection image and a bottom surface inspection image are captured for each inspection range of a semiconductor element. The bottom surface inspection image includes an alignment mark. During image inspection, the top surface inspection image and the normal top surface image are compared using the positions of the alignment marks included in the bottom surface inspection image and the normal bottom surface image as references. In other words, the relative positions of the top surface inspection image and the normal top surface image are determined using the alignment marks included in the bottom surface inspection image and the normal bottom surface image, and the top surface inspection image and the normal top surface image are compared based on these relative positions. Therefore, even if there are no feature points on the top surface of the semiconductor element, alignment can be achieved between the top surface inspection image and the normal top surface image. Therefore, this inspection method allows for accurate detection of defects even if there are no feature points within the inspection range.

FIG. FIG. 10 is a plan view of the semiconductor wafer after the top surface reference marks are formed. FIG. 10 is a cross-sectional view of the semiconductor wafer after the top surface reference marks are formed. FIG. 2 is a plan view of a semiconductor wafer after semiconductor elements are formed. FIG. FIG. 2 is an enlarged plan view showing an inspection range of a semiconductor element. FIG. 10 is an enlarged plan view of a semiconductor element after alignment marks are formed. FIG. 10 is a cross-sectional view of the inspection area after the alignment mark is formed. FIG. 10 is a diagram showing positioning using an upper surface reference mark. FIG. 2 is an explanatory diagram of an image inspection device 60. FIG. 4 is an explanatory diagram of the position of an alignment mark. FIG. 10 is an explanatory diagram of the difference in the positions of alignment marks. 10 is an explanatory diagram of how to superimpose an upper surface inspection image and an upper surface normal image. FIG. 10 is a plan view of the semiconductor wafer after the bottom surface reference marks are formed. FIG. 10 is a cross-sectional view of the semiconductor wafer after the bottom surface reference marks are formed. FIG. 2 is an explanatory diagram of an image inspection device 70. 10 is an explanatory diagram of how to superimpose an upper surface inspection image and an upper surface normal image. FIG. 10 is an explanatory diagram of another form of alignment mark. FIG. 10 is an explanatory diagram of another form of alignment mark. FIG. 10 is an explanatory diagram of another form of alignment mark. FIG. 10 is an explanatory diagram of another form of alignment mark.

In one example of an image inspection method disclosed herein, the semiconductor element may be provided on a semiconductor wafer (10). The semiconductor wafer may be optically transparent.

If the semiconductor wafer is optically transparent, the process of capturing the top surface inspection image and the bottom surface inspection image may include a process of capturing the top surface inspection image from the top surface side of the semiconductor element, and a process of capturing an image of the bottom surface seen through the semiconductor wafer from the top surface side of the semiconductor element as the bottom surface inspection image.

This configuration makes it possible to capture top and bottom inspection images from the top side of the semiconductor element.

When the semiconductor wafer is optically transparent, the semiconductor wafer may have an upper surface reference mark (12) provided on its upper surface. In the step of forming the alignment marks within the inspection ranges on the lower surface of the semiconductor element, the alignment marks may be formed by positioning the upper surface reference marks by photographing them from the lower surface side of the semiconductor wafer.

With this configuration, alignment marks can be formed on the lower surface by positioning them based on the upper surface reference mark.

In one example of an image inspection method disclosed herein, the semiconductor element may be provided on a semiconductor wafer. The semiconductor wafer may have an upper surface reference mark provided on its upper surface. The step of forming the alignment mark within each of the inspection areas on the lower surface of the semiconductor element may include the steps of forming a lower surface reference mark (13) on the lower surface of the semiconductor wafer by positioning the upper surface reference mark as a reference, and forming the alignment mark within each of the inspection areas on the lower surface of the semiconductor element by positioning the lower surface reference mark as a reference.

With this configuration, alignment marks can be formed on the lower surface by positioning them based on the upper surface reference mark.

In the above image inspection method, the image inspection may detect the relative positions of the top surface reference mark and the bottom surface reference mark, and compare the top surface inspection image and the top surface normal image based on the relative positions, the position of the alignment mark included in the bottom surface inspection image, and the position of the alignment mark included in the bottom surface normal image.

This configuration allows the top surface inspection image and the top surface normal image to be compared while correcting for the effects of misalignment between the top surface reference mark and the bottom surface reference mark. Therefore, defects can be detected more accurately.

An example of an image inspection method disclosed in this specification may further include a step of removing the alignment mark after the image inspection is performed.

In one example of an image inspection method disclosed in this specification, the imaging device that captures the top surface inspection image and the bottom surface inspection image may include an upper camera (74) that captures the top surface of the semiconductor element, and a lower camera (75) that is positioned simultaneously with the upper camera and captures the bottom surface of the semiconductor element.

This configuration reduces misalignment between the top surface inspection image and the bottom surface inspection image.

A manufacturing method for semiconductor elements according to Example 1 will be described. The manufacturing method according to Example 1 includes an image inspection method for semiconductor elements. Figure 1 shows a semiconductor wafer 10 used in manufacturing semiconductor elements. The semiconductor wafer 10 has a disk shape. An orientation flat 10c is provided on the outer peripheral surface of the semiconductor wafer 10. In Example 1, the semiconductor wafer 10 is made of an optically transparent material such as GaN or SiC.

(Upper surface reference mark forming process)
First, a top surface reference mark forming step is performed. In the top surface reference mark forming step, as shown in Figures 2 and 3, top surface reference marks 12 are formed on the top surface 10a of the semiconductor wafer 10. The top surface reference marks 12 are optically detectable marks. For example, the top surface reference marks 12 may be recesses provided on the top surface 10a. The top surface reference marks 12 are formed by positioning them based on the outer peripheral surface of the semiconductor wafer 10 (for example, an orientation flat 10c, etc.). The top surface reference marks 12 are formed in the outer peripheral portion of the top surface 10a where no semiconductor elements are formed.

(Semiconductor element structure forming process)
Next, a semiconductor element forming process is performed. In the semiconductor element forming process, as shown in FIG. 4, the upper surface 10a of the semiconductor wafer 10 is processed to form multiple semiconductor elements 14 on the semiconductor wafer 10. For example, in the semiconductor element forming process, multiple semiconductor elements 14 are formed on the upper surface 10a of the semiconductor wafer 10 by ion implantation, epitaxial growth, etching, etc. The semiconductor elements 14 are formed by positioning them based on the upper surface reference mark 12. FIG. 5 illustrates an enlarged plan view of the upper surface 10a of one semiconductor element 14 (i.e., the upper surface 10a of the semiconductor wafer 10 within the scope of one semiconductor element 14). The semiconductor element 14 has two element regions 14a on the upper surface 10a. A trench-type FET is formed in each element region 14a. Therefore, a striped pattern formed by the trenches appears in each element region 14a. Note that, in figures other than FIG. 5, the striped pattern in each element region 14a is omitted for clarity. As will be described in detail later, image inspection is performed on the top surface 10a of the semiconductor element 14. In the image inspection, as shown in FIG. 6, the top surface 10a of the semiconductor element 14 is divided into a plurality of inspection areas 50, and inspection is performed on each inspection area 50. The inspection area 50x shown in FIG. 6 does not include feature points such as the outer periphery of the element region 14a. The image inspection method of the first embodiment can also properly inspect the inspection area 50x that does not include feature points.

(Alignment mark forming process)
Next, an alignment mark forming process is performed. In the alignment mark forming process, as shown in FIGS. 7 and 8 , multiple alignment marks 20 are formed on the underside 10b of the semiconductor elements 14. Here, the alignment marks 20 are formed within the respective inspection ranges 50 of each semiconductor element 14. Here, each alignment mark 20 is formed by positioning it based on the top surface reference mark 12. In Example 1, alignment marks 20 composed of a film having a predetermined shape are formed on the underside 10b of the semiconductor wafer 10. More specifically, first, a film is formed to cover the underside 10b of the semiconductor wafer 10. Next, as shown in FIG. 9 , the semiconductor wafer 10 is placed on the stage 40 of an exposure apparatus so that the underside 10b of the semiconductor wafer 10 (i.e., the underside 10b covered with the film) faces upward. The exposure apparatus has a camera 42 that photographs the semiconductor wafer 10 from above. Next, the top surface reference mark 12 is photographed by the camera 42. As described above, the semiconductor wafer 10 is optically transparent, allowing the camera 42 to capture an image of the top surface reference mark 12 from the bottom surface 10b. Next, using the top surface reference mark 12 captured by the camera 42 as a reference, a mask is formed by photolithography to cover the bottom surface 10b of the semiconductor wafer 10 (i.e., the surface of the film). Next, the film is etched using the mask to form alignment marks 20 within each inspection range 50 of each semiconductor element 14, as shown in FIGS. 7 and 8 . The film constituting the alignment mark 20 preferably has a lower optical transmittance than the semiconductor wafer 10. For example, the film constituting the alignment mark 20 may be composed of polysilicon or a metal film (e.g., Al, Ti, Ni, etc.). As described above, the structure on the top surface of the semiconductor element 14 is formed by positioning the top surface reference mark 12 as a reference. Therefore, by forming the alignment mark 20 by positioning the top surface reference mark 12 as a reference, the alignment mark 20 can be formed with high positional accuracy relative to the structure on the top surface of the semiconductor element 14.

(Image inspection process)
Next, an image inspection process is performed. In the image inspection process, the upper surface 10a of each semiconductor element 14 is photographed for each inspection range 50, and the upper surface 10a is inspected for defects. An image inspection device 60 shown in FIG. 10 is used in the image inspection process. The image inspection device 60 includes a stage 62, a camera 64, a storage device 66, and an arithmetic circuit 68. First, as shown in FIG. 10, the semiconductor wafer 10 is placed on the stage 62. Here, the semiconductor wafer 10 is placed on the stage 62 with the upper surface 10a facing upward. The stage 62 is a hollow stage with a hole 62a in its center. Therefore, the uneven shape of the lower surface 10b of the semiconductor wafer 10, which is formed by each alignment mark 20, does not come into contact with the stage 62. The stage 62 supports the outer periphery of the lower surface 10b of the semiconductor wafer 10. Note that if there is no problem even if the entire lower surface 10b of the semiconductor wafer 10 comes into contact with the stage 62, the stage 62 does not need to be a hollow stage.

The image inspection device 60 can move the camera 64 and stage 62 (i.e., the semiconductor wafer 10) relative to each other along the x and y directions in Figures 7 and 10. This allows the camera 64's imaging range to be moved along the x and y directions relative to the semiconductor wafer 10. The x direction is a direction parallel to the top surface 10a of the semiconductor wafer 10. The y direction is a direction parallel to the top surface 10a of the semiconductor wafer 10 and perpendicular to the x direction. After the semiconductor wafer 10 is placed on the stage 62, the arithmetic circuit 68 executes an inspection program. The arithmetic circuit 68 then photographs the top surface reference mark 12 using the camera 64. This allows the arithmetic circuit 68 to position the camera 64 relative to the semiconductor wafer 10. This positioning allows the camera 64's imaging range to be accurately controlled relative to the semiconductor wafer 10. In other embodiments, a camera that photographs the top surface reference mark 12 may be provided separately from the camera 64.

Next, the arithmetic circuit 68 performs image inspection on each semiconductor element 14. As shown in FIG. 7, multiple inspection areas 50 are set for each semiconductor element 14. The arithmetic circuit 68 performs image inspection on each inspection area 50. First, the arithmetic circuit 68 selects one inspection area 50 from the multiple inspection areas 50 and moves the camera 64's imaging range to the coordinates corresponding to the selected inspection area 50. Next, the arithmetic circuit 68 captures an image with the camera 64 focused on the top surface 10a. This captures an image of the top surface 10a of the selected inspection area 50 (hereinafter referred to as the top surface inspection image). Next, the arithmetic circuit 68 captures an image with the camera 64 focused on the bottom surface 10b without moving the camera 64's imaging range. Because the semiconductor wafer 10 is optically transparent, the camera 64 can capture an image of the bottom surface 10b from the top surface 10a. This captures an image of the bottom surface 10b of the selected inspection area 50 (hereinafter referred to as the bottom surface inspection image). Because an alignment mark 20 is formed on the bottom surface 10b of the inspection area 50, the alignment mark 20 is included in the bottom surface inspection image. In this way, the arithmetic circuit 68 captures a top surface inspection image and a bottom surface inspection image of the selected inspection area 50. By capturing the top surface inspection image and the bottom surface inspection image by changing the focus in this way, the top surface inspection image and the bottom surface inspection image can be captured on the same axis. Therefore, it is possible to suppress misalignment of the capturing range between the top surface inspection image and the bottom surface inspection image.

Next, the arithmetic circuit 68 accesses the storage device 66 to read out the normal top surface image and the normal bottom surface image. First, the normal top surface image and the normal bottom surface image will be described. The normal top surface image and the normal bottom surface image are images of the top surface 10a and bottom surface 10b of the inspection area 50 of a semiconductor element 14 that does not have any defects. The normal top surface image and the normal bottom surface image are taken for all inspection areas 50. The normal top surface image and the normal bottom surface image are taken in advance by the image inspection device 60. The normal top surface image and the normal bottom surface image for all inspection areas 50 are stored in the storage device 66. After the arithmetic circuit 68 has taken the top surface inspection image and the bottom surface inspection image of the selected inspection area 50, it reads out the normal top surface image and the normal bottom surface image of that inspection area 50 from the storage device 66.

Next, the arithmetic circuit 68 calculates the difference (Δx, Δy) in the position of the alignment mark 20 between the lower surface inspection image and the lower surface normal image. For example, as shown in FIG. 11, the arithmetic circuit 68 identifies the coordinates (x1, y1) of the center position of the alignment mark 20 within the shooting range of the lower surface inspection image. Similarly, the arithmetic circuit 68 identifies the coordinates (x2, y2) of the center position of the alignment mark 20 within the shooting range of the lower surface normal image. Then, using the formulas Δx = x1 - x2 and Δy = y1 - y2, the arithmetic circuit 68 calculates the difference (Δx, Δy) in the position of the alignment mark 20 between the lower surface inspection image and the lower surface normal image. In another example, as shown in FIG. 12, the arithmetic circuit 68 may overlay the lower surface inspection image and the lower surface normal image so that the alignment mark 20 coincides between them, and then calculate the difference (Δx, Δy) in the position in the x and y directions between the lower surface inspection image and the lower surface normal image. The difference (Δx, Δy) can be calculated using either method shown in Figures 11 and 12.

Next, the arithmetic circuit 68 overlays the normal top surface image on the top surface inspection image, as shown in FIG. 13. At this time, the arithmetic circuit 68 overlays the normal top surface image on the top surface inspection image while shifting the position by the same amount as the difference in position (Δx, Δy) between the bottom surface inspection image and the normal bottom surface image. By overlaying the normal top surface image on the top surface inspection image in this way, an image of a normal semiconductor element 14 that is substantially the same portion as the top surface inspection image can be accurately overlaid on the top surface inspection image. By overlaying the normal top surface image on the top surface inspection image in this way, the arithmetic circuit 68 detects differences between the top surface inspection image and the normal top surface image as defects.

The arithmetic circuit 68 performs image inspection on all inspection areas 50 of all semiconductor elements 14. As a result, the arithmetic circuit 68 detects the presence or absence of defects in each inspection area 50 of each semiconductor element 14. Marking is applied to semiconductor elements 14 for which defects are detected during image inspection.

(Bottom surface polishing process)
Next, a bottom surface polishing step is performed in which the bottom surface 10b of the semiconductor wafer 10 is polished to remove all of the alignment marks 20.

Next, electrodes (e.g., FET source electrodes, signal electrode pads, etc.) are formed on the top surface 10a of each semiconductor element 14. Next, electrodes (e.g., FET drain electrodes) are formed across the entire bottom surface 10b of the semiconductor wafer 10. Next, the semiconductor wafer 10 is divided into multiple semiconductor element 14 chips. After that, semiconductor elements 14 with detected defects are removed, and normal semiconductor elements 14 are shipped. In this way, this manufacturing method makes it possible to manufacture semiconductor elements 14 without defects on their top surfaces.

As described above, the image inspection method of Example 1 identifies the difference (Δx, Δy) in the position of the alignment mark 20 between the bottom surface inspection image and the bottom surface normal image. The top surface inspection image and the top surface normal image are then overlaid and compared at positions offset by the same amount as the difference in the position of the alignment mark 20. Because the alignment mark 20 and the structure on the top surface of the semiconductor element 14 are both positioned relative to the top surface reference mark 12, the alignment mark 20 is formed with high positional accuracy relative to the structure on the top surface of the semiconductor element 14. Furthermore, because the top surface inspection image and the bottom surface inspection image are captured coaxially by the camera 64, the deviation in the x and y directions between the capture ranges of the top surface inspection image and the bottom surface inspection image is small. Similarly, the deviation in the x and y directions between the capture ranges of the top surface normal image and the bottom surface normal image is small. Therefore, the difference in the position of the alignment mark 20 between the bottom surface inspection image and the bottom surface normal image approximately matches the deviation in the capture range between the top surface inspection image and the top surface normal image. Therefore, by overlaying the top surface inspection image and the normal top surface image at positions shifted by the same amount as the difference in the positions of the alignment marks 20, it is possible to accurately overlay an image of substantially the same portion of a normal semiconductor element 14 on an image of the inspection area 50 of the semiconductor element 14 being inspected. This allows for accurate detection of defects in the semiconductor element 14. Therefore, this image inspection method allows for accurate defect detection even when there are no feature points on the top surface 10a within the inspection area 50. In particular, it is possible to reduce false defect detection. For example, in image inspection of an element region 14a having a striped pattern extending in the x direction as shown in Figure 5, if the top surface inspection image and the normal top surface image cannot be accurately aligned, the entire area where the trenches are misaligned will be erroneously detected as a defect. In contrast, the image inspection method of Example 1 allows for accurate alignment of the top surface inspection image and the normal top surface image, thereby reducing false defect detection.

A method for manufacturing a semiconductor device according to Example 2 will now be described. The semiconductor wafer 10 used in Example 2 may or may not be optically transparent. In the manufacturing method according to Example 2, the semiconductor wafer 10 is processed to the state shown in Figures 4 and 5 in the same manner as in Example 1.

(Bottom surface reference mark formation process)
Next, a bottom surface reference mark forming step is carried out. In the bottom surface reference mark forming step, as shown in Figures 14 and 15, bottom surface reference marks 13 are formed on the bottom surface 10b of the semiconductor wafer 10. The bottom surface reference marks 13 are marks that can be optically detected. For example, the bottom surface reference marks 13 may be recesses provided on the bottom surface 10b. The bottom surface reference marks 13 are formed by positioning them based on the top surface reference marks 12. The bottom surface reference marks 13 are formed on the outer periphery of the bottom surface 10b where no semiconductor elements 14 are formed.

(Alignment mark forming process)
Next, an alignment mark forming process is performed. In the alignment mark forming process, a plurality of alignment marks 20 are formed on the bottom surface 10b of the semiconductor wafer 10, as in FIGS. 7 and 8 . Here, the alignment marks 20 are formed within each inspection range 50 of each semiconductor element 14. Here, each alignment mark 20 is formed by positioning based on the bottom surface reference mark 13. The structure on the top surface side of the semiconductor element 14 is formed by positioning based on the top surface reference mark 12. The bottom surface reference mark 13 is formed by positioning based on the top surface reference mark 12. Therefore, by forming the alignment marks 20 by positioning based on the bottom surface reference mark 13, the alignment marks 20 can be formed with high positional accuracy relative to the structure on the top surface side of the semiconductor element 14.

(Image inspection process)
Next, an image inspection process is performed. In the image inspection process of Example 2, an image inspection device 70 shown in FIG. 16 is used. The image inspection device 70 has a stage 72, cameras 74 and 75, a storage device 76, and an arithmetic circuit 78. The stage 72 is a hollow stage with a hole 72a in the center. The camera 74 is disposed above the stage 72 and takes images in the vertically downward direction. The camera 75 is disposed below the stage 72 and takes images in the vertically upward direction. The relative positions of the cameras 74 and 75 are fixed. The cameras 74 and 75 are disposed coaxially. First, as shown in FIG. 16, the semiconductor wafer 10 is placed on the stage 72. Here, the semiconductor wafer 10 is placed on the stage 72 with the upper surface 10a facing upward. Therefore, the camera 74 takes an image of the upper surface 10a of the semiconductor wafer 10, and the camera 75 takes an image of the lower surface 10b of the semiconductor wafer 10.

The image inspection device 70 can move the cameras 74, 75 and the stage 72 (i.e., the semiconductor wafer 10) relative to each other along the x and y directions in Figures 7 and 16. This allows the imaging ranges of the cameras 74, 75 to be moved along the x and y directions relative to the semiconductor wafer 10. After the semiconductor wafer 10 is placed on the stage 72, the arithmetic circuit 78 executes the inspection program. The arithmetic circuit 78 then photographs the lower surface reference mark 13 with the camera 75. This allows the arithmetic circuit 78 to position the camera 75 relative to the semiconductor wafer 10. This positioning allows the imaging ranges of the cameras 74, 75 to be accurately controlled relative to the semiconductor wafer 10. Next, the arithmetic circuit 78 photographs the upper surface reference mark 12 with the camera 74. This allows the arithmetic circuit 78 to calculate the relative position (xa, ya) of the upper surface reference mark 12 with respect to the lower surface reference mark 13. Furthermore, the calculation circuit 78 calculates the deviation (Δxa, Δya) of the relative position (xa, ya) from the design value.

Next, the arithmetic circuit 78 performs image inspection on each semiconductor element 14. The arithmetic circuit 78 performs image inspection on each inspection area 50. The arithmetic circuit 78 selects one inspection area 50 from the multiple inspection areas 50 and moves the imaging areas of the cameras 74 and 75 to the coordinates corresponding to the selected inspection area 50. Next, the arithmetic circuit 78 captures an image of the top surface 10a of the inspection area 50 with the camera 74 (hereinafter referred to as the top surface inspection image) and an image of the bottom surface 10b of the inspection area 50 with the camera 75 (hereinafter referred to as the bottom surface inspection image). Because an alignment mark 20 is formed on the bottom surface 10b of the inspection area 50, the alignment mark 20 is included in the bottom surface inspection image. Because the cameras 74 and 75 are arranged coaxially, the top surface inspection image and the bottom surface inspection image can be captured coaxially. This reduces misalignment of the imaging areas between the top surface inspection image and the bottom surface inspection image.

After capturing the top surface inspection image and bottom surface inspection image of the selected inspection area 50, the arithmetic circuit 78 reads out the top surface normal image and bottom surface normal image of that inspection area 50 from the storage device 76. Next, the arithmetic circuit 78 calculates the difference (Δx, Δy) in the position of the alignment mark 20 between the bottom surface inspection image and the bottom surface normal image, in the same manner as in Example 1.

Next, the arithmetic circuit 78 calculates the slide amount (Δxs, Δys) based on the deviation (Δxa, Δya) of the relative positions of the top surface reference mark 12 and the bottom surface reference mark 13 from the design values and the difference (Δx, Δy) in the position of the alignment mark 20 between the bottom surface inspection image and the bottom surface normal image. For example, the slide amount (Δxs, Δys) can be calculated using the formulas Δxs = Δxa + Δx and Δys = Δya + Δy. Next, as shown in FIG. 17, the arithmetic circuit 78 overlays the top surface normal image on the top surface inspection image at a position shifted by the slide amount (Δxs, Δys). Overlaying the top surface normal image on the top surface inspection image in this manner allows an image of a normal semiconductor element 14 in a substantially identical portion to the top surface inspection image to be accurately overlaid on the top surface inspection image. By overlaying the top surface normal image on the top surface inspection image in this manner, the arithmetic circuit 68 detects differences between the top surface inspection image and the top surface normal image as defects.

The arithmetic circuit 68 performs image inspection on all inspection areas 50 of all semiconductor elements 14. As a result, the arithmetic circuit 68 detects the presence or absence of defects in each inspection area 50 of each semiconductor element 14. Marking is applied to semiconductor elements 14 for which defects are detected during image inspection.

(Bottom surface polishing process)
Next, the same bottom surface polishing step as in Example 1 is carried out to remove the alignment marks 20 .

Next, electrodes and the like are formed on the semiconductor wafer 10 in the same manner as in Example 1, and then the semiconductor wafer 10 is divided into chips of semiconductor elements 14. Any semiconductor elements 14 in which defects are detected are then removed, and normal semiconductor elements 14 are shipped. In this way, this manufacturing method makes it possible to manufacture semiconductor elements 14 that have no defects on their upper surfaces.

As described above, in the image inspection method of Example 2, the normal top surface image is overlaid on the bottom surface inspection image by adjusting the position based on the difference (Δx, Δy) in the position of the alignment mark 20 between the bottom surface inspection image and the normal bottom surface image and the deviation (Δxa, Δya) of the relative position of the top surface reference mark 12 and the bottom surface reference mark 13 from the design value. If the relative positions of the top surface reference mark 12 and the bottom surface reference mark 13 are deviated from the design value (i.e., an error), the alignment mark 20 on the bottom surface 10b side and the semiconductor element structure on the top surface 10a side will be misaligned by the amount of the error. Therefore, by overlaying the top surface inspection image and the normal top surface image based on the deviation (Δxa, Δya), the influence of the error can be suppressed. This allows the top surface inspection image and the normal top surface image to be overlaid more accurately. This allows defects in the semiconductor element 14 to be accurately detected. Note that if sufficient accuracy can be achieved without considering the deviation (Δxa, Δya), the deviation (Δxa, Δya) may not be taken into account. That is, as in Example 1, the top surface inspection image and the top surface normal image may be superimposed at positions shifted by the difference in the position of the alignment mark 20 (Δx, Δy).

In Example 1, as shown in FIG. 10, a top surface inspection image was captured by camera 64, and a bottom surface inspection image observed through the semiconductor wafer 10 was also captured by the same camera 64. However, in Example 1, the top surface inspection image and the bottom surface inspection image may be captured by separate cameras, such as cameras 74 and 75 in FIG. 16. Also, in Example 1, as shown in FIG. 9, the top surface reference mark 12 observed through the semiconductor wafer 10 from the bottom surface 10b side was captured by camera 42, but the top surface reference mark 12 may also be captured from the top surface 10a side.

In the first and second embodiments described above, the alignment mark 20 was a patterned film. However, various optically detectable structures can be employed as the alignment mark 20. For example, as shown in FIG. 18, the alignment mark 20 may be a film (e.g., a film made of polysilicon or metal) embedded in a recess provided in the lower surface 10b. As shown in FIG. 19, the alignment mark 20 may be a mark formed by irradiating the lower surface 10b with a laser L. As shown in FIG. 20, the alignment mark 20 may be composed of a region formed by implanting ions I into the lower surface 10b. As shown in FIG. 21, the alignment mark 20 may be a region roughened by etching the lower surface 10b.

Furthermore, in the above-described Examples 1 and 2, the top surface inspection image and the bottom surface inspection image were captured coaxially. However, the capture range of the top surface inspection image and the capture range of the bottom surface inspection image may be misaligned due to errors, etc. Even in this case, image inspection can be performed appropriately as long as the relative positional relationship between the capture range of the top surface inspection image and the capture range of the bottom surface inspection image is fixed.

In addition, in the above-described first and second embodiments, the top surface inspection image and the top surface normal image are superimposed and compared, but defects may also be detected by comparing them in other ways.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings demonstrate technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of those objectives itself has technical utility.

10: Semiconductor wafer, 12: Top surface reference mark, 13: Bottom surface reference mark, 14: Semiconductor element, 20: Alignment mark

Claims (10)

A method for image inspection of a semiconductor device (14), comprising:
The semiconductor device has a plurality of test areas (50);
The image inspection method comprises:
a step of forming alignment marks (20) within the respective inspection areas on the lower surface (10b) of the semiconductor element by positioning the alignment marks (20) relative to the upper surface structure of the semiconductor element;
capturing an upper surface inspection image, which is an image of the upper surface of the semiconductor element, and a lower surface inspection image, which is an image of the lower surface of the semiconductor element, for each of the inspection ranges of the semiconductor element;
A step of performing an image inspection using an image inspection device;
and
the image inspection device stores, for each of the inspection ranges of the semiconductor element, a normal upper surface image that is a normal image of the upper surface of the semiconductor element and a normal lower surface image that is a normal image of the lower surface of the semiconductor element;
each of the lower surface normal images is an image including the alignment mark,
In the image inspection, the image inspection device compares the upper surface inspection image with the upper surface normal image for each inspection range based on the positions of the alignment marks included in the lower surface inspection image and the positions of the alignment marks included in the lower surface normal image, thereby determining whether or not the upper surface inspection image contains a defect;
The semiconductor element is provided on a semiconductor wafer (10),
the semiconductor wafer is optically transparent;
The semiconductor wafer has an upper surface reference mark (12) provided on its upper surface,
The method further includes a step of forming the upper surface side structure of the semiconductor element on the upper surface of the semiconductor wafer by aligning the upper surface reference mark as a reference,
In the step of forming the alignment marks within the respective inspection ranges on the lower surface of the semiconductor element, the alignment marks are formed by positioning the alignment marks based on the upper surface reference marks by photographing the upper surface reference marks from the lower surface side of the semiconductor wafer .
Imaging methods. A method for image inspection of a semiconductor device (14), comprising:
The semiconductor device has a plurality of test areas (50);
The image inspection method comprises:
a step of forming alignment marks (20) within the respective inspection areas on the lower surface (10b) of the semiconductor element by positioning the alignment marks (20) relative to the upper surface structure of the semiconductor element;
capturing an upper surface inspection image, which is an image of the upper surface of the semiconductor element, and a lower surface inspection image, which is an image of the lower surface of the semiconductor element, for each of the inspection ranges of the semiconductor element;
A step of performing an image inspection using an image inspection device;
and
the image inspection device stores, for each of the inspection ranges of the semiconductor element, a normal upper surface image that is a normal image of the upper surface of the semiconductor element and a normal lower surface image that is a normal image of the lower surface of the semiconductor element;
each of the lower surface normal images is an image including the alignment mark,
In the image inspection, the image inspection device compares the upper surface inspection image with the upper surface normal image for each inspection range based on the positions of the alignment marks included in the lower surface inspection image and the positions of the alignment marks included in the lower surface normal image, thereby determining whether or not the upper surface inspection image contains a defect;
The method further includes forming the top surface structure of the semiconductor element on a semiconductor wafer,
the semiconductor wafer has an upper surface reference mark provided on its upper surface;
In the step of forming the upper surface side structure, the upper surface side structure of the semiconductor element is formed on the upper surface of the semiconductor wafer while being positioned based on the upper surface reference mark;
the step of forming the alignment marks within the respective inspection areas on the lower surface of the semiconductor element includes:
a step of forming a lower surface reference mark (13) on the lower surface of the semiconductor wafer by aligning the upper surface reference mark based on the reference mark;
forming the alignment marks within the respective inspection areas on the bottom surface of the semiconductor element by positioning the bottom surface reference marks as a reference;
having
Imaging methods. 3. The image inspection method according to claim 2, wherein the image inspection detects the relative positions of the upper surface reference mark and the lower surface reference mark, and compares the upper surface inspection image with the upper surface normal image based on the relative positions, the position of the alignment mark included in the lower surface inspection image, and the position of the alignment mark included in the lower surface normal image. 4. The image inspection method according to claim 1 , further comprising the step of removing the alignment mark after the image inspection is performed. The image inspection method according to claim 1 , wherein in the step of capturing the top surface inspection image and the bottom surface inspection image, the top surface inspection image and the bottom surface inspection image are captured coaxially. 4. The image inspection method according to claim 2 or 3, wherein the photographing device for photographing the top surface inspection image and the bottom surface inspection image has an upper camera (74) for photographing the top surface of the semiconductor element, and a lower camera (75) arranged coaxially with the upper camera for photographing the bottom surface of the semiconductor element. An image inspection method according to any one of claims 1 to 6, wherein in the image inspection, the image inspection device calculates the difference between the position of the alignment mark included in the bottom surface inspection image and the position of the alignment mark included in the bottom surface normal image for each inspection range, and determines whether or not the top surface inspection image contains a defect by comparing the top surface inspection image with the top surface normal image based on the difference. In the image inspection, the image inspection device calculates the difference between the position of the alignment mark included in the bottom surface inspection image and the position of the alignment mark included in the bottom surface normal image for each inspection range, and determines whether or not the top surface inspection image contains a defect by overlaying the top surface inspection image and the top surface normal image with their positions shifted by the same amount as the difference. In the image inspection, the image inspection device
Detecting the relative positions of the upper surface reference mark and the lower surface reference mark;
calculating a difference between the position of the alignment mark included in the lower surface inspection image and the position of the alignment mark included in the lower surface normal image for each of the inspection ranges;
calculating a slide amount for each of the inspection ranges based on the relative position and the difference;
and determining whether or not a defect is included in the upper surface inspection image by superimposing the upper surface inspection image and the upper surface normal image in a state where the positions are shifted by the slide amount.
The image inspection method according to claim 2 . A method for manufacturing a semiconductor device, comprising the image inspection method according to any one of claims 1 to 9 .