JP7798680B2 - Wafer processing device, semiconductor chip manufacturing method, and semiconductor chip - Google Patents

Description

This invention relates to a wafer processing device, a semiconductor chip manufacturing method, and semiconductor chips, and in particular to a wafer processing device that performs dicing operations, a semiconductor chip manufacturing method, and semiconductor chips.

Conventionally, wafer processing systems that perform dicing operations are known (see, for example, Patent Document 1).

Patent Document 1 above discloses a substrate processing system (wafer processing system) that performs operations such as dicing substrates, thinning substrates, attaching DAF (Die Attach Film) to substrates, widening the gap between chips, and mounting substrates.

Patent No. 6956788

However, in a substrate processing system such as that described in Patent Document 1, if a bottleneck task (task with a long cycle time) exists, a mismatch will occur between the cycle times of the bottleneck task and other tasks. In this case, the mismatch in cycle times will result in lost time in equipment operation, resulting in reduced productivity.

This invention was made to solve the above-mentioned problems, and one object of this invention is to provide a wafer processing device, a semiconductor chip manufacturing method, and semiconductor chips that can prevent a decline in productivity even when a bottleneck task exists.

A wafer processing apparatus according to a first aspect of the present invention includes a wafer storage unit that stores wafers on which a plurality of semiconductor chips are formed, a dicing operation unit that performs dicing on wafers supplied from the wafer storage unit to divide the wafers into individual semiconductor chips, a non-dicing operation unit that performs operations other than dicing on the wafers that have been diced, a wafer transport unit that transports wafers between the wafer storage unit, the dicing operation unit, and the non-dicing operation unit, and a control unit. The control unit is configured to perform dicing priority control to shorten the downtime of the dicing operation compared to the downtime of the operations other than the dicing operation when the cycle time of the dicing operation is longer than the cycle time of the operations other than the dicing operation, and to perform non-dicing priority control to shorten the downtime of the operations other than the dicing operation compared to the downtime of the dicing operation when the cycle time of the operations other than the dicing operation is longer than the cycle time of the dicing operation. The dicing operation is dicing the wafer using a laser, and the non-dicing operation is expansion-related operation including expanding an elastic sheet member to which the wafer is attached .
A wafer processing apparatus according to a second aspect of the present invention includes a wafer storage unit that stores wafers on which a plurality of semiconductor chips are formed, a dicing operation unit that performs dicing on wafers supplied from the wafer storage unit to divide the wafers into individual semiconductor chips, a non-dicing operation unit that performs operations other than dicing on wafers that have already been diced, a wafer transport unit that transports wafers between the wafer storage unit, the dicing operation unit, and the non-dicing operation unit, and a control unit. The control unit is configured to perform dicing priority control to shorten the downtime of the dicing operation compared to the downtime of the operations other than the dicing operation when the cycle time of the dicing operation is longer than the cycle time of the operations other than the dicing operation, and to perform non-dicing priority control to shorten the downtime of the operations other than the dicing operation compared to the downtime of the dicing operation when the cycle time of the operations other than the dicing operation is longer than the cycle time of the dicing operation. When performing dicing priority control, the control unit is configured to complete the dicing operation while the wafer for the next dicing operation is withdrawn from the wafer storage unit by the wafer transport unit and kept waiting.
A wafer processing apparatus according to a third aspect of the present invention includes a wafer accommodation unit that accommodates wafers on which a plurality of semiconductor chips are formed, a dicing operation unit that performs dicing on wafers supplied from the wafer accommodation unit to divide the wafers into individual semiconductor chips, a non-dicing operation unit that performs operations other than dicing on the wafers that have been diced, a wafer transport unit that transports wafers between the wafer accommodation unit, the dicing operation unit, and the non-dicing operation unit, and a control unit. The control unit is configured to perform dicing priority control to shorten the downtime of the dicing operation compared to the downtime of the operations other than the dicing operation when the cycle time of the dicing operation is longer than the cycle time of the operations other than the dicing operation, and to perform non-dicing priority control to shorten the downtime of the operations other than the dicing operation compared to the downtime of the dicing operation when the cycle time of the operations other than the dicing operation is longer than the cycle time of the dicing operation. The control unit is configured, when performing dicing priority control, to control the wafer transport unit to accommodate wafers on which operations other than the dicing operation have been completed into the wafer accommodation unit during the dicing operation.
A wafer processing apparatus according to a fourth aspect of the present invention includes a wafer accommodation unit that accommodates wafers having a plurality of semiconductor chips formed thereon; a dicing operation unit that performs dicing on wafers supplied from the wafer accommodation unit to divide the wafers into individual semiconductor chips; a non-dicing operation unit that performs operations other than dicing on the wafers that have been diced; a wafer transport unit that transports wafers between the wafer accommodation unit, the dicing operation unit, and the non-dicing operation unit; and a control unit. The control unit is configured to perform dicing priority control to shorten the downtime of the dicing operation compared to the downtime of the operations other than the dicing operation when the cycle time of the dicing operation is longer than the cycle time of the operations other than the dicing operation, and to perform non-dicing priority control to shorten the downtime of the operations other than the dicing operation compared to the downtime of the dicing operation when the cycle time of the operations other than the dicing operation is longer than the cycle time of the dicing operation. When performing non-dicing priority control, the control unit is configured to perform control to complete the operations other than the dicing operation while the wafer transport unit is empty.
A wafer processing apparatus according to a fifth aspect of the present invention includes a wafer accommodation unit that accommodates a wafer having a plurality of semiconductor chips formed thereon; a dicing operation unit that performs dicing on the wafer supplied from the wafer accommodation unit to divide the wafer into individual semiconductor chips; a non-dicing operation unit that performs operations other than dicing on the wafer that has been diced; a wafer transport unit that transports the wafer between the wafer accommodation unit, the dicing operation unit, and the non-dicing operation unit; and a control unit. The control unit is configured to perform dicing priority control to shorten the downtime of the dicing operation compared to the downtime of the operations other than the dicing operation when the cycle time of the dicing operation is longer than the cycle time of the operations other than the dicing operation, and to perform non-dicing priority control to shorten the downtime of the operations other than the dicing operation compared to the downtime of the dicing operation when the cycle time of the operations other than the dicing operation is longer than the cycle time of the dicing operation. When performing non-dicing priority control, the control unit is configured to perform control to complete the operations other than the dicing operation with the wafer released from fixation in the dicing operation unit.

In the wafer processing apparatus according to the first to fifth aspects of the present invention, as described above, the control unit is configured to perform dicing priority control to shorten the downtime of the dicing operation compared to the downtime of the other operations when the cycle time of the dicing operation is longer than the cycle time of the other operations, and to perform non-dicing priority control to shorten the downtime of the other operations compared to the dicing operation when the cycle time of the other operations is longer than the cycle time of the dicing operation. This allows the downtime of the bottleneck operation (the operation with the long cycle time) between the dicing operation and the other operations to be reduced compared to when priority control is not performed. As a result, whether the bottleneck is the dicing operation or the other operations, the occurrence of lost time in equipment operation can be suppressed. This prevents a decrease in productivity even when a bottleneck operation exists.

In the wafer processing apparatus according to the first aspect , the dicing operation is a dicing operation in which the wafer is diced by a laser, and the operation other than the dicing operation is an expansion-related operation including expanding an elastic sheet member to which the wafer is attached. With this configuration, even if a bottleneck operation exists in a wafer processing apparatus that performs a dicing operation in which the wafer is diced by a laser and an expansion-related operation, a decrease in productivity can be suppressed.

In the wafer processing apparatus according to the second aspect , when dicing priority control is performed, the control unit is configured to control the dicing operation to be completed while the wafer for the next dicing operation is withdrawn from the wafer storage unit by the wafer transport unit and placed on standby. This configuration allows the wafer for the next dicing operation to be placed on standby, so that when the next dicing operation begins, the wafer for the next dicing operation can be quickly supplied. As a result, when the dicing operation becomes a bottleneck, the downtime of the dicing operation can be easily reduced.

In the wafer processing apparatus according to the third aspect , when dicing priority control is performed, the control unit is configured to control the wafer transport unit to store wafers for which operations other than dicing have been completed in the wafer storage unit during the dicing operation. With this configuration, by storing wafers for which operations other than dicing have been completed in the wafer storage unit during the dicing operation, it is possible to store wafers for which operations other than dicing have been completed in the wafer storage unit at an effective timing that does not extend the downtime of the dicing operation.

In the wafer processing apparatus according to the fourth aspect , when the control unit performs priority control for operations other than dicing, the control unit is configured to perform control to complete operations other than dicing while keeping the wafer transport unit empty. By configuring in this way, by keeping the wafer transport unit empty, when operations other than dicing are completed, the wafer can be quickly transferred to the wafer transport unit, and when operations other than dicing become a bottleneck, the downtime of operations other than dicing can be easily reduced.

In the wafer processing apparatus according to the fifth aspect , when the control unit performs non-dicing priority control, the control unit is configured to perform control to complete operations other than dicing while the wafer is released from the dicing unit. With this configuration, by releasing the wafer from the dicing unit, when operations other than dicing are completed, the wafer after dicing can be quickly supplied to operations other than dicing. As a result, downtime for operations other than dicing can be easily reduced.

A method for manufacturing semiconductor chips according to a sixth aspect of the present invention includes the steps of: performing, by a dicing work unit, a dicing operation on a wafer supplied from a wafer accommodation unit that accommodates wafers having a plurality of semiconductor chips formed thereon, to divide the wafer into individual semiconductor chips; performing, by a non-dicing work unit, operations other than the dicing operation on the wafer that has been diced; transporting the wafer between the wafer accommodation unit, the dicing work unit, and the non-dicing work unit by a wafer transport unit; and performing dicing priority control to shorten the downtime of the dicing operation compared to the downtime of the operations other than the dicing operation when the cycle time of the dicing operation is longer than the cycle time of the operations other than the dicing operation, and performing non-dicing priority control to shorten the downtime of the operations other than the dicing operation compared to the downtime of the dicing operation when the cycle time of the operations other than the dicing operation is longer than the cycle time of the dicing operation. The dicing operation is dicing the wafer with a laser, and the operations other than the dicing operation is expansion-related operation including expanding an elastic sheet member to which the wafer is attached .

In a semiconductor chip manufacturing method according to a sixth aspect of the present invention, as described above, when the cycle time of the dicing operation is longer than the cycle time of operations other than the dicing operation, dicing priority control is performed to shorten the downtime of the dicing operation compared to the downtime of the operations other than the dicing operation. When the cycle time of the operations other than the dicing operation is longer than the cycle time of the dicing operation, non-dicing priority control is performed to shorten the downtime of the operations other than the dicing operation compared to the downtime of the operations other than the dicing operation. This reduces the downtime of the bottleneck operation (the operation with the long cycle time) compared to when priority control is not performed. As a result, whether the bottleneck is the dicing operation or the operations other than the dicing operation, lost time in equipment operation can be reduced. This provides a semiconductor chip manufacturing method that can suppress a decrease in productivity even when a bottleneck operation exists.

A semiconductor chip according to a seventh aspect of the present invention comprises a wafer storage unit that stores a wafer on which a plurality of semiconductor chips are formed, a dicing work unit that performs dicing work on the wafer supplied from the wafer storage unit to divide the wafer into individual semiconductor chips, a non-dicing work unit that performs work other than dicing on the wafer that has been diced, a wafer transport unit that transports the wafer between the wafer storage unit, the dicing work unit, and the non-dicing work unit, and a control unit, wherein the control unit is configured to perform dicing priority control to make the downtime of the dicing work shorter than the downtime of the work other than the dicing work when the cycle time of the dicing work is longer than the cycle time of the work other than the dicing work, and to perform non-dicing priority control to make the downtime of the work other than the dicing work shorter than the downtime of the dicing work when the cycle time of the work other than the dicing work is longer than the cycle time of the dicing work, and is manufactured by a wafer processing apparatus in which the dicing work is dicing work that dices the wafer with a laser and the work other than dicing work is expand-related work including expanding an elastic sheet member to which the wafer is attached .

In a semiconductor chip according to a seventh aspect of the present invention, as described above, the control unit is configured to perform dicing priority control to shorten the downtime of the dicing operation compared to the downtime of the other operations when the cycle time of the dicing operation is longer than the cycle time of the other operations, and to perform non-dicing priority control to shorten the downtime of the other operations compared to the dicing operation when the cycle time of the other operations is longer than the cycle time of the dicing operation. This allows the downtime of the bottleneck operation (the operation with the long cycle time) between the dicing operation and the other operations to be reduced compared to when priority control is not performed. As a result, whether the bottleneck is the dicing operation or the other operations, lost time in equipment operation can be reduced. This makes it possible to provide a semiconductor chip that can suppress a decrease in productivity even when a bottleneck operation exists.

According to the present invention, as described above, even when a bottleneck task exists, it is possible to prevent a decline in productivity.

1 is a plan view showing a semiconductor wafer processing apparatus provided with a dicing apparatus and an expanding apparatus according to a first embodiment; 1 is a plan view showing a wafer ring structure processed in the semiconductor wafer processing apparatus according to the first embodiment; FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 2 is a plan view of a dicing device disposed adjacent to the expanding device according to the first embodiment. 10 is a side view of the dicing device arranged adjacent to the expanding device according to the first embodiment, viewed from the Y2 direction side. FIG. FIG. 2 is a plan view of the expanding device according to the first embodiment. FIG. 2 is a side view of the expanding device according to the first embodiment as viewed from the Y2 direction side. FIG. 2 is a side view of the expanding device according to the first embodiment as viewed from the X1 direction side. 1 is a block diagram showing a control configuration of a semiconductor wafer processing apparatus according to a first embodiment. 10 is a flowchart of the first half of a semiconductor chip manufacturing process of the semiconductor wafer processing apparatus according to the first embodiment. 10 is a flowchart of the second half of the semiconductor chip manufacturing process of the semiconductor wafer processing apparatus according to the first embodiment. 5A and 5B are diagrams for explaining dicing priority control of the semiconductor wafer processing apparatus according to the first embodiment. 10A and 10B are diagrams for explaining priority control of operations other than dicing in the semiconductor wafer processing apparatus according to the first embodiment. FIG. 10 is a plan view showing a semiconductor wafer processing apparatus provided with a dicing apparatus and an expanding apparatus according to a second embodiment. 10 is a side view of a semiconductor wafer processing apparatus provided with a dicing apparatus and an expanding apparatus according to a second embodiment, as viewed from the Y2 direction. FIG. 10 is a side view of a semiconductor wafer processing apparatus provided with a dicing apparatus and an expanding apparatus according to a second embodiment, as viewed from the X1 direction. FIG. FIG. 10 is a block diagram showing a control configuration of a semiconductor wafer processing apparatus according to a second embodiment. 10 is a flowchart of the first half of a semiconductor chip manufacturing process of a semiconductor wafer processing apparatus according to a second embodiment. 10 is a flowchart of the second half of the semiconductor chip manufacturing process of the semiconductor wafer processing apparatus according to the second embodiment.

The following describes an embodiment of the present invention with reference to the drawings.

[First embodiment]
The configuration of a semiconductor wafer processing apparatus 100 according to a first embodiment of the present invention will be described with reference to Figures 1 to 13. The semiconductor wafer processing apparatus 100 is an example of the "wafer processing apparatus" set forth in the claims.

(Semiconductor wafer processing equipment)
1, the semiconductor wafer processing apparatus 100 is an apparatus for processing a wafer W1 provided on a wafer ring structure W. The semiconductor wafer processing apparatus 100 is configured to form a modified layer on the wafer W1 and to divide the wafer W1 along the modified layer to form a plurality of semiconductor chips Ch (see FIG. 8).

Now, with reference to Figures 2 and 3, the wafer ring structure W will be described. The wafer ring structure W includes a wafer W1, a sheet member W2, and a ring-shaped member W3.

The wafer W1 is a thin, circular plate made of crystals of a semiconductor material that is used to make semiconductor integrated circuits. A modified layer is formed inside the wafer W1 along the dividing line due to processing in the semiconductor wafer processing apparatus 100. In other words, the wafer W1 is processed so that it can be divided along the dividing line. The sheet member W2 is a stretchable adhesive tape. An adhesive layer is provided on the upper surface W21 of the sheet member W2. The wafer W1 is attached to the adhesive layer of the sheet member W2. The ring-shaped member W3 is a metal frame that is ring-shaped in a plan view. The ring-shaped member W3 is attached to the adhesive layer of the sheet member W2 while surrounding the wafer W1.

The semiconductor wafer processing apparatus 100 also includes a dicing apparatus 1 and an expanding apparatus 2. The vertical direction is the Z direction, the upward direction is the Z1 direction, and the downward direction is the Z2 direction. The horizontal direction perpendicular to the Z direction in which the dicing apparatus 1 and the expanding apparatus 2 are aligned is the X direction, the X1 direction is the expanding apparatus 2 side of the X direction, and the X2 direction is the dicing apparatus 1 side of the X direction. The horizontal direction perpendicular to the X direction is the Y direction, one side of the Y direction is the Y1 direction, and the other side of the Y direction is the Y2 direction. The dicing apparatus 1 is an example of a "dicing work unit" in the claims.

(Dicing equipment)
As shown in FIGS. 1, 4, and 5, the dicing apparatus 1 is configured to perform a dicing operation on a wafer W1 on which a plurality of semiconductor chips Ch are formed and supplied from a cassette unit 202 (described later) to divide the wafer W1 into the plurality of semiconductor chips Ch. Specifically, the dicing operation is a dicing operation in which the wafer W1 is diced using a laser. The dicing apparatus 1 is configured to form a modified layer by irradiating the wafer W1 with a laser having a wavelength that is transparent to the wafer W1 along dividing lines (streets). The modified layer refers to cracks, voids, and the like formed inside the wafer W1 by the laser. The technique of forming a modified layer on the wafer W1 in this manner is called dicing.

Specifically, the dicing device 1 includes a base 11, a chuck table unit 12, a laser unit 13, and an imaging unit 14.

The base 11 is a base on which the chuck table 12 is installed. The base 11 has a rectangular shape in a plan view.

<Chuck table section>
The chuck table 12 includes a suction portion 12a, a clamp portion 12b, a rotation mechanism 12c, and a table movement mechanism 12d. The suction portion 12a is configured to suction the wafer ring structure W onto its upper surface on the Z1 side. The suction portion 12a is a table provided with suction holes and suction lines for suctioning the lower surface of the ring-shaped member W3 of the wafer ring structure W on the Z2 side. The suction portion 12a is supported by the table movement mechanism 12d via the rotation mechanism 12c. The clamp portion 12b is provided at the upper end of the suction portion 12a. The clamp portion 12b is configured to hold the wafer ring structure W held by the suction portion 12a. The clamp portion 12b holds the ring-shaped member W3 of the wafer ring structure W held by the suction portion 12a from the Z1 side. In this manner, the wafer ring structure W is gripped by the suction portion 12a and the clamp portion 12b.

The rotation mechanism 12c is configured to rotate the suction unit 12a in the circumferential direction around a rotation center axis C extending parallel to the Z direction. The rotation mechanism 12c is attached to the upper end of the table movement mechanism 12d. The table movement mechanism 12d is configured to move the wafer ring structure W in the X and Y directions. The table movement mechanism 12d has an X-direction movement mechanism 121 and a Y-direction movement mechanism 122. The X-direction movement mechanism 121 is configured to move the rotation mechanism 12c in the X1 or X2 direction. The X-direction movement mechanism 121 has, for example, a linear conveyor module or a drive unit including a ball screw and a motor with an encoder. The Y-direction movement mechanism 122 is configured to move the rotation mechanism 12c in the Y1 or Y2 direction. The Y-direction movement mechanism 122 has, for example, a linear conveyor module or a drive unit including a ball screw and a motor with an encoder.

<Laser section>
The laser unit 13 is configured to irradiate a wafer W1 of the wafer ring structure W held by the chuck table 12 with laser light. The laser unit 13 is disposed on the Z1 side of the chuck table 12. The laser unit 13 includes a laser irradiation unit 13a, a mounting member 13b, and a Z-direction movement mechanism 13c. The laser irradiation unit 13a is configured to irradiate a pulsed laser light. The mounting member 13b is a frame to which the laser unit 13 and the imaging unit 14 are attached. The Z-direction movement mechanism 13c is configured to move the laser unit 13 in the Z1 direction or the Z2 direction. The Z-direction movement mechanism 13c includes, for example, a linear conveyor module or a drive unit having a ball screw and an encoder-equipped motor. Note that the laser irradiation unit 13a may be a laser irradiation unit that oscillates a continuous-wave laser light as the laser light, other than a pulsed laser light, as long as it is capable of forming a modified layer through multiphoton absorption.

<Imaging unit>
The imaging unit 14 is configured to capture an image of the wafer W1 of the wafer ring structure W held by the chuck table 12. The imaging unit 14 is disposed on the Z1 direction side of the chuck table 12. The imaging unit 14 has a high-resolution camera 14a, a wide-angle camera 14b, a Z-direction movement mechanism 14c, and a Z-direction movement mechanism 14d.

The high-resolution camera 14a and the wide-angle camera 14b are near-infrared imaging cameras. The high-resolution camera 14a has a narrower viewing angle than the wide-angle camera 14b. The high-resolution camera 14a has higher resolution than the wide-angle camera 14b. The wide-angle camera 14b has a wider viewing angle than the high-resolution camera 14a. The wide-angle camera 14b has lower resolution than the high-resolution camera 14a. The high-resolution camera 14a is positioned on the X1 side of the laser irradiation unit 13a. The wide-angle camera 14b is positioned on the X2 side of the laser irradiation unit 13a. In this way, the high-resolution camera 14a, the laser irradiation unit 13a, and the wide-angle camera 14b are positioned adjacent to each other in this order from the X1 side to the X2 side.

The Z-direction movement mechanism 14c is configured to move the high-resolution camera 14a in the Z1 or Z2 direction. The Z-direction movement mechanism 14c has, for example, a linear conveyor module or a drive unit having a ball screw and a motor with an encoder. The Z-direction movement mechanism 14d is configured to move the wide-angle camera 14b in the Z1 or Z2 direction. The Z-direction movement mechanism 14d has, for example, a linear conveyor module or a drive unit having a ball screw and a motor with an encoder.

(Expanding device)
As shown in Figures 1, 6, and 7, the expanding device 2 is configured to divide the wafer W1 to form a plurality of semiconductor chips Ch (see Figure 8). The expanding device 2 is also configured to form sufficient gaps between the plurality of semiconductor chips Ch. Here, a modified layer is formed on the wafer W1 by irradiating the wafer W1 along dividing lines (streets) with a laser having a wavelength that is transparent to the wafer W1 in the dicing device 1. In the expanding device 2, the wafer W1 is divided along the modified layer that was previously formed in the dicing device 1, thereby forming a plurality of semiconductor chips Ch.

Therefore, by expanding the sheet member W2 in the expanding device 2, the wafer W1 is divided along the modified layer. Furthermore, by expanding the sheet member W2 in the expanding device 2, the gaps between the multiple semiconductor chips Ch formed by division are widened.

The expansion device 2 includes a base 201, a cassette unit 202, a lift-up hand unit 203, and a suction hand unit 204. The expansion device 2 also includes an expansion-related work unit 2a that performs work other than dicing on the wafer W1 after the dicing work has been performed. In the first embodiment, the work other than dicing is expansion-related work, including cooling the sheet member W2, expanding the sheet member W2, heat-shrinking the sheet member W2, irradiating the sheet member W2 with ultraviolet light, and squeegee braking the wafer W1. The expansion-related work unit 2a includes a base 205, a cold air supply unit 206, a cooling unit 207, an expansion unit 208, a base 209, an expansion-maintaining member 210, a heat-shrink unit 211, an ultraviolet light irradiation unit 212, a squeegee unit 213, and a clamp unit 214. The expanding-related work unit 2a is an example of a "non-dicing work unit" in the claims. The cassette unit 202 is an example of a "wafer storage unit" in the claims. The lift-up hand unit 203 and the suction hand unit 204 are an example of a "wafer transport unit" in the claims.

<base>
The base 201 is a base on which the cassette unit 202 and the lift-up hand unit 203 are installed. The base 201 has a rectangular shape in a plan view.

<Cassette section>
The cassette unit 202 is configured to be able to accommodate a plurality of wafer ring structures W (wafers W1). The cassette unit 202 includes a wafer cassette 202a, a Z-direction movement mechanism 202b, and a pair of mounting units 202c.

Multiple (three) wafer cassettes 202a are arranged in the Z direction. Each wafer cassette 202a has a storage space that can accommodate multiple (five) wafer ring structures W. The wafer ring structures W are manually supplied and placed in the wafer cassette 202a. Note that each wafer cassette 202a may accommodate one to four wafer ring structures W, or six or more wafer ring structures W. One, two, or four or more wafer cassettes 202a may also be arranged in the Z direction.

The Z-direction movement mechanism 202b is configured to move the wafer cassette 202a in the Z1 or Z2 direction. The Z-direction movement mechanism 202b has, for example, a linear conveyor module or a drive unit having a ball screw and a motor with an encoder. The Z-direction movement mechanism 202b also has a mounting table 202d that supports the wafer cassette 202a from below. Multiple mounting tables 202d (three in total) are arranged to match the positions of the multiple wafer cassettes 202a.

Multiple pairs of mounting portions 202c (five in total) are arranged inside the wafer cassette 202a. The ring-shaped member W3 of the wafer ring structure W is placed on the pair of mounting portions 202c from the Z1 side. One of the pair of mounting portions 202c protrudes in the X2 direction from the inner surface of the wafer cassette 202a on the X1 side. The other of the pair of mounting portions 202c protrudes in the X1 direction from the inner surface of the wafer cassette 202a on the X2 side.

<Lift-up hand part>
The lift-up hand portion 203 is configured to be able to take out the wafer ring structure W from the cassette portion 202. The lift-up hand portion 203 is also configured to be able to store the wafer ring structure W in the cassette portion 202.

Specifically, the lift-up hand unit 203 includes a Y-direction movement mechanism 203a and a lift-up hand 203b. The Y-direction movement mechanism 203a has, for example, a linear conveyor module or a drive unit having a ball screw and a motor with an encoder. The lift-up hand 203b is configured to support the ring-shaped member W3 of the wafer ring structure W from the Z2 direction side.

<Suction hand section>
The suction hand portion 204 is configured to suck the ring-shaped member W3 of the wafer ring structure W from the Z1 direction side.

Specifically, the suction hand unit 204 includes an X-direction movement mechanism 204a, a Z-direction movement mechanism 204b, and a suction hand 204c. The X-direction movement mechanism 204a is configured to move the suction hand 204c in the X direction. The Z-direction movement mechanism 204b is configured to move the suction hand 204c in the Z direction. The X-direction movement mechanism 204a and the Z-direction movement mechanism 204b each have a drive unit including, for example, a linear conveyor module or a ball screw and a motor with an encoder. The suction hand 204c is configured to suction and support the ring-shaped member W3 of the wafer ring structure W from the Z1 direction. Here, the suction hand 204c generates negative pressure to support the ring-shaped member W3 of the wafer ring structure W. The wafer ring structure W (wafer W1) is transported between the cassette unit 202, the dicing device 1, and the expansion-related work unit 2a by the lift-up hand unit 203 and the suction hand unit 204.

<base>
7 and 8, the base 205 is a base on which the expanding section 208, the cooling unit 207, the ultraviolet irradiation section 212, and the squeegee section 213 are mounted. The base 205 has a rectangular shape in a plan view. In addition, in Fig. 8, the clamp section 214, which is positioned in the Z1 direction of the cooling unit 207, is indicated by a dotted line.

<Cold air supply section>
The cool air supply unit 206 is configured to supply cool air to the sheet member W2 from the Z1 direction side when the expanding unit 208 expands the sheet member W2.

Specifically, the cold air supply unit 206 has a supply unit main body 206a, a cold air supply port 206b, and a movement mechanism 206c. The cold air supply port 206b is configured to allow cold air supplied from the cold air supply device to flow out. The cold air supply port 206b is provided at the end of the supply unit main body 206a on the Z2 direction side. The cold air supply port 206b is located in the center of the end of the supply unit main body 206a on the Z2 direction side. The movement mechanism 206c has, for example, a linear conveyor module or a motor with a ball screw and an encoder.

The cold air supply device is a device for generating cold air. The cold air supply device supplies air that has been cooled, for example, by a heat pump. Such a cold air supply device is installed on the base 205. The cold air supply unit 206 and the cold air supply device are connected by a hose (not shown).

<Cooling unit>
The cooling unit 207 is configured to cool the sheet member W2 from the Z2 direction side.

Specifically, the cooling unit 207 includes a cooling member 207a having a cooling body 271 and a Peltier element 272, and a Z-direction movement mechanism 207b. The cooling body 271 is made of a material with a large heat capacity and high thermal conductivity. The cooling body 271 is made of a metal such as aluminum. The Peltier element 272 is configured to cool the cooling body 271. Note that the cooling body 271 is not limited to aluminum and may be made of another material with a large heat capacity and high thermal conductivity. The Z-direction movement mechanism 207b is a cylinder.

The cooling unit 207 is configured to be movable in the Z1 or Z2 direction by the Z-direction movement mechanism 207b. This allows the cooling unit 207 to move to a position in contact with the sheet material W2 and to a position spaced apart from the sheet material W2.

<Expanding section>
The expanding section 208 is configured to expand the sheet member W2 of the wafer ring structure W, thereby dividing the wafer W1 along the dividing line.

Specifically, the expansion section 208 has an expansion ring 281. The expansion ring 281 is configured to support the sheet member W2 from the Z2 direction side, thereby expanding (expanding) the sheet member W2. The expansion ring 281 has a ring shape in a plan view. The structure of the expansion ring 281 will be described in detail later.

<base>
The base 209 is a base material on which the cold air supply part 206, the expansion and maintaining member 210 and the heat shrink part 211 are installed.

<Expansion maintenance member>
As shown in Figures 7 and 8, the expansion maintaining member 210 is configured to press the sheet member W2 from the Z1 direction side so that the sheet member W2 near the wafer W1 does not shrink due to heating by the heating ring 211a.

Specifically, the expansion retention member 210 has a pressure ring portion 210a, a lid portion 210b, and an intake portion 210c. The pressure ring portion 210a has a ring shape in a plan view. The lid portion 210b is attached to the pressure ring portion 210a so as to close the opening of the pressure ring portion 210a. The intake portion 210c is an intake ring having a ring shape in a plan view. Multiple intake ports are formed on the underside of the intake portion 210c on the Z2 side. The pressure ring portion 210a is configured to move in the Z direction by a Z-direction movement mechanism 210d. That is, the Z-direction movement mechanism 210d is configured to move the pressure ring portion 210a to a position where it presses the sheet member W2 and to a position away from the sheet member W2. The Z-direction movement mechanism 210d has, for example, a linear conveyor module or a drive unit including a ball screw and a motor with an encoder.

<Heat shrink section>
The heat shrink section 211 is configured to shrink the sheet member W2 expanded by the expanding section 208 by heating while maintaining the gaps between the plurality of semiconductor chips Ch.

The heat shrink unit 211 has a heating ring 211a and a Z-direction movement mechanism 211b. The heating ring 211a has a ring shape in a plan view. The heating ring 211a also has a sheathed heater that heats the sheet member W2. The Z-direction movement mechanism 211b is configured to move the heating ring 211a in the Z direction. The Z-direction movement mechanism 211b has, for example, a linear conveyor module or a drive unit having a ball screw and a motor with an encoder.

<Ultraviolet irradiation section>
The ultraviolet irradiating unit 212 is configured to irradiate the sheet member W2 with ultraviolet rays in order to reduce the adhesive strength of the adhesive layer of the sheet member W2. Specifically, the ultraviolet irradiating unit 212 has an ultraviolet illuminator. The ultraviolet irradiating unit 212 is disposed at the end of the squeegee unit 213 on the Z1 direction side of a pressing unit 213a (described later). The ultraviolet irradiating unit 212 is configured to irradiate the sheet member W2 with ultraviolet rays while moving together with the squeegee unit 213.

<Squeegee Section>
The squeegee unit 213 is configured to expand the sheet member W2 and then locally press the wafer W1 from the Z2 direction side to further divide the wafer W1 along the modified layer. Specifically, the squeegee unit 213 has a pressing unit 213a, a Z-direction moving mechanism 213b, an X-direction moving mechanism 213c, and a rotating mechanism 213d.

The pressing unit 213a is configured to press the wafer W1 from the Z2 direction side via the sheet member W2 while moving using the rotation mechanism 213d and the X-direction movement mechanism 213c, thereby generating bending stress in the wafer W1 and dividing the wafer W1 along the modified layer. When the pressing unit 213a is raised to an elevated position on the Z1 direction side by the Z-direction movement mechanism 213b, the wafer W1 is pressed via the sheet member W2. When the pressing unit 213a is lowered to a lower position on the Z2 direction side by the Z-direction movement mechanism 213b, the wafer W1 is no longer pressed. The pressing unit 213a is a squeegee.

The pressing unit 213a is attached to the Z1-direction end of the Z-direction movement mechanism 213b. The Z-direction movement mechanism 213b is configured to move the pressing unit 213a linearly in the Z1 or Z2 direction. The Z-direction movement mechanism 213b is, for example, a cylinder. The Z-direction movement mechanism 213b is attached to the Z1-direction end of the X-direction movement mechanism 213c.

The X-direction movement mechanism 213c is attached to the end of the rotation mechanism 213d on the Z1 direction side. The X-direction movement mechanism 213c is configured to move the pressing part 213a linearly in one direction. The X-direction movement mechanism 213c has, for example, a linear conveyor module or a drive unit having a ball screw and a motor with an encoder.

In the squeegee unit 213, the pressing unit 213a is raised to a raised position by the Z-direction movement mechanism 213b. In the squeegee unit 213, the pressing unit 213a locally presses the wafer W1 from the Z2 direction side via the sheet member W2 while the X-direction movement mechanism 213c moves the pressing unit 213a in the Y direction, thereby dividing the wafer W1. In the squeegee unit 213, the pressing unit 213a is lowered to a lowered position by the Z-direction movement mechanism 213b. In the squeegee unit 213, after the pressing unit 213a has finished moving in the Y direction, the pressing unit 213a is rotated 90 degrees by the rotation mechanism 213d.

In the squeegee unit 213, the pressing unit 213a is raised to a raised position by the Z-direction movement mechanism 213b. After the pressing unit 213a rotates 90 degrees, the pressing unit 213a locally presses the wafer W1 from the Z2 direction via the sheet member W2 while the X-direction movement mechanism 213c moves the pressing unit 213a in the X direction, thereby dividing the wafer W1.

<Clamp section>
The clamp unit 214 (expanding table) is configured to grip the ring-shaped member W3 of the wafer ring structure W. Specifically, the clamp unit 214 has a gripping unit 214a, a Z-direction movement mechanism 214b, and a Y-direction movement mechanism 214c. The gripping unit 214a supports the ring-shaped member W3 from the Z2 direction side and presses the ring-shaped member W3 from the Z1 direction side. In this manner, the ring-shaped member W3 is gripped by the gripping unit 214a. The gripping unit 214a is attached to the Z-direction movement mechanism 214b.

The Z-direction movement mechanism 214b is configured to move the clamp unit 214 in the Z direction. Specifically, the Z-direction movement mechanism 214b is configured to move the gripping unit 214a in the Z1 direction or the Z2 direction. The Z-direction movement mechanism 214b has, for example, a linear conveyor module or a drive unit having a ball screw and a motor with an encoder. The Z-direction movement mechanism 214b is attached to the Y-direction movement mechanism 214c. The Y-direction movement mechanism 214c is configured to move the Z-direction movement mechanism 214b in the Y1 direction or the Y2 direction. The Y-direction movement mechanism 214c has, for example, a linear conveyor module or a drive unit having a ball screw and a motor with an encoder.

(Control configuration of semiconductor wafer processing device)
9, semiconductor wafer processing apparatus 100 includes a control unit 120 and a memory unit 112. Control unit 120 includes a first control unit 101, a second control unit 102, a third control unit 103, a fourth control unit 104, a fifth control unit 105, a sixth control unit 106, a seventh control unit 107, an eighth control unit 108, an expansion control calculation unit 109, a handling control calculation unit 110, and a dicing control calculation unit 111.

The first control unit 101 is configured to control the squeegee unit 213. The first control unit 101 includes a CPU (Central Processing Unit) and a storage unit having a ROM (Read Only Memory) and a RAM (Random Access Memory). The first control unit 101 may also include a storage unit such as a HDD (Hard Disk Drive) that retains stored information even after the voltage is cut off. The HDD may also be shared by the first control unit 101, second control unit 102, third control unit 103, fourth control unit 104, fifth control unit 105, sixth control unit 106, seventh control unit 107, and eighth control unit 108.

The second control unit 102 is configured to control the cold air supply unit 206 and the cooling unit 207. The second control unit 102 includes a CPU and a storage unit having ROM, RAM, etc. The third control unit 103 is configured to control the heat shrink unit 211 and the ultraviolet light irradiation unit 212. The third control unit 103 includes a CPU and a storage unit having ROM, RAM, etc. Note that the second control unit 102 and the third control unit 103 may include a storage unit such as an HDD that retains stored information even after the voltage is cut off.

The fourth control unit 104 is configured to control the cassette unit 202 and the lift-up hand unit 203. The fourth control unit 104 includes a CPU and a storage unit having ROM, RAM, etc. The fifth control unit 105 is configured to control the suction hand unit 204. The fifth control unit 105 includes a CPU and a storage unit having ROM, RAM, etc. Note that the fourth control unit 104 and the fifth control unit 105 may include a storage unit such as an HDD that retains stored information even after the voltage is cut off.

The sixth control unit 106 is configured to control the chuck table unit 12. The sixth control unit 106 includes a CPU and a storage unit having ROM, RAM, etc. The seventh control unit 107 is configured to control the laser unit 13. The seventh control unit 107 includes a CPU and a storage unit having ROM, RAM, etc. The eighth control unit 108 is configured to control the imaging unit 14. The eighth control unit 108 includes a CPU and a storage unit having ROM, RAM, etc. Note that the sixth control unit 106, seventh control unit 107, and eighth control unit 108 may each include a storage unit such as an HDD that retains stored information even after the voltage is cut off.

The expansion control calculation unit 109 is configured to perform calculations related to the expansion process of the sheet member W2 based on the processing results of the first control unit 101, the second control unit 102, and the third control unit 103. The expansion control calculation unit 109 includes a CPU and a storage unit having ROM, RAM, etc.

The handling control calculation unit 110 is configured to perform calculations related to the movement process of the wafer ring structure W based on the processing results of the fourth control unit 104 and the fifth control unit 105. The handling control calculation unit 110 includes a CPU and a storage unit having ROM, RAM, etc.

The dicing control calculation unit 111 is configured to perform calculations related to the dicing process of the wafer W1 based on the processing results of the sixth control unit 106, seventh control unit 107, and eighth control unit 108. The dicing control calculation unit 111 includes a CPU and a storage unit having ROM, RAM, etc.

The memory unit 112 stores programs for operating the dicing device 1 and the expanding device 2. The memory unit 112 includes ROM, RAM, HDD, etc.

(Semiconductor chip manufacturing process)
10 and 11, the general operation of the semiconductor wafer processing apparatus 100 will be described below. The detailed operation of the semiconductor wafer processing apparatus 100 will be described later.

In step S1, the wafer ring structure W is removed from the cassette unit 202. That is, the wafer ring structure W contained in the cassette unit 202 is supported by the lift-up hand 203b, and then the lift-up hand 203b is moved in the Y1 direction by the Y-direction movement mechanism 203a, thereby removing the wafer ring structure W from the cassette unit 202. In step S2, the wafer ring structure W is transferred to the chuck table unit 12 of the dicing apparatus 1 by the suction hand 204c. That is, the wafer ring structure W removed from the cassette unit 202 is moved in the X2 direction by the X-direction movement mechanism 204a while being sucked by the suction hand 204c. Then, the wafer ring structure W moved in the X2 direction is transferred from the suction hand 204c to the chuck table unit 12, and then gripped by the chuck table unit 12.

In step S3, a modified layer is formed on wafer W1 by laser unit 13. In step S4, the wafer ring structure W having wafer W1 on which the modified layer has been formed is transferred to clamp unit 214 by suction hand 204c. In step S5, sheet material W2 is cooled by cold air supply unit 206 and cooling unit 207. That is, the wafer ring structure W held by clamp unit 214 is moved (lowered) in the Z2 direction by Z-direction movement mechanism 214b to contact cooling unit 207, and cold air is supplied from the Z1 direction by cold air supply unit 206, thereby cooling sheet material W2.

In step S6, the wafer ring structure W is moved to the expansion unit 208 by the clamp unit 214. That is, the wafer ring structure W, with the sheet member W2 cooled, is moved in the Y1 direction by the Y-direction movement mechanism 214c while held by the clamp unit 214. In step S7, the sheet member W2 is expanded by the expansion unit 208. That is, the wafer ring structure W is moved in the Z2 direction by the Z-direction movement mechanism 214b while held by the clamp unit 214. Then, the sheet member W2 comes into contact with the expansion ring 281 and is expanded by being pulled by the expansion ring 281. As a result, the wafer W1 is divided along the division line (modified layer).

In step S8, the expanded sheet member W2 is pressed from the Z1 direction by the expansion retention member 210. That is, the pressure ring portion 210a is moved (lowered) in the Z2 direction by the Z-direction movement mechanism 210d until it abuts against the sheet member W2. Then, the process proceeds from point A in Figure 10 via point A in Figure 11 to step S9.

As shown in FIG. 11, in step S9, after the sheet member W2 is pressed by the expansion maintaining member 210, the squeegee unit 213 presses the wafer W1 while the ultraviolet irradiation unit 212 irradiates ultraviolet rays onto the sheet member W2. This causes the wafer W1 to be further divided by the squeegee unit 213. In addition, the adhesive strength of the sheet member W2 is reduced by the ultraviolet rays irradiated from the ultraviolet irradiation unit 212.

In step S10, the sheet material W2 is heated and shrunk by the heat shrink unit 211 while the clamp unit 214 rises. At this time, the intake unit 210c sucks in air near the heated sheet material W2. In step S11, the wafer ring structure W is transferred from the clamp unit 214 to the suction hand 204c. That is, while the wafer ring structure W is held by the clamp unit 214, it is moved in the Y2 direction by the Y-direction movement mechanism 214c. Then, at a position on the Z1 direction side of the cooling unit 207, the wafer ring structure W is released from the clamp unit 214 and then sucked by the suction hand 204c.

In step S12, the wafer ring structure W is transferred to the lift-up hand 203b by the suction hand 204c. In step S13, the wafer ring structure W is stored in the cassette unit 202. That is, the wafer ring structure W supported by the lift-up hand 203b is moved in the Y1 direction by the Y-direction movement mechanism 203a, and the wafer ring structure W is stored in the cassette unit 202. This completes the processing performed on one wafer ring structure W. Then, the process returns from point B in Figure 11 via point B in Figure 10 to step S1.

(Priority control)
12 and 13, in the first embodiment, the control unit 120 is configured to perform dicing priority control (see FIG. 12) in which the downtime of the dicing operation is made shorter than the downtime of the operation other than the dicing operation when the cycle time of the dicing operation is longer than the cycle time of the operation other than the dicing operation, and to perform non-dicing priority control (see FIG. 13) in which the downtime of the operation other than the dicing operation is made shorter than the downtime of the operation other than the dicing operation when the cycle time of the operation other than the dicing operation (expansion-related operation) is longer than the cycle time of the dicing operation. That is, the control unit 120 is configured to perform dicing priority control in which the dicing operation is a bottleneck between the dicing operation and the operation other than the dicing operation (expansion-related operation), and to perform non-dicing priority control in which the operation other than the dicing operation (expansion-related operation) is a bottleneck between the dicing operation and the operation other than the dicing operation (expansion-related operation).

In other words, the method for manufacturing semiconductor chips Ch using this semiconductor wafer processing apparatus 100 includes the steps of: using the dicing apparatus 1 to perform a dicing operation on a wafer W1 supplied from a cassette unit 202 that stores a wafer W1 on which multiple semiconductor chips Ch are formed, in order to divide the wafer W1 into individual semiconductor chips Ch; using the expansion-related work unit 2a to perform operations other than dicing on the diced wafer W1; transporting the wafer W1 between the cassette unit 202, the dicing apparatus 1, and the expansion-related work unit 2a using the lift-up hand unit 203 and the suction hand unit 204; and, if the cycle time for the dicing operation is longer than the cycle time for operations other than dicing, performing dicing priority control to shorten the downtime of the dicing operation shorter than the downtime of operations other than dicing, and, if the cycle time for operations other than dicing is longer than the cycle time for the dicing operation, performing non-dicing priority control to shorten the downtime of operations other than dicing.

The semiconductor chips Ch manufactured by this semiconductor wafer processing device 100 are made up of a cassette unit 202 that accommodates a wafer W1 on which multiple semiconductor chips Ch are formed, a dicing device 1 that performs dicing work on the wafer W1 supplied from the cassette unit 202 to divide it into individual semiconductor chips Ch, an expansion-related work unit 2a that performs work other than dicing on the wafer W1 that has undergone dicing work, a lift-up hand unit 203 that transports the wafer W1 between the cassette unit 202, the dicing device 1, and the expansion-related work unit 2a, and The semiconductor wafers are manufactured using a semiconductor wafer processing device 100 that includes a suction hand unit 204 and a control unit 120. The control unit 120 is configured to perform dicing priority control to make the downtime of dicing work shorter than the downtime of work other than dicing when the cycle time of the dicing work is longer than the cycle time of work other than dicing, and to perform non-dicing priority control to make the downtime of work other than dicing shorter than the downtime of dicing when the cycle time of work other than dicing is longer than the cycle time of the dicing work.

In addition, in the first embodiment, when dicing priority control is performed, the control unit 120 is configured to perform control such that the dicing operation is completed while the wafer W1 (wafer ring structure W) for the next dicing operation is pulled out of the cassette unit 202 by the lift-up hand unit 203 and left waiting. In addition, in the first embodiment, when dicing priority control is performed, the control unit 120 is configured to perform control such that the wafer W1 (wafer ring structure W) for which operations other than dicing have been completed is placed back into the cassette unit 202 by the lift-up hand unit 203 during the dicing operation.

In addition, in the first embodiment, when priority control is performed for operations other than dicing, the control unit 120 is configured to perform control to complete operations other than dicing while the lift-up hand unit 203 is free.In addition, in the first embodiment, when priority control is performed for operations other than dicing, the control unit 120 is configured to perform control to complete operations other than dicing while the wafer W1 (wafer ring structure W) is released from the chuck table unit 12 of the dicing device 1.

(Dicing priority control)
An example of operation in the case of dicing priority control will be described with reference to Figure 12. Dicing priority control is performed, for example, when the size of the semiconductor chip Ch is small, causing the dicing operation cycle time to be longer than the operation time (cycle time) of operations other than dicing (expansion-related operations), making the dicing operation a bottleneck. Note that in Figures 12 and 13, "n,""n+1," and "n+2" represent the nth, n+1th, and n+2th wafers W1 (wafer ring structures W), respectively. Furthermore, the operation of each unit in the dicing priority control is controlled by each control unit of the control unit 120.

As shown in FIG. 12 , first, the nth wafer W1 (wafer ring structure W) is pulled out of the cassette unit 202 by the lift-up hand unit 203. The suction hand unit 204 is moved to a position above the lift-up hand unit 203. The nth wafer W1 (wafer ring structure W) supported by the lift-up hand unit 203 is then transferred from the lift-up hand unit 203 to the suction hand unit 204. The suction hand unit 204 and the chuck table unit 12 are then moved, and the suction hand unit 204 is moved to a position above the chuck table unit 12. The nth wafer W1 (wafer ring structure W) suctioned and supported by the suction hand unit 204 is then transferred from the suction hand unit 204 to the chuck table unit 12. The nth wafer W1 (wafer ring structure W) is then gripped and fixed by the chuck table unit 12.

Thenth wafer W1 on the chuck table 12 is then imaged by the imaging unit 14. Based on the image of the nth wafer W1 by the imaging unit 14, any misalignment of the nth wafer W1 is corrected. The laser unit 13 then irradiates the nth wafer W1 with laser light. This forms a modified layer on the nth wafer W1, which will serve as the starting point for division. The nth wafer W1 (wafer ring structure W) is then rotated 90 degrees by the chuck table 12. After being rotated 90 degrees, the imaging unit 14 again images the nth wafer W1, and the laser unit 13 again irradiates the nth wafer W1 with laser light. The two laser light irradiations then form modified layers along the grid-like dividing lines (streets) of the nth wafer W1.

Furthermore, during the dicing operation on the nth wafer W1 (in FIG. 12, at the same time as the first image of the nth wafer W1 is taken by the imaging unit 14), the n+1th wafer W1 (i.e., the wafer W1 for the next dicing operation) is withdrawn from the cassette unit 202 by the lift-up hand unit 203. As a result, when the dicing operation on the nth wafer W1 is completed, the n+1th wafer W1 (wafer ring structure W) has been withdrawn from the cassette unit 202 and is waiting on the lift-up hand unit 203.

Furthermore, when the formation of the modified layer on the nth wafer W1 is completed, the chuck table 12 is moved to a position below the suction hand unit 204, and the nth wafer W1 (wafer ring structure W) is released from the chuck table 12. The nth wafer W1 (wafer ring structure W) is then transferred from the chuck table 12 to the suction hand unit 204.

Then, the suction hand unit 204 and the clamp unit 214 are moved, and the suction hand unit 204 is moved to a position above the clamp unit 214. The nth wafer W1 (wafer ring structure W) that has been sucked and supported by the suction hand unit 204 is then transferred from the suction hand unit 204 to the clamp unit 214.

Furthermore, after the nth wafer W1 (wafer ring structure W) is transferred from the suction hand unit 204 to the clamp unit 214, the suction hand unit 204 is moved to a position above the lift-up hand unit 203, where the (n+1)th wafer W1 (wafer ring structure W) is waiting. Then, the (n+1)th wafer W1 (wafer ring structure W) supported by the lift-up hand unit 203 is transferred from the lift-up hand unit 203 to the chuck table unit 12 via the suction hand unit 204. Then, the dicing operation is performed on the (n+1)th wafer W1 in the same manner as for the nth wafer W1.

Furthermore, when the nth wafer W1 (wafer ring structure W) is transferred from the suction hand unit 204 to the clamp unit 214, the nth wafer W1 (wafer ring structure W) is gripped and fixed in the clamp unit 214. Then, the sheet member W2 to which the nth wafer W1 fixed in the clamp unit 214 is attached is cooled by the cold air supply unit 206 and the cooling unit 207.

The clamp unit 214 is then moved to a position above the expander unit 208. The sheet member W2 to which the nth wafer W1 fixed by the clamp unit 214 is attached is expanded by the expander unit 208. At this time, the expansion of the sheet member W2 divides the nth wafer W1 along the modified layer. The sheet member W2 expanded by the expander unit 208 is then held down by the expansion maintaining member 210. The ultraviolet irradiation unit 212 then irradiates the sheet member W2 held down by the expansion maintaining member 210 with ultraviolet light, and the squeegee unit 213 presses the nth wafer W1 through the sheet member W2 (squeegee breaking). The heat shrink unit 211 then heat-shrinks the sheet member W2.

Then, the clamp unit 214 is moved to the position of the cold air supply unit 206 and the cooling unit 207, and the clamp unit 214 releases the nth wafer W1 (wafer ring structure W). The nth wafer W1 (wafer ring structure W) is then transferred from the clamp unit 214 to the suction hand unit 204. The suction hand unit 204 is then moved to a position above the lift-up hand unit 203. The nth wafer W1 (wafer ring structure W) is then transferred from the suction hand unit 204 to the lift-up hand unit 203. The nth wafer W1 (wafer ring structure W) is then placed in the cassette unit 202 by the lift-up hand unit 203.

At this time, since the dicing operation is being performed on the n+1th wafer W1, while the dicing operation on the n+1th wafer W1 is in progress, the nth wafer W1 (wafer ring structure W), for which operations other than dicing (expansion-related operations) have been completed, is stored in the cassette unit 202 by the lift-up hand unit 203. Operations other than dicing (expansion-related operations) are then stopped until the dicing operation on the n+1th wafer W1 is completed.

Furthermore, during the dicing operation on the n+1th wafer W1 (in FIG. 12, at the same time as the first irradiation of laser light by the laser unit 13 onto the n+1th wafer W1), the n+2th wafer W1 (i.e., the wafer W1 for the next dicing operation) is withdrawn from the cassette unit 202 by the lift-up hand unit 203. As a result, when the dicing operation on the n+1th wafer W1 is completed, the n+2th wafer W1 (wafer ring structure W) has been withdrawn from the cassette unit 202 and is waiting on the lift-up hand unit 203.

Furthermore, when the formation of the modified layer on the (n+1)th wafer W1 is completed, the (n+1)th wafer W1 (wafer ring structure W) is moved to the clamp unit 214 by the suction hand unit 204, just as in the case of the nth wafer W1.

Furthermore, after the (n+1)th wafer W1 (wafer ring structure W) is transferred to the clamp unit 214 by the suction hand unit 204, the suction hand unit 204 is moved to a position above the lift-up hand unit 203, where the (n+2)th wafer W1 (wafer ring structure W) is waiting. Then, the (n+2)th wafer W1 (wafer ring structure W) supported by the lift-up hand unit 203 is transferred from the lift-up hand unit 203 to the chuck table unit 12 via the suction hand unit 204. Then, the dicing operation is performed on the (n+2)th wafer W1 in the same manner as for the nth and (n+1)th wafers W1.

Furthermore, when the (n+1)th wafer W1 (wafer ring structure W) is transferred to the clamp unit 214 by the suction hand unit 204, the (n+1)th wafer W1 (wafer ring structure W) is gripped and fixed in the clamp unit 214. Then, as with the nth wafer W1, cooling of the sheet member W2, expansion of the sheet member W2 (division of the wafer W1), ultraviolet irradiation of the sheet member W2, squeegee breaking of the wafer W1, and heat shrinking of the sheet member W2 are performed. Then, as with the nth wafer W1, the (n+1)th wafer W1 is transferred from the clamp unit 214 to the cassette unit 202 via the suction hand unit 204 and lift-up hand unit 203.

At this time, since the dicing operation is being performed on the n+2th wafer W1, while the dicing operation on the n+2th wafer W1 is in progress, the n+1th wafer W1 (wafer ring structure W), for which operations other than dicing (expansion-related operations) have been completed, is stored in the cassette unit 202 by the lift-up hand unit 203. Operations other than dicing (expansion-related operations) are then stopped until the dicing operation on the n+2th wafer W1 is completed. Thereafter, the operations described above are repeated.

With dicing priority control, between one non-dicing operation (expanding-related operation) and the next non-dicing operation, the non-dicing operation is stopped until the dicing operation is completed. On the other hand, between one dicing operation and the next, the only downtime is the transfer of the wafer W1 between the chuck table 12 and the suction hand 204, and the dicing operation is essentially performed continuously. With dicing priority control, dicing operations are performed with approximately minimal downtime, and the downtime of dicing operations is shorter than the downtime of operations other than dicing operations.

(Priority control other than dicing)
An example of operation in the case of non-dicing priority control will be described with reference to Figure 13. Non-dicing priority control is performed, for example, when the size of the semiconductor chip Ch is large, causing the cycle time of work other than dicing (expanding-related work) to be longer than the work time (cycle time) of the dicing work, and the work other than dicing becomes a bottleneck. Note that the operation of each part in non-dicing priority control is controlled by each control unit of the control unit 120. Also, detailed description of parts similar to those in the above-mentioned dicing priority control will be omitted.

As shown in FIG. 13, first, the dicing operation for the nth wafer W1 is performed in the same manner as in the case of the dicing priority control described above. Then, as in the case of the dicing priority control described above, work other than dicing (expansion-related work) is performed on the nth wafer W1. Then, the dicing operation for the (n+1)th wafer W1 is performed in the same manner as in the case of the dicing priority control described above.

Furthermore, during an operation other than the dicing operation on the nth wafer W1 (in FIG. 13, at the same time as the movement of the clamp unit 214), the (n+1)th wafer W1 (wafer ring structure W) is released from the chuck table unit 12. As a result, when the operation other than the dicing operation on the nth wafer W1 is completed, the (n+1)th wafer W1 (wafer ring structure W) is released from the chuck table unit 12. Furthermore, during an operation other than the dicing operation on the nth wafer W1, the lift-up hand unit 203 is withdrawn from the cassette unit 202 and is no longer supporting the wafer W1. As a result, when the operation other than the dicing operation on the nth wafer W1 is completed, the lift-up hand unit 203 is empty.

Furthermore, when the dicing operation for the n+1th wafer W1 is completed, work other than dicing (expansion-related work) is being performed on the nth wafer W1, so the dicing operation for the n+1th wafer W1 is halted until the work other than dicing for the nth wafer W1 is completed.

Furthermore, after the nth wafer W1 (wafer ring structure W) is transferred from the suction hand unit 204 to the lift-up hand unit 203, the suction hand unit 204 is moved to a position above the chuck table unit 12 where the released n+1th wafer W1 (wafer ring structure W) is waiting. Then, the n+1th wafer W1 (wafer ring structure W) supported on the chuck table unit 12 is transferred from the chuck table unit 12 to the clamp unit 214 via the suction hand unit 204. Then, as with the nth wafer W1, operations other than dicing (expansion-related operations) are performed on the n+1th wafer W1.

Furthermore, when the nth wafer W1 (wafer ring structure W) is placed in the cassette unit 202 by the lift-up hand unit 203, the (n+2)th wafer W1 (wafer ring structure W) is withdrawn from the cassette unit 202 by the lift-up hand unit 203. The suction hand unit 204 is then moved to a position above the lift-up hand unit 203. The (n+2)th wafer W1 (wafer ring structure W) supported by the lift-up hand unit 203 is then transferred from the lift-up hand unit 203 to the chuck table unit 12 via the suction hand unit 204. Then, the dicing operation for the (n+2)th wafer W1 is performed in the same manner as for the nth and (n+1)th wafers W1.

Furthermore, during operations other than dicing of the n+1th wafer W1 (in FIG. 13, before the clamp unit 214 is released), the n+2th wafer W1 (wafer ring structure W) is released from the chuck table unit 12. As a result, when operations other than dicing of the n+1th wafer W1 are completed, the n+2th wafer W1 (wafer ring structure W) is released from the chuck table unit 12. Furthermore, during operations other than dicing of the n+1th wafer W1, the lift-up hand unit 203 is withdrawn from the cassette unit 202 and is no longer supporting the wafer W1. As a result, when operations other than dicing of the n+1th wafer W1 are completed, the lift-up hand unit 203 is empty.

Furthermore, when the dicing operation for the n+2th wafer W1 is completed, operations other than dicing (expansion-related operations) are being performed on the n+1th wafer W1, so the dicing operation for the n+2th wafer W1 is halted until operations other than dicing for the n+1th wafer W1 are completed. Thereafter, the operations described above are repeated.

With non-dicing priority control, between one dicing operation and the next, the dicing operation is stopped until the non-dicing operation is completed. On the other hand, between one non-dicing operation (expanding-related operation) and the next non-dicing operation, the only downtime is the transfer of wafer W1 between the clamp unit 214 and the suction hand unit 204, and the operations are essentially performed continuously. With non-dicing priority control, operations other than dicing are performed with approximately minimal downtime, and the downtime of operations other than dicing is shorter than the downtime of dicing.

(Effects of the first embodiment)
In the first embodiment, the following effects can be obtained.

In the first embodiment, as described above, the control unit 120 is configured to perform dicing priority control, which shortens the downtime of dicing operations compared to the downtime of operations other than dicing, when the cycle time of the dicing operation is longer than the cycle time of operations other than dicing; and to perform non-dicing priority control, which shortens the downtime of operations other than dicing, when the cycle time of operations other than dicing is longer than the cycle time of the dicing operation. This makes it possible to reduce the downtime of the bottleneck operation (operation with a long cycle time) between dicing and operations other than dicing, compared to when priority control is not performed. As a result, whether dicing or operations other than dicing are the bottleneck, it is possible to prevent lost time in equipment operation. This makes it possible to prevent a decrease in productivity even when a bottleneck operation exists.

Furthermore, in the first embodiment, as described above, the dicing operation is a dicing operation in which the wafer W1 is diced using a laser, and the operations other than the dicing operation are expansion-related operations, including expanding the stretchable sheet member W2 to which the wafer W1 is attached. This makes it possible to suppress a decline in productivity even when a bottleneck operation exists in the semiconductor wafer processing apparatus 100, which performs the dicing operation in which the wafer W1 is diced using a laser and expansion-related operations.

Furthermore, in the first embodiment, as described above, when performing dicing priority control, the control unit 120 is configured to perform control to complete the dicing operation while the wafer W1 for the next dicing operation is being withdrawn from the cassette unit 202 by the lift-up hand unit 203 and left waiting. This allows the wafer W1 for the next dicing operation to be left waiting, so that when the next dicing operation begins, the wafer W1 for the next dicing operation can be quickly supplied. As a result, when the dicing operation becomes a bottleneck, the downtime of the dicing operation can be easily reduced.

Furthermore, in the first embodiment, as described above, when dicing priority control is performed, the control unit 120 is configured to control the lift-up hand unit 203 to store, into the cassette unit 202, a wafer W1 for which operations other than dicing have been completed, during the dicing operation. This allows the wafer W1 for which operations other than dicing have been completed to be stored into the cassette unit 202 at an effective timing that does not extend the downtime of the dicing operation.

Furthermore, in the first embodiment, as described above, when performing non-dicing priority control, the control unit 120 is configured to perform control to complete operations other than dicing while leaving the lift-up hand unit 203 free. By leaving the lift-up hand unit 203 free, the wafer W1 can be quickly transferred to the lift-up hand unit 203 when operations other than dicing are completed. Therefore, when operations other than dicing become a bottleneck, the downtime of operations other than dicing can be easily reduced.

Furthermore, in the first embodiment, as described above, when performing non-dicing priority control, the control unit 120 is configured to perform control to complete operations other than dicing while the wafer W1 is released from the dicing apparatus 1. In this way, by releasing the wafer W1 from the dicing apparatus 1, when operations other than dicing are completed, the wafer W1 for which the dicing operation has been completed can be quickly supplied to operations other than dicing. As a result, the downtime of operations other than dicing can be easily reduced.

Second Embodiment
The configuration of a semiconductor wafer processing apparatus 300 according to the second embodiment will be described with reference to Figures 14 to 19. In the second embodiment, unlike the first embodiment, a squeegee unit 3213 is disposed outside an expand ring 3281. Note that in the second embodiment, detailed description of the same configuration as in the first embodiment will be omitted. Note that the semiconductor wafer processing apparatus 300 is an example of a "wafer processing apparatus" in the claims.

(Semiconductor wafer processing equipment)
As shown in FIGS. 14 and 15, the semiconductor wafer processing apparatus 300 is an apparatus for processing a wafer W1 provided on a wafer ring structure W.

The semiconductor wafer processing device 300 also includes a dicing device 1 and an expanding device 302. The vertical direction is the Z direction, the upward direction is the Z1 direction, and the downward direction is the Z2 direction. The horizontal direction perpendicular to the Z direction in which the dicing device 1 and the expanding device 302 are aligned is the X direction, the X1 direction is the X side of the X direction toward the expanding device 302, and the X2 direction is the X side of the X direction toward the dicing device 1. The horizontal direction perpendicular to the X direction is the Y direction, one side of the Y direction is the Y1 direction, and the other side of the Y direction is the Y2 direction.

(Dicing equipment)
The dicing device 1 is configured to form a modified layer by irradiating the wafer W1 with a laser having a wavelength that is transparent to the wafer W1 along the dividing lines (streets).

Specifically, the dicing device 1 includes a base 11, a chuck table unit 12, a laser unit 13, and an imaging unit 14.

(Expanding device)
As shown in FIGS. 15 and 16, the expanding device 302 is configured to divide the wafer W1 into a plurality of semiconductor chips Ch.

The expansion device 302 includes a base 201, a cassette unit 202, a lift-up hand unit 203, and a suction hand unit 204. The expansion device 302 also includes an expansion-related work unit 302a that performs work other than dicing on the wafer W1 after the dicing work has been performed. In the second embodiment, the work other than dicing is expansion-related work, including cooling the sheet member W2, expanding the sheet member W2, heat-shrinking the sheet member W2, irradiating the sheet member W2 with ultraviolet light, and squeegee braking the wafer W1. The expansion-related work unit 302a includes a base 205, a cold air supply unit 206, a cooling unit 207, an expansion unit 3208, a base 209, an expansion maintenance member 210, a heat-shrink unit 211, an ultraviolet light irradiation unit 212, a squeegee unit 3213, and a clamp unit 214. The expanding-related work unit 302a is an example of a "work unit other than dicing" in the claims.

<Expanding section>
The expanding section 3208 is configured to expand the sheet member W2 of the wafer ring structure W, thereby dividing the wafer W1 along the dividing line.

Specifically, the expansion section 3208 has an expansion ring 3281 and a Z-direction movement mechanism 3282.

The expansion ring 3281 is configured to support the sheet member W2 from the Z2 direction side, thereby expanding the sheet member W2. The expansion ring 3281 has a ring shape in a plan view. The Z-direction movement mechanism 3282 is configured to move the expansion ring 3281 in the Z1 direction or the Z2 direction. The Z-direction movement mechanism 3282 has, for example, a linear conveyor module or a drive unit having a ball screw and a motor with an encoder. The Z-direction movement mechanism 3282 is attached to the base 205.

<Squeegee Section>
The squeegee unit 3213 is configured to expand the sheet member W2 and then press the wafer W1 from the Z2 direction side to further divide the wafer W1 along the modified layer. Specifically, the squeegee unit 3213 has a pressing unit 3213a, an X-direction moving mechanism 3213b, a Z-direction moving mechanism 3213c, and a rotating mechanism 3213d.

The pressing unit 3213a is configured to move in the Z1 direction by the Z-direction movement mechanism 3213c, and then move by the rotation mechanism 3213d and the X-direction movement mechanism 3213b while pressing the wafer W1 from the Z2 direction via the sheet member W2, thereby generating bending stress in the wafer W1 and dividing the wafer W1 along the modified layer. The pressing unit 3213a is a squeegee. The pressing unit 3213a is attached to the Z1 direction end of the rotation mechanism 3213d. The Z-direction movement mechanism 3213c is configured to move the rotation mechanism 3213d in the Z1 direction or the Z2 direction. The Z-direction movement mechanism 3213c has, for example, a cylinder. The Z-direction movement mechanism 3213c is attached to the Z1 direction end of the X-direction movement mechanism 3213b. The X-direction movement mechanism 3213b has, for example, a linear conveyor module or a drive unit including a ball screw and a motor with an encoder. The X-direction movement mechanism 3213b is attached to the end of the base 205 on the Z1 direction side.

The squeegee unit 3213 is moved in the Z1 direction by the Z-direction movement mechanism 3213c, and then the pressing unit 3213a presses the wafer W1 from the Z2 direction side via the sheet member W2 while the X-direction movement mechanism 3213b moves the pressing unit 3213a in the Y direction, thereby dividing the wafer W1. After the pressing unit 3213a has finished moving in the Y direction, the rotation mechanism 3213d rotates the pressing unit 3213a 90 degrees. After the pressing unit 3213a rotates 90 degrees, the squeegee unit 3213 is moved in the X direction by the X-direction movement mechanism 3213b while the pressing unit 3213a presses the wafer W1 from the Z2 direction side via the sheet member W2, thereby dividing the wafer W1.

(Control configuration of semiconductor wafer processing device)
17 , semiconductor wafer processing apparatus 300 includes a control unit 320 and a memory unit 112. Control unit 320 includes a first control unit 101, a second control unit 102, a third control unit 103, a fourth control unit 3104, a fifth control unit 3105, a sixth control unit 3106, a seventh control unit 3107, an eighth control unit 3108, a ninth control unit 3109, an expanding control calculation unit 3110, a handling control calculation unit 3111, a dicing control calculation unit 3112, and a memory unit 3113. The first control unit 101, the second control unit 102, the third control unit 103, the fifth control unit 3105, the sixth control unit 3106, the seventh control unit 3107, the eighth control unit 3108, the ninth control unit 3109, the expansion control calculation unit 3110, the handling control calculation unit 3111, the dicing control calculation unit 3112, and the memory unit 3113 have the same configuration as the first control unit 101, the second control unit 102, the third control unit 103, the fourth control unit 104, the fifth control unit 105, the sixth control unit 106, the seventh control unit 107, the eighth control unit 108, the expansion control calculation unit 109, the handling control calculation unit 110, the dicing control calculation unit 111, and the memory unit 112 of the first embodiment, respectively, and therefore their explanation will be omitted.

The fourth control unit 3104 is configured to control the expansion unit 3208. The fourth control unit 3104 includes a CPU and a storage unit having ROM, RAM, etc. The fourth control unit 3104 may also include a storage unit such as an HDD that retains stored information even after the voltage is cut off.

(Semiconductor chip manufacturing process)
18 and 19, the general operation of the semiconductor wafer processing apparatus 300 will be described below.

Steps S1 to S6, S8, and S11 are the same as steps S1 to S6, S8, and S11, respectively, in the semiconductor chip manufacturing process of the first embodiment, and therefore will not be described here.

In step S307, the sheet member W2 is expanded by the expansion unit 3208. That is, the expansion ring 3281 is moved in the Z1 direction by the Z-direction movement mechanism 3282. The wafer ring structure W, while held by the clamp unit 214, is moved in the Z2 direction by the Z-direction movement mechanism 214b. Then, the sheet member W2 comes into contact with the expansion ring 3281 and is expanded by being pulled by the expansion ring 3281. As a result, the wafer W1 is divided along the division line (modified layer).

As shown in FIG. 19, in step S309, the heat shrink unit 211 heats and shrinks the sheet material W2, and the ultraviolet irradiation unit 212 irradiates ultraviolet light onto the sheet material W2 while the clamp unit 214 rises. At this time, the intake unit 210c sucks in air near the heated sheet material W2. In step S310, the clamp unit 214 moves the wafer ring structure W to the squeegee unit 3213. That is, while the wafer ring structure W is held by the clamp unit 214, it is moved in the Y2 direction by the Y-direction movement mechanism 214c.

In step S311, the wafer ring structure W is moved to the squeegee portion 3213, and then the wafer W1 is pressed by the squeegee portion 3213. As a result, the wafer W1 is further divided by the squeegee portion 3213.

The configuration of the control unit 320 is similar to that of the control unit 120 in the first embodiment, and therefore a detailed description will be omitted. That is, when the cycle time of the dicing operation is longer than the cycle time of operations other than dicing, the control unit 320 performs dicing priority control to shorten the downtime of the dicing operation compared to the downtime of operations other than dicing, and when the cycle time of operations other than dicing (expanding-related operations) is longer than the cycle time of the dicing operation, the control unit 320 performs non-dicing priority control to shorten the downtime of operations other than dicing compared to the downtime of the dicing operation. The remaining configuration of the second embodiment is similar to that of the first embodiment.

(Effects of the second embodiment)
In the second embodiment, the following effects can be obtained.

In the second embodiment, the control unit 320 is configured to perform dicing priority control, which shortens the downtime of dicing operations compared to the downtime of operations other than dicing, when the cycle time of the dicing operation is longer than the cycle time of operations other than dicing, and to perform non-dicing priority control, which shortens the downtime of operations other than dicing, when the cycle time of operations other than dicing is longer than the cycle time of the dicing operation. This makes it possible to suppress declines in productivity even when a bottleneck operation exists, just like in the first embodiment. Note that other effects of the second embodiment are the same as those of the first embodiment.

[Modification]
It should be noted that the embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims rather than the description of the above embodiments, and further includes all modifications (variations) within the meaning and scope equivalent to the claims.

For example, in the first and second embodiments described above, an example was shown in which the control unit includes multiple control units, but the present invention is not limited to this. In the present invention, the control unit may be a single control unit. Furthermore, the control units in the first and second embodiments described above are merely examples, and there are no particular limitations on the number of control units or the division of functions.

In addition, in the first and second embodiments described above, an example was shown in which the dicing operation was a dicing operation in which a wafer was diced using a laser, but the present invention is not limited to this. In the present invention, the dicing operation may be a dicing operation other than a dicing operation in which a wafer is diced using a laser.

In addition, while the first and second embodiments above show examples in which the work other than the dicing work is expansion-related work, the present invention is not limited to this. In the present invention, the work other than the dicing work may be work other than expansion-related work. Furthermore, the expansion-related work does not have to include all of cooling the sheet member, expanding the sheet member, heat-shrinking the sheet member, irradiating the sheet member with ultraviolet light, and squeegee breaking the wafer. Furthermore, the expansion-related work may include work other than cooling the sheet member, expanding the sheet member, heat-shrinking the sheet member, irradiating the sheet member with ultraviolet light, and squeegee breaking the wafer.

Furthermore, in the above first and second embodiments, an example was shown in which the wafer transfer unit included a lift-up hand unit and a suction hand unit, but the present invention is not limited to this. In the present invention, the wafer transfer unit may have a configuration other than a configuration including a lift-up hand unit and a suction hand unit.

Furthermore, in the above first and second embodiments, for the sake of convenience, an example has been shown in which the control processing is explained using a flow-driven flowchart in which processing is performed sequentially according to a processing flow, but the present invention is not limited to this. In the present invention, the control processing may be performed by event-driven processing in which processing is performed on an event-by-event basis. In this case, the control processing may be performed completely event-driven, or may be performed in a combination of event-driven and flow-driven processing.

1. Dicing device (dicing work section)
2a, 302a Expanding related work section (work section other than dicing)
100, 300 Semiconductor wafer processing device (wafer processing device)
120, 320 Control unit 202 Cassette unit (wafer storage unit)
203 Lift-up hand unit (wafer transport unit)
204 suction hand unit (wafer transport unit)
Ch Semiconductor chip W1 Wafer W2 Sheet material

Claims (7)

a wafer accommodating section for accommodating a wafer on which a plurality of semiconductor chips are formed;
a dicing operation unit that performs a dicing operation on the wafer supplied from the wafer accommodation unit to divide the wafer into individual semiconductor chips;
a non-dicing operation unit that performs an operation other than the dicing operation on the wafer on which the dicing operation has been performed;
a wafer transfer unit that transfers the wafer between the wafer accommodation unit, the dicing work unit, and the non-dicing work unit;
a control unit,
the control unit is configured to, when a cycle time of the dicing operation is longer than a cycle time of an operation other than the dicing operation, perform dicing priority control to make the stop time of the dicing operation shorter than the stop time of the operation other than the dicing operation, and, when the cycle time of the operation other than the dicing operation is longer than the cycle time of the dicing operation, perform non-dicing priority control to make the stop time of the operation other than the dicing operation shorter than the stop time of the dicing operation ,
the dicing operation is a dicing operation of dicing the wafer by a laser,
The wafer processing apparatus , wherein the operation other than the dicing operation is an expansion-related operation including expanding an elastic sheet member to which the wafer is attached . a wafer accommodating section for accommodating a wafer on which a plurality of semiconductor chips are formed;
a dicing operation unit that performs a dicing operation on the wafer supplied from the wafer accommodation unit to divide the wafer into individual semiconductor chips;
a non-dicing operation unit that performs an operation other than the dicing operation on the wafer on which the dicing operation has been performed;
a wafer transfer unit that transfers the wafer between the wafer accommodation unit, the dicing work unit, and the non-dicing work unit;
a control unit,
the control unit is configured to, when a cycle time of the dicing operation is longer than a cycle time of an operation other than the dicing operation, perform dicing priority control to make the stop time of the dicing operation shorter than the stop time of the operation other than the dicing operation, and, when the cycle time of the operation other than the dicing operation is longer than the cycle time of the dicing operation, perform non-dicing priority control to make the stop time of the operation other than the dicing operation shorter than the stop time of the dicing operation,
The control unit is configured to control the wafer processing apparatus so that, when the dicing priority control is performed , the dicing operation is completed while the wafer for the next dicing operation is withdrawn from the wafer storage unit by the wafer transport unit and left waiting. a wafer accommodating section for accommodating a wafer on which a plurality of semiconductor chips are formed;
a dicing operation unit that performs a dicing operation on the wafer supplied from the wafer accommodation unit to divide the wafer into individual semiconductor chips;
a non-dicing operation unit that performs an operation other than the dicing operation on the wafer on which the dicing operation has been performed;
a wafer transfer unit that transfers the wafer between the wafer accommodation unit, the dicing work unit, and the non-dicing work unit;
a control unit,
the control unit is configured to, when a cycle time of the dicing operation is longer than a cycle time of an operation other than the dicing operation, perform dicing priority control to make the stop time of the dicing operation shorter than the stop time of the operation other than the dicing operation, and, when the cycle time of the operation other than the dicing operation is longer than the cycle time of the dicing operation, perform non-dicing priority control to make the stop time of the operation other than the dicing operation shorter than the stop time of the dicing operation,
The control unit is configured to control the wafer processing apparatus so that, when the dicing priority control is performed , the wafer transport unit accommodates the wafer on which operations other than the dicing operation have been completed in the wafer accommodation unit during the dicing operation. a wafer accommodating section for accommodating a wafer on which a plurality of semiconductor chips are formed;
a dicing operation unit that performs a dicing operation on the wafer supplied from the wafer accommodation unit to divide the wafer into individual semiconductor chips;
a non-dicing operation unit that performs an operation other than the dicing operation on the wafer on which the dicing operation has been performed;
a wafer transfer unit that transfers the wafer between the wafer accommodation unit, the dicing work unit, and the non-dicing work unit;
a control unit,
the control unit is configured to, when a cycle time of the dicing operation is longer than a cycle time of an operation other than the dicing operation, perform dicing priority control to make the stop time of the dicing operation shorter than the stop time of the operation other than the dicing operation, and, when the cycle time of the operation other than the dicing operation is longer than the cycle time of the dicing operation, perform non-dicing priority control to make the stop time of the operation other than the dicing operation shorter than the stop time of the dicing operation,
The control unit is configured to perform control to complete operations other than the dicing operation while keeping the wafer transport unit empty when performing the priority control for operations other than dicing. a wafer accommodating section for accommodating a wafer on which a plurality of semiconductor chips are formed;
a dicing operation unit that performs a dicing operation on the wafer supplied from the wafer accommodation unit to divide the wafer into individual semiconductor chips;
a non-dicing operation unit that performs an operation other than the dicing operation on the wafer on which the dicing operation has been performed;
a wafer transfer unit that transfers the wafer between the wafer accommodation unit, the dicing work unit, and the non-dicing work unit;
a control unit,
the control unit is configured to, when a cycle time of the dicing operation is longer than a cycle time of an operation other than the dicing operation, perform dicing priority control to make the stop time of the dicing operation shorter than the stop time of the operation other than the dicing operation, and, when the cycle time of the operation other than the dicing operation is longer than the cycle time of the dicing operation, perform non-dicing priority control to make the stop time of the operation other than the dicing operation shorter than the stop time of the dicing operation,
The control unit is configured to perform control to complete operations other than the dicing operation while releasing the fixation of the wafer in the dicing operation unit when performing the priority control for operations other than dicing. a step of performing a dicing operation by a dicing operation unit on a wafer supplied from a wafer accommodation unit that accommodates a wafer on which a plurality of semiconductor chips are formed, for dividing the wafer into the semiconductor chips;
a step of performing an operation other than the dicing operation on the wafer on which the dicing operation has been performed by a non-dicing operation unit;
transporting the wafer between the wafer accommodation unit, the dicing work unit, and the non-dicing work unit by a wafer transport unit;
a step of performing dicing priority control to make the downtime of the dicing operation shorter than the downtime of the operation other than the dicing operation when the cycle time of the dicing operation is longer than the cycle time of the operation other than the dicing operation, and performing non-dicing priority control to make the downtime of the operation other than the dicing operation shorter than the downtime of the dicing operation when the cycle time of the operation other than the dicing operation is longer than the cycle time of the dicing operation ,
the dicing operation is a dicing operation of dicing the wafer by a laser,
A method for manufacturing semiconductor chips, wherein the operations other than the dicing operation are expansion-related operations including expanding an elastic sheet member to which the wafer is attached . a wafer storage unit that stores a wafer on which a plurality of semiconductor chips are formed; a dicing operation unit that performs a dicing operation on the wafer supplied from the wafer storage unit to divide the wafer into the semiconductor chips; a non-dicing operation unit that performs an operation other than the dicing operation on the wafer on which the dicing operation has been performed; a wafer transport unit that transports the wafer between the wafer storage unit, the dicing operation unit, and the non-dicing operation unit; and a control unit, wherein the control unit is configured to stop the dicing operation when a cycle time of the dicing operation is longer than a cycle time of an operation other than the dicing operation. and if the cycle time of the operation other than the dicing operation is longer than the cycle time of the dicing operation, performs dicing priority control such that the stop time of the operation other than the dicing operation is shorter than the stop time of the dicing operation , wherein the dicing operation is a dicing operation of dicing the wafer with a laser, and the operation other than the dicing operation is an expansion-related operation including expanding an elastic sheet member to which the wafer is attached .