JP7798749B2 - Method for manufacturing nitride semiconductor device - Google Patents

Description

The technology disclosed in this specification relates to a method for manufacturing a nitride semiconductor device.

In order to activate dopants ion-implanted into nitride semiconductor layers made from GaN (gallium nitride), high-temperature heat treatment at temperatures above 1200°C is required. However, when heat treatment is performed at such high temperatures, nitrogen is removed from the surface of the nitride semiconductor layer, resulting in the formation of pits on the surface of the nitride semiconductor layer.

Patent Document 1 discloses a technique for forming a cap layer made of AlGaN (aluminum gallium nitride) on the surface of a nitride semiconductor layer to prevent nitrogen from escaping from the surface of the nitride semiconductor layer.

JP 2015-534058 A

When the aluminum composition ratio of an AlGaN (aluminum gallium nitride) cap layer is reduced, the lattice mismatch with the GaN (gallium nitride) nitride semiconductor layer is reduced, suppressing the occurrence of cracks during high-temperature heat treatment; however, the melting point is lowered and heat resistance is impaired. On the other hand, when the aluminum composition ratio of an AlGaN (aluminum gallium nitride) cap layer is increased, the melting point is raised and heat resistance is improved; however, the lattice mismatch with the GaN (gallium nitride) nitride semiconductor layer is increased, causing cracks to occur during high-temperature heat treatment. Thus, it is difficult for an AlGaN (aluminum gallium nitride) cap layer to achieve both the suppression of cracks during high-temperature heat treatment and heat resistance.

The present specification aims to provide a capping layer that is suitable for suppressing nitrogen loss from the surface of a nitride semiconductor layer during high-temperature heat treatment.

The method for manufacturing a nitride semiconductor device (1) disclosed herein may include the steps of ion-implanting a dopant into a nitride semiconductor layer (14) made of GaN, forming a cap layer (50) on at least a portion of the surface of the nitride semiconductor layer, and annealing to activate the dopant by heat treatment. Here, the surface of the nitride semiconductor layer is the surface that would be exposed to the outside during the annealing step if no cap layer were formed. The cap layer may be formed on the entire surface of the nitride semiconductor layer, or on only a portion of the surface where electrical characteristics may be affected by pits due to nitrogen loss. The cap layer includes a material that has a lattice mismatch with GaN of less than 2.5% and a melting point of 1500°C or higher. The cap layer used in the above manufacturing method is not particularly limited, but may contain at least one material selected from the group consisting of ScN, Sc _x Al _1-x N (0<x≦0.36), HfN, ZrN, ZnO, ScMgAlO ₄ , MnO, TaC, NbC, Mo, W, ZrB ₂ , WB ₂ , MoB ₂ , and ITO.

AlN (aluminum nitride), a commonly used cap layer material, has a lattice mismatch with GaN (gallium nitride) of 2.5%. Cap layers made of AlN (aluminum nitride) have been known to suffer from cracking during high-temperature heat treatment due to the difference in lattice constant between AlN and nitride semiconductor layers made of GaN (gallium nitride). The material contained in the cap layer used in the above manufacturing method has a lattice mismatch with GaN (gallium nitride) of less than 2.5%, which is smaller than that of AlN (aluminum nitride). Therefore, the cap layer used in the above manufacturing method is less susceptible to cracking than a cap layer made of AlN (aluminum nitride). Furthermore, the material contained in the cap layer used in the above manufacturing method has a melting point of 1500°C or higher. Therefore, the cap layer used in the above manufacturing method is stable during high-temperature heat treatment and has high heat resistance. As such, the cap layer used in the above manufacturing method is able to suppress the occurrence of cracks during high-temperature heat treatment while also providing heat resistance, making it suitable for preventing nitrogen from escaping from the surface of the nitride semiconductor layer during high-temperature heat treatment.

1 is a schematic cross-sectional view of a main part of an embodiment of a semiconductor device; 2 shows a partial manufacturing flow of a method for manufacturing the semiconductor device of FIG. 1 . 2A to 2C are schematic cross-sectional views of a main part of a manufacturing process in the manufacturing method of the semiconductor device of FIG. 1; 2A to 2C are schematic cross-sectional views of a main part of a manufacturing process in the manufacturing method of the semiconductor device of FIG. 1; 2A to 2C are schematic cross-sectional views of a main part of a manufacturing process in the manufacturing method of the semiconductor device of FIG. 1; 2A to 2C are schematic cross-sectional views of a main part of a manufacturing process in a modified example of the manufacturing method of the semiconductor device of FIG. 1; 2A to 2C are schematic cross-sectional views of a main part of a manufacturing process in a modified example of the manufacturing method of the semiconductor device of FIG. 1; 2A to 2C are schematic cross-sectional views of a main part of a manufacturing process in a modified example of the manufacturing method of the semiconductor device of FIG. 1;

The semiconductor device and manufacturing method thereof disclosed in this specification will be described below with reference to the drawings. For the purpose of clarity, common components may be designated by a single reference symbol in each drawing.

As shown in FIG. 1, the semiconductor device 1 includes a nitride semiconductor substrate 12, a nitride semiconductor layer 14, a drain electrode 32 provided to cover the lower surface of the nitride semiconductor substrate 12, a source electrode 34 provided to cover part of the upper surface of the nitride semiconductor layer 14, and a planar insulated gate 40 provided to cover part of the upper surface of the nitride semiconductor layer 14. The insulated gate 40 has a gate insulating film 42 and a gate electrode 44.

The nitride semiconductor substrate 12 is not particularly limited, but may be, for example, a semiconductor substrate made of gallium nitride (GaN). The nitride semiconductor substrate 12 contains a high concentration of n-type dopant and also functions as the drain region 21. The n-type dopant is not particularly limited, but may be, for example, silicon. The drain region 21 is in ohmic contact with the drain electrode 32.

The nitride semiconductor layer 14 is provided so as to be in contact with the upper surface of the nitride semiconductor substrate 12. The nitride semiconductor layer 14 is a semiconductor layer made of GaN (gallium nitride). The nitride semiconductor layer 14 is formed by crystal growth from the upper surface of the nitride semiconductor substrate 12 using a crystal growth technique. The nitride semiconductor layer 14 has an n-type drift region 22, a p ^- type body region 24, an n ⁺ type source region 25, and a p ⁺ type body contact region 26 formed therein.

The drift region 22 is provided so as to contact the upper surface of the drain region 21, and is disposed between the drain region 21 and the body region 24. The drift region 22 also has a JFET region 23 provided so as to be sandwiched between the body region 24 in the plane direction of the nitride semiconductor layer 14 (left-right direction on the page). In other words, the JFET region 23 is a part of the drift region 22 provided so as to penetrate the body region 24 from the upper surface of the nitride semiconductor layer 14. The JFET region 23 is provided in a position exposed on the upper surface of the nitride semiconductor layer 14, and is in contact with the insulated gate 40. The drift region 22 contains an n-type dopant at a lower concentration than the drain region 21. The n-type dopant is not particularly limited, but may be, for example, silicon.

The body region 24 is provided in contact with the upper surface of the drift region 22 and is disposed adjacent to the side surface of the JFET region 23. A portion of the body region 24 is provided in a position exposed on the upper surface of the nitride semiconductor layer 14 and is in contact with the insulated gate 40. The body region 24 contains a p-type dopant. The p-type dopant is not particularly limited, but may be, for example, magnesium.

The source region 25 is provided in contact with the upper surface of the body region 24 and is separated from the drift region 22 by the body region 24. The source region 25 is provided in a position exposed on the upper surface of the nitride semiconductor layer 14 and is in contact with the insulated gate 40. The source region 25 contains a higher concentration of n-type dopant than the drift region 22. The n-type dopant is not particularly limited, but may be, for example, silicon. The source region 25 is in ohmic contact with the source electrode 34.

The body contact region 26 is provided so as to contact the upper surface of the body region 24. The body contact region 26 is provided in a position exposed at the upper surface of the nitride semiconductor layer 14. The body contact region 26 contains a p-type dopant at a higher concentration than the body region 24. The p-type dopant is not particularly limited, but may be, for example, magnesium. The body contact region 26 is in ohmic contact with the source electrode 34.

The insulated gate 40 is provided in contact with a portion of the upper surface of the nitride semiconductor layer 14 and has a silicon oxide gate insulating film 42 and a polysilicon gate electrode 44. The gate insulating film 42 is disposed between the nitride semiconductor layer 14 and the gate electrode 44 and is in contact with both the nitride semiconductor layer 14 and the gate electrode 44. The gate electrode 44 faces the body region 24, which is located between the JFET region 23, which is part of the drift region 22, and the source region 25, and the JFET region 23, via the gate insulating film 42.

Next, the operation of the semiconductor device 1 will be described. During use, a positive voltage is applied to the drain electrode 32, and the source electrode 34 is grounded. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 44, an inversion layer is formed in the body region 24, i.e., the channel region, separating the JFET region 23 and the source region 25. Electrons flow from the source region 25 into the JFET region 23 through the inversion layer formed in the channel region. The electrons that flow into the JFET region 23 flow vertically through the JFET region 23 and drift region 22 toward the drain electrode 32. This brings the drain electrode 32 and source electrode 34 into conduction, turning the semiconductor device 1 on. When the gate electrode 44 is grounded, the inversion layer disappears, turning the semiconductor device 1 off. In this way, the semiconductor device 1 can perform a switching operation that switches the drain electrode 32 and source electrode 34 on and off based on the voltage applied to the gate electrode 44.

(Method for manufacturing semiconductor device 1)
2 is a manufacturing flow showing a flow of some of the steps for manufacturing the semiconductor device 1. FIGS. 3 to 5 are cross-sectional views of the main part in the manufacturing process corresponding to the manufacturing flow of FIG.

First, as shown in FIG. 3, a crystal growth technique is used to grow the nitride semiconductor layer 14 from the upper surface of the nitride semiconductor substrate 12 (step S1 in FIG. 2). The nitride semiconductor layer 14 is formed by crystal growth so as to contain an n-type dopant.

Next, as shown in FIG. 4, ion implantation technology is used to implant p-type dopants and n-type dopants into predetermined regions in the upper layer of the nitride semiconductor layer 14 to form the body region 24, source region 25, and body contact region 26 (step S2 in FIG. 2). The order in which these semiconductor regions 24, 25, and 26 are formed is not particularly limited.

Next, as shown in FIG. 5, a cap layer 50 is formed on the upper surface of the nitride semiconductor layer 14 and the lower surface of the nitride semiconductor substrate 12 to prevent nitrogen from escaping during the heat treatment described below (step S3 in FIG. 2). The cap layer 50 is formed by crystal growth from the upper surface of the nitride semiconductor layer 14 and the lower surface of the nitride semiconductor substrate 12 using crystal growth technology. Note that the cap layer 50 may be formed only on the upper surface of the nitride semiconductor layer 14. The upper surface of the nitride semiconductor layer 14 includes a portion that will become the channel region, and is a surface where the electrical characteristics are likely to be adversely affected if pits due to nitrogen escaping are formed. For this reason, it is sufficient that the cap layer 50 is formed on at least the upper surface of the nitride semiconductor layer 14.

The material contained in the cap layer 50 has a lattice mismatch with GaN of less than 2.5% and a melting point of 1500° C. or higher. The cap layer 50 is not particularly limited, but may contain at least one material selected from the group consisting of ScN, Sc _x Al _1-x N (0<x≦0.36), HfN, ZrN, ZnO, ScMgAlO ₄ , MnO, TaC, NbC, Mo, W, ZrB ₂ , WB ₂ , MoB ₂ , and ITO. A layer such as these materials, i.e., a layer composed of a material having a lattice mismatch with GaN of less than 2.5% and a melting point of 1500° C. or higher, is referred to herein as a high-melting-point lattice-matched layer.

Next, a heat treatment is performed to activate the semiconductor regions 24, 25, and 26 (step S4 in Figure 2). The temperature of the heat treatment is not particularly limited, but may be, for example, 1200°C or higher and lower than 1500°C. Such high-temperature heat treatment can effectively activate the implanted dopants, particularly magnesium, which is a p-type dopant.

AlN (aluminum nitride), a conventionally commonly used cap layer material, has a lattice mismatch with GaN (gallium nitride) of 2.5%. A cap layer made of AlN (aluminum nitride) has had the problem of cracking during high-temperature heat treatment due to the difference in lattice constant between the AlN (aluminum nitride) and the GaN (gallium nitride) nitride semiconductor layer. The material contained in the cap layer 50 used in the above manufacturing method is a material with a lattice mismatch with GaN (gallium nitride) of less than 2.5%, which is a material with a smaller lattice mismatch with GaN (gallium nitride) than AlN (aluminum nitride). Therefore, the cap layer 50 used in the above manufacturing method is less likely to crack than a cap layer made of AlN (aluminum nitride). The material contained in the cap layer 50 may be ScN or Sc _x Al _1-x N (0<x≦0.36). These materials have a lattice mismatch with GaN (gallium nitride) of 0.1% or less. Therefore, the cap layer 50 made of these materials is significantly less likely to crack during high-temperature heat treatment.

Furthermore, the material contained in the cap layer 50 used in the above manufacturing method has a melting point of 1500°C or higher. Therefore, the cap layer 50 used in the above manufacturing method remains stable even during high-temperature heat treatment and has high heat resistance. In this way, the cap layer 50 used in the above manufacturing method is able to both suppress the occurrence of cracks during high-temperature heat treatment and provide heat resistance, thereby suppressing the loss of nitrogen from the upper surface of the nitride semiconductor layer 14 and the lower surface of the nitride semiconductor substrate 12 during high-temperature heat treatment and suppressing the formation of pits on the upper surface of the nitride semiconductor layer 14 and the lower surface of the nitride semiconductor substrate 12.

Next, after removing the cap layer 50, the insulated gate 40, drain electrode 32, and source electrode 34 are formed using known manufacturing techniques (step S5 in Figure 2). Through these steps, the semiconductor device 1 shown in Figure 1 can be manufactured.

The cap layer 50 can be modified as follows:

The cap layer 50 shown in FIG. 6 is characterized by having a first cap layer 52 and a second cap layer 54. The first cap layer 52 is formed so as to contact the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12) and is disposed between the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12) and the second cap layer 54. The second cap layer 54 is formed so as to contact the surface of the first cap layer 52 and is disposed on the outermost surface of the cap layer 50. The second cap layer 54 is composed of the high-melting-point lattice-matched layer described above.

The material of the first cap layer 52 is AlGaN (aluminum gallium nitride). Specifically, the material of the first cap layer 52 is Al _y Ga _1-y N (0≦y≦1). The AlGaN first cap layer 52 is less likely to react with the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12) during high-temperature heat treatment than the high-melting-point lattice-matched layer described above. Therefore, by interposing the first cap layer 52, the crystallinity of the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12) can be maintained well during high-temperature heat treatment. The material of the first cap layer 52 may be Al _y Ga _1-y N (0<y≦1), which always contains aluminum. In this case, the lattice constant difference between the first cap layer 52 and the nitride semiconductor layer 14 (or the nitride semiconductor substrate 12) can be reduced.

The cap layer 50 shown in FIG. 7 is characterized in that the first cap layer 52 shown in FIG. 6 is composed of a stack of multiple AlGaN layers with different compositions. In this example, the first cap layer 52 is composed of two stacked AlGaN layers with different compositions. Alternatively, the first cap layer 52 may be composed of three or more stacked AlGaN layers with different compositions. The first cap layer 52 has a lower AlGaN layer 56 and an upper AlGaN layer 58. The lower AlGaN layer 56 is formed so as to contact the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12) and is disposed between the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12) and the upper AlGaN layer 58. The upper AlGaN layer 58 is formed so as to contact the surface of the lower AlGaN layer 56 and is disposed between the lower AlGaN layer 56 and the second cap layer 54.

The material of the lower AlGaN layer 56 is Al _ya Ga _1-ya N (0≦ya≦1). The material of the upper AlGaN layer 58 is Al _yb Ga _1-yb N (0<yb≦1, yb>ya). The aluminum composition ratio of the upper AlGaN layer 58 is greater than the aluminum composition ratio of the lower AlGaN layer 56. In this way, by increasing the aluminum composition ratio in the multiple AlGaN layers constituting the first cap layer 52 with increasing distance from the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12), it is possible to improve heat resistance while suppressing the lattice constant difference between the first cap layer 52 and the nitride semiconductor layer 14 (or the nitride semiconductor substrate 12).

The cap layer 50 shown in FIG. 8 has a superlattice structure in which first cap layers 52 and second cap layers 54 are alternately repeated along the thickness direction. The thickness of each cap layer 52, 54 is not particularly limited and may be, for example, 10 nm or less. The specific material of the first cap layer 52 constituting the superlattice structure is not particularly limited and may be, for example, Al _yc Ga _1-yc N (0.5≦yc≦1). Thus, the aluminum composition ratio of the first cap layer 52 constituting the superlattice structure is set relatively high. In this superlattice structure, the first cap layer 52 is disposed in contact with the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12), and the second cap layer 54 is disposed on the outermost surface of the cap layer 50. The second cap layer 54 is formed of the high-melting-point lattice-matched layer described above.

As described above, the aluminum composition ratio of the first cap layer 52 that forms the superlattice structure is relatively high. However, because the first cap layer 52 forms a superlattice structure with the second cap layer, which is a high-melting-point lattice-matching layer, the lattice mismatch between the cap layer 50 as a whole and the nitride semiconductor layer 14 (or nitride semiconductor substrate 12) is alleviated. On the other hand, because the aluminum composition ratio of the first cap layer 52 that forms the superlattice structure is relatively high, the heat resistance of the entire cap layer 50 is improved.

The above describes the technology disclosed in this specification using a semiconductor device 1 with a planar-type insulated gate 40, but the technology disclosed in this specification can also be applied to semiconductor devices with trench-type insulated gates.

The above manufacturing method may further include a step of forming a carbon film on the surface of the cap layer 50 after forming the cap layer 50 and before the activation heat treatment. The carbon film formed can prevent atmospheric gas from penetrating into the cap layer 50 during the activation heat treatment.

The following summarizes the features of the technology disclosed in this specification. Note that the technical elements described below are independent and may demonstrate technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

(Feature 1)
A method for manufacturing a nitride semiconductor device, comprising:
a step of ion-implanting a dopant into a nitride semiconductor layer made of GaN;
forming a cap layer on at least a portion of a surface of the nitride semiconductor layer;
an annealing step of activating the dopant by heat treatment,
The method of manufacturing the cap layer, wherein the cap layer comprises a material that has a lattice mismatch with GaN of less than 2.5% and a melting point of 1500° C. or higher.

(Feature 2)
2. The method of claim 1, wherein the cap layer comprises at least one material selected from the group consisting of ScN, Sc _x Al _1-x N (0<x≦0.36), HfN, ZrN, ZnO, ScMgAlO ₄ , MnO, TaC, NbC, Mo, W, ZrB ₂ , WB ₂ , MoB ₂ , and ITO.

(Feature 3)
3. The method of claim 2, wherein the cap layer includes at least one of ScN and Sc _x Al _1-x N (0<x≦0.36).

(Feature 4)
The cap layer is
a first cap layer (52) formed on the surface of the nitride semiconductor layer;
a second cap layer (54) formed on the first cap layer,
the material of the first cap layer is Al _y Ga _1-y N (0≦y≦1);
4. The method of claim 2 or 3, wherein the second cap layer comprises at least one material selected from the group consisting of ScN, Sc _x Al _1-x N (0<x≦0.36), HfN, ZrN, ZnO, ScMgAlO ₄ , MnO, TaC, NbC, Mo, W, ZrB ₂ , WB ₂ , MoB ₂ , and ITO.

(Feature 5)
5. The manufacturing method according to Feature 4, wherein the first cap layer is configured by stacking a plurality of AlGaN layers (56, 58) having different compositions.

(Feature 6)
6. The manufacturing method according to Feature 5, wherein the plurality of AlGaN layers constituting the first cap layer are configured such that a composition ratio of aluminum increases with increasing distance from the surface of the nitride semiconductor layer.

(Feature 7)
The first cap layer (52) and the second cap layer (54) form a superlattice structure in which they are alternately repeated in the thickness direction,
the material of the first cap layer is Al _y Ga _1-y N (0≦y≦1);
3. The method of claim 2, wherein the second cap layer comprises at least one material selected from the group consisting of ScN, Sc _x Al _1-x N (0<x≦0.36), HfN, ZrN, ZnO, ScMgAlO ₄ , MnO, TaC, NbC, Mo, W, ZrB ₂ , WB ₂ , MoB ₂ , and ITO.

(Feature 8)
8. The method of any one of Features 1 to 7, further comprising forming a carbon film on the cap layer.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings may demonstrate technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

1: Semiconductor device, 12: Nitride semiconductor substrate, 14: Nitride semiconductor layer, 21: Drain region, 22: Drift region, 23: JFET region, 25: Source region, 26: Body contact region, 32: Drain electrode, 34: Source electrode, 40: Insulated gate, 42: Gate insulating film, 44: Gate electrode, 50: Cap layer, 52: First cap layer, 54: Second cap layer, 56: Lower AlGaN layer, 58: Upper AlGaN layer

Claims (4)

A method for manufacturing a nitride semiconductor device (1), comprising:
A step of ion-implanting a dopant into a nitride semiconductor layer (14) made of GaN;
forming a cap layer (50) on at least a portion of the surface of the nitride semiconductor layer;
an annealing step of activating the dopant by heat treatment,
the cap layer includes a material having a lattice mismatch with GaN of less than 2.5% and a melting point of 1500°C or higher;
The method for manufacturing the semiconductor device, wherein the cap layer contains at least one of ScN and Sc _x Al _1-x N (0<x≦0.36). A method for manufacturing a nitride semiconductor device (1), comprising:
A step of ion-implanting a dopant into a nitride semiconductor layer (14) made of GaN;
forming a cap layer (50) on at least a portion of the surface of the nitride semiconductor layer;
an annealing step of activating the dopant by heat treatment,
the cap layer includes a material having a lattice mismatch with GaN of less than 2.5% and a melting point of 1500°C or higher;
The cap layer is
a first cap layer (52) formed on the surface of the nitride semiconductor layer;
a second cap layer (54) formed on the first cap layer,
The material of the first cap layer is Al _y Ga _1-y N (0≦y≦1),
The second cap layer is made of ScN, Sc _x Al _1-x N (0<x≦0.36), HfN, ZrN, ZnO, ScMgAlO ₄ , MnO, TaC, NbC, Mo, W, ZrB ₂ , W.B. ₂ , MoB ₂ , ITO,
The first cap layer is configured by stacking a plurality of AlGaN layers (56, 58) having different compositions,
The plurality of AlGaN layers constituting the first cap layer are configured so that the aluminum composition ratio increases with increasing distance from the surface of the nitride semiconductor layer. A method for manufacturing a nitride semiconductor device (1), comprising:
A step of ion-implanting a dopant into a nitride semiconductor layer (14) made of GaN;
forming a cap layer (50) on at least a portion of the surface of the nitride semiconductor layer;
an annealing step of activating the dopant by heat treatment,
the cap layer includes a material having a lattice mismatch with GaN of less than 2.5% and a melting point of 1500°C or higher;
The cap layer has a superlattice structure in which first cap layers (52) and second cap layers (54) are alternately repeated in the thickness direction,
The material of the first cap layer is Al _y Ga _1-y N (0≦y≦1),
The second cap layer is made of ScN, Sc _x Al _1-x N (0<x≦0.36), HfN, ZrN, ZnO, ScMgAlO ₄ , MnO, TaC, NbC, Mo, W, ZrB ₂ , W.B. ₂ , MoB ₂ , ITO. The manufacturing method according to claim 1 , further comprising the step of forming a carbon film on the cap layer.