JP7798752B2 - Reference power supply circuit - Google Patents

Description

The present invention relates to a reference power supply circuit that generates a reference voltage.

Reference power supply circuits are required to output a stable reference voltage, and so configurations have been considered that include a function to suppress output fluctuations, which are fluctuations in the reference voltage due to various factors. Patent Documents 1 and 2 disclose reference power supply circuits configured to correct output fluctuations due to temperature characteristics. Patent Document 3 discloses a reference power supply circuit equipped with a sensor for correcting output fluctuations due to stress characteristics. In the following description, the prior art disclosed in Patent Documents 1, 2, and 3 will be referred to as the first prior art, second prior art, and third prior art, respectively.

US Patent Application Publication No. 2020/0218302 US Patent Application Publication No. 2021/0124386 U.S. Pat. No. 1,043,835

The first and second conventional technologies use a configuration in which the positive temperature characteristic of the Zener diode is offset by the positive temperature characteristic of the differential voltage of the bipolar junction transistor. Note that in this specification, bipolar junction transistors may be abbreviated as bipolar transistors or BJTs. While the first and second conventional technologies can correct output fluctuations due to temperature characteristics, they cannot correct output fluctuations due to stress characteristics, which means that the output reference voltage may fluctuate due to stress fluctuations such as package distortion.

The third prior art uses a configuration in which a stress sensor using a resistor measures the stress applied to the circuit, and then indirectly digitally corrects fluctuations in the reference voltage based on the measured stress. This third prior art requires a stress sensor, and also requires a relatively large circuit such as an A/D converter to perform the digital correction, which may increase the circuit size. Furthermore, the third prior art also poses problems with the accuracy of the correction itself, as the reference voltage used in the A/D converter itself fluctuates depending on the stress characteristics.

The present invention was made in consideration of the above circumstances, and its purpose is to provide a reference power supply circuit that can accurately correct output fluctuations due to temperature and stress characteristics without increasing the circuit size.

The reference power supply circuit described in claim 1 comprises a Zener diode (2), a first current generating circuit (4, 4A, 4B, 4C) that generates a first current proportional to absolute temperature, a second current generating circuit (5, 5A, 5B, 5C) that generates a second current dependent on stress, and an arithmetic circuit (6, 42, 52). The arithmetic circuit performs a calculation to correct the temperature and stress characteristics of the Zener voltage of the Zener diode or a voltage corresponding to the Zener voltage using the first and second currents, and outputs the calculated voltage as a reference voltage. As a result, the reference voltage output from the reference power supply circuit is a voltage in which output fluctuations due to temperature and stress characteristics have been corrected.

With the above configuration, fluctuations in the reference voltage due to stress characteristics are directly corrected in an analog manner without A/D conversion, eliminating the need for an A/D converter and enabling accurate correction of output fluctuations due to stress characteristics. Furthermore, with the above configuration, only the Zener diode is strongly affected by stress, making it inherently resistant to stress. In other words, with the above configuration, fluctuations in the reference voltage due to stress are kept to a minimum in the first place. Thus, with the above configuration, the excellent effect of accurately correcting output fluctuations due to temperature and stress characteristics can be achieved without increasing the circuit size.

As described in claim 2, the operational circuit includes an operational amplifier (22), one input terminal of which is directly or indirectly connected to the cathode of the Zener diode. The anode of the Zener diode is connected to ground, which is the reference potential of the circuit. The other input terminal of the operational amplifier is connected to the first current output node of the first current generating circuit and the second current output node of the second current generating circuit.

More specifically, as described in claim 3, the operational circuit further includes a resistive voltage divider circuit (21, 43) including a plurality of series-connected resistors (R21, R22, R41-R44) and a feedback resistor (Rf) connected between the inverting input terminal and output terminal of the operational amplifier. The resistive voltage divider circuit outputs a divided voltage obtained by dividing the voltage between the anode and cathode of the Zener diode. The non-inverting input terminal of the operational amplifier is connected to the output node of the resistive voltage divider circuit. The inverting input terminal of the operational amplifier is connected to the output node of the first current of the first current generation circuit and the output node of the second current of the second current generation circuit.

With this configuration, the Zener diode and the first current generating circuit are not directly connected, but are separated by the operational amplifier provided in the operational circuit. This configuration reduces the occurrence of correction errors caused by the Zener diode and the first current generating circuit influencing each other, and as a result, output fluctuations due to temperature characteristics can be accurately corrected.

FIG. 1 is a diagram illustrating a schematic configuration of a reference power supply circuit according to a first embodiment; FIG. 1 is a diagram schematically illustrating a first specific configuration example of an Iptat generation circuit according to a first embodiment; FIG. 10 is a diagram schematically illustrating a second specific configuration example of the Iptat generation circuit according to the first embodiment; FIG. 10 is a diagram schematically illustrating a third specific configuration example of the Iptat generation circuit according to the first embodiment; FIG. 1 is a diagram schematically illustrating a first specific configuration example of a bandgap generation circuit according to a first embodiment; FIG. 1 is a diagram schematically illustrating a second specific configuration example of the bandgap generation circuit according to the first embodiment; FIG. 10 is a diagram schematically illustrating a third specific configuration example of the bandgap generation circuit according to the first embodiment; FIG. 1 is a diagram schematically illustrating an example of a planar layout of a BJT included in a bandgap generation circuit according to a first embodiment; FIG. 1 is a diagram showing a specific configuration example of a reference power supply circuit according to a first embodiment; FIG. 10 is a diagram showing a specific configuration example of a reference power supply circuit according to a second embodiment; FIG. 10 is a diagram showing a specific example of the configuration of a reference power supply circuit according to a third embodiment;

Hereinafter, several embodiments will be described with reference to the drawings. Note that substantially the same components in the respective embodiments will be denoted by the same reference numerals, and the description thereof will be omitted.
(First embodiment)
The first embodiment will be described below with reference to FIGS.

<Outline of the reference power supply circuit>
As shown in Fig. 1, the reference power supply circuit 1 of this embodiment is a circuit that generates and outputs a constant reference voltage Vout using semiconductor elements, and includes a Zener diode 2, a current source 3, an Iptat generation circuit 4, a bandgap generation circuit 5, and an arithmetic circuit 6. In this case, the reference power supply circuit 1, together with various circuits to which the reference voltage Vout is supplied, is configured as a semiconductor device, i.e., an IC. The Zener diode 2 is, for example, a buried Zener diode, and its anode is connected to ground, which is the reference potential of the circuit. The cathode of the Zener diode 2 is connected to node N1.

Current source 3 is configured as a constant current source that outputs a constant current. Current source 3 is connected between power supply line L1, which is supplied with power supply voltage VDD_H, and node N1. When the current output from current source 3 flows through Zener diode 2, a voltage Vz corresponding to the Zener voltage of Zener diode 2 is generated at node N1. In this case, the Zener voltage of Zener diode 2 is, for example, 7 V. In addition, in this case, power supply voltage VDD_H is a voltage higher than the Zener voltage, for example, 9 V. The voltage Vz at node N1 is supplied to arithmetic circuit 6.

The Iptat generation circuit 4 generates and outputs the current Iptat, which is a PTAT current. PTAT is an abbreviation for Proportional To Absolute Temperature. The current Iptat is proportional to absolute temperature and corresponds to the first current. The current Iptat has a positive temperature characteristic similar to that of the Zener diode 2. In this way, the Iptat generation circuit 4 functions as a first current generation circuit that generates the first current proportional to absolute temperature. The current Iptat output from the Iptat generation circuit 4 is provided to the calculation circuit 6.

The bandgap generation circuit 5 generates and outputs a current IEg that depends on the bandgap voltage of silicon. The current IEg depends on the stress applied to the circuit and corresponds to the second current. In this way, the bandgap generation circuit 5 functions as a second current generation circuit that generates a second current that depends on the stress. The current IEg output from the bandgap generation circuit 5 is provided to the calculation circuit 6.

Calculation circuit 6 performs calculations to correct the temperature and stress characteristics of voltage Vz or a voltage corresponding to voltage Vz using current Iptat and current IEg, and outputs the calculated voltage as reference voltage Vout. The reference voltage Vout obtained by such calculations can be expressed by the following equation (1), where α, β, and γ are all coefficients determined according to the specific configuration of each circuit.

<Specific Configuration of Iptat Generation Circuit>
The Iptat generating circuit 4 includes two bipolar transistors, and generates a current Iptat that depends on a potential difference ΔVBE, which is the difference between the base-emitter voltages of the two bipolar transistors.

In this case, the two bipolar transistors can be transistors that pass the same collector current but have different area ratios, or transistors that pass different collector currents but have the same area ratio. Specific configurations of this Iptat generation circuit 4 can include, for example, the first configuration example shown in Figure 2, the second configuration example shown in Figure 3, and the third configuration example shown in Figure 4.

2, the Iptat generation circuit 4A of the first configuration example includes transistors Q1 to Q3 and Q31, resistors R1 to R4, and an amplifier 11. The transistor Q1 is a P-channel MOS transistor, and its source is connected to a power supply line L2 to which a power supply voltage VDD_L is applied. The power supply voltage VDD_L is a voltage lower than the power supply voltage VDD_H, for example, 5 V.

The drain of transistor Q1 is connected to its gate. Transistor Q31 is a P-channel MOS transistor, and its source is connected to power supply line L2. The gate of transistor Q31 is connected to the gate of transistor Q1. In this case, the current flowing through transistor Q31, that is, the drain current of transistor Q31, is current Iptat.

The drain of transistor Q1 is connected to the inverting input terminal of amplifier 11 via resistor R1 and to the non-inverting input terminal of amplifier 11 via resistor R2. Transistors Q2 and Q3 are NPN-type BJTs and are examples of the two bipolar transistors mentioned above. The collector of transistor Q2 is connected to the inverting input terminal of amplifier 11, and its emitter is connected to ground via resistors R3 and R4. The collector of transistor Q3 is connected to the non-inverting input terminal of amplifier 11, and its emitter is connected to ground via resistor R4. The bases of transistors Q2 and Q3 are connected to the output terminal of amplifier 11.

[2] Second Configuration Example As shown in Figure 3, the Iptat generation circuit 4B of the second configuration example includes transistors Q4 to Q7 and Q41, resistors R5 to R7, and an amplifier 12. The transistors Q4 and Q5 are both P-channel MOS transistors. The sources of the transistors Q4 and Q5 are connected to the power supply line L2.

The gates of transistors Q4 and Q5 are connected to the output terminal of amplifier 12. Transistor Q41 is a P-channel MOS transistor, and its source is connected to power supply line L2. The gate of transistor Q41 is connected to the output terminal of amplifier 12. In this case, the current flowing through transistor Q41, i.e., the drain current of transistor Q41, is current Iptat.

The drain of transistor Q4 is connected to the non-inverting input terminal of amplifier 12 via resistor R5. The drain of transistor Q5 is connected to the inverting input terminal of amplifier 12 via resistor R6. Transistors Q6 and Q7 are NPN-type BJTs and are examples of the two bipolar transistors mentioned above. The collector of transistor Q6 is connected to its base and to the non-inverting input terminal of amplifier 12. The collector of transistor Q7 is connected to its base and to the inverting input terminal of amplifier 12 via resistor R7. The emitters of transistors Q6 and Q7 are connected to ground.

[3] Third Configuration Example As shown in FIG. 4, the Iptat generation circuit 4C of the third configuration example includes transistors Q8 to Q13, Q42, and a resistor R8. The transistors Q8 and Q9 are both P-channel MOS transistors. The sources of the transistors Q8 and Q9 are connected to the power supply line L2. The transistor Q9 has its gate and drain connected together, forming a so-called diode connection.

The gates of transistors Q8 and Q9 are connected to each other. Transistor Q42 is a P-channel MOS transistor, and its source is connected to power supply line L2. The gate of transistor Q42 is connected to the gates of transistors Q8 and Q9. In this case, the current flowing through transistor Q42, that is, the drain current of transistor Q42, is current Iptat.

Transistors Q10 and Q11 are both N-channel MOS transistors. Transistor Q10 has its gate and drain connected together, forming a so-called diode connection. The drain of transistor Q10 is connected to the drain of transistor Q8. The drain of transistor Q11 is connected to the drain of transistor Q9.

Transistors Q12 and Q13 are NPN-type BJTs and are examples of the two bipolar transistors mentioned above. The collector of transistor Q12 is connected to its base and to the source of transistor Q10. The collector of transistor Q13 is connected to its base and to the source of transistor Q11 via resistor R8. The emitters of transistors Q12 and Q13 are connected to ground.

<Specific Configuration of Bandgap Generator Circuit>
The bandgap generation circuit 5 includes two or more bipolar transistors and generates a current IEg that depends on the silicon bandgap. Specific configurations of the bandgap generation circuit 5 include a first configuration example shown in Fig. 5, a second configuration example shown in Fig. 6, and a third configuration example shown in Fig. 7.

5, a bandgap generation circuit 5A of the first configuration example includes transistors Q14 to Q17 and Q32, resistors R9 to R11, and an amplifier 13. The transistors Q14 and Q15 are both P-channel MOS transistors. The sources of the transistors Q14 and Q15 are connected to the power supply line L2.

The gates of transistors Q14 and Q15 are connected to the output terminal of amplifier 13. Transistor Q32 is a P-channel MOS transistor, and its source is connected to power supply line L2. The gate of transistor Q32 is connected to the output terminal of amplifier 13. In this case, the current flowing through transistor Q32, that is, the drain current of transistor Q32, is current IEg.

The drain of transistor Q14 is connected to the inverting input terminal of amplifier 13 and to ground via resistor R9. The drain of transistor Q15 is connected to the non-inverting input terminal of amplifier 13 and to ground via resistor R10. Transistors Q16 and Q17 are NPN-type BJTs and are an example of the two or more bipolar transistors mentioned above.

The collector of transistor Q16 is connected to its base and to the inverting input terminal of amplifier 13. The collector of transistor Q17 is connected to its base and to the non-inverting input terminal of amplifier 13 via resistor R11. The emitters of transistors Q16 and Q17 are connected to ground.

[2] Second Configuration Example As shown in Fig. 6, the bandgap generation circuit 5B of the second configuration example differs from the bandgap generation circuit 5A of the first configuration example shown in Fig. 5 in that transistors Q18 and Q19 and resistors R12 and R13 are added. The transistor Q18 is a P-channel MOS transistor, and its source is connected to the power supply line L2.

The gate of transistor Q18 is connected to the output terminal of amplifier 13. The drain of transistor Q18 is connected to the non-inverting input terminal of amplifier 13 via resistor R12 and to the inverting input terminal of amplifier 13 via resistor R13. Transistor Q19 is an NPN-type BJT and is an example of the two or more bipolar transistors mentioned above. The collector of transistor Q19 is connected to its base and to the drain of transistor Q18. The emitter of transistor Q19 is connected to ground.

[3] Third Configuration Example As shown in FIG. 7, a bandgap generation circuit 5C of the third configuration example includes transistors Q20 to Q29 and Q43 and resistors R14 and R15. Transistors Q20 to Q22 are all P-channel MOS transistors. The sources of transistors Q20 to Q22 are connected to the power supply line L2. The drain of transistor Q20 is connected to the gate of transistor Q21.

The drain of transistor Q22 is connected to its gate. Transistor Q43 is a P-channel MOS transistor, and its source is connected to power supply line L2. The gate of transistor Q43 is connected to the gate of transistor Q22. In this case, the current flowing through transistor Q43, that is, the drain current of transistor Q43, is current IEg. Transistors Q23 to Q29 are all NPN-type BJTs, and are examples of the two or more bipolar transistors mentioned above.

The collector of transistor Q23 is connected to the drain of transistor Q20, and its gate is connected to the drain of transistor Q21. The collector of transistor Q24 is connected to its base and to the emitter of transistor Q23. The collector of transistor Q25 is connected to its base and to the emitter of transistor Q24. The collector of transistor Q26 is connected to its base and to the emitter of transistor Q25. The emitter of transistor Q26 is connected to ground via resistor R14.

The collector of transistor Q27 is connected to the drain of transistor Q22, and its gate is connected to the drain of transistor Q21. The collector of transistor Q28 is connected to its base and to the emitter of transistor Q27. The collector of transistor Q29 is connected to its base and to the emitter of transistor Q28. The emitter of transistor Q29 is connected to ground via resistor R15.

<Layout example of BJT in bandgap generation circuit 5>
The following arrangement can be adopted as the planar layout of the BJT included in the bandgap generation circuit 5. That is, the BJT included in the bandgap generation circuit 5 can be arranged adjacent to the Zener diode 2. With this arrangement, the stress fluctuations in the Zener diode 2 and the BJT included in the bandgap generation circuit 5 will be the same, thereby improving the accuracy of correction.

Furthermore, the BJTs included in the bandgap generation circuit 5 can be arranged in a common centroid configuration centered on the Zener diode 2, as shown in FIG. 8. In this case, regions A1, A2, A3, A4, A5, A6, A7, and A8 in which the BJTs are formed are arranged to surround region A9 in which the Zener diode 2 is formed. In other words, in this case, the center of gravity of regions A1 to A8 in which the BJTs are formed coincides with the center of gravity of region A9 in which the Zener diode 2 is formed. With this configuration, stress fluctuations in the Zener diode 2 and the BJTs included in the bandgap generation circuit 5 become more consistent, further improving the accuracy of correction.

<Specific Configuration of Reference Power Supply Circuit>
In this embodiment, the Iptat generation circuit 4A of the first configuration example shown in Fig. 2 is used as the Iptat generation circuit 4. The reason for this is as follows: The Iptat generation circuit 4A has the advantage of being less susceptible to the offset of the amplifier 11, and also has the advantage of not causing errors due to the bypass current because the bases of the transistors Q2 and Q3 are connected to the output terminal of the amplifier 11 and the currents flowing through their collectors are not bypassed, making it possible to accurately generate the current Iptat proportional to the absolute temperature.

In this embodiment, the bandgap generation circuit 5B of the second configuration example shown in Figure 6 is used as the bandgap generation circuit 5. The reason for this is as follows: Namely, the bandgap generation circuit 5B can accurately generate a current IEg that depends on the bandgap of silicon based on a theoretical formula.

As a specific configuration of the reference power supply circuit 5 of this embodiment, which employs the Iptat generation circuit 4A of the first configuration example as the Iptat generation circuit 4 and the bandgap generation circuit 5B of the second configuration example as the bandgap generation circuit 5, for example, the configuration example shown in Figure 9 can be used.

The Iptat generation circuit 4 of this configuration example has a configuration similar to the Iptat generation circuit 4A of the first configuration example shown in Figure 2. With this configuration, the current flowing through transistor Q31, i.e., the drain current of transistor Q31, becomes the current Iptat and is output to the arithmetic circuit 6. In this case, the drain of transistor Q31 corresponds to the output node of the current Iptat.

The bandgap generation circuit 5 of this configuration example has a configuration similar to that of the bandgap generation circuit 5B of the second configuration example shown in Figure 6. With this configuration, the current flowing through transistor Q32, i.e., the drain current of transistor Q32, becomes current IEg and is output to the arithmetic circuit 6. In this case, the drain of transistor Q32 corresponds to the output node of current IEg.

The arithmetic circuit 6 of this configuration example includes a resistive voltage divider circuit 21, an amplifier 22, and a resistor Rf. The resistive voltage divider circuit 21 includes two resistors R21 and R22 connected in series. One terminal of resistor R21 is connected to node N1, and the other terminal is connected to ground via resistor R22. With the above configuration, a divided voltage is generated at node N21, which is the interconnection node of resistors R21 and R22, by dividing voltage Vz, which is the voltage between the anode and cathode of Zener diode 2, using the voltage division ratio of resistive voltage divider circuit 21.

In this way, the resistive voltage divider circuit 21 is configured to divide the voltage Vz and output the divided voltage from node N21. The voltage division ratio of the resistive voltage divider circuit 21 is determined according to the input range of the amplifier 22, the desired voltage value of the reference voltage Vout, and other factors. Node N21 corresponds to the output node of the divided voltage of the resistive voltage divider circuit 21. The amplifier 22 functions as an operational amplifier, and one of its input terminals, the non-inverting input terminal, is indirectly connected to the cathode of the Zener diode 2 via the resistive voltage divider circuit 21. Specifically, the non-inverting input terminal of the amplifier 22 is connected to node N21, which is the output node of the divided voltage of the resistive voltage divider circuit 21.

The drain of transistor Q31, which corresponds to the output node of current Iptat of Iptat generation circuit 4, and the drain of transistor Q32, which corresponds to the output node of current IEg of bandgap generation circuit 5, are connected to the other input terminal, or inverting input terminal, of amplifier 22. Resistor Rf functions as a feedback resistor and is connected between the inverting input terminal and output terminal of amplifier 22. With the above configuration, the output voltage of amplifier 22 is output as reference voltage Vout.

Next, the mechanism of operation relating to the generation of the reference voltage Vout by the reference power supply circuit 1 configured as described above will be described.
<Mechanism of Bandgap Generation Circuit 5>
In the bandgap generating circuit 5, it is assumed that the resistors R9 and R10 have the same resistance value Ra, and the resistors R12 and R13 have the same resistance value Rb.

The current IEg output from the bandgap generation circuit 5 is then expressed by the following equation (2). Here, the current flowing through resistor R9 is Ia, the current flowing through resistor R12 is Ib, the current flowing through transistor Q16 is Ic, the bandgap is Eg, the process constant related to the BJT is η, the Boltzmann constant is kB, the temperature at that time is T, and the temperature near room temperature is Tref.

In this case, if the resistance values Ra and Rb are adjusted to match the process constant η, specifically, if the resistance values Ra and Rb are adjusted so that the term "Ia + Ib" in equation (2) becomes zero, the current IEg will become a current that depends on the bandgap Eg, as expressed in equation (3) below. Note that the resistance values Ra and Rb can be adjusted by, for example, trimming. The condition for these resistance values Ra and Rb is expressed by equation (4) below.

<Mechanism of Iptat generation circuit 4>
In the Iptat generating circuit 4, it is assumed that resistors R1 and R2 have the same resistance value. Then, the potential difference between the emitter of transistor Q2 and the emitter of transistor Q3, i.e., the potential difference ΔVBE between the terminals of resistor R3, is expressed by the following equation (5), where VBE1 is the base-emitter voltage of transistor Q2, VBE2 is the base-emitter voltage of transistor Q3, and is the area ratio of the two BJT transistors Q2 and Q3.

The potential difference ΔVBE is a voltage that is directly proportional to temperature. Therefore, the current flowing through resistor R3, and therefore the current Iptat, is directly proportional to temperature, as expressed in equation (6) below. Here, the resistance value of resistor R3 is Rc.

<Mechanism of arithmetic circuit 6>
A divided voltage obtained by dividing the voltage Vz using a resistive voltage divider circuit 21 is input to the non-inverting input terminal of the amplifier 22 of the arithmetic circuit 6. A voltage generated by the currents Iptat and IEg flowing through the resistor Rf is input to the inverting input terminal of the amplifier 22 of the arithmetic circuit 6. The amplifier 22 outputs a voltage corresponding to the difference between the divided voltage input to the inverting input terminal and the voltage input to the non-inverting input terminal as a reference voltage Vout.

Such reference voltage Vout is expressed by the following equation (7). Here, the resistance value of resistor R21 is Rd, the resistance value of resistor R22 is Re, the resistance value of resistor Rf is Rf, the size ratio of the MOS transistors that make up the current mirror circuit in the output stage of bandgap generation circuit 5 is AW/L, and the size ratio of the MOS transistors that make up the current mirror circuit in the output stage of Iptat generation circuit 4 is BW/L.

In the above equation (7), the term multiplied by the voltage Vz corresponds to "α" in equation (1), the term multiplied by the current Iptat corresponds to "β" in equation (1), and the term multiplied by the current IEg corresponds to "γ" in equation (1).

According to the present embodiment described above, the following effects can be obtained.
The reference power supply circuit 1 includes a Zener diode 2, an Iptat generation circuit 4 that generates a current Iptat proportional to absolute temperature, a bandgap generation circuit 5 that generates a current IEg that depends on stress, and an arithmetic circuit 6. The arithmetic circuit 6 performs a calculation to correct the temperature and stress characteristics of a voltage corresponding to the Zener voltage of the Zener diode 2 using the current Iptat and the current IEg, and outputs the calculated voltage as a reference voltage Vout. As a result, the reference voltage Vout output from the reference power supply circuit 1 is a voltage in which output fluctuations due to the temperature and stress characteristics have been corrected.

With the above configuration, fluctuations in the reference voltage Vout due to stress characteristics are directly corrected in an analog manner without A/D conversion, eliminating the need for an A/D converter and enabling accurate correction of output fluctuations due to stress characteristics. Furthermore, with the above configuration, only the Zener diode 2 is strongly affected by stress, making it inherently resistant to stress. In other words, with the above configuration, fluctuations in the reference voltage Vout due to stress are kept to a minimum in the first place. Thus, this embodiment provides the excellent effect of accurately correcting output fluctuations due to temperature and stress characteristics without increasing the circuit size.

The arithmetic circuit 6 includes an amplifier 22, one of whose input terminals, the non-inverting input terminal, is indirectly connected to the cathode of a Zener diode 2. The anode of the Zener diode 2 is connected to ground, which is the reference potential of the circuit. The other input terminal, the inverting input terminal, of the amplifier 22 is connected to the output node of the current Iptat of the Iptat generation circuit 4 and the output node of the current IEg of the bandgap generation circuit 5.

More specifically, the arithmetic circuit 6 further includes a resistive voltage divider circuit 21 including multiple series-connected resistors R11 and R12, and a resistor Rf connected between the inverting input terminal and output terminal of the amplifier 22. The resistive voltage divider circuit 21 outputs a divided voltage obtained by dividing the voltage between the anode and cathode of the Zener diode 2. The output node of the divided voltage of the resistive voltage divider circuit 21 is connected to the non-inverting input terminal of the amplifier 22. The output node of the current Iptat of the Iptat generation circuit 4 and the output node of the current IEg of the bandgap generation circuit 5 are connected to the inverting input terminal of the amplifier 22.

With this configuration, the Zener diode 2 and the Iptat generation circuit 4 are not directly connected, but are separated by the amplifier 22 provided in the calculation circuit 6. As a result, the above configuration prevents correction errors caused by the Zener diode 2 and the Iptat generation circuit 4 influencing each other, and as a result, output fluctuations due to temperature characteristics can be accurately corrected.

Second Embodiment
A second embodiment in which the specific configuration of the arithmetic circuit is changed from that of the first embodiment will be described below with reference to FIG.
10, a reference power supply circuit 41 of this embodiment differs from the reference power supply circuit 1 of the first embodiment shown in FIG. 9 in that it includes an arithmetic circuit 42 instead of the arithmetic circuit 6. The arithmetic circuit 42 differs from the arithmetic circuit 6 in that it includes a resistive voltage divider circuit 43 instead of the resistive voltage divider circuit 21.

The resistive voltage divider circuit 43 consists of ladder resistors connected in series and multiple switches connected in parallel to each node of the resistors. For example, the resistive voltage divider circuit 43 includes resistors R41 to R44 and four switches S41 to S44. Resistors R41, R42, R43, and R44 are connected in series, in this order, between node N1 and ground. With the above configuration, divided voltages obtained by dividing voltage Vz, which is the voltage between the anode and cathode of Zener diode 2, at different voltage division ratios are generated at node N41, which is the interconnection node of resistors R41 and R42; node N42, which is the interconnection node of resistors R42 and R43; and node N43, which is the interconnection node of resistors R43 and R44.

Switches S41 to S44 are connected between each terminal of resistors R41 to R44 and the non-inverting input terminal of amplifier 22. That is, switch S41 is connected between node N1 and the non-inverting input terminal of amplifier 22. Switch S42 is connected between node N41 and the non-inverting input terminal of amplifier 22. Switch S43 is connected between node N42 and the non-inverting input terminal of amplifier 22. Switch S44 is connected between node N43 and the non-inverting input terminal of amplifier 22.

Switches S41 to S44 are controlled so that one of them is turned on while the others are turned off. Therefore, when switch S41 is turned on, voltage Vz is applied to the non-inverting input terminal of amplifier 22; when switch S42 is turned on, the divided voltage generated at node N41 is applied; when switch S43 is turned on, the divided voltage generated at node N42 is applied; and when switch S44 is turned on, the divided voltage generated at node N43 is applied.

In this way, the resistive voltage divider circuit 43 is configured to be able to switch the voltage division ratio by controlling the on/off of the four switches S41 to S44. In other words, the resistive voltage divider circuit 43 is configured to be able to switch between a state in which it outputs voltage Vz as is without dividing it, and a state in which it outputs one of three types of divided voltages obtained by dividing voltage Vz at different voltage division ratios.

In the present embodiment described above, the resistive voltage divider circuit 43 included in the arithmetic circuit 42 is configured to be able to switch between a state in which it outputs voltage Vz directly without dividing it, and a state in which it outputs one of three types of divided voltages obtained by dividing voltage Vz at different voltage division ratios. This configuration makes it possible to make fine adjustments to the calculations performed by the arithmetic circuit 42, thereby enabling fine adjustments to the overall temperature characteristics of the reference voltage Vout.

(Third embodiment)
A third embodiment in which the specific configuration of the arithmetic circuit is changed from that of the first embodiment will be described below with reference to FIG.
11, a reference power supply circuit 51 of this embodiment differs from the reference power supply circuit 1 of the first embodiment shown in FIG. 9 in that it includes an arithmetic circuit 52 instead of the arithmetic circuit 6. The arithmetic circuit 52 differs from the arithmetic circuit 6 in that switches S51 and S52 are added.

Switch S51 is connected between the drain of transistor Q31, which corresponds to the output node of current Iptat from Iptat generation circuit 4, and the inverting input terminal of amplifier 22, and functions as a first switch. Switch S52 is connected between the drain of transistor Q32, which corresponds to the output node of current IEg from bandgap generation circuit 5, and the inverting input terminal of amplifier 22, and functions as a second switch.

In the above configuration, when switches S51 and S52 are turned on, current Iptat and current IEg flow toward the inverting input terminal of amplifier 22, as in the first embodiment, and calculation circuit 52 performs the same calculation as calculation circuit 6. In other words, in the configuration of this embodiment, when switches S51 and S52 are turned on, a correction function can be executed to correct output fluctuations due to temperature and stress characteristics, as in the first embodiment.

On the other hand, in the above configuration, when switches S51 and S52 are turned off, current Iptat and current IEg do not flow toward the inverting input terminal of amplifier 22, and therefore calculations similar to those performed by calculation circuit 6 are not performed in calculation circuit 52. In other words, in the configuration of this embodiment, when switches S51 and S52 are turned off, the above-mentioned correction function can be stopped. In this way, in the configuration of this embodiment, it is possible to switch whether or not calculations are performed in calculation circuit 52 by controlling the on/off of switches S51 and S52.

According to the present embodiment described above, it is possible to switch between running and stopping the correction function that corrects output fluctuations due to temperature and stress characteristics. Therefore, according to this embodiment, when the reference power supply circuit 51 is used in an application that requires a relatively high level of accuracy for the reference voltage Vout, the accuracy of the reference voltage Vout can be improved by running the correction function by the arithmetic circuit 52. Furthermore, according to this embodiment, when the reference power supply circuit 51 is used in an application that requires a relatively low level of accuracy for the reference voltage Vout, the power consumption of the reference power supply circuit 51 can be reduced by stopping the correction function by the arithmetic circuit 52.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, but can be modified, combined, or expanded as desired without departing from the spirit of the invention.
The numerical values and the like shown in the above embodiments are examples and are not limited to these.

The first current generation circuit does not have to be limited to the Iptat generation circuit 4, etc., and can be configured to generate a first current proportional to absolute temperature. The second current generation circuit does not have to be limited to the bandgap generation circuit 5, etc., and can be configured to generate a second current dependent on stress. The calculation circuit does not have to be limited to the calculation circuit 6, etc., and can be configured to perform calculations to correct the temperature and stress characteristics using the first and second currents for the Zener voltage of the Zener diode 2 or a voltage corresponding to the Zener voltage, and to output the calculated voltage as a reference voltage.

While the present disclosure has been described with reference to exemplary embodiments, it is understood that the present disclosure is not limited to those embodiments or structures. The present disclosure also encompasses various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

1, 41, 51...Reference power supply circuit, 2...Zener diode, 4, 4A, 4B, 4C...Iptat generation circuit, 5, 5A, 5B, 5C...Bandgap generation circuit, 6, 42, 52...Calculation circuit, 21, 43...Resistance voltage divider circuit, 22...Amplifier, Q2, Q3, Q6, Q7, Q12, Q13...Bipolar transistor, Q16, Q17, Q19, Q23-Q29...Bipolar transistor, R21, R22...Resistor, R41-R44...Resistor, Rf...Resistor, S41-S44...Switch, S51, S52...Switch.

Claims (9)

Zener diode (2),
a first current generating circuit (4, 4A, 4B, 4C) that generates a first current proportional to absolute temperature;
a second current generating circuit (5, 5A, 5B, 5C) that generates a second current that depends on stress;
an arithmetic circuit (6, 42, 52) that performs an arithmetic operation to correct temperature characteristics and stress characteristics for a Zener voltage of the Zener diode or a voltage corresponding to the Zener voltage using the first current and the second current, and outputs the calculated voltage as a reference voltage;
A reference power supply circuit comprising: The operational circuit comprises an operational amplifier (22);
a cathode of the Zener diode is directly or indirectly connected to one input terminal of the operational amplifier;
The anode of the Zener diode is connected to the ground, which is the reference potential of the circuit.
2. The reference power supply circuit according to claim 1, wherein the other input terminal of the operational amplifier is connected to an output node of the first current of the first current generating circuit and an output node of the second current of the second current generating circuit. The operational circuit further includes a resistor voltage divider circuit (21, 43) including a plurality of resistors (R21, R22, R41 to R44) connected in series, and a feedback resistor (Rf) connected between the inverting input terminal and the output terminal of the operational amplifier,
the resistive voltage divider circuit outputs a divided voltage obtained by dividing the voltage between the anode and cathode of the Zener diode;
an output node of the divided voltage of the resistive voltage divider circuit is connected to a non-inverting input terminal of the operational amplifier;
3. The reference power supply circuit according to claim 2, wherein an output node of the first current of the first current generating circuit and an output node of the second current of the second current generating circuit are connected to an inverting input terminal of the operational amplifier. The resistive voltage divider circuit (43)
a plurality of switches (S41 to S44) connected between each terminal of the plurality of resistors and a non-inverting input terminal of the operational amplifier;
4. The reference power supply circuit according to claim 3, wherein the voltage division ratio can be changed by controlling the on/off of the plurality of switches. The reference power supply circuit of any one of claims 1 to 4, wherein the second current generating circuit includes two or more bipolar transistors (Q16, Q17, Q19, Q23-Q29) and generates a current dependent on the silicon bandgap as the second current. The reference power supply circuit of claim 5, wherein the bipolar transistor is disposed adjacent to the Zener diode. The reference power supply circuit described in claim 6, wherein the bipolar transistor is arranged in a common centroid configuration centered on the Zener diode. The reference power supply circuit of any one of claims 1 to 4, wherein the first current generating circuit includes two bipolar transistors (Q2, Q3, Q6, Q7, Q12, Q13) that pass equivalent collector currents but have different area ratios, or includes two bipolar transistors (Q2, Q3, Q6, Q7, Q12, Q13) that pass different collector currents but have the same area ratio, and generates as the first current a current that depends on the difference between the base-emitter voltages of the two bipolar transistors. The arithmetic circuit (52)
Further, the power supply circuit includes a first switch (S51) connected between an output node of the first current of the first current generating circuit and the other input terminal of the operational amplifier, and a second switch (S52) connected between an output node of the second current of the second current generating circuit and the other input terminal of the operational amplifier,
5. The reference power supply circuit according to claim 2, wherein the first switch and the second switch are controlled to be turned on or off to switch whether or not the calculation is performed.