JP7799583B2 - Power Conversion Device - Google Patents

Description

This disclosure relates to a power conversion device.

In conventional power conversion devices, an active clamp circuit is provided between the collector and gate terminals of a semiconductor switching element to protect the element from surge voltages. This active clamp circuit is made up of a diode, a Zener diode, and a resistor connected in series. In conventional power conversion devices, when the current flowing through the active clamp circuit exceeds a threshold for a predetermined period of time, the Zener diode in the active clamp circuit is determined to be abnormal (see, for example, Patent Document 1).

JP 2019-135884 A

Instead of Zener diodes, active clamp circuits can also use capacitors. However, capacitor degradation is less likely to manifest as a change in current. Therefore, when an active clamp circuit using a capacitor instead of a Zener diode is applied to a conventional power conversion device, it is difficult to properly determine an abnormality in the capacitor within the active clamp circuit using the abnormality detection method described above.

This disclosure has been made to solve the above-mentioned problems, and aims to provide a power conversion device that can properly detect abnormalities in capacitors within a surge voltage suppression circuit.

The power conversion device according to the present disclosure includes an inverter that converts DC voltage to AC voltage and outputs the converted AC voltage to a load. The inverter has a control terminal, a high-potential side terminal, and a low-potential side terminal. The inverter includes a semiconductor switching element that controls the current flowing from the high-potential side terminal to the low-potential side terminal based on a control signal input to the control terminal, a buffer circuit that supplies a control signal from the pulse drive circuit to the control terminal, a surge voltage suppression circuit that is provided between the high-potential side terminal and the buffer circuit and that suppresses the off-surge voltage that occurs between the high-potential side terminal and the low-potential side terminal when the semiconductor switching element is turned off, an abnormality detection circuit that detects an abnormality in the surge voltage suppression circuit, and a power supply voltage regulator within the inverter. The surge voltage suppression circuit has a feedback capacitor, a backflow prevention diode, and a feedback resistor. The feedback capacitor, backflow prevention diode, and feedback resistor are connected in series. The backflow prevention diode is positioned so that current flows from the high-potential terminal toward the buffer circuit. The feedback resistor converts the feedback current flowing through the surge voltage suppression circuit into a voltage and supplies it to the buffer circuit. The abnormality detection circuit detects abnormalities by comparing the connection point voltage, which is the voltage at the connection point between the feedback capacitor and the backflow prevention diode, with the reference voltage.

The power conversion device disclosed herein can properly detect abnormalities in the capacitors within the surge voltage suppression circuit.

1 is a configuration diagram showing an outline of a power conversion device according to a first embodiment; 2 is a configuration diagram of an active clamp circuit applied to each of the semiconductor switching elements of FIG. 1. 10 is a time chart for explaining the operation of the active clamp circuit during the turn-off operation of the semiconductor switching element. 10 is a time chart for explaining the operation of the active clamp circuit during the turn-on operation of the semiconductor switching element. 10 is a diagram showing a first capacitance value, a second capacitance value, a first resistance value, and a second resistance value when the active clamp circuit is normal; FIG. 10 is a time chart for explaining the operation of the active clamp circuit when the active clamp circuit is normal. 10 is a diagram showing the first capacitance value, the second capacitance value, the first resistance value, and the second resistance value when the second capacitance value indicates an abnormal value; FIG. 10 is a time chart for explaining the operation of the active clamp circuit when the second capacitance value indicates an abnormal value. 10 is a diagram showing a first capacitance value, a second capacitance value, a first resistance value, and a second resistance value when the second resistance value indicates an abnormal value; FIG. 10 is a time chart for explaining the operation of the active clamp circuit when the second resistance value indicates an abnormal value.

Hereinafter, embodiments will be described with reference to the drawings.
Embodiment 1.
1 is a schematic diagram illustrating a power conversion device 10 according to embodiment 1. The power conversion device 10 includes a step-up/step-down converter 20, a first inverter 30, and a second inverter 40. The power conversion device 10 is connected to a high-voltage battery 11, a generator 12 as a load, and an electric motor 13 as a load.

The high-voltage battery 11 generates DC voltage and can store DC power. The generator 12 is a three-phase AC generator. The electric motor 13 is a three-phase AC motor.

The step-up/step-down converter 20 has a first reactor 21, a second reactor 22, four semiconductor switching elements 23a, 24a, 25a, and 26a, a first smoothing capacitor 27, and a second smoothing capacitor 28.

Each of the four semiconductor switching elements 23a, 24a, 25a, and 26a uses a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Furthermore, body diodes 23b, 24b, 25b, and 26b are connected in anti-parallel between the drain and source terminals of the four semiconductor switching elements 23a, 24a, 25a, and 26a, respectively.

One end of the first reactor 21 is connected to the positive terminal of the high-voltage battery 11, and the other end of the first reactor 21 is connected to the source terminal of the semiconductor switching element 23a and the drain terminal of the semiconductor switching element 24a.

One end of the second reactor 22 is connected to the positive terminal of the high-voltage battery 11, and the other end of the second reactor 22 is connected to the source terminal of the semiconductor switching element 25a and the drain terminal of the semiconductor switching element 26a.

The drain terminal of semiconductor switching element 23a and the drain terminal of semiconductor switching element 25a are connected to the high-voltage side bus 15. The source terminal of semiconductor switching element 24a and the source terminal of semiconductor switching element 26a are connected to the low-voltage side bus 16.

The first smoothing capacitor 27 is connected between the positive and negative terminals of the high-voltage battery 11. The second smoothing capacitor 28 is connected between the high-voltage bus 15 and the low-voltage bus 16.

The buck-boost converter 20 uses four semiconductor switching elements 23a, 24a, 25a, and 26a to boost the DC voltage from the high-voltage battery 11 and apply it to the first inverter 30 and the second inverter 40. The buck-boost converter 20 also uses four semiconductor switching elements 23a, 24a, 25a, and 26a to step down the DC voltage from the first inverter 30 and apply it to the high-voltage battery 11.

The first inverter 30 has six semiconductor switching elements 31a, 32a, 33a, 34a, 35a, and 36a. Each of the six semiconductor switching elements 31a, 32a, 33a, 34a, 35a, and 36a uses a Si-IGBT (Silicon Carbide-Insulated Gate Bipolar Transistor).

In addition, body diodes 31b, 32b, 33b, 34b, 35b, and 36b are connected in anti-parallel between the collector terminals and emitter terminals of the six semiconductor switching elements 31a, 32a, 33a, 34a, 35a, and 36a, respectively.

The collector terminals of semiconductor switching elements 31a, 33a, and 35a are connected to the high-voltage bus 15. The emitter terminals of semiconductor switching elements 32a, 34a, and 36a are connected to the low-voltage bus 16.

The emitter terminal of semiconductor switching element 31a is connected to the collector terminal of semiconductor switching element 32a. The emitter terminal of semiconductor switching element 33a is connected to the collector terminal of semiconductor switching element 34a. The emitter terminal of semiconductor switching element 35a is connected to the collector terminal of semiconductor switching element 36a.

The connection point between semiconductor switching element 31a and semiconductor switching element 32a is connected to the U-phase terminal of generator 12. The connection point between semiconductor switching element 33a and semiconductor switching element 34a is connected to the V-phase terminal of generator 12. The connection point between semiconductor switching element 35a and semiconductor switching element 36a is connected to the W-phase terminal of generator 12.

The second inverter 40 has six semiconductor switching elements 41a, 42a, 43a, 44a, 45a, and 46a. Each of the six semiconductor switching elements 41a, 42a, 43a, 44a, 45a, and 46a uses a Si-IGBT.

In addition, body diodes 41b, 42b, 43b, 44b, 45b, and 46b are connected in anti-parallel between the collector terminals and emitter terminals of the six semiconductor switching elements 41a, 42a, 43a, 44a, 45a, and 46a, respectively.

The collector terminals of semiconductor switching elements 41a, 43a, and 45a are connected to the high-voltage bus 15. The emitter terminals of semiconductor switching elements 42a, 44a, and 46a are connected to the low-voltage bus 16.

The emitter terminal of semiconductor switching element 41a is connected to the collector terminal of semiconductor switching element 42a. The emitter terminal of semiconductor switching element 43a is connected to the collector terminal of semiconductor switching element 44a. The emitter terminal of semiconductor switching element 45a is connected to the collector terminal of semiconductor switching element 46a.

The connection point between semiconductor switching element 41a and semiconductor switching element 42a is connected to the U-phase terminal of electric motor 13. The connection point between semiconductor switching element 43a and semiconductor switching element 44a is connected to the V-phase terminal of electric motor 13. The connection point between semiconductor switching element 45a and semiconductor switching element 46a is connected to the W-phase terminal of electric motor 13.

Figure 2 is a schematic diagram of an active clamp circuit applied to each of the semiconductor switching elements 41a to 46a of the second inverter 40 in Figure 1. Figure 2 shows some of the semiconductor switching elements 41a and 42a in the second inverter 40, while the remaining semiconductor switching elements 43a to 46a are omitted.

The second inverter 40 has a buffer circuit 50, an active clamp circuit 60 as a surge voltage suppression circuit, an abnormality detection circuit 70, and a reference voltage generation circuit 80 corresponding to the semiconductor switching element 42a. Note that in Figure 2, the active clamp circuit, abnormality detection circuit, and reference voltage generation circuit for the semiconductor switching element 41a are omitted because they are similar to the respective circuits for the semiconductor switching element 42a.

A DC power supply 100 is connected between the high-voltage bus 15 and the low-voltage bus 16. This DC power supply 100 corresponds to the step-up/step-down converter 20 in Figure 1. The output voltage of the DC power supply 100, i.e., the bus voltage, is Vpn.

The buffer circuit 50 is inserted between a pulse drive circuit 90 external to the second inverter 40 and the gate terminal G, which serves as the control terminal of the semiconductor switching element 42a. The buffer circuit 50 includes a first transistor 51, a second transistor 52, a gate-on resistor 53, and a gate-off resistor 54. Power is supplied to the buffer circuit 50 from the low-voltage power supply Vcc. The pulse drive circuit 90 outputs a gate command pulse voltage as a control signal to the gate terminal G via the buffer circuit 50.

The active clamp circuit 60 suppresses the off-surge voltage that occurs between the collector terminal C, which serves as the high-potential terminal of the semiconductor switching element 42a, and the emitter terminal E, which serves as the low-potential terminal of the semiconductor switching element 42a, when the element 42a is turned off. The off-surge voltage is calculated as the product L x di/dt of the wiring inductance L within the second inverter 40 and the change di/dt in the collector current Ic of the semiconductor switching element 42a. The active clamp circuit 60 is located between the collector terminal C and the buffer circuit 50.

The active clamp circuit 60 includes a first feedback capacitor 61a, a second feedback capacitor 61b, a first balancing resistor 62a, a second balancing resistor 62b, a backflow prevention diode 63, a first feedback resistor 64a, a second feedback resistor 64b, a clamp capacitor 65, a reverse blocking diode 66, and a discharge resistor 67. In the active clamp circuit 60, the first feedback capacitor 61a, the second feedback capacitor 61b, the backflow prevention diode 63, the first feedback resistor 64a, and the second feedback resistor 64b are connected in series in this order.

The first feedback capacitor 61a is connected to the collector terminal C. The second feedback resistor 64b is connected to the pulse drive circuit 90. The point between the first feedback resistor 64a and the second feedback resistor 64b is connected to the input terminal, which serves as the midpoint of the buffer circuit 50.

The first feedback capacitor 61a and the second feedback capacitor 61b generate a feedback current Ifb that corresponds to the change dv/dt in the collector-emitter voltage Vce of the semiconductor switching element 42a. Here, the capacitance value of the first feedback capacitor 61a is the first capacitance value C1, and the capacitance value of the second feedback capacitor 61b is the second capacitance value C2.

Furthermore, if the combined capacitance of the first feedback capacitor 61a and the second feedback capacitor 61b is represented by combined capacitance C0, the feedback current Ifb is expressed as the product C0 x dv/dt of combined capacitance C0 and the change in collector-emitter voltage Vce (dv/dt). In this embodiment, the first capacitance C1 and the second capacitance C2 are designed to be equal. For example, the first capacitance C1 and the second capacitance C2 are 100 pF.

The first balancing resistor 62a is connected in parallel with the first feedback capacitor 61a. The second balancing resistor 62b is connected in parallel with the second feedback capacitor 61b. The first balancing resistor 62a and the second balancing resistor 62b are arranged so that the voltage applied to the first feedback capacitor 61a and the voltage applied to the second feedback capacitor 61b are evenly distributed. The resistance value of the first balancing resistor 62a is the first resistance value R1, and the resistance value of the second balancing resistor 62b is the second resistance value R2.

The backflow prevention diode 63 is positioned so that current flows from the collector terminal C toward the buffer circuit 50. A Schottky barrier diode is used as the backflow prevention diode 63. Generally, the junction capacitance of a Schottky barrier diode is larger than that of a PN junction diode. For example, the junction capacitance of the backflow prevention diode 63 when the semiconductor switching element 42a is turned on is several hundred pF.

Therefore, the capacitance value of the junction capacitance of the backflow prevention diode 63 when the semiconductor switching element 42a is turned on is on the same order as the first capacitance value C1 and the second capacitance value C2.

The first feedback resistor 64a and the second feedback resistor 64b convert the feedback current Ifb into a voltage and provide it to the buffer circuit 50. More specifically, the first feedback resistor 64a and the second feedback resistor 64b change the midpoint voltage Vmid of the buffer circuit 50 in accordance with the feedback current Ifb. The midpoint voltage Vmid is the voltage at the input terminal of the buffer circuit 50.

The clamp capacitor 65 is connected between one end of the first feedback resistor 64a and the ground terminal. One end of the first feedback resistor 64a is connected to the cathode of the backflow prevention diode 63. The clamp capacitor 65 adjusts the timing of feedback by the active clamp circuit 60.

By providing a clamp capacitor 65, it is possible to apply feedback to the off-surge voltage at the optimal timing when the gate of the semiconductor switching element 42a turns on, thereby suppressing an increase in switching loss of the semiconductor switching element 42a.

The reverse-blocking diode 66 is oriented so as to block current flow from the collector terminal C toward the ground terminal. A Schottky barrier diode is used as the reverse-blocking diode 66. The reverse-blocking diode 66 has the same characteristics as the backflow prevention diode 63.

The reverse-blocking diode 66 and discharge resistor 67 are connected in series between the connection point CT and the ground terminal. The reverse-blocking diode 66 and discharge resistor 67 form a discharge circuit. In other words, the active clamp circuit 60 has a discharge circuit. This discharge circuit is provided to prevent the voltage applied to the reverse-current prevention diode 63 from becoming excessive when the semiconductor switching element 42a transitions from a turn-off operation to a turn-on operation.

Generally, there is a trade-off between off-surge voltage and switching-off loss. Generally, when the resistance value of the gate-off resistor is reduced, the change in off-surge voltage dv/dt increases, resulting in a higher off-surge voltage. However, by using the active clamp circuit 60, the off-surge voltage is clamped, making it possible to reduce switching-off loss while suppressing increases in off-surge voltage.

Resistor 42c is a resistor used to prevent self-turn-on of semiconductor switching element 42a.

The abnormality detection circuit 70 includes a comparator 71 and a detection signal generation circuit 72. The abnormality detection circuit 70 detects abnormalities by comparing the connection point voltage Vct with a reference voltage Vref. The connection point voltage Vct is the voltage at the connection point CT between the second feedback capacitor 61b and the backflow prevention diode 63. The reference voltage Vref is a voltage generated by the reference voltage generation circuit 80. The connection point voltage Vct is determined based on the ratio of the combined capacitance value C0 to the junction capacitance of the backflow prevention diode 63 during turn-on operation.

The comparator 71 compares the connection point voltage Vct with the reference voltage Vref and outputs the comparison result to the detection signal generation circuit 72.

The detection signal generation circuit 72 generates an abnormality detection signal Vmf based on the comparison result output from the comparator 71 and outputs the generated abnormality detection signal to a control unit (not shown). The control unit is, for example, an ECU (Electronic Control Unit).

For example, when the connection point voltage Vct exceeds the reference voltage Vref, the detection signal generation circuit 72 outputs a high-level signal to the ECU as the abnormality detection signal Vmf. Furthermore, when the connection point voltage Vct is equal to or lower than the reference voltage Vref, the detection signal generation circuit 72 outputs a low-level signal, different from the high-level signal, to the ECU as the abnormality detection signal Vmf. The logic of the abnormality detection signal Vmf may be inverted.

If the abnormality detection signal Vmf is a low-level signal, the ECU determines that the active clamp circuit 60 is normal. On the other hand, if the abnormality detection signal Vmf is a high-level signal, that is, if the abnormality detection circuit 70 detects a voltage higher than the reference voltage Vref, the ECU determines that the active clamp circuit 60 is abnormal. If the active clamp circuit 60 is determined to be abnormal, the ECU sets the gate command pulse voltage for all semiconductor switching elements 41a to 46a in the second inverter 40 to zero. In other words, the ECU stops the operation of all semiconductor switching elements 41a to 46a in the second inverter 40.

The reference voltage generation circuit 80 has a first dividing resistor 81, a second dividing resistor 82, and a third dividing resistor 83. The reference voltage generation circuit 80 is arranged between the high-voltage side bus 15 and the low-voltage side bus 16. The first dividing resistor 81, the second dividing resistor 82, and the third dividing resistor 83 are connected in series in this order from the high-voltage side bus 15 to the low-voltage side bus 16. The reference voltage Vref is the voltage between the second dividing resistor 82 and the third dividing resistor 83. In this embodiment, the resistance values of the first dividing resistor 81, the second dividing resistor 82, and the third dividing resistor 83 are set so that the reference voltage Vref is 4.0 V.

Figure 3 is a time chart illustrating the operation of the active clamp circuit 60 when the semiconductor switching element 42a is turned off. Figure 3 shows the gate-emitter voltage Vge of the semiconductor switching element 42a, the collector-emitter voltage Vce of the semiconductor switching element 42a, and the collector current Ic of the semiconductor switching element 42a.

The gate-emitter voltage Vge of the semiconductor switching element 42a will be referred to simply as the gate voltage Vge below. The collector-emitter voltage Vce of the semiconductor switching element 42a will be referred to simply as the collector voltage Vce below.

At time t1, as the gate command pulse voltage from the pulse drive circuit 90 decreases, the gate voltage Vge begins to decrease. As a result, the collector current Ic begins to decrease and the collector voltage Vce begins to increase. In response to the feedback current Ifb = C0 × dv/dt, the midpoint voltage Vmid of the buffer circuit 50 increases, and the gate of the semiconductor switching element 42a turns on again.

This causes the collector current Ic to flow, reducing the change di/dt in the collector current Ic. As a result, the collector voltage Vce, including the off-surge voltage, is clamped to the bus voltage Vpn. After that, at time t2, the collector current Ic becomes zero, and the collector voltage Vce becomes a constant value.

Figure 4 is a time chart illustrating the operation of the active clamp circuit 60 when the semiconductor switching element 42a is turned on. Figure 4 shows the gate command pulse voltage Vdrv, the connection point voltage Vct, the midpoint voltage Vmid, the gate voltage Vge, the collector voltage Vce, and the collector current Ic.

At time t3, when the gate command pulse voltage Vdrv rises, charging of the gate parasitic capacitance begins, and the gate voltage Vge begins to rise. The gate parasitic capacitance is the capacitance parasitic on the gate terminal G of the semiconductor switching element 42a.

Furthermore, at time t3, a gate command pulse voltage Vdrv = 15 V is applied to the first feedback resistor 64a and the second feedback resistor 64b, and the connection point voltage Vct is increased by the feedback voltage Vfb. The feedback voltage Vfb is a voltage determined by the product of the sum of the resistance values of the first feedback resistor 64a and the second feedback resistor 64b and the output current value. The output current is the current flowing through the first feedback resistor 64a and the second feedback resistor 64b.

Also, at time t3, the midpoint voltage Vmid is raised by a voltage determined by the product of the resistance value of the second feedback resistor 64b and the output current value, but then returns to the voltage immediately before turn-on.

After time t3, the gate voltage Vge gradually increases until it reaches its maximum value of 15 V. During this time, the gate parasitic capacitance continues to charge. As the gate voltage Vge increases, the node voltage Vct also gradually increases. Time t3 marks the start of the gate charging period.

At time t4, when the gate voltage Vge reaches the gate threshold voltage Vth, the semiconductor switching element 42a turns on and the collector current Ic begins to flow. This reduces the resistance between the collector terminal C and the emitter terminal E, and the collector voltage Vce begins to decrease. Time t4 is the first time point at which the gate voltage Vge reaches the gate threshold voltage Vth.

Furthermore, as the collector voltage Vce decreases, the charge stored in the first feedback capacitor 61a and the charge stored in the second feedback capacitor 61b are discharged, causing the connection point voltage Vct to begin to decrease. The time constant for the charge discharge is determined by the product of the combined capacitance value C0 and the resistance value of the discharge resistor 67.

At time t5, the gate voltage Vge reaches the Miller period, which is a period of constant voltage, and then reaches the maximum drive voltage of 15 V.

Figure 5 shows the first capacitance value C1, second capacitance value C2, first resistance value R1, and second resistance value R2 when the active clamp circuit 60 is normal. The first capacitance value C1 and second capacitance value C2 are both 100 pF. The first resistance value R1 and second resistance value R2 are both 1 MΩ.

Figure 6 is a time chart illustrating the operation of the active clamp circuit 60 when the active clamp circuit 60 is operating normally. Figure 6 shows the connection point voltage Vct, gate voltage Vge, gate current Ig, collector current Ic, and collector voltage Vce.

When the active clamp circuit 60 is operating normally, the connection point voltage Vct during turn-on operation reaches its maximum at time t4, i.e., the first point in time, and in this case is 3.7 V.

Because the collector voltage Vce is relatively stable from time t3 to time t4, i.e., the period up to the first point in time, the connection point voltage Vct during this period is also relatively stable. Furthermore, the connection point voltage Vct during this period reflects changes in the first capacitance value C1 or the second capacitance value C2. Therefore, the period from time t3 to time t4, which is the first point in time, is set as the valid period for the abnormality detection timing.

The abnormality detection circuit 70 compares the maximum value of the connection point voltage Vct during the valid period with the reference voltage Vref. As described above, the reference voltage Vref is set to 4.0 V. Therefore, in this case, the maximum value of the connection point voltage Vct during turn-on operation is smaller than the reference voltage Vref. Therefore, the abnormality detection circuit 70 does not detect an abnormality in the active clamp circuit 60.

During the mirror period from time t5 onwards, the collector voltage Vce drops due to the collector current Ic flowing between the collector and emitter of the semiconductor switching element 42a, making the connection point voltage Vct prone to instability. Therefore, the mirror period is set to a period during which the abnormality detection timing is disabled.

Figure 7 shows the first capacitance value C1, second capacitance value C2, first resistance value R1, and second resistance value R2 when the second capacitance value C2 indicates an abnormal value. The first capacitance value C1 is 100 pF. The second capacitance value C2 is 80 pF, which is 20% lower than the normal value of 100 pF. The first resistance value R1 and second resistance value R2 are both 1 MΩ.

Figure 8 is a timing chart illustrating the operation of the active clamp circuit 60 when the second capacitance value C2 indicates an abnormal value. When the second capacitance value C2 is 80 pF, the collector voltage Vce is no longer clamped properly during the turn-off operation, and an off-surge voltage occurs in the collector voltage Vce.

In this way, when the second capacitance value C2 decreases, the feedback current, which is determined by the change in collector voltage Vce dv/dt and the capacitor capacitance, decreases, and the amount of off-surge voltage clamping also decreases. Therefore, the maximum value of the connection point voltage Vct, which is determined by the capacitance ratio between the first capacitance value C1, the second capacitance value C2, and the junction capacitance of the backflow prevention diode 63, exceeds the reference voltage Vref during turn-on operation and becomes 4.3 V.

The abnormality detection circuit 70 compares the maximum value of the connection point voltage Vct during turn-on operation with the reference voltage Vref. In this case, the maximum value of the connection point voltage Vct during turn-on operation is greater than the reference voltage Vref. Therefore, the abnormality detection circuit 70 detects an abnormality in the active clamp circuit 60.

Figure 9 shows the first capacitance value C1, second capacitance value C2, first resistance value R1, and second resistance value R2 when the second resistance value R2 indicates an abnormal value. The first capacitance value C1 and second capacitance value C2 are both 100 pF. The first resistance value R1 is 1 MΩ. The second resistance value R2 is 800 kΩ, which is 20% lower than the normal value of 1 MΩ.

Figure 10 is a timing chart illustrating the operation of the active clamp circuit 60 when the second resistance value R2 indicates an abnormal value. When the second resistance value R2 is 800 kΩ, the collector voltage Vce is no longer clamped properly during the turn-off operation, and an off-surge voltage occurs in the collector voltage Vce.

In this way, when the second resistance value R2 decreases, the balance between the voltage applied across the first feedback capacitor 61a and the voltage applied across the second feedback capacitor 61b (of the collector voltage Vce) is disrupted, causing the feedback current Ifb to decrease. This also reduces the amount of off-surge voltage clamping. As a result, the maximum value of the connection point voltage Vct, determined by the resistance ratio of the balancing resistors R1 and R2, exceeds the reference voltage Vref during turn-on operation and becomes 4.1 V.

As such, if the second balancing resistor 62b deteriorates, the active clamp circuit 60 will no longer operate normally, just as it would if the second feedback capacitor 61b deteriorated. Furthermore, the connection point voltage Vct during turn-on operation changes in response to changes in the resistance value of at least one of the first balancing resistor 62a and the second balancing resistor 62b.

The abnormality detection circuit 70 compares the maximum value of the connection point voltage Vct during turn-on operation with the reference voltage Vref. In this case, the maximum value of the connection point voltage Vct during turn-on operation is greater than the reference voltage Vref. Therefore, the abnormality detection circuit 70 detects an abnormality in the active clamp circuit 60.

As such, the power conversion device according to embodiment 1 includes a second inverter 40. The second inverter 40 converts DC voltage into AC voltage and outputs the converted AC voltage to the electric motor 13. The second inverter 40 includes a semiconductor switching element 42a, a buffer circuit 50, an active clamp circuit 60, an abnormality detection circuit 70, and a reference voltage generation circuit 80.

The semiconductor switching element 42a has a gate terminal G, a collector terminal C, and an emitter terminal E, and controls the collector current Ic based on the gate command pulse voltage input to the gate terminal G. The collector current Ic is a current that flows from the collector terminal C to the emitter terminal E.

The buffer circuit 50 is a circuit that supplies a control signal from the pulse drive circuit 90 to the gate terminal G.

The active clamp circuit 60 is provided between the collector terminal C and the buffer circuit 50 and suppresses off-surge voltage when the semiconductor switching element 42a is turned off. The off-surge voltage is the voltage generated between the collector terminal C and the emitter terminal E. The abnormality detection circuit 70 detects abnormalities in the active clamp circuit 60. The reference voltage generation circuit 80 generates a reference voltage Vref by dividing the bus voltage Vpn of the second inverter 40.

The active clamp circuit 60 has a first feedback capacitor 61a, a second feedback capacitor 61b, a backflow prevention diode 63, a first feedback resistor 64a, and a second feedback resistor 64b. The first feedback capacitor 61a, the second feedback capacitor 61b, the backflow prevention diode 63, the first feedback resistor 64a, and the second feedback resistor 64b are connected in series. The backflow prevention diode 63 is positioned so that current flows from the collector terminal C toward the buffer circuit 50. The first feedback resistor 64a and the second feedback resistor 64b convert the feedback current Ifb flowing through the active clamp circuit 60 into a voltage and provide it to the buffer circuit 50.

The abnormality detection circuit 70 detects an abnormality in the active clamp circuit 60 by comparing the connection point voltage Vct with a reference voltage Vref. The connection point voltage Vct is the voltage at the connection point between the second feedback capacitor 61b and the backflow prevention diode 63.

Abnormalities due to capacitor degradation often manifest as a decrease in the capacitor's capacitance. When the capacitance of at least one of the first feedback capacitor 61a and the second feedback capacitor 61b decreases, the connection point voltage Vct changes depending on the degree of capacitance decrease. Therefore, by detecting changes in the connection point voltage Vct, it is possible to detect an abnormality in at least one of the first feedback capacitor 61a and the second feedback capacitor 61b, i.e., an abnormality in the active clamp circuit 60. Therefore, the power conversion device 10 according to this embodiment can appropriately detect an abnormality in at least one of the first feedback capacitor 61a and the second feedback capacitor 61b in the active clamp circuit 60.

This prevents the semiconductor switching element 42a from being destroyed due to a loss of off-surge voltage suppression effect and an increase in switching-off loss. As a result, the reliability of the power conversion device can be improved.

In addition, the connection point voltage Vct is determined based on the ratio of the combined capacitance of the first feedback capacitor 61a and the second feedback capacitor 61b to the junction capacitance of the backflow prevention diode 63 when the semiconductor switching element 42a is turned on.

As a result, when the semiconductor switching element 42a is turned on, a change in at least one of the first capacitance value C1 and the second capacitance value C2 is detected as a change in the connection point voltage Vct. Therefore, abnormalities in the first feedback capacitor 61a and the second feedback capacitor 61b can be more appropriately detected. In other words, this makes it possible to detect signs of abnormalities due to changes in the characteristics of the components that make up the active clamp circuit 60 in response to changes in the connection point voltage Vct.

Furthermore, the timing at which the abnormality detection circuit 70 detects the connection point voltage Vct is during the gate charging period during turn-on operation, specifically, the timing from when the semiconductor switching element 42a turns on and the collector current Ic begins to flow until the collector voltage Vce begins to decrease to the gate threshold voltage Vth.

During the gate charging period, the connection point voltage Vct increases as the gate voltage Vge increases until the gate voltage Vge exceeds the gate threshold voltage Vth. The degree of increase in the connection point voltage Vct during the gate charging period increases as the first capacitance value C1 decreases. Similarly, the degree of increase in the connection point voltage Vct during the gate charging period increases as the second capacitance value C2 decreases. Therefore, by detecting the connection point voltage Vct at a timing during the gate charging period, abnormalities in the first feedback capacitor 61a and the second feedback capacitor 61b can be more appropriately detected.

Furthermore, during the gate charging period, the period from time t3, which is the start of the gate charging period, to time t4, which is the first time point at which the gate voltage Vge reaches the gate threshold voltage Vth, is considered to be the valid period of detection timing, and the mirror period after the first time point is considered to be the invalid period of detection timing. The mirror period is the period during which the voltage at the gate terminal G is constant.

The connection point voltage Vct increases from time t3 to time t4, when the gate voltage Vge reaches the gate threshold voltage Vth. During this period, the connection point voltage Vct reflects changes in the first capacitance value C1 or the second capacitance value C2. Furthermore, during the mirror period, fluctuations in the collector voltage Vce are relatively large, making the connection point voltage Vct prone to instability. Therefore, this allows for accurate detection of abnormalities in the first feedback capacitor 61a and the second feedback capacitor 61b.

The active clamp circuit 60 also includes a discharge circuit. The discharge circuit is composed of a reverse-blocking diode 66 and a discharge resistor 67. The reverse-blocking diode 66 and the discharge resistor 67 are connected in series between the connection point CT and the ground terminal. The reverse-blocking diode 66 is oriented so as to block current flowing from the collector terminal C toward the ground terminal.

In this way, by connecting the reverse blocking diode 66 and the discharge resistor 67 in series, a resistor with a lower voltage resistance can be used as the discharge resistor 67.

The active clamp circuit 60 also includes a clamp capacitor 65. The clamp capacitor 65 is connected between one end of the first feedback resistor 64a and the ground terminal. One end of the first feedback resistor 64a is connected to the backflow prevention diode 63.

This allows the timing at which the active clamp circuit 60 clamps the collector voltage Vce to be delayed without impairing the feedback responsiveness of the active clamp circuit 60 during turn-off operation. As a result, the collector voltage Vce can be clamped in accordance with the gate-on timing, thereby reducing switching-off losses.

The system also includes a control unit that stops the operation of the semiconductor switching elements 41a to 46a in the second inverter 40 when the abnormality detection circuit 70 detects a voltage that exceeds the reference voltage Vref.

This allows all semiconductor switching elements in the second inverter 40 to be protected.

The active clamp circuit 60 also has a first feedback capacitor 61a and a second feedback capacitor 61b. The active clamp circuit 60 further has a first balancing resistor 62a and a second balancing resistor 62b. The first balancing resistor 62a is connected in parallel with the first feedback capacitor 61a. The second balancing resistor 62b is connected in parallel with the second feedback capacitor 61b. The connection point voltage Vct changes in response to changes in the resistance value of the first balancing resistor 62a or the resistance value of the second balancing resistor 62b.

As a result, even if at least one of the first resistance value R1 and the second resistance value R2 changes, this can be detected as an abnormality in the active clamp circuit 60. In other words, this makes it possible to detect signs of an abnormality due to a change in the characteristics of the components that make up the active clamp circuit 60 based on changes in the connection point voltage Vct.

Note that the order of the first feedback capacitor 61a, the second feedback capacitor 61b, the backflow prevention diode 63, and the first feedback resistor 64a and the second feedback resistor 64b is not limited to that shown in embodiment 1.

Furthermore, the reverse blocking diode 66 does not necessarily have to have the same characteristics as the reverse current prevention diode 63.

Also, the clamp capacitor 65 is not necessarily required.

Also, the reverse blocking diode 66 is not necessarily required.

In addition, in embodiment 1, the collector voltage Vce, including the off-surge voltage, was clamped to the bus voltage Vpn, but the clamped voltage need only be equal to or less than the maximum cut-off voltage of the system. The maximum cut-off voltage is the cut-off voltage when hard cut-off is performed during overvoltage protection or overcurrent protection.

In addition, in embodiment 1, the voltage resistance of the capacitors used as feedback capacitors was taken into consideration, and as a result, the first feedback capacitor 61a and the second feedback capacitor 61b are connected in series. If the voltage resistance of the capacitors is acceptable, a single feedback capacitor is sufficient. Furthermore, if there is only one feedback capacitor, a balancing resistor is not required.

The active clamp circuit 60 may also include a high-voltage avalanche diode instead of the first feedback capacitor 61a and the second feedback capacitor 61b. In this case, the connection point voltage Vct is determined based on the ratio of the junction capacitance of the avalanche diode to the junction capacitance of the backflow prevention diode 63 when the semiconductor switching element 42a is turned on.

In general, avalanche diodes have a higher withstand voltage than the capacitors used as the first feedback capacitor 61a and the second feedback capacitor 61b in embodiment 1. Therefore, the first feedback capacitor 61a, the second feedback capacitor 61b, the first balancing resistor 62a, and the second balancing resistor 62b can be replaced with a single avalanche diode. This allows for a reduction in the number of components in the active clamp circuit 60.

Furthermore, one end of the active clamp circuit 60 was connected to the input side of the buffer circuit 50, but it may also be connected to the output side of the buffer circuit 50. Specifically, one end of the active clamp circuit 60 may be connected between the first transistor 51 and the gate-on resistor 53.

Furthermore, the collector voltage Vce at time t4, when the collector voltage Vce begins to decrease during the turn-on operation, may be used as the voltage within the second inverter 40 for generating the reference voltage Vref. The collector voltage Vce at time t4 is stable compared to other periods.

Furthermore, if it is determined that the active clamp circuit 60 is abnormal, the ECU may prevent damage to the semiconductor switching elements 41a-46a by switching the operation of the electric motor 13 to power saving mode. Power saving mode is an operation that limits the torque and rotation speed of the electric motor 13 by limiting the drive current of the electric motor 13.

In other words, if the abnormality detection circuit 70 detects a voltage exceeding the reference voltage Vref, the ECU may limit the torque and rotation speed of the electric motor 13. This protects all of the semiconductor switching elements 41a to 46a in the second inverter 40.

The active clamp circuits provided in the semiconductor switching elements 41a and 43a to 46a other than the semiconductor switching element 42a of the second inverter 40 are also described in the same manner. The active clamp circuits provided in the semiconductor switching elements 31a to 36a of the first inverter 30 are also described in the same manner.

In addition, in embodiment 1, Si-IGBTs were used as the semiconductor switching elements 31a to 36a and 41a to 46a, but these semiconductor switching elements are not limited to Si semiconductors and may also be wide bandgap semiconductors. Wide bandgap semiconductors have higher breakdown voltages, superior heat dissipation properties, and are capable of high-speed switching operations compared to Si semiconductors.

Examples of wide bandgap semiconductors that can be used include SiC (Silicon Carbide)-based materials, GaN (Gallium Nitride)-based materials, and diamond-based materials. Diamond-based materials have the highest dielectric strength and thermal conductivity of all wide bandgap semiconductors.

SiC-MOSFETs (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors) are capable of faster switching operations than Si-IGBTs. Therefore, when an active clamp circuit 60 is applied to an inverter using SiC-MOSFETs, the trade-off relationship between off-surge voltage and switching loss during turn-off operation can be more appropriately designed.

In this way, the semiconductor switching element 42a may be constructed from a next-generation wide bandgap semiconductor. This enables faster switching operations, allowing for a more appropriate distribution of the off-surge voltage generated during turn-off operations and switching-off losses.

Furthermore, in embodiment 1, the power conversion device 10 in FIG. 1 is merely an example, and the active clamp circuit is not limited to application to the semiconductor switching elements 31a to 36a and 41a to 46a of the power conversion device 10.

Furthermore, while the present disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various modifications and combinations. Therefore, countless modifications and combinations not illustrated are contemplated within the scope of the technology disclosed in this specification. For example, this includes cases in which at least one component is modified, added, or omitted, and even cases in which at least one component is extracted and combined with components of another embodiment.

The above describes preferred embodiments, etc., but the present invention is not limited to the above-described embodiments, etc., and various modifications and substitutions can be made to the above-described embodiments, etc., without departing from the scope of the claims.

The various aspects of this disclosure are summarized below as appendices.

(Appendix 1)
an inverter that converts a DC voltage into an AC voltage and outputs the converted AC voltage to a load;
The inverter is
a semiconductor switching element having a control terminal, a high potential side terminal, and a low potential side terminal, and controlling a current flowing from the high potential side terminal to the low potential side terminal based on a control signal input to the control terminal;
a buffer circuit for supplying the control signal from the pulse driver circuit to the control terminal;
a surge voltage suppression circuit provided between the high potential side terminal and the buffer circuit, for suppressing an off-surge voltage generated between the high potential side terminal and the low potential side terminal during a turn-off operation of the semiconductor switching element;
an abnormality detection circuit that detects an abnormality in the surge voltage suppression circuit; and a reference voltage generation circuit that generates a reference voltage by dividing the voltage in the inverter,
the surge voltage suppression circuit includes a feedback capacitor, a backflow prevention diode, and a feedback resistor;
the feedback capacitor, the backflow prevention diode, and the feedback resistor are connected in series;
the backflow prevention diode is disposed in a direction in which a current flows from the high potential side terminal toward the buffer circuit,
the feedback resistor converts a feedback current flowing through the surge voltage suppression circuit into a voltage and supplies the voltage to the buffer circuit;
The abnormality detection circuit detects the abnormality by comparing a connection point voltage, which is a voltage at a connection point between the feedback capacitor and the backflow prevention diode, with the reference voltage.
(Appendix 2)
The power conversion device according to claim 1, wherein the connection point voltage is determined based on a ratio between a capacitance of the feedback capacitor and a junction capacitance of the blocking diode during a turn-on operation of the semiconductor switching element.
(Appendix 3)
The power conversion device according to claim 2, wherein the timing at which the abnormality detection circuit detects the connection point voltage is during a gate charging period during which a parasitic capacitance of the control terminal is charged during the turn-on operation.
(Appendix 4)
During the gate charging period, a period from a start point of the gate charging period to a first point in time at which the voltage of the control terminal reaches a gate threshold voltage is defined as a valid period of the detection timing, and a mirror period after the first point in time is defined as an invalid period of the detection timing,
The power conversion device according to claim 3, wherein the mirror period is a period during which the voltage of the control terminal is constant.
(Appendix 5)
the surge voltage suppression circuit further includes a discharge circuit;
the discharge circuit is composed of a reverse blocking diode and a discharge resistor,
the reverse blocking diode and the discharge resistor are connected in series between the connection point and a ground terminal,
The power conversion device according to any one of Supplementary Note 1 to Supplementary Note 4, wherein the reverse blocking diode is disposed in a direction to block current flowing from the high potential side terminal toward the ground terminal.
(Appendix 6)
The power conversion device according to any one of Supplementary Note 1 to Supplementary Note 5, wherein the surge voltage suppression circuit further includes a clamp capacitor that is a capacitor connected between one end of the feedback resistor and a ground terminal.
(Appendix 7)
The power conversion device according to any one of Supplementary Note 1 to Supplementary Note 6, wherein the semiconductor switching element is configured by a next-generation wide bandgap semiconductor.
(Appendix 8)
The power conversion device according to any one of Supplementary Note 1 to Supplementary Note 7, further comprising: a control unit that stops operation of the semiconductor switching elements in the inverter when the abnormality detection circuit detects a voltage exceeding the reference voltage.
(Appendix 9)
The power conversion device according to any one of Supplementary Note 1 to Supplementary Note 8, further comprising a control unit that limits a torque and a rotation speed of a motor serving as a load of the inverter when the abnormality detection circuit detects a voltage exceeding the reference voltage.
(Appendix 10)
the surge voltage suppression circuit includes a plurality of capacitors as the feedback capacitor, and further includes a plurality of balancing resistors connected in parallel with the plurality of capacitors, respectively;
The power conversion device according to any one of Supplementary Note 2 to Supplementary Note 9, wherein the connection point voltage changes in accordance with a change in resistance value of the plurality of balancing resistors.
(Appendix 11)
the surge voltage suppression circuit has a high-voltage avalanche diode instead of the feedback capacitor,
The power conversion device according to claim 1, wherein the connection point voltage is determined based on a ratio of a junction capacitance of the avalanche diode to a junction capacitance of the blocking diode during a turn-on operation of the semiconductor switching element.

40 second inverter (inverter), 42a semiconductor switching element, 50 buffer circuit, 60 active clamp circuit (surge voltage suppression circuit), 61a first feedback capacitor (feedback capacitor), 61b second feedback capacitor (feedback capacitor), 62a first balancing resistor (balancing resistor), 62b second balancing resistor (balancing resistor), 63 reverse current prevention diode, 64a first feedback resistor (feedback resistor), 64b second feedback resistor (feedback resistor), 65 clamp capacitor, 66 reverse blocking diode, 67 discharge resistor, 70 abnormality detection circuit, 80 reference voltage generation circuit, 90 pulse drive circuit, C collector terminal (high potential side terminal), E emitter terminal (low potential side terminal), G gate terminal (control terminal), Ifb feedback current, Vct connection point voltage, Vpn bus voltage, Vref reference voltage, Vth gate threshold voltage.

Claims (11)

an inverter that converts a DC voltage into an AC voltage and outputs the converted AC voltage to a load;
The inverter is
a semiconductor switching element having a control terminal, a high potential side terminal, and a low potential side terminal, and controlling a current flowing from the high potential side terminal to the low potential side terminal based on a control signal input to the control terminal;
a buffer circuit for supplying the control signal from the pulse driver circuit to the control terminal;
a surge voltage suppression circuit provided between the high potential side terminal and the buffer circuit, for suppressing an off-surge voltage generated between the high potential side terminal and the low potential side terminal during a turn-off operation of the semiconductor switching element;
an abnormality detection circuit that detects an abnormality in the surge voltage suppression circuit; and a reference voltage generation circuit that generates a reference voltage by dividing the voltage in the inverter,
the surge voltage suppression circuit includes a feedback capacitor, a backflow prevention diode, and a feedback resistor;
the feedback capacitor, the backflow prevention diode, and the feedback resistor are connected in series;
the backflow prevention diode is disposed in a direction in which a current flows from the high potential side terminal toward the buffer circuit,
the feedback resistor converts a feedback current flowing through the surge voltage suppression circuit into a voltage and supplies the voltage to the buffer circuit;
The abnormality detection circuit detects the abnormality by comparing a connection point voltage, which is a voltage at a connection point between the feedback capacitor and the backflow prevention diode, with the reference voltage. The power conversion device according to claim 1 , wherein the connection point voltage is determined based on a ratio between a capacitance of the feedback capacitor and a junction capacitance of the blocking diode during a turn-on operation of the semiconductor switching element. The power conversion device according to claim 2 , wherein the timing at which the abnormality detection circuit detects the node voltage is during a gate charging period during which a parasitic capacitance of the control terminal is charged during the turn-on operation. During the gate charging period, a period from a start point of the gate charging period to a first point in time at which the voltage of the control terminal reaches a gate threshold voltage is defined as a valid period of the detection timing, and a mirror period after the first point in time is defined as an invalid period of the detection timing,
The power conversion device according to claim 3 , wherein the mirror period is a period during which the voltage of the control terminal is constant. the surge voltage suppression circuit further includes a discharge circuit;
the discharge circuit is composed of a reverse blocking diode and a discharge resistor,
the reverse blocking diode and the discharge resistor are connected in series between the connection point and a ground terminal,
The power conversion device according to claim 1 , wherein the reverse blocking diode is disposed in a direction that blocks current flowing from the high potential side terminal toward the ground terminal. The power conversion device according to claim 1 , wherein the surge voltage suppression circuit further includes a clamp capacitor connected between one end of the feedback resistor and a ground terminal. The power conversion device according to claim 1 , wherein the semiconductor switching elements are made of next-generation wide bandgap semiconductors. The power conversion device according to claim 1 , further comprising a control unit that stops operation of the semiconductor switching elements in the inverter when the abnormality detection circuit detects a voltage that exceeds the reference voltage. 5. The power conversion device according to claim 1, further comprising a control unit that limits a torque and a rotation speed of a motor serving as a load of the inverter when the abnormality detection circuit detects a voltage exceeding the reference voltage. the surge voltage suppression circuit includes a plurality of capacitors as the feedback capacitor, and further includes a plurality of balancing resistors connected in parallel with the plurality of capacitors, respectively;
The power conversion device according to claim 2 , wherein the connection point voltage changes in accordance with a change in resistance value of the plurality of balancing resistors. the surge voltage suppression circuit has a high-voltage avalanche diode instead of the feedback capacitor,
The power conversion device according to claim 1 , wherein the connection point voltage is determined based on a ratio between a junction capacitance of the avalanche diode and a junction capacitance of the blocking diode during a turn-on operation of the semiconductor switching element.