JP7800059B2 - Image sensor and image pickup device - Google Patents

Description

The present invention relates to an imaging element and an imaging device.

An image sensor capable of processing signals output from a plurality of pixels in parallel is known (see, for example, Japanese Patent Application Laid-Open No. 2006-121997). Conventionally, an increase in current consumption due to parallel processing of signals from the pixels has been a problem.
[Prior art documents]
[Patent Documents]
[Patent Document 1] International Publication WO2013/129202

In a first aspect of the present invention, an image sensor includes a plurality of conversion units arranged in a row direction and converting analog signals into digital signals; first output lines connected to a plurality of first conversion units among the plurality of conversion units and outputting signals converted into digital signals by the first conversion units; and second output lines connected to a plurality of second conversion units among the plurality of conversion units and outputting signals converted into digital signals by the second conversion units.

A second aspect of the present invention is an imaging device comprising the above-described imaging element.

Note that the above summary of the invention does not list all of the features of the present invention. Subcombinations of these features may also constitute inventions.

FIG. 1 is a diagram showing an overview of an image sensor 400 according to the present embodiment. 2 shows an example of a planar layout of the first semiconductor substrate 100. 2 shows an example of a planar layout of a second semiconductor substrate 200. 2 shows an example of the circuit configuration of the pixel 112 and the pixel circuit 212. FIG. 10 is a schematic diagram illustrating the circuitry for reading out the pixel memory 220. 1 shows an example of a planar layout of a third semiconductor substrate 300. A memory block 312 is shown schematically. FIG. 10 is a schematic diagram illustrating another circuit for reading data from the pixel memory 220 to the memory unit 310. 8A and 8B show an example of the arrangement of pixel circuits 212 and 213 adjacent to each other in the row direction. 10 is a schematic diagram illustrating yet another circuit for reading data from the pixel memory 220 to the memory unit 310. FIG. 10 is a schematic diagram illustrating yet another circuit for reading data from the pixel memory 220 to the memory unit 310. FIG. 10 is a schematic diagram illustrating yet another circuit for reading data from the pixel memory 220 to the memory unit 310. FIG. 10 is a schematic diagram illustrating yet another circuit for reading data from the pixel memory 220 to the memory unit 310. FIG. FIG. 4 is a diagram showing an overview of another image sensor 402. The CDS block 316 is shown schematically. Another CDS block 318 is shown schematically. FIG. 1 is a block diagram illustrating an example of the configuration of an imaging device 500 according to an embodiment.

The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

Figure 1 is a diagram showing an overview of an image sensor 400 according to this embodiment. The image sensor 400 captures an image of a subject. The image sensor 400 generates image data of the captured subject. The image sensor 400 includes a first semiconductor substrate 100, a second semiconductor substrate 200, and a third semiconductor substrate 300. As shown in Figure 1, the first semiconductor substrate 100 is stacked on the second semiconductor substrate 200. The second semiconductor substrate 200 is stacked on the third semiconductor substrate 300.

The first semiconductor substrate 100 has a pixel section 110. The pixel section 110 outputs a pixel signal based on incident light. The first semiconductor substrate 100 is sometimes called a pixel chip.

The second semiconductor substrate 200 has a processing circuit section 210 and a peripheral circuit section 230. The second semiconductor substrate 200 is sometimes referred to as a signal processing chip.

The third semiconductor substrate 300 has a memory section 310 and a peripheral circuit section 320. The third semiconductor substrate 300 is sometimes referred to as a memory chip.

The processing circuit unit 210 receives the pixel signals output from the first semiconductor substrate 100. The processing circuit unit 210 processes the input pixel signals. For example, the processing circuit unit 210 converts analog signals into digital signals. Specifically, the processing circuit unit 210 converts the input pixel signals into digital signals. The processing circuit unit 210 may also perform other signal processing.

In this example, the processing circuit unit 210 is disposed on the second semiconductor substrate 200 at a position facing the pixel unit 110. In other words, the processing circuit unit 210 is disposed so as to at least partially overlap the pixel unit 110 in the optical axis direction. The processing circuit unit 210 may output a control signal to the pixel unit 110 for controlling the driving of the pixel unit 110.

The peripheral circuit unit 230 controls the driving of the processing circuit unit 210. The peripheral circuit unit 230 is arranged around the processing circuit unit 210 on the second semiconductor substrate 200. The peripheral circuit unit 230 may also be electrically connected to the first semiconductor substrate 100 and control the driving of the pixel unit 110.

The memory unit 310 receives and stores pixel signals processed by the processing circuit unit 210 via output lines 302 and 304. In Figure 1, the image sensor 400 is shown in an exploded view, so the output lines 203 and 304 appear long, but because the output lines 302 and 304 are inter-substrate wiring using TSVs or the like, they can be shorter than in-plane wiring.

The peripheral circuit unit 320 performs image processing such as noise removal on the pixel signals stored in the memory unit 310. The structure of the image sensor 400 may be either a back-illuminated type or a front-illuminated type. The following explanation uses a back-illuminated type as an example.

Figure 2 shows an example of the planar layout of the first semiconductor substrate 100. The pixel section 110 is arranged near the center of the surface of the first semiconductor substrate 100.

The pixel unit 110 has a plurality of pixels 112 arranged side by side in the row and column directions. In this example, the pixel unit 110 has M x N pixels 112 (M and N are natural numbers). In this example, the case where M is different from N is illustrated, but M and N may be equal.

Figure 3 shows an example of the planar layout of the second semiconductor substrate 200. The processing circuit unit 210 is arranged near the center of the surface of the second semiconductor substrate 200.

The processing circuit unit 210 has multiple pixel circuits 212 arranged in rows and columns. In this example, the processing circuit unit 210 has M x N pixel circuits 212.

In this embodiment, the pixel circuit 212 and the pixel 112 are arranged in an overlapping position when viewed from the optical axis direction. In this case, the areas of the pixel circuit 212 and the pixel 112 may be approximately the same, including the margin between adjacent blocks.

The pixel circuit 212 controls the driving of the electrically connected pixel 112. The electrical connection between the pixel circuit 212 and the pixel 112 is sometimes referred to as "corresponding."

In this embodiment, pixel circuits 212 and pixels 112 that are arranged in overlapping positions are connected. However, instead of connecting pixel circuits 212 and pixels 112 that are arranged in overlapping positions, pixel circuits 212 and pixels 112 that are arranged in non-overlapping positions may be connected.

A pixel control circuit 250 and a readout control circuit 260, which are examples of the peripheral circuit 230, are arranged around the processing circuit unit 210. The pixel control circuit 250 controls the pixels 112 and pixel circuits 212. The pixel control circuit 250 supplies, for example, a control signal that causes the pixel circuit 212 to AD convert the signal from the pixel 112. The pixel control circuit 250 also controls, for example, the exposure time of the pixel 112. The readout control circuit 260 controls the reading of the pixel signals stored in the pixel circuit 212 to be output to the memory unit 310.

Figure 4 shows an example of the circuit configuration of the pixel 112 and pixel circuit 212. The pixel 112 includes a photoelectric conversion unit 130, a reset unit 132, a storage unit 134, and a transfer unit 136.

The photoelectric conversion unit 130 has a photoelectric conversion function that converts light into electric charges and a storage function that stores the photoelectrically converted electric charges. The photoelectric conversion unit 130 is, for example, a photodiode.

The storage unit 134 converts the charge generated by the photoelectric conversion unit 130 into a voltage corresponding to the amount of charge. The storage unit 134 is an example of a floating diffusion (FD).

The reset unit 132 discharges the charge in the storage unit 134 to a power supply line that supplies a predetermined power supply voltage VDD based on the control signal φRST. The reset unit 132 resets the potential of the storage unit 134 to the predetermined power supply voltage VDD based on the control signal φRST. The gate terminal of the reset unit 132 is connected to the pixel control circuit 250.

The transfer unit 136 transfers the charge accumulated in the photoelectric conversion unit 130 to the storage unit 134 based on the control signal φTX. The transfer unit 136 also discharges the charge accumulated in the photoelectric conversion unit 130 to the power supply wiring that supplies a predetermined power supply voltage VDD based on the control signal φTX. For example, by simultaneously supplying the control signal φTX and the control signal φRST, the transfer unit 136 discharges the charge accumulated in the photoelectric conversion unit 130 to the power supply wiring that supplies a predetermined power supply voltage VDD. The transfer unit 136 is an example of a transfer gate that transfers the charge of the photoelectric conversion unit 130. In other words, the transfer unit 136 serves as the gate, the photoelectric conversion unit 130 serves as the source, and the storage unit 134 serves as the drain, forming a so-called transfer transistor.

The pixel circuit 212 includes a comparator 216, a control circuit 214, and a pixel memory 220. The comparator 216 compares the voltage of the storage unit 134 with a reference voltage RAMP supplied from the pixel control circuit 250, and outputs the comparison result to the control circuit 214. The comparator 216 is configured, for example, as a differential pair. A source follower circuit may also be disposed between the comparator 216 and the storage unit 134, for example. The control circuit 214 controls the pixel memory 220 based on the signal from the comparator 216 and the φCTL signal.

The pixel memory 220 stores pixel signals converted into digital signals. For example, the pixel memory 220 receives a count signal supplied by the pixel control circuit 250, and when the control signal output from the control circuit 214 is inverted, stores the value of the count signal at that time. The pixel memory 220 also outputs the stored pixel signals based on the selection signal φSEL. An example of the pixel memory 220 is an SRAM.

An example of the operation of the pixel 112 and pixel circuit 212 for one frame will be described below. First, at the start of accumulation for one frame, the pixel control circuit 250 simultaneously supplies the control signal φTX and the control signal φRST to reset the charge accumulated in the photoelectric conversion unit 130. Next, during the readout period at the end of one frame, the pixel control circuit 250 supplies the control signal φRST to reset the voltage of the accumulation unit 134 to a predetermined voltage. The pixel control circuit 250 then controls the control signal φCTL, the reference voltage RAMP, and the count signal supplied to the pixel memory 220 to store a value corresponding to the reset voltage of the accumulation unit 134 in the pixel memory 220 (DARK conversion). The readout control circuit 260 then controls the selection signal φSEL to read the DARK conversion result data stored in the pixel memory 220 to the memory unit 310. Data readout from the pixel memory 220 will be described further below. Furthermore, the pixel control circuit 250 supplies a control signal φTX to transfer the charge accumulated in the photoelectric conversion unit 130 to the storage unit 134. After that, the pixel control circuit 250 controls the control signal φCTL, the reference voltage RAMP, and the count signal supplied to the pixel memory 220 to store in the pixel memory 220 a value corresponding to the voltage of the storage unit 134 after the charge transfer (SIG conversion). Finally, the readout control circuit 260 controls the selection signal φSEL to read out the data resulting from the SIG conversion stored in the pixel memory 220 to the memory unit 310.

In this embodiment, one pixel circuit 212 is provided for each pixel 112, and all pixels 112 and pixel circuits 212 are controlled simultaneously. This allows for so-called global shutter operation, in which multiple pixels 112 included in the pixel unit 110 are exposed at the same time. It is also possible to perform an operation in which each pixel 112 is exposed at a different time.

Figure 5 is a schematic diagram illustrating the circuit that reads data from the pixel memory 220 to the memory unit 310. Components that are not explained are omitted from the diagram.

The processing circuit unit 210 is provided with M x N pixel memories 220 corresponding to the M x N pixels 121. If read operations are performed from many pixel memories 220 at once, the current during readout increases. Therefore, in this embodiment, as explained below, the current during readout is reduced by bundling the output lines of pixel signals read out from multiple pixel memories 220 and temporarily storing the read pixel signals in the memory unit 310.

In FIG. 5, six pixel memories 220 arranged in three rows and two columns are commonly connected to an output line 302. Pixel signals read from the pixel memories 220 are output to output line 266. The output line 266 is sometimes called a bit line. More specifically, three pixel memories 220 arranged in three rows and one column are connected to one sub-output line 270, and three pixel memories 220 adjacent to these in the column direction, also arranged in three rows and one column, are connected to another sub-output line 272, and the sub-output line 270 and the sub-output line 272 are connected to the output line 302.

Here, the pixel memory 220 stores a digital signal with a bit count corresponding to the gradation of the image signal, and therefore each pixel 112 has a memory cell corresponding to that bit count. For example, if 8 bits are used to represent the pixel signal of one pixel in 256 monochrome gradations, eight memory cells are used. Therefore, if the output from the pixel memory 220 is not time-shared, at least the same number of output lines 302 as the corresponding bits are used per column of pixel memory 220. In Figure 5 and subsequent figures, lines are shaded, as in the output line 302 in Figure 5, to indicate that multiple lines are represented by a single line.

Furthermore, in the example of Figure 5, the six pixel memories 220 arranged in three rows and two columns connected to output line 302 and the six pixel memories 220 arranged in three rows and two columns adjacent to them in the row direction are commonly connected to output line 304. More specifically, three pixel memories 220 arranged in three rows and one column are connected to one sub-output line 280, and three pixel memories 220 arranged in three rows and one column adjacent to them in the column direction are connected to another sub-output line 282, and the sub-output lines 280 and 282 are connected to output line 304.

With the above configuration, it can be said that the six pixel memories 220 arranged in three rows and two columns are grouped together for readout. For ease of explanation, the grouped multiple pixel memories 220 are sometimes referred to as groups 290 and 291.

Among multiple groups 290, 291, pixel memories 220 at corresponding positions are commonly connected to row selection lines 264, 265 of the readout control circuit 260. A selection signal φSEL, which is an example of a control signal for reading out pixel signals stored in the pixel memories 220, is output to the row selection lines 264, 265. The row selection line 264 is sometimes also called a word selection line.

For each group 290, 291, the pixel memories 220 included in that group are selected one by one by the selection signal φSEL, and the pixel signals of the selected pixel memories 220 are output to the respective output lines 302, 304. In other words, sequential readout occurs within each group 290, 291, and simultaneous readout occurs between groups.

It is preferable that each group 290, 291 includes pixel memories 220 arranged in at least two rows. On the other hand, from the perspective of speeding up readout, it is preferable that the processing circuit unit 210 as a whole be divided into two or more groups in the row direction. Similarly, it is preferable that each group 290, 291 includes pixel memories 220 arranged in at least two columns, but it is also preferable that the processing circuit unit 210 as a whole be divided into two or more groups in the column direction.

Figure 6 shows an example of a planar layout of the third semiconductor substrate 300. The memory section 310 is arranged near the center of the surface of the third semiconductor substrate 300.

The memory unit 310 has multiple memory blocks 312 arranged side by side in the row and column directions. The number of memory blocks 312 may be the same as the number of groups of pixel memories 220 included in the processing circuit unit 210. For example, if the pixel memories 220 are grouped into p rows and q columns, the memory unit 310 may have (M/p) x (N/q) memory blocks 312. Note that the electrical connection between a memory block 312 and a group 290 via an output line 302 is sometimes referred to as "corresponding."

In this embodiment, the memory block 312 and the corresponding group 290 of pixel memory 220 are arranged in an overlapping position when viewed from the optical axis direction. In this case, the areas of the memory block 312 and the group 290 may be approximately the same, including the margin between adjacent blocks. However, the number and arrangement of the memory blocks 312 are not limited to the example in Figure 6.

A peripheral circuit unit 320 is arranged around the memory unit 310. The peripheral circuit unit 320 includes a CDS circuit 322. The CDS circuit 322 is an example of a noise removal unit that performs CDS (correlated double sampling) by, for example, subtracting the result of the DARK conversion from the result of the SIG conversion for each pixel.

Figure 7 shows a schematic diagram of the memory block 312. The memory block 312 has memory pairs 350 for k pixels for one output line 302. Each memory pair 350 has a DARK memory 352 that stores the results of DARK conversion for one pixel, and a SIG memory 354 that stores the results of SIG conversion. The DARK memory 352 and the SIG memory 354 may each be SRAM.

Therefore, one memory block 312 has 2k memories corresponding to the k pixels included in one corresponding group 290. If a group 290 has pixel memories 220 corresponding to six pixels as shown in Figure 5, then the memory block 312 has 2 x 6 = 12 memories. However, more than 2k memories may be provided.

As explained in Figure 5, pixel signals resulting from DARK conversion are sequentially read out from multiple pixel memories 220 within group 290 to output line 302, and each pixel signal is stored in each DARK memory 352. Next, pixel signals resulting from SIG conversion are sequentially read out from multiple pixel memories 220 within group 290 to output line 302, and each pixel signal is stored in each SIG memory 354. After that, the results of DARK conversion and SIG conversion stored for each memory pair 350 corresponding to each pixel are read out to CDS circuit 322 and subjected to noise removal processing.

In addition, in this embodiment, a memory block 312 is provided downstream of the pixel memory 220, which acts as a latch that temporarily stores the pixel signal converted to a digital signal by the comparator 216. This shortens the period that must be read out quickly, reducing the current that flows during readout.

Figure 8 is a schematic diagram illustrating another circuit that reads data from pixel memory 220 to memory unit 310. Components that are the same as those in Figures 1 to 7 are given the same reference numbers and will not be described again. Also, Figure 8 illustrates one group 292.

In Figure 8, six pixel memories 220 arranged in three rows and two columns are commonly connected to an output line 302. However, unlike Figure 5, adjacent pixel memories 220 in the row direction are directly connected to the common output line 302. This allows the number of output wirings to be further reduced.

Figure 9 shows a schematic example of the arrangement of pixel circuits 212 and 213 adjacent to each other in the row direction of Figure 8. In Figure 9, at least a portion of the arrangement of one pixel circuit 212 and the other pixel circuit 213 is line-symmetrical with respect to the output line 302. In the example of Figure 9, the arrangement of the comparator 216, control circuit 214, and pixel memory 220 is line-symmetrical. The arrangement of the elements of each circuit may also be line-symmetrical. Furthermore, the arrangement may be line-symmetrical, even including the pixel 112.

Figure 10 is a schematic diagram illustrating yet another circuit that reads data from pixel memory 220 to memory unit 310. Components that are the same as those in Figures 1 to 9 are given the same reference numbers and will not be described again. Also, Figure 10 illustrates one group 293.

In FIG. 10, three pixel memories 220 arranged in three rows and one column are connected to one sub-output line 270, and three pixel memories 220 adjacent to these in the column direction, also arranged in three rows and one column, are connected to another sub-output line 272. One of the two sub-output lines 270, 272 is connected to output line 302 via a switching unit 274.

The switching unit 274 is operated in conjunction with the selection signal φSEL. When a pixel signal is output to the sub-output line 270, the switching unit 274 connects the sub-output line 270 to the output line 302. On the other hand, when a pixel signal is output to the sub-output line 272, the switching unit 274 connects the sub-output line 272 to the output line 302. This allows for further reduction in wiring capacitance.

Figure 11 is a schematic diagram illustrating yet another circuit that reads data from pixel memory 220 to memory unit 310. Components that are the same as those in Figures 1 to 10 are given the same reference numbers and will not be described again. Also, Figure 11 illustrates one group 294.

Group 294 in Figure 11 is a combination of group 292 in Figure 8 and group 293 in Figure 10. First, six pixel memories 220 arranged in three rows and two columns are directly connected to sub-output line 270, and another six pixel memories 220 arranged in three rows and two columns are directly connected to sub-output line 272. One of the two sub-output lines 270, 272 is connected to output line 302 via switching unit 274. This allows for further reduction in wiring capacitance.

Figure 12 is a schematic diagram illustrating yet another circuit that reads data from pixel memory 220 to memory unit 310. Components that are the same as those in Figures 1 to 11 are given the same reference numbers and descriptions will be omitted. Also, one group 295 is illustrated in Figure 12.

Group 295 corresponds to group 293 in Figure 10 in which the row selection line 265 is omitted. Within each group 295, the output from the pixel memory 220 in the row direction can essentially be switched by the switching unit 274, so sequential readout within group 293 is possible even if the number of row selection lines selecting the row direction is omitted.

Figure 13 is a schematic diagram illustrating yet another circuit that reads data from pixel memory 220 to memory unit 310. Components that are the same as those in Figures 1 to 12 are given the same reference numbers and will not be described again. Also, Figure 13 illustrates one group 296.

Group 296 corresponds to group 294 in Figure 11 in which the row selection line 265 is omitted. Within each group 295, the output from the pixel memory 220 in the row direction can essentially be switched by the switching unit 274, so sequential readout within group 295 is possible even if the number of row selection lines for selecting the row direction is omitted.

Figure 14 is a diagram showing an overview of another image sensor 402. In the image sensor 402, the same components as those in the image sensor 400 are assigned the same reference numerals and their descriptions are omitted.

The image sensor 402 differs from the image sensor 400 in that it has a CDS section 314 and an output section 326 instead of the memory section 310 and peripheral circuit section 320 on the third semiconductor substrate 300. The CDS section 314 has multiple CDS blocks 316. The number, arrangement, and connection relationship of the CDS blocks 316 to the pixel memory 220 may be the same as those of the memory block 312 of the image sensor 400. The output section 326 reads out the pixel signals stored in the CDS section 314.

Figure 15 shows a schematic diagram of the CDS block 316. The CDS block 316 includes a Gray code-to-binary conversion circuit 360, a CDS circuit 362, and multiple dual-purpose memories 364.

The Gray code to binary conversion circuit 360 converts the pixel signal output to the output line 302 from Gray code to binary and outputs the converted signal to the CDS circuit 362. The CDS circuit 362 has the same functions as the CDS circuit 322 described above, except where otherwise noted.

Each of the multiple dual-purpose memories 364 is selectively connected to signal line 367 via switch 366 and selectively connected to signal line 369 via switch 368. It is preferable that the number of dual-purpose memories 364 is k+1, which is the number of pixels in the corresponding pixel memory 220 group. For example, in the example of Figure 5, if group 290 includes pixel memories 600 for six pixels, it is preferable that CDS block 316 includes dual-purpose memories 364 for seven pixels. However, the number of dual-purpose memories 364 may be greater than that. Each dual-purpose memory 364 may be an SRAM. For ease of explanation, the dual-purpose memories are numbered (0) to (k) to distinguish them.

In the CDS block 316, the results of the DARK conversion are first output sequentially from the corresponding multiple pixel memories 220, and then converted from Gray code to binary by the Gray code-to-binary conversion circuit 360. The φBYPS signal is then sent to the CDS circuit to bypass this circuit, and the DARK conversion results after the Gray code-to-binary conversion are stored directly in the dual-purpose memory. In this case, by sequentially turning on and off the switches 368 for dual-purpose memories (1) to (k), the results of the DARK conversion are stored for each of the first through kth pixels output to the signal line 369.

Next, the results of the SIG conversion are output sequentially from the corresponding multiple pixel memories 220 and are converted from Gray code to binary by the Gray code-to-binary conversion circuit 360. Here, when the result of the SIG conversion for the jth pixel (j is an integer from 1 to k) is converted from Gray code to binary, the result of the DARK conversion stored in the dual-purpose memory (j) is output to signal line 367 by turning on switch 366 and input to the CDS circuit 362, and the result of the SIG conversion is also input to the CDS circuit 362. This causes CDS processing to be performed by the CDS circuit 362, and the switch 368 of the dual-purpose memory (j-1) is turned on to store the result. This is repeated for j = 1 to k.

In addition, the dual-purpose memory (j) is a memory that stores the results of the jth DARK conversion, and also stores the results of the (j+1)th CDS processing. In this embodiment, multiple dual-purpose memories 364 are provided downstream of the pixel memory 220, which acts as a latch that temporarily stores the pixel signal converted to a digital signal by the comparator 216. This shortens the period that must be read out quickly, making it possible to reduce the current that flows during readout.

Figure 16 shows a schematic diagram of another CDS block 318. In CDS block 318, the same components as those in CDS block 316 in Figure 15 are given the same reference numbers and will not be described again.

The CDS block 318 has k multipurpose memories 364 and one buffer memory 370. The buffer memory 370 may be an SRAM, and there may be two or more of them.

In the CDS block 318, the results of the DARK conversion are first output sequentially from the corresponding pixel memories 220, and then converted from Gray code to binary by the Gray code-to-binary conversion circuit 360. Furthermore, the φBYPS signal is sent to the CDS circuit to bypass this circuit, and the DARK conversion results after the Gray code-to-binary conversion are stored as is in dual-purpose memories (0) to (k-1) sequentially.

Next, the results of the SIG conversion are output sequentially from the corresponding multiple pixel memories 220 and are converted from Gray code to binary by the Gray code-to-binary conversion circuit 360. Here, when the SIG conversion result of the jth pixel (j is an integer from 1 to k) is converted from Gray code to binary, the DARK conversion result stored in the dual-purpose memory (j-1) is buffered in the buffer memory 370 via signal line 367 by turning on switch 366. The DARK conversion result in the buffer memory 370 and the jth SIG conversion result output from the Gray code-to-binary conversion circuit 360 are input to the CDS circuit 362. This causes CDS processing to be performed by the CDS circuit 362, and the result is stored by turning on switch 368 of the dual-purpose memory (j-1), which has already been emptied.

In addition, the dual-purpose memory (j) is a memory that stores the results of the jth DARK conversion and also stores the results of the jth CDS processing. The buffer memory 370 is a buffer used exclusively for k pixels. In this embodiment, in addition to the pixel memory 220, which acts as a latch that temporarily stores the pixel signals converted to digital signals by the comparator 216, multiple dual-purpose memories 364 and at least one buffer memory 370 are provided downstream. This shortens the period that must be read out quickly, making it possible to reduce the current that flows during readout.

As described above, according to this embodiment, the current that flows during readout can be reduced. In the above embodiment, one control circuit 214 is provided for one pixel 112. Alternatively, one control circuit 214 may be provided for multiple pixels 112. In this case, if the multiple pixels 112 corresponding to one control circuit 214 are called a pixel block, the pixels 112 included in one pixel block are arranged in m rows and n columns (m is a natural number that is 2 or greater and less than M, and n is a natural number that is 2 or greater and less than N), and multiple pixel blocks may be arranged in the row and column directions.

All of the above embodiments have a three-layer structure having a first semiconductor substrate 100, a second semiconductor substrate 300, and a third semiconductor substrate 300. Alternatively, the second semiconductor substrate 200 may be provided with the configuration and functions of the third semiconductor substrate of the above embodiments. In other words, the processing circuit unit 210, etc. and the memory unit 310, etc. (or the CDS unit 314) may be provided on the same semiconductor substrate while maintaining at least one of the wiring structures shown in Figures 5 to 13, 15, and 16.

Figure 17 is a block diagram showing an example configuration of an imaging device 500 according to an embodiment. The imaging device 500 includes an imaging element 400, a system control unit 501, a drive unit 502, a photometry unit 503, a work memory 504, a recording unit 505, a display unit 506, a drive unit 514, and a photographing lens 520. An imaging element 402 may be used instead of the imaging element 400.

The taking lens 520 guides the subject light beam incident along the optical axis OA to the image sensor 400. The taking lens 520 is composed of a group of multiple optical lenses, and focuses the subject light beam from the scene near its focal plane. The taking lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. Note that in Figure 17, the taking lens 520 is represented by a single virtual lens placed near the pupil.

The driver 514 drives the photographing lens 520. In one example, the driver 514 moves the optical lens group of the photographing lens 520 to change the focus position. The driver 514 may also drive an iris diaphragm within the photographing lens 520 to control the amount of subject light entering the image sensor 400.

The drive unit 502 has a control circuit that performs charge accumulation control such as timing control and area control of the image sensor 400 in accordance with instructions from the system control unit 501. The operation unit 508 also accepts instructions from the photographer using a release button, etc.

The image sensor 400 passes pixel signals to the image processing unit 511 of the system control unit 501. The image processing unit 511 generates image data by performing various image processes using the work memory 504 as a workspace. For example, when generating image data in JPEG file format, a color video signal is generated from the signal obtained using the Bayer array, and then compression processing is performed. The generated image data is recorded in the recording unit 505 and converted into a display signal, which is displayed on the display unit 506 for a preset time.

The photometry unit 503 detects the luminance distribution of the scene prior to a series of shooting sequences that generate image data. The photometry unit 503 includes, for example, an AE sensor with approximately 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance for each region of the scene.

The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. The image sensor 400 may also serve as the photometry unit 503. The calculation unit 512 also performs various calculations to operate the image capture device 500. Part or all of the drive unit 502 may be mounted on the image sensor 400. Part of the system control unit 501 may be mounted on the image sensor 400.

The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

The order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," or the like, and it should be noted that processes can be performed in any order, unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that it is necessary to perform the processes in that order.

100 First semiconductor substrate, 110 Pixel section, 112 Pixel, 130 Photoelectric conversion section, 132 Reset section, 134 Storage section, 136 Transfer section, 200 Second semiconductor substrate, 210 Processing circuit section, 212, 213 Pixel circuit, 214 Control circuit, 216 Comparator, 220 Pixel memory, 230 Peripheral circuit section, 250 Pixel control circuit, 260 Readout control circuit, 264, 265 Row selection line, 270, 272, 280, 282 Sub-output line, 274 Switching section, 290, 291, 292 Group, 302, 304 Output line, 310 Memory section, 312 Memory block, 314 CDS section, 316, 318 CDS block, 320 Peripheral circuit section, 322, 362 CDS circuit, 326 Output section, 350: Memory pair, 352: DARK memory, 354: SIG memory, 360: Gray code/binary conversion circuit, 364: Dual-purpose memory, 366, 368: Switch, 367, 369: Signal line, 370: Buffer memory, 400, 402: Image sensor, 500: Image capture device, 501: System control section, 502: Drive section, 503: Photometric section, 504: Work memory, 505: Recording section, 506: Display section, 508: Operation section, 511: Image processing section, 512: Calculation section, 514: Drive section, 520: Photographing lens

Claims (59)

a first semiconductor substrate having a pixel unit including a first photoelectric conversion unit that converts light into electric charges, a second photoelectric conversion unit that converts light into electric charges and is arranged alongside the first photoelectric conversion unit in a first direction, and a third photoelectric conversion unit that converts light into electric charges and is arranged alongside the first photoelectric conversion unit in a second direction that intersects with the first direction;
a second semiconductor substrate having a first circuit unit, the second semiconductor substrate being a semiconductor substrate laminated together with the first semiconductor substrate, the first circuit unit including a first storage unit that stores a first digital signal obtained by converting a first signal based on charges converted by the first photoelectric conversion unit into a digital signal, a second storage unit that stores a second digital signal obtained by converting a second signal based on charges converted by the second photoelectric conversion unit into a digital signal, and a third storage unit that stores a third digital signal obtained by converting a third signal based on charges converted by the third photoelectric conversion unit into a digital signal;
a third semiconductor substrate that is stacked together with the first semiconductor substrate, the third semiconductor substrate including a fourth memory unit that stores the first digital signal read from the first memory unit, a fifth memory unit that stores the second digital signal read from the second memory unit, and a sixth memory unit that stores the third digital signal read from the third memory unit, and the third semiconductor substrate has a second circuit unit that is disposed at a position facing the first circuit unit in a third direction in which the first semiconductor substrate and the second semiconductor substrate are stacked;
a first connection portion that electrically connects the first storage portion and the fourth storage portion, the first connection portion being disposed between the first circuit portion and the second circuit portion in the third direction, and through which the first digital signal read out from the first storage portion is output;
a second connection portion that electrically connects the second storage portion and the fifth storage portion, the second connection portion being disposed between the first circuit portion and the second circuit portion in the third direction, and through which the second digital signal read from the second storage portion is output;
an imaging element comprising: a connection portion that electrically connects the third memory portion and the sixth memory portion, the third connection portion being arranged between the first circuit portion and the second circuit portion in the third direction, and through which the third digital signal read out from the third memory portion is output . 2. The imaging device according to claim 1,
the fourth storage unit is disposed at a position facing the first storage unit in the third direction,
the fifth storage unit is disposed at a position facing the second storage unit in the third direction,
the sixth storage unit is disposed at a position facing the third storage unit in the third direction;
Image sensor. 3. The imaging device according to claim 2,
the first connection portion is disposed between the first storage portion and the fourth storage portion in the third direction;
the second connection portion is disposed between the second storage portion and the fifth storage portion in the third direction;
the third connection portion is disposed between the third memory portion and the sixth memory portion in the third direction;
Image sensor. 4. The imaging device according to claim 1,
the first connection unit has a first output line through which the first digital signal read from the first storage unit is output;
the second connection unit has a second output line through which the second digital signal read from the second storage unit is output,
the third connection unit has a third output line through which the third digital signal read from the third storage unit is output;
Image sensor. 5. The imaging device according to claim 4,
the first connection unit has a first switch for electrically connecting or disconnecting the first storage unit and the first output line;
the second connection unit has a second switch for electrically connecting or disconnecting the second storage unit and the second output line;
the third connection unit has a third switch for electrically connecting or disconnecting the third storage unit and the third output line;
Image sensor. 6. The imaging device according to claim 1,
the first connection unit has a first through electrode through which the first digital signal read from the first storage unit is output;
the second connection unit has a second through electrode through which the first digital signal read from the second storage unit is output,
the third connection unit has a third through electrode through which the third digital signal read from the third storage unit is output.
Image sensor. 7. The imaging device according to claim 1,
the third semiconductor substrate has a signal processing unit that performs signal processing on at least the first digital signal read from the fourth storage unit, of the first digital signal read from the fourth storage unit, the second digital signal read from the fifth storage unit, and the third digital signal read from the sixth storage unit;
Image sensor. 8. The imaging device according to claim 7,
the signal processing unit performs, as the signal processing, processing for removing noise contained in the first digital signal read from the fourth storage unit.
Image sensor. 9. The imaging device according to claim 7,
the signal processing unit performs correlated double sampling on the first digital signal read from the fourth storage unit as the signal processing.
Image sensor. 7. The imaging device according to claim 1,
the fourth storage unit includes a first storage circuit that stores the first digital signal read from the first storage unit, and a second storage circuit that stores a fourth digital signal that is read from the first storage unit and is used to perform signal processing on the first digital signal.
Image sensor. The imaging device according to claim 10,
the third semiconductor substrate has a signal processing unit that performs signal processing on the first digital signal read out from the first storage circuit by using the fourth digital signal read out from the second storage circuit;
Image sensor. The imaging device according to claim 11,
the signal processing unit performs, as the signal processing, a process for removing noise contained in the first digital signal read out from the first storage circuit, using the fourth digital signal read out from the second storage circuit.
Image sensor. 13. The imaging device according to claim 11,
the signal processing unit performs correlated double sampling on the first digital signal read out from the first storage circuit using the fourth digital signal read out from the second storage circuit, as the signal processing.
Image sensor. The imaging device according to any one of claims 1 to 13,
the first circuit unit includes a first conversion unit for converting the first signal into a digital signal, a second conversion unit for converting the second signal into a digital signal, and a third conversion unit for converting the third signal into a digital signal;
the first storage unit stores the first digital signal converted from the first signal into a digital signal by the first conversion unit;
the second storage unit stores the second digital signal converted from the second signal into a digital signal by the second conversion unit;
the third storage unit stores the third digital signal converted from the third signal into a digital signal by the third conversion unit;
Image sensor. The imaging device according to any one of claims 1 to 14,
the second photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the first direction,
the third photoelectric conversion unit is disposed adjacent to the first photoelectric conversion unit in the second direction.
Image sensor. 4. The imaging device according to claim 1,
the pixel unit includes a fourth photoelectric conversion unit that converts light into electric charges and is disposed adjacent to the first photoelectric conversion unit in the first direction;
the first storage unit includes a first storage circuit that stores a first digital signal obtained by converting a first signal based on the charge converted by the first photoelectric conversion unit into a digital signal, and a second storage circuit that stores a fourth digital signal obtained by converting a fourth signal based on the charge converted by the fourth photoelectric conversion unit into a digital signal,
the fourth storage unit includes a third storage circuit that stores the first digital signal read from the first storage circuit, and a fourth storage circuit that stores the fourth digital signal read from the second storage circuit;
the first connection section outputs the first digital signal read from the first storage circuit and the fourth digital signal read from the second storage circuit;
Image sensor. 17. The imaging device according to claim 16,
the first connection unit has a first output line through which the first digital signal read from the first storage circuit and the fourth digital signal read from the second storage circuit are output;
Image sensor. 18. The imaging device according to claim 17,
the first connection unit has a first switch for electrically connecting or disconnecting the first memory circuit and the first output line;
Image sensor. 19. The imaging device according to claim 18,
the first connection unit has a second switch for electrically connecting or disconnecting the second memory circuit and the first output line;
Image sensor. 20. The imaging device according to claim 16,
the first connection portion has a first through electrode through which the first digital signal read from the first memory circuit and the fourth digital signal read from the second memory circuit are output;
Image sensor. 21. The imaging device according to claim 16,
the third semiconductor substrate has a signal processing unit that performs signal processing on at least the first digital signal read out from the third storage circuit, of the first digital signal read out from the third storage circuit and the fourth digital signal read out from the fourth storage circuit;
Image sensor. 22. The imaging device according to claim 21,
the signal processing unit performs, as the signal processing, processing for removing noise contained in the first digital signal read out from the third storage circuit.
Image sensor. 23. The imaging device according to claim 21 or 22,
the signal processing unit performs correlated double sampling on the first digital signal read from the third storage circuit as the signal processing.
Image sensor. 21. The imaging device according to claim 16,
the fourth storage unit includes a fifth storage circuit that stores a fifth digital signal that is a digital signal read from the first storage circuit and is used to perform signal processing on the first digital signal, and a sixth storage circuit that stores a sixth digital signal that is a digital signal read from the second storage circuit and is used to perform signal processing on the fourth digital signal;
Image sensor. 25. The imaging device according to claim 24,
the third semiconductor substrate has a signal processing unit that performs first signal processing on the first digital signal read from the third storage circuit using the fifth digital signal read from the fifth storage circuit, and that performs second signal processing on the fourth digital signal read from the fourth storage circuit using the sixth digital signal read from the sixth storage circuit;
Image sensor. 26. The imaging device according to claim 25,
the signal processing unit performs, as the first signal processing, a process for removing noise contained in the first digital signal read from the third storage circuit, using the fifth digital signal read from the fifth storage circuit, and performs, as the second signal processing, a process for removing noise contained in the fourth digital signal read from the fourth storage circuit, using the sixth digital signal read from the sixth storage circuit.
Image sensor. 27. The imaging device according to claim 25 or 26,
the signal processing unit performs, as the first signal processing, a correlated double sampling process on the first digital signal read from the third storage circuit using the fifth digital signal read from the fifth storage circuit, and performs, as the second signal processing, a correlated double sampling process on the fourth digital signal read from the fourth storage circuit using the sixth digital signal read from the sixth storage circuit.
Image sensor. 28. The imaging device according to claim 16,
the first circuit unit includes a first conversion unit for converting the first signal into a digital signal, a second conversion unit for converting the second signal into a digital signal, a third conversion unit for converting the third signal into a digital signal, and a fourth conversion unit for converting the fourth signal into a digital signal;
the first storage unit stores the first digital signal converted from the first signal into a digital signal using the first conversion unit and the fourth digital signal converted from the fourth signal into a digital signal using the fourth conversion unit;
the second storage unit stores the second digital signal converted from the second signal into a digital signal by the second conversion unit;
the third storage unit stores the third digital signal converted from the third signal into a digital signal by the third conversion unit;
Image sensor. 17. The imaging device according to claim 16,
the pixel unit includes a fifth photoelectric conversion unit that converts light into electric charges and is disposed adjacent to the first photoelectric conversion unit in the second direction;
the first storage unit includes a third storage circuit configured to store a fifth digital signal obtained by converting a fifth signal based on the electric charge converted by the fifth photoelectric conversion unit into a digital signal;
the fourth storage unit includes a fourth storage circuit that stores the first digital signal read from the first storage circuit, a fifth storage circuit that stores the fourth digital signal read from the second storage circuit, and a sixth storage circuit that stores the fifth digital signal read from the third storage circuit;
the first connection section outputs the first digital signal read from the first storage circuit, the fourth digital signal read from the second storage circuit, and the fifth digital signal read from the third storage circuit;
Image sensor. 30. The imaging device according to claim 29,
the first connection unit has a first output line through which the first digital signal read from the first storage circuit, the fourth digital signal read from the second storage circuit, and the fifth digital signal read from the third storage circuit are output;
Image sensor. 31. The imaging device according to claim 30,
the first connection unit has a first switch for electrically connecting or disconnecting the first memory circuit and the first output line;
Image sensor. 32. The imaging device according to claim 31,
the first switch is used to electrically connect or disconnect the third memory circuit and the first output line;
Image sensor. 33. The imaging device according to claim 31 or 32,
the first connection unit has a second switch for electrically connecting or disconnecting the second memory circuit and the first output line;
Image sensor. 31. The imaging device according to claim 30,
the first connection unit includes a first wiring electrically connected to the first output line, through which the first digital signal read from the first memory circuit and the fifth digital signal read from the third memory circuit are output, and a second wiring electrically connected to the first output line, through which the fourth digital signal read from the second memory circuit is output.
Image sensor. 35. The imaging device according to claim 34,
the first connection unit has a first switch for electrically connecting or disconnecting the first wiring and the first output line;
Image sensor. 36. The imaging device according to claim 35,
the first connection unit has a second switch for electrically connecting or disconnecting the second wiring and the first output line;
Image sensor. 37. The imaging device according to claim 29,
the first connection portion has a first through electrode through which the first digital signal read from the first memory circuit, the fourth digital signal read from the second memory circuit, and the fifth digital signal read from the third memory circuit are output;
Image sensor. 38. The imaging device according to claim 29,
the third semiconductor substrate has a signal processing unit that performs signal processing on at least the first digital signal read out from the fourth storage circuit, out of the first digital signal read out from the fourth storage circuit, the fourth digital signal read out from the fifth storage circuit, and the fifth digital signal read out from the sixth storage circuit;
Image sensor. 39. The imaging device according to claim 38,
the signal processing unit performs, as the signal processing, processing for removing noise contained in the first digital signal read out from the fourth storage circuit.
Image sensor. 40. The imaging device according to claim 38 or 39,
the signal processing unit performs correlated double sampling on the first digital signal read from the fourth storage circuit as the signal processing.
Image sensor. 38. The imaging device according to claim 29,
the fourth storage unit has a seventh storage circuit that stores a sixth digital signal that is a digital signal read from the first storage circuit and is used to perform signal processing on the first digital signal, an eighth storage circuit that stores a seventh digital signal that is a digital signal read from the second storage circuit and is used to perform signal processing on the fourth digital signal, and a ninth storage circuit that stores an eighth digital signal that is a digital signal read from the third storage circuit and is used to perform signal processing on the fifth digital signal.
Image sensor. 42. The imaging device according to claim 41,
the third semiconductor substrate has a signal processing unit that performs first signal processing on the first digital signal read out from the fourth storage circuit by using the sixth digital signal read out from the seventh storage circuit;
Image sensor. 43. The imaging device according to claim 42,
the signal processing unit performs, as the first signal processing, processing for removing noise contained in the first digital signal read out from the fourth storage circuit, using the sixth digital signal read out from the seventh storage circuit.
Image sensor. 44. The imaging device according to claim 43,
the signal processing unit performs, as the first signal processing, a correlated double sampling process on the first digital signal read out from the fourth storage circuit, using the sixth digital signal read out from the seventh storage circuit.
Image sensor. 45. The imaging device according to claim 42,
the signal processing unit performs second signal processing on the fourth digital signal read out from the fifth storage circuit using the seventh digital signal read out from the eighth storage circuit.
Image sensor. 46. The imaging device according to claim 45,
the signal processing unit performs, as the second signal processing, a process for removing noise contained in the fourth digital signal read out from the fifth storage circuit, using the seventh digital signal read out from the eighth storage circuit.
Image sensor. 47. The imaging device according to claim 46,
the signal processing unit performs, as the second signal processing, a correlated double sampling process on the fourth digital signal read out from the fifth storage circuit, using the seventh digital signal read out from the eighth storage circuit.
Image sensor. 48. The imaging device according to claim 45,
the signal processing unit performs third signal processing on the fifth digital signal read out from the sixth storage circuit using the eighth digital signal read out from the ninth storage circuit.
Image sensor. 49. The imaging device according to claim 48,
the signal processing unit performs, as the third signal processing, a process for removing noise contained in the fifth digital signal read out from the sixth storage circuit, using the eighth digital signal read out from the ninth storage circuit.
Image sensor. 50. The imaging device according to claim 49,
the signal processing unit performs, as the third signal processing, a correlated double sampling process on the fifth digital signal read out from the sixth storage circuit, using the eighth digital signal read out from the ninth storage circuit.
Image sensor. 51. The imaging device according to claim 29,
the first circuit unit includes a first conversion unit for converting the first signal into a digital signal, a second conversion unit for converting the second signal into a digital signal, a third conversion unit for converting the third signal into a digital signal, a fourth conversion unit for converting the fourth signal into a digital signal, and a fifth conversion unit for converting the fifth signal into a digital signal;
the first storage unit stores the first digital signal converted from the first signal into a digital signal using the first conversion unit, the fourth digital signal converted from the fourth signal into a digital signal using the fourth conversion unit, and the fifth digital signal converted from the fifth signal into a digital signal using the fifth conversion unit;
the second storage unit stores the second digital signal converted from the second signal into a digital signal by the second conversion unit;
the third storage unit stores the third digital signal converted from the third signal into a digital signal by the third conversion unit;
Image sensor. 52. The imaging device according to claim 1,
the second storage unit is disposed alongside the first storage unit in the first direction;
the third storage unit is disposed alongside the first storage unit in the second direction;
Image sensor. 53. The imaging device according to claim 1,
the fifth storage unit is disposed alongside the fourth storage unit in the first direction,
the sixth storage unit is disposed alongside the fifth storage unit in the second direction;
Image sensor. 54. The imaging device according to claim 1,
the first circuit unit is disposed at a position facing the pixel unit in the third direction;
Image sensor. An imaging device comprising the imaging element according to any one of claims 1 to 54. 56. The imaging device of claim 55,
an imaging device comprising a generation unit electrically connected to the imaging element and configured to generate image data; 57. The imaging device according to claim 55 or 56,
An imaging device comprising a driving unit for driving an optical system that emits light to the imaging element. 58. The imaging device of claim 57,
An imaging device comprising a mounting portion to which the optical system can be detachably attached. An imaging device comprising the optical system according to claim 57 or 58.