JP7800838B2 - Semiconductor device and standby current reduction method - Google Patents

Description

The present invention relates to a semiconductor device and a method for reducing standby current.

In semiconductor devices, multiple capacitance elements are connected between the power supply line and ground to smooth out power supply noise and suppress fluctuations in the power supply voltage. Such capacitance elements are sometimes called smoothing capacitances.

Japanese Patent Application Publication No. 11-233719 Japanese Patent Application Laid-Open No. 2017-195306 Japanese Patent Application Laid-Open No. 2003-017569

If there is a capacitor element with a large leakage current among the multiple capacitor elements used as smoothing capacitance, that capacitor element could increase the standby current of the semiconductor device, potentially resulting in the product being judged as defective during testing before shipment.

In one aspect, the present invention aims to provide a semiconductor device and a method for reducing standby current that can reduce standby current.

In one embodiment, there is provided a semiconductor device in which, after power is turned on, standby state periods including a standby period and operating periods are repeated, the semiconductor device comprising: a switch circuit that switches whether or not a first power supply potential is applied to a first power supply line in accordance with a first control signal; a plurality of smoothing capacitance circuits each including a first capacitance element connected between the first power supply line and a second power supply line having a second power supply potential lower than the first power supply potential; and a first detection circuit that detects a first leakage current in the first capacitance element each time the semiconductor device enters the standby state ; a memory circuit that stores a first detection result of the first detection circuit; and a smoothing capacitance setting circuit that, each time the semiconductor device enters the standby state, supplies the first control signal to the first smoothing capacitance circuit, based on the first detection result stored in the memory circuit, to stop application of the first power supply potential to the first power supply line of a first smoothing capacitance circuit in which the first leakage current is detected, among the plurality of smoothing capacitance circuits.

Also, in one embodiment, a method for reducing standby current is provided.

In one aspect, the present invention can reduce the standby current of a semiconductor device.

1 is a diagram illustrating an example of a semiconductor device according to a first embodiment; FIG. 1 is a diagram illustrating a circuit configuration of an example of a leakage current detection circuit. 10 is a timing chart showing an example of the operation of a semiconductor device when a leakage current occurs; 10 is a timing chart showing an example of the operation of the semiconductor device when no leakage current occurs; FIG. 1 is a diagram illustrating a semiconductor device according to a first comparative example. FIG. 10 is a diagram illustrating a semiconductor device according to a second comparative example. FIG. 10 illustrates an example of a semiconductor device according to a second embodiment; FIG. 2 is a diagram illustrating an example of a smoothing capacitance setting circuit. 10 is a timing chart showing an example of the operation of a semiconductor device when a leakage current occurs; 10 is a timing chart showing an example of the operation of the semiconductor device when no leakage current occurs; 10 is a timing chart showing an example of setting a control signal for a smoothing capacitance circuit in which a leak current is detected. 10 is a timing chart showing an example of setting a control signal for a smoothing capacitance circuit in which no leakage current is detected; FIG. 10 illustrates an example of a semiconductor device according to a third embodiment. FIG. 10 is a diagram illustrating an example of setting a control signal supplied to a smoothing capacitance circuit. FIG. 10 is a diagram illustrating an example of a smoothing capacitance setting circuit in the semiconductor device according to the third embodiment. 15 is a timing chart showing an example of the operation of the semiconductor device in Case 1 in which the leakage current of FIG. 14 is detected. 15 is a timing chart showing an example of the operation of the semiconductor device in Case 2 in which the leakage current of FIG. 14 is detected. FIG. 1 is a diagram illustrating a circuit configuration of an example of a leakage current detection circuit. FIG. 10 is a diagram illustrating a modified example of a smoothing capacitance circuit.

Hereinafter, embodiments of the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a semiconductor device according to a first embodiment.

The semiconductor device 10a of the first embodiment is, for example, a one-chip semiconductor integrated circuit, and includes multiple smoothing capacitance circuits 11a1, 11a2, ..., 11aN, a memory circuit 12, and a smoothing capacitance setting circuit 13. Other internal circuits of the semiconductor device 10a are not shown in the illustration.

Smoothing capacitance circuits 11a1 to 11aN are provided on the periphery of semiconductor device 10a and smooth power supply noise to suppress fluctuations in the power supply voltage. Figure 1 shows an example of smoothing capacitance circuit 11a1. The other smoothing capacitance circuits 11a2 to 11aN have the same circuit configuration as smoothing capacitance circuit 11a1.

The smoothing capacitance circuit 11 a 1 includes a switch circuit 15 , capacitance elements (four capacitance elements 16 a , 16 b , 16 c , and 16 d in the example of FIG. 1 ), and a leakage current detection circuit 17 .
The switch circuit 15 switches whether or not the power supply potential VDD2 is applied to the power supply line 18 in response to control signals SETP<1> and SETN<1>. The power supply potential VDD2 is, for example, a potential obtained by lowering the power supply potential VDD1, which is an external power supply potential. For example, VDD1=3.3V, and VDD2=1.8V. However, if the withstand voltage of the capacitance elements 16a to 16d is higher than the power supply potential VDD1, the smoothing capacitance circuit 11a1 described above can be applied even when the power supply potential VDD1 is used, just as when the power supply potential VDD2 is used. Note that the potential VDE indicates the potential of the power supply line 18.

The switch circuit 15 includes, for example, a p-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) (hereafter abbreviated as pMOS) 15a and an n-channel MOSFET (hereafter abbreviated as nMOS) 15b. The power supply potential VDD2 is applied to the source of pMOS 15a, and the drain of pMOS 15a is connected to the drain of nMOS 15b and the power supply line 18. The source of nMOS 15b is grounded. A control signal SETP<1> is input to the gate of pMOS 15a, and a control signal SETN<1> is input to the gate of nMOS 15b.

Capacitor elements 16a to 16d are connected between power supply line 18 and power supply line 19, which has a power supply potential lower than power supply potential VDD2 (VSS (ground potential) in the example of Figure 1). That is, in the example of Figure 1, one end of capacitor elements 16a to 16d is connected to power supply line 18, and the other end is connected to power supply line 19.

Capacitive elements 16a-16d may be, for example, MOS capacitors or ferroelectric capacitors. The number of capacitive elements is not limited to four and may be one.

The leakage current detection circuit 17 detects leakage current in the capacitance elements 16a to 16d. The input terminal of the leakage current detection circuit 17 is connected to the power supply line 18, and the output terminal of the leakage current detection circuit 17 outputs a detection result DET<1> indicating the leakage current detection result (presence or absence of leakage current).

The memory circuit 12 stores the detection results of the leakage current in each of the smoothing capacitance circuits 11a1 to 11aN. The memory circuit 12 may be a volatile memory circuit such as RAM (Random Access Memory), or a non-volatile memory circuit such as EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, or ferroelectric memory.

The smoothing capacitance setting circuit 13 supplies control signals SETP<1> to SETP<N> and SETN<1> to SETN<N> to the smoothing capacitance circuits 11a1 to 11aN based on the leakage current detection results stored in the memory circuit 12. When the semiconductor device 10a is in standby mode, the smoothing capacitance setting circuit 13 supplies a control signal to the smoothing capacitance circuit in which a leakage current has been detected, causing the smoothing capacitance circuit to stop applying the power supply potential VDD2 to the power supply line 18 of that smoothing capacitance circuit.

When the semiconductor device 10a is operating, the smoothing capacitance setting circuit 13 supplies a control signal to the smoothing capacitance circuit in which a leak current is detected, causing the power supply potential VDD2 to be applied to the power supply line 18 of that smoothing capacitance circuit.

FIG. 2 is a diagram showing a circuit configuration of an example of a leakage current detection circuit.
The leakage current detection circuit 17 includes an inverter circuit 17a, a pMOS 17b, an nMOS 17c, and inverter circuits 17d and 17e.

A control signal SETP<1> is input to the input terminal of inverter circuit 17a. The output terminal of inverter circuit 17a is connected to the gate of nMOS 17c. The gate of pMOS 17b is connected to power supply line 18 and is at potential VDE. The power supply potential VDD2 is applied to the source of pMOS 17b, and the drain of pMOS 17b is connected to the drain of nMOS 17c and the input terminal of inverter circuit 17d. The source of nMOS 17c is grounded. Inverter circuits 17d and 17e, connected in series, function as a buffer circuit, and the output of the buffer circuit (output of inverter circuit 17e) is the detection result DET<1>.

Although not shown in the figure, the output terminal of the leakage current detection circuit 17 is connected to the smoothing capacitance setting circuit 13. Note that a bus holder that holds the output state of the leakage current detection circuit 17 may also be connected to the output terminal of the leakage current detection circuit 17.

Next, an example of operation of the semiconductor device 10a (a method for reducing standby current) will be described, focusing on the operation at the time of initial setting of the smoothing capacitance circuits 11a1 to 11aN by the smoothing capacitance setting circuit 13.
3 is a timing chart showing an example of the operation of the semiconductor device when a leakage current occurs, which shows an example of time variations of the signals CEB, SET, and ACT, the control signals SETN<1> and SETP<1>, the potential VDE, and the detection result DET<1>.

Signal CEB is a chip enable signal whose logic level is L (low) (e.g., ground potential) when semiconductor device 10a is operating. Signal SET is a signal whose logic level is H (high) (e.g., power supply potential VDD2) when the latch circuit in smoothing capacitance setting circuit 13 holds the leakage current detection result. Signal ACT is a signal whose logic level is H when the capacitive elements (e.g., capacitive elements 16a-16d) of smoothing capacitance circuits 11a1-11aN are charging and when semiconductor device 10a is in standby or operating mode. Signal CEB is a signal input from outside (off-chip) semiconductor device 10a, which is, for example, a one-chip semiconductor integrated circuit. Signals SET and ACT are signals generated, for example, by a control circuit (not shown) in semiconductor device 10a (e.g., a command generating circuit, described below).

When the logic level of signal ACT rises from L to H (timing t1), the smoothing capacitance setting circuit 13 lowers the logic levels of control signals SETN<1> and SETP<1> from H to L. This turns on pMOS 15a and turns off nMOS 15b of switch circuit 15 in smoothing capacitance circuit 11a1, causing potential VDE to rise and capacitance elements 16a to 16d to begin charging. Potential VDE rises to power supply potential VDD2.

When the logic level of the signal ACT falls from H level to L level (timing t2), the smoothing capacitance setting circuit 13 raises the logic level of the control signal SETP<1> to H level. This turns off the pMOS 15a of the switch circuit 15, the power supply line 18 enters a floating state, and the leakage current detection period begins.

Although not shown in the figure, the smoothing capacitance setting circuit 13 also changes the control signals SETP<2> to SETP<N> and SETN<2> to SETN<N> supplied to the smoothing capacitance circuits 11a2 to 11aN in the same manner as the control signals SETN<1> and SETP<1>.

When a leak current occurs in any of the capacitance elements 16a-16d of the smoothing capacitance circuit 11a1, the potential VDE decreases, as shown in FIG. 3. When the potential VDE falls below the threshold of the pMOS 17b of the leakage current detection circuit 17, the pMOS 17b turns on, and the logic level of the detection result DET<1> rises to the H level (power supply potential VDD2) (timing t2a). At this time, the smoothing capacitance setting circuit 13 raises the logic level of the control signal SETN<1> to the H level. This turns on the nMOS 15b of the switch circuit 15.

When the logic level of the signal SET rises to H level (timing t3), a latch period begins in which the latch circuit in the smoothing capacitance setting circuit 13 holds the detection result of the leakage current.
Although not shown in the figure, the detection result of the leakage current is then stored in the memory circuit 12. This completes the initial setting of the smoothing capacitance circuits 11a1 to 11aN.

When the logical level of signal SET falls to L level and the logical level of signal ACT rises to H level (timing t4), the standby period begins. At this time, the logical levels of the control signals SETN<1> and SETP<1> supplied to the smoothing capacitance circuit 11a1 in which leakage current was detected remain at H level. As a result, the switch circuit 15 stops applying the power supply potential VDD2 to the power supply line 18. Note that in smoothing capacitance circuits in which leakage current was not detected, the application of the power supply potential VDD2 to the power supply line 18 is not stopped.

When the logic level of signal CEB falls to L level (timing t5), the standby period ends and the normal operation period of semiconductor device 10a begins. At this time, smoothing capacitance setting circuit 13 falls the logic levels of control signals SETN<1> and SETP<1> to L level. This turns on pMOS 15a of switch circuit 15, and power supply potential VDD2 is again applied to the power supply line 18 of smoothing capacitance circuit 11a1 in which leakage current was detected, causing potential VDE to begin rising.

Figure 4 is a timing chart showing an example of the operation of a semiconductor device when no leakage current is occurring. Similar to Figure 3, Figure 4 shows an example of the time changes of the signals CEB, SET, and ACT, the control signals SETN<1> and SETP<1>, the potential VDE, and the detection result DET<1>.

If no leak current is occurring, the potential VDE does not decrease during the leak detection period from timing t2 to timing t3. As a result, the logic levels of the detection result DET<1> and the control signal SETN<1> remain at the L level. Therefore, even during the standby period from timing t4 to timing t5, the power supply potential VDD2 is applied to the power supply line 18. In other words, the potential VDE remains at the power supply potential VDD2.

Next, before describing the effects of the semiconductor device 10a of the first embodiment, a comparative example will be described.
(Comparative Example)
FIG. 5 is a diagram showing a semiconductor device of a first comparative example.

Semiconductor device 10b has a smoothing capacitance circuit 11b arranged on the periphery of semiconductor device 10b. Smoothing capacitance circuit 11b has multiple capacitance elements 11b1, 11b2, 11b3, 11b4, ... arranged between power supply line 18, to which power supply potential VDD2 is applied, and power supply line 19, which has power supply potential VSS. Note that the resistance indicated by the dotted line represents the parasitic resistance of capacitance element 11b1.

In such a semiconductor device 10b, for example, if a leakage current flows through capacitive element 11b1 in the direction indicated by the arrow in Figure 5, the standby current of semiconductor device 10b increases, and the device may be determined to be defective during testing before shipping. For example, if the standby current exceeds 200 μA, the device may be determined to be defective and may not be shipped. If stacked ferroelectric capacitors (formed by stacking multiple ferroelectric capacitors in the thickness direction) are used as capacitive elements 11b1, 11b2, 11b3, 11b4, etc., there is a large variation in leakage current.

When semiconductor device 10b, which has a relatively large current, is used, it is desirable for the capacitance value of the capacitive element used as a smoothing capacitance to be around 20 nF, but this will also result in a large leakage current. However, this leakage current has little effect on the operation of semiconductor device 10b at startup.

FIG. 6 is a diagram showing a semiconductor device of a second comparative example.
The semiconductor device 10c includes a smoothing capacitance circuit 11c provided on the periphery of the semiconductor device 10c. The smoothing capacitance circuit 11c includes a plurality of pairs of capacitance elements connected in series between a power supply line 18 to which a power supply potential VDD2 is applied and a power supply line 19 having a power supply potential VSS. For example, a pair of capacitance elements 11c1 and 11c2, a pair of capacitance elements 11c3 and 11c4, and a pair of capacitance elements 11c5 and 11c6 are connected between the power supply line 18 and the power supply line 19. The resistances indicated by dotted lines represent the parasitic resistances of the capacitance elements 11c1 and 11c2.

In such a semiconductor device 10c, even if the parasitic resistance of one of the series-connected capacitance elements 11c1 and 11c2 is small, if the parasitic resistance of the other is large, the leakage current flowing in the direction indicated by the arrow in Figure 6 can be reduced.

However, when two capacitance elements with the same capacitance value are connected in series, the capacitance value is reduced to half compared to when a single capacitance element is connected. To obtain a capacitance value equivalent to that of the smoothing capacitance circuit 11b in semiconductor device 10b of Comparative Example 1, the area occupied by the capacitance elements would be four times that of semiconductor device 10b.

(Effects of the semiconductor device 10a of the first embodiment)
1, the semiconductor device 10a of the first embodiment differs from the semiconductor devices 10b and 10c of the comparative examples 1 and 2 in that a plurality of capacitance elements functioning as smoothing capacitances are divided into a plurality of blocks as smoothing capacitance circuits 11a1 to 11aN. Each of the smoothing capacitance circuits 11a1 to 11aN is provided with a switch circuit (e.g., switch circuit 15) that switches whether or not the power supply potential VDD2 is applied to the power supply line 18. Furthermore, each of the smoothing capacitance circuits 11a1 to 11aN detects leakage current, and the detection result is stored in the memory circuit 12.

Then, based on the leakage current detection results stored in the memory circuit 12, the smoothing capacitance setting circuit 13 stops the application of the power supply potential VDD2 to the power supply line 18 of the smoothing capacitance circuit in which the leakage current was detected when the semiconductor device 10a is in standby mode.

As a result, the capacitance elements in the smoothing capacitance circuit where the application of the power supply potential VDD2 to the power supply line 18 has stopped are not used as smoothing capacitance, and the standby current is no longer increased due to leakage current, thereby reducing the standby current of the semiconductor device 10a.

In addition, in smoothing capacitance circuits where no leakage current is detected, the application of power supply potential VDD2 to power supply line 18 is not stopped even in standby mode, thereby suppressing unnecessary charging and discharging of electric charge.

Furthermore, during normal operation of the semiconductor device 10a, leakage current has little effect on the operation of the semiconductor device 10a at startup. Therefore, by resuming application of the power supply potential VDD2 to a smoothing capacitance circuit in which application of the power supply potential VDD2 to the power supply line 18 was stopped while the semiconductor device 10a was in standby mode, the capacitance element included in the smoothing capacitance circuit can be used as a smoothing capacitance.

Furthermore, semiconductor device 10a can reduce leakage current without connecting a capacitance element in series between power supply lines 18 and 19, as in semiconductor device 10c of comparative example 2, thereby minimizing the increase in area due to the capacitance element.

Second Embodiment
FIG. 7 is a diagram illustrating an example of a semiconductor device according to the second embodiment.
The semiconductor device 20 of the second embodiment is, for example, a one-chip semiconductor integrated circuit including a ferroelectric memory 21 .

The semiconductor device 20 includes a ferroelectric memory 21, an address decoder 22, a row decoder 23, a column decoder 24, a command generating circuit 25, an oscillator/counter circuit 26, a timing circuit 27, a regulator 28, and an input/output circuit 29. Furthermore, the semiconductor device 20 includes smoothing capacitance circuits 30a1, 30a2, ..., 30aN, a smoothing capacitance setting circuit 31, and a switch circuit 32.

The ferroelectric memory 21 has a memory cell array consisting of multiple ferroelectric memory cells arranged in a matrix, and multiple bit lines, multiple word lines, and multiple plate lines, each connected to one of the multiple ferroelectric memory cells. A detection result storage unit 21a that stores the leakage current detection results is provided in part of the memory cell array. The detection result storage unit 21a is an example of the memory circuit 12 shown in Figure 1.

The ferroelectric memory 21 includes a driver circuit, a sense amplifier, a column switch, a write amplifier, and the like.
The address decoder 22 generates a row address and a column address from an address signal ADDRESS received from outside the semiconductor device 20, based on a command generated by the command generating circuit 25. Then, the address decoder 22 supplies the row address to a row decoder 23 and supplies the column address to a column decoder 24.

The row decoder 23 generates a row decode signal by decoding the row address at a timing based on the timing signal generated by the timing circuit 27, and supplies the generated row decode signal to the driver circuit of the ferroelectric memory 21. The driver circuit applies a predetermined voltage for a predetermined period to the word line or plate line specified by the row decode signal among the multiple word lines.

The column decoder 24 generates a column decode signal by decoding the column address. The generated column decode signal is supplied to the column switch of the ferroelectric memory 21, and the column switch selects one of the multiple bit lines to connect to the write amplifier and input/output circuit 29 based on the column decode signal.

The command generation circuit 25 generates various commands (signals ACT, SET, PWON, RESTORE, etc.) in synchronization with the clock signal supplied from the oscillator/counter circuit 26 based on signals CEB, WEB, OEB, and MODE received from outside the semiconductor device 20. The signal CEB is a chip enable signal, the signal WEB is a write enable signal, the signal OEB is an output enable signal, and the signal MODE is a mode signal indicating the operating mode.

When the reset state is released by the power-on reset signal POR, the oscillator/counter circuit 26 counts the number of times the leakage current detection results DET<1> to DET<N> are written to the detection result memory unit 21a and the number of times they are read from the detection result memory unit 21a. The count result is supplied to the command generation circuit 25. As described below, the N-bit detection results DET<1> to DET<N> are read and written n bits at a time, so the number of times it takes to complete reading and writing all N bits is T = N/n.

The timing circuit 27 generates timing signals that determine the operation timing of the row decoder 23, regulator 28, and input/output circuit 29 based on the commands generated by the command generation circuit 25.

Regulator 28 generates power supply potential VDD2 by stepping down external power supply potential VDD1 based on the timing signal generated by timing circuit 27. Regulator 28 also generates power-on reset signal POR.

The input/output circuit 29 includes a write buffer that receives and holds, for example, the leakage current detection result Q<1:n> and write data supplied from outside the semiconductor device 20 via the switch circuit 32 and the bus "BUS." The write buffer may also have the function of holding data read by the sense amplifier of the ferroelectric memory 21 for write back. The input/output circuit 29 also holds and outputs the value of the data determined by the sense amplifier.

Smoothing capacitance circuits 30a1-30aN are provided on the periphery of semiconductor device 20 and smooth power supply noise to suppress fluctuations in the power supply voltage. Each of smoothing capacitance circuits 30a1-30aN has a circuit configuration similar to that of smoothing capacitance circuit 11a1 shown in Figure 1.

The smoothing capacitance setting circuit 31 performs the following operations based on the signals ACT, SET, and PWON generated by the command generating circuit 25 and the power-on reset signal POR supplied from the regulator 28.

The smoothing capacitance setting circuit 31 receives the leakage current detection results DET<1> to DET<N> from the smoothing capacitance circuits 30a1 to 30aN, stores them, and supplies them to the switch circuit 32 as detection results Q<1> to Q<n> in units of the bus bit width (= n bits).

Furthermore, the smoothing capacitance setting circuit 31 receives and holds the leakage current detection results DET<1> to DET<N> stored in the detection result memory unit 21a from the switch circuit 32 in units of the bus bit width. Then, based on the detection results DET<1> to DET<N>, the smoothing capacitance setting circuit 31 supplies control signals SETP<1> to SETP<N> and SETN<1> to SETN<N> to the smoothing capacitance circuits 30a1 to 30aN. Note that in Figure 7, the control signals SETP<1> to SETP<N> are collectively referred to as SETP<1:N>, and the control signals SETN<1> to SETN<N> are collectively referred to as SETN<1:N>.

Based on the RESTORE signal generated by the command generating circuit 25, the switch circuit 32 switches between connecting the external terminal through which write data and read data are input and output to the input/output circuit 29, or connecting the smoothing capacitance setting circuit 31 to the input/output circuit 29.

FIG. 8 is a diagram illustrating an example of a smoothing capacitance setting circuit.
The smoothing capacitance setting circuit 31 includes a selection circuit 31a, latch circuits 31b1, 31b2, ..., 31bN, and control signal setting circuits 31c1, 31c2, ..., 31cN. In Fig. 8, the latch circuits 31b1 to 31bN are denoted as LAT<1>, LAT<2>, ..., LAT<N>, and the control signal setting circuits 31c1 to 31cN are denoted as SET<1>, SET<2>, ..., SET<N>.

When detecting leakage current in smoothing capacitance circuits 30a1-30aN, selection circuit 31a selects n bits at a time from the N-bit detection results DET<1>-DET<N> held in latch circuits 31b1-31bN and supplies them as detection results Q<1>-Q<n> to switch circuit 32. Selection circuit 31a also receives n bits of leakage current detection results DET<1>-DET<N> stored in detection result memory unit 21a from switch circuit 32 as detection results Q<1>-Q<n>. Selection circuit 31a then selects n latch circuits 31b1-31bN at a time and supplies detection results Q<1>-Q<n>.

When the reset state is released by the power-on reset signal POR, the latch circuits 31b1 to 31bN hold the detection results DET<1> to DET<N> based on the signals ACT and SET.

When the logic level of the signal PWON is high, the control signal setting circuits 31c1-31cN supply the control signals SETP<1>-SETP<N> and SETN<1>-SETN<N> to the smoothing capacitance circuits 30a1-30aN based on the detection results DET<1>-DET<N> held in the latch circuits 31b1-31bN.

Next, an example of the operation of the semiconductor device 20 will be described, focusing on the operation at the time of initial setting of the smoothing capacitance circuits 30a1 to 30aN by the smoothing capacitance setting circuit 31.
9 is a timing chart showing an example of the operation of the semiconductor device when a leakage current occurs, illustrating an example of time variations of the signals CEB, RESTORE, PWON, ACT, and SET, the control signals SETN<1> and SETP<1>, the potential VDE, and the detection results DET<1> and Q<1>.

When the logic level of signal ACT rises from L to H (timing t10), the control signal setting circuit 31c1 of the smoothing capacitance setting circuit 31 lowers the logic levels of the control signals SETN<1> and SETP<1> from H to L. This causes the potential VDE to rise in the smoothing capacitance circuit 30a1, and the capacitive elements included in the smoothing capacitance circuit 30a1 (capacitive elements 16a to 16d in the example of Figure 1) begin to charge. The potential VDE rises to the power supply potential VDD2.

When the logic levels of the signals PWON and ACT fall from H to L (timing t11), the control signal setting circuit 31c1 raises the logic level of the control signal SETP<1> to H. This causes the power supply line (power supply line 18 in the example shown in Figure 1) connected to the capacitance element included in the smoothing capacitance circuit 30a1 to enter a floating state, and the leakage current detection period begins.

Although not shown in the figure, the control signal setting circuits 31c2 to 31cN also change the control signals SETP<2> to SETP<N> and SETN<2> to SETN<N> supplied to the smoothing capacitance circuits 30a2 to 30aN in the same way as the control signals SETN<1> and SETP<1>.

When a leak current occurs in the capacitance element included in the smoothing capacitance circuit 30a1, the potential VDE decreases, as shown in FIG. 9. When the potential VDE falls below a predetermined threshold (below the threshold of the pMOS 17b of the leakage current detection circuit 17 shown in FIG. 2), the logic level of the detection result DET<1> rises to the H level (power supply potential VDD2) (timing t11a). At this time, the control signal setting circuit 31c1 raises the logic level of the control signal SETN<1> to the H level. As a result, the power supply line connected to the capacitance element included in the smoothing capacitance circuit 30a1 is grounded via the switch circuit 15 shown in FIG. 1.

When the logical level of the signal SET rises to H level (timing t12), the latch period begins, during which the latch circuits 31b1 to 31bN in the smoothing capacitance setting circuit 31 hold the leakage current detection results DET<1> to DET<N>.

When the logical levels of the signals RESTORE, PWON, and ACT rise to high and the logical level of the signal SET falls to low (timing t13), the storage period during which the detection results DET<1> to DET<N> are stored in the detection result memory unit 21a begins.

During the storage period, the N-bit detection results DET<1> to DET<N> held in the latch circuits 31b1 to 31bN are selected n bits at a time by the selection circuit 31a and supplied to the switch circuit 32 as detection results Q<1> to Q<n>. In the example of FIG. 9, the logic level of the detection result DET<1> is high, so at timing t13, the logic level of the detection result Q<1> rises to high. When the logic level of the signal RESTORE is high, the switch circuit 32 connects the smoothing capacitance setting circuit 31 to the input/output circuit 29. When the logic level of the signal RESTORE is high, the address decoder 22 generates a row address and a column address that specify the detection result storage unit 21a of the ferroelectric memory 21 as a storage area. As a result, the detection results Q<1> to Q<n> are written to and stored in the detection result storage unit 21a via the input/output circuit 29. If N = T x n, this process is repeated T times.

When the detection results DET<1> to DET<N> have finished being saved, the logic level of the signal RESTORE falls to the L level (timing t14). This completes the initial setup of the smoothing capacitance circuits 30a1 to 30aN, and the standby period begins. At this time, the logic levels of the control signals SETN<1> and SETP<1> supplied to the smoothing capacitance circuit 30a1 in which leakage current was detected remain at the H level. As a result, the application of the power supply potential VDD2 to the power supply line to which the capacitance element in the smoothing capacitance circuit 30a1 is connected is stopped. Note that in smoothing capacitance circuits in which leakage current was not detected, the application of the power supply potential VDD2 to the power supply line to which the capacitance element is connected is not stopped.

When the logic level of signal CEB falls to L level (timing t15), the standby period ends and the normal operation period of semiconductor device 20 begins. At this time, control signal setting circuit 31c1 falls the logic levels of control signals SETN<1> and SETP<1> to L level. As a result, power supply potential VDD2 is again applied to the power supply line to which the capacitive element of smoothing capacitance circuit 30a1, in which leakage current was detected, is connected, and potential VDE begins to rise.

Figure 10 is a timing chart showing an example of the operation of a semiconductor device when no leakage current is occurring. Similar to Figure 9, Figure 10 shows an example of the time changes of the signals CEB, RESTORE, PWON, ACT, and SET, the control signals SETN<1> and SETP<1>, the potential VDE, and the detection results DET<1> and Q<1>.

If no leak current is occurring, the potential VDE does not decrease during the leak detection period from timing t11 to timing t12. As a result, the logic levels of the detection result DET<1> and the control signal SETN<1> remain at the L level. Therefore, even during the standby period from timing t14 to timing t15, the power supply potential VDD2 is applied to the power supply line to which the capacitive element in the smoothing capacitance circuit 30a1 is connected. In other words, the potential VDE remains at the power supply potential VDD2.

Next, an example of the operation of the smoothing capacitance setting circuit 31 when the semiconductor device 20 is started up after the initial setting will be described.
11 is a timing chart showing an example of setting control signals for a smoothing capacitance circuit in which a leak current has been detected. Fig. 11 shows an example of time variations of the power-on reset signal POR, signals RESTORE, PWON, and ACT, control signals SETN<1> and SETP<1>, potential VDE, and detection results DET<1> and Q<1>. Fig. 11 also shows an example of setting the control signals SETN<1> and SETP<1> supplied to the smoothing capacitance circuit 30a1 at startup when a leak current has been detected in the smoothing capacitance circuit 30a1 during initial setup.

When power is applied to semiconductor device 20 and the logic levels of power-on reset signal POR, signals RESTORE, and PWON rise to the H level (timing t20), the read period for leak current detection results DET<1> to DET<N> begins.

During the read period, the detection results DET<1> to DET<N> stored in the detection result memory unit 21a are read out n bits at a time as detection results Q<1> to Q<n>. If leakage current is detected in the smoothing capacitance circuit 30a1, the logic level of the detection result Q<1> rises to the H level during readout. The selection circuit 31a of the smoothing capacitance setting circuit 31 receives the detection results Q<1> to Q<n> via the switch circuit 32. The selection circuit 31a then selects n latch circuits 31b1 to 31bN and supplies the detection results Q<1> to Q<n>. If N = T x n, this process is repeated T times, and the detection results DET<1> to DET<N> are held in the latch circuits 31b1 to 31bN.

At timing t20, the logic levels of the control signals SETN<1> to SETN<N> and SETP<1> to SETP<N> fall to the L level. As a result, the power supply potential VDD2 is applied to the power supply lines to which the capacitive elements of the smoothing capacitance circuits 30a1 to 30aN are connected, and the potential VDE rises to the power supply potential VDD2.

When the logic level of the signal RESTORE falls to the L level and the signal ACT rises to the H level (timing t21), the standby period begins.
During the standby period, the control signal setting circuits 31c1 to 31cN set the control signals SETN<1> to SETN<N> and SETP<1> to SETP<N> based on the detection results DET<1> to DET<N> held in the latch circuits 31b1 to 31bN. The control signal setting circuits 31c1 to 31cN then supply the set control signals SETN<1> to SETN<N> and SETP<1> to the smoothing capacitance circuits 30a1 to 30aN. In the example of FIG. 11 , the control signal setting circuit 31c1 sets the logic level of the control signals SETN<1> and SETP<1> to the H level and supplies them to the smoothing capacitance circuit 30a1. This stops the application of the power supply potential VDD2 to the power supply line to which the capacitance element in the smoothing capacitance circuit 30a1 is connected. In addition, in the smoothing capacitance circuit in which no leakage current is detected, the application of the power supply potential VDD2 to the power supply line to which the capacitance element is connected is not stopped.

As shown in Figures 9 and 10, when the logic level of signal CEB falls to L level, the standby period ends and the normal operation period of semiconductor device 20 begins (timing t22). At this time, control signal setting circuit 31c1 falls the logic levels of control signals SETN<1> and SETP<1> to L level. As a result, power supply potential VDD2 is again applied to the power supply line to which the capacitive element of smoothing capacitance circuit 30a1 in which leakage current was detected is connected, and potential VDE begins to rise.

Therefore, the capacitance element included in the smoothing capacitance circuit 30a1 in which the leakage current is detected is also used as a smoothing capacitance.
Fig. 12 is a timing chart showing an example of setting control signals for a smoothing capacitance circuit in which no leakage current is detected. Similar to Fig. 11, Fig. 12 shows examples of time variations of the power-on reset signal POR, signals RESTORE, PWON, and ACT, control signals SETN<1> and SETP<1>, potential VDE, and detection results DET<1> and Q<1>. Fig. 12 also shows an example of setting the control signals SETN<1> and SETP<1> supplied to the smoothing capacitance circuit 30a1 at startup when no leakage current is detected in the smoothing capacitance circuit 30a1 during initial setup.

If no leakage current is detected in the smoothing capacitance circuit 30a1, the logic level of the detection result Q<1> read during the read period from timing t20 to t21 is low. Therefore, during the standby period from timing t21 to t22, the control signal setting circuit 31c1 sets the logic levels of the control signals SETN<1> and SETP<1> to low and supplies them to the smoothing capacitance circuit 30a1. Therefore, even during the standby period, the power supply potential VDD2 is applied to the power supply line to which the capacitance element in the smoothing capacitance circuit 30a1 is connected. In other words, the potential VDE remains at the power supply potential VDD2.

As described above, the semiconductor device 20 of the second embodiment also achieves the same effects as the semiconductor device 10a of the first embodiment. That is, in a smoothing capacitance circuit in which leakage current is detected, by stopping the application of power supply potential to the power supply line connected to the capacitance element during standby, the standby current is prevented from increasing due to leakage current. This makes it possible to reduce the standby current of the semiconductor device 20.

Furthermore, in a smoothing capacitance circuit where no leakage current is detected, the application of power supply potential VDD2 to the power supply line to which the capacitance element is connected is not stopped even in standby mode, thereby suppressing unnecessary charging and discharging of electric charge.

Furthermore, during normal operation of the semiconductor device 20, the application of the power supply potential VDD2 to a smoothing capacitance circuit to which the application of the power supply potential VDD2 was stopped during standby mode can be resumed, allowing the capacitance element included in that smoothing capacitance circuit to be used as a smoothing capacitance.

Furthermore, semiconductor device 20 can reduce standby current without connecting a capacitance element in series between power supply lines 18 and 19, as in semiconductor device 10c of comparative example 2, thereby minimizing the increase in area due to the capacitance element.

Since the semiconductor device 20 of the second embodiment includes a ferroelectric memory 21, the capacitance elements included in the smoothing capacitance circuits 30a1 to 30aN can be ferroelectric capacitors, which can be manufactured in the manufacturing process for the ferroelectric memory 21. If stacked ferroelectric capacitors are used, the leakage current will vary greatly. However, as described above, the semiconductor device 20 of the second embodiment can individually control whether or not to apply the power supply potential VDD2 to the smoothing capacitance circuits in which leakage current is detected, thereby reducing the standby current even when ferroelectric capacitors are used as capacitance elements.

(Third embodiment)
FIG. 13 is a diagram illustrating an example of a semiconductor device according to the third embodiment.
The semiconductor device 40 of the third embodiment is, for example, a one-chip semiconductor integrated circuit, and includes a plurality of smoothing capacitance circuits 41a1, 41a2, ..., 41aN, a memory circuit 42, and a smoothing capacitance setting circuit 43. Other internal circuits of the semiconductor device 40 are not shown in the drawing.

Smoothing capacitance circuits 41a1 to 41aN are provided on the periphery of semiconductor device 40 and smooth power supply noise to suppress fluctuations in the power supply voltage. Figure 13 shows an example of smoothing capacitance circuit 41a1. The other smoothing capacitance circuits 41a2 to 41aN have the same circuit configuration as smoothing capacitance circuit 41a1.

The smoothing capacitance circuit 41a1 includes a switch circuit 45, capacitance elements (eight capacitance elements 46a1, 46a2, 46a3, 46a4, 46b1, 46b2, 46b3, and 46b4 in the example of Figure 1), and leakage current detection circuits 47a and 47b.

Switch circuit 45 switches whether or not power supply potential VDD1 is applied to power supply line 48a in response to control signals SET1P<1> and SET1N<1>. Furthermore, switch circuit 45 switches whether or not power supply potential VDD2 is applied to power supply line 48b in response to control signals SET2P<1> and SET2N<1>.

The power supply potential VDD2 is a potential obtained by lowering the power supply potential VDD1. The potential VDE1 indicates the potential of the power supply line 48a, and the potential VDE2 indicates the potential of the power supply line 48b.
The switch circuit 45 includes, for example, pMOSs 45a and 45c and nMOSs 45b and 45d. A power supply potential VDD1 is applied to the source of the pMOS 45a, and the drain of the pMOS 45a is connected to the drain of the nMOS 45b and the power supply line 48a. The source of the nMOS 45b is grounded. A control signal SET1P<1> is input to the gate of the pMOS 45a, and a control signal SET1N<1> is input to the gate of the nMOS 45b. A power supply potential VDD2 is applied to the source of the pMOS 45c, and the drain of the pMOS 45c is connected to the drain of the nMOS 45d and the power supply line 48b. The source of the nMOS 45d is grounded. A control signal SET2P<1> is input to the gate of the pMOS 45c, and a control signal SET2N<1> is input to the gate of the nMOS 45d.

Capacitor elements 46a1 to 46a4 are connected between power supply line 48a and power supply line 48b. That is, in the example of FIG. 13, one end of capacitor elements 46a1 to 46a4 is connected to power supply line 48a, and the other end is connected to power supply line 48b. Capacitor elements 46b1 to 46b4 are connected between power supply line 48b and power supply line 49, which has a power supply potential lower than power supply potential VDD2 (power supply potential VSS in the example of FIG. 13). That is, in the example of FIG. 13, one end of capacitor elements 46b1 to 46b4 is connected to power supply line 48b, and the other end is connected to power supply line 49.

For example, capacitive elements 46a1 to 46a4 are arranged on the IN side (inside) of semiconductor device 40, and capacitive elements 46b1 to 46b4 are arranged on the OUT side (outside) of semiconductor device 40.

Capacitive elements 46a1-46a4 and 46b1-46b4 may be, for example, MOS capacitors or ferroelectric capacitors. The number of capacitive elements connected between power supply lines 48a and 48b and the number of capacitive elements connected between power supply lines 48b and 49 are not limited to four, and may be one each.

The leakage current detection circuit 47a detects leakage current in the capacitive elements 46a1 to 46a4. The input terminal of the leakage current detection circuit 47a is connected to the power supply line 48a, and the output terminal of the leakage current detection circuit 47a outputs a detection result DET1<1> indicating the leakage current detection result.

The leakage current detection circuit 47b detects leakage current in the capacitive elements 46b1 to 46b4. The input terminal of the leakage current detection circuit 47b is connected to the power supply line 48b, and the output terminal of the leakage current detection circuit 47b outputs a detection result DET2<1> indicating the leakage current detection result.

The memory circuit 42 stores the detection results of the leakage current in each of the smoothing capacitance circuits 41a1 to 41aN. The memory circuit 42 may be a volatile memory circuit such as RAM, or a non-volatile memory circuit such as EEPROM, flash memory, or ferroelectric memory.

The smoothing capacitance setting circuit 43 supplies control signals SET1P<1> to SET1P<N> and SET1N<1> to SET1N<N> to the smoothing capacitance circuits 41a1 to 41aN based on the detection results of the leakage current of the capacitance elements 46a1 to 46a4 stored in the memory circuit 42. Furthermore, the smoothing capacitance setting circuit 43 supplies control signals SET2P<1> to SET2P<N> and SET2N<1> to SET2N<N> to the smoothing capacitance circuits 41a1 to 41aN based on the detection results of the leakage current of the capacitance elements 46b1 to 46b4 stored in the memory circuit 42.

When the semiconductor device 40 is in standby mode, the smoothing capacitance setting circuit 43 supplies a control signal to a smoothing capacitance circuit in which a leak current is detected in the capacitance elements 46a1 to 46a4, causing the smoothing capacitance circuit to stop applying the power supply potential VDD1 to the power supply line 48a of the smoothing capacitance circuit. Furthermore, when the semiconductor device 40 is in standby mode, the smoothing capacitance setting circuit 43 supplies a control signal to a smoothing capacitance circuit in which a leak current is detected in the capacitance elements 46b1 to 46b4, causing the smoothing capacitance circuit to stop applying the power supply potential VDD2 to the power supply line 48b of the smoothing capacitance circuit.

When the semiconductor device 40 is operating, the smoothing capacitance setting circuit 43 supplies a control signal to the smoothing capacitance circuit in which a leak current has been detected, causing the smoothing capacitance circuit to apply power supply potential VDD1 to power supply line 48a and power supply potential VDD2 to power supply line 48b.

The circuit configuration of the leakage current detection circuit 47b is the same as the circuit configuration of the leakage current detection circuit 17 shown in Figure 2. However, in the leakage current detection circuit 47b, the control signal SET2P<1> is input to the inverter circuit 17a in Figure 2. An example circuit configuration of the leakage current detection circuit 47a will be described later (see Figure 18).

Although not shown in the figure, the output terminals of the leakage current detection circuits 47a and 47b are connected to the smoothing capacitance setting circuit 43. A bus holder that holds the output state of the leakage current detection circuits 47a and 47b may also be connected to the output terminals of the leakage current detection circuits 47a and 47b.

Figure 14 shows example settings for the control signals supplied to the smoothing capacitance circuit. Figure 14 shows example settings for the control signals SET1P<1>, SET1N<1>, SET2P<1>, and SET2N<1> in two cases: when no leakage current is detected in the smoothing capacitance circuit 41a1, and when a leakage current is detected.

In FIG. 14, the control signals SET1P<1>, SET1N<1>, SET2P<1>, and SET2N<1> are abbreviated as 1P, 1N, 2P, and 2N.
In the semiconductor device 40 of the third embodiment, leakage current detection is performed when the logic levels of the control signals SET1P<1>, SET1N<1>, SET2P<1>, and SET2N<1> are all set to the L level (setting procedure (1)).

If no leakage current is detected, the logic levels of the detection results DET1<1> and DET2<2> output by the leakage current detection circuits 47a and 47b will be L level. In this case, even in standby mode, the logic levels of the control signals SET1P<1>, SET1N<1>, SET2P<1>, and SET2N<1> are maintained at L level. As a result, the capacitive elements 46a1 to 46a4 and 46b1 to 46b4 all function as smoothing capacitors.

In the first case where leakage current is detected, the logic level of the detection result DET1<1> output by the leakage current detection circuit 47a is high, and the logic level of the detection result DET2<1> output by the leakage current detection circuit 47b is low. In other words, leakage current occurs in one of the capacitive elements 46a1-46a4, but not in the capacitive elements 46b1-46b4. In this case, in the standby state, the logic level of the control signal SET1P<1> is set high, and the logic levels of the control signals SET1N<1>, SET2P<1>, and SET2N<1> are set low (setting procedure (2)). This turns off the pMOS 45a of the switch circuit 45, thereby stopping the application of the power supply potential VDD1 to the power supply line 48a. This eliminates leakage current. On the other hand, because pMOS 45c is not turned off, the power supply potential VDD2 continues to be applied to power line 48b, and capacitive elements 46b1 to 46b4 function as smoothing capacitors.

In the second case where leakage current is detected, the logic levels of the detection results DET1<1> and DET2<1> output by the leakage current detection circuits 47a and 47b are H level. In other words, leakage current occurs in one of the capacitive elements 46a1 to 46a4, and leakage current also occurs in one of the capacitive elements 46b1 to 46b4. In this case, in the standby state, the logic levels of the control signals SET1P<1>, SET1N<1>, SET2P<1>, and SET2N<1> are all set to H level (setting procedure (2)). This turns off the pMOSs 45a and 45c of the switch circuit 45, thereby stopping the application of the power supply potentials VDD1 and VDD2 to the power supply lines 48a and 48b. As a result, all of the capacitive elements 46a1-46a4 and 46b1-46b4 no longer function as smoothing capacitors in standby mode, but leakage current can be eliminated.

The semiconductor device 40 of the third embodiment described above can also be applied as a semiconductor device 20 having a ferroelectric memory 21 as shown in Figure 7. In that case, a smoothing capacitance setting circuit 43 as shown below is used instead of the smoothing capacitance setting circuit 31 shown in Figure 8.

FIG. 15 is a diagram illustrating an example of a smoothing capacitance setting circuit in the semiconductor device according to the third embodiment.
The smoothing capacitance setting circuit 43 includes a selection circuit 43a, latch circuits 43b1, 43b2, . . . , 43bN, and control signal setting circuits 43c1, 43c2, .

When detecting leakage current in smoothing capacitance circuits 41a1-41aN, selection circuit 43a selects n bits at a time from the N x 2-bit detection results DET1<1>-DET1<N> and DET2<1>-DET2<N> held in latch circuits 43b1-43bN. Then, selection circuit 43a supplies the selected n-bit detection results to switch circuit 32 as detection results Q<1>-Q<n>.

The selection circuit 43a also receives the leakage current detection results DET1<1> to DET1<N> and DET2<1> to DET2<N> stored in the detection result storage unit 21a from the switch circuit 32 in n-bit increments as detection results Q<1> to Q<n>. The selection circuit 43a then selects n/2 latch circuits 43b1 to 43bN at a time and supplies the detection results Q<1> to Q<n>.

When the reset state is released by the power-on reset signal POR, the latch circuits 43b1 to 43bN hold two bits of the detection results DET1<1> to DET1<N> and DET2<1> to DET2<N> based on the signals ACT and SET. For example, the latch circuit 43b1 holds the detection results DET1<1> and DET2<1>.

When the logic level of the signal PWON is high, the control signal setting circuits 43c1 to 43cN receive the detection results DET1<1> to DET1<N> and DET2<1> to DET2<N> held in the latch circuits 43b1 to 43bN.

Then, the control signal setting circuits 43c1 to 43cN supply control signals SET1P<1> to SET1P<N> and SET1N<1> to SET1N<N> to the smoothing capacitance circuits 41a1 to 41aN based on the detection results DET1<1> to DET1<N>. Furthermore, the control signal setting circuits 43c1 to 43cN supply control signals SET2P<1> to SET2P<N> and SET2N<1> to SET2N<N> to the smoothing capacitance circuits 41a1 to 41aN based on the detection results DET2<1> to DET2<N>.

Next, we will explain an example of the operation of the semiconductor device 40 when it is applied as a semiconductor device 20 having a ferroelectric memory 21 as shown in Figure 7, focusing on the operation during initial setup of the smoothing capacitance circuits 41a1 to 41aN by the smoothing capacitance setting circuit 43.

Figure 16 is a timing chart showing an example of the operation of the semiconductor device in Case 1, where the leakage current in Figure 14 is detected. Figure 16 shows an example of the changes over time in the signals CEB, RESTORE, PWON, ACT, and SET, the control signals SET1N<1> and SET1P<1>, the potential VDE1, and the detection results DET1<1> and Q<1>.

When the logic level of signal ACT rises from L level to H level (timing t30), the control signal setting circuit 43c1 of the smoothing capacitance setting circuit 43 drops the logic levels of the control signals SET1N<1> and SET1P<1> from H level to L level. Although not shown, the logic levels of the control signals SET2N<1> and SET2P<1> also fall from H level to L level.

As a result, the potential VDE1 (and potential VDE2, not shown) in the smoothing capacitance circuit 41a1 begins to rise, and the capacitance elements 46a1-46a4 and 46b1-46b4 included in the smoothing capacitance circuit 40a1 begin to charge. The potential VDE1 rises to VDD1.

When the logic levels of the signals PWON and ACT fall from H level to L level (timing t31), the leakage current detection period begins.
When a leakage current occurs in the capacitive elements 46a1-46a4 selected for the power supply line 48a, the potential VDE1 drops as shown in FIG. 16. When the potential VDE1 falls below a predetermined threshold, the logic level of the detection result DET1<1> rises to the H level (timing t31a). At this time, the control signal setting circuit 43c1 raises the logic level of the control signal SET1P<1> to the H level. This places the potential VDE1 of the power supply line 48a in a high-impedance state.

When the logical level of the signal SET rises to H level (timing t32), the latch circuits 43b1 to 43bN in the smoothing capacitance setting circuit 43 enter a latch period in which they hold the leakage current detection results DET1<1> to DET1<N> and DET2<1> to DET2<N>.

When the logical levels of the RESTORE, PWON, and ACT signals rise to high and the logical level of the SET signal falls to low (timing t33), the storage period for the detection results DET1<1> to DET1<N> and DET2<1> to DET2<N> begins.

When the detection results DET1<1> to DET1<N> and DET2<1> to DET2<N> have finished being saved, the logic level of the RESTORE signal falls to the L level (timing t34). This completes the initial setting of the smoothing capacitance circuits 41a1 to 41aN, and the standby period begins.

At this time, the logic levels of the control signals SET1N<1> and SET1P<1> supplied to the smoothing capacitance circuit 41a1 in which a leak current was detected remain L level for the control signal SET1N<1> and H level for the control signal SET1P<1>. Therefore, the application of the power supply potential VDD1 to the power supply line 48a in the smoothing capacitance circuit 41a1 is stopped. Meanwhile, the logic levels of the control signals SET2N<1> and SET2P<1> remain L level. Furthermore, in smoothing capacitance circuits in which a leak current was not detected, the application of the power supply potentials VDD1 and VDD2 to the power supply lines 48a and 48b is not stopped.

When the logic level of signal CEB falls to L level (timing t35), the standby period ends and the normal operation period of semiconductor device 40 begins. At this time, control signal setting circuit 43c1 falls the logic level of control signal SET1P<1> to L level. As a result, power supply potential VDD1 is reapplied to power supply line 48a of smoothing capacitance circuit 41a1 in which leakage current was detected, and potential VDE1 begins to rise. Then, capacitive elements 46a1 to 46a4 and 46b1 to 46b4 all function as smoothing capacitances.

Figure 17 is a timing chart showing an example of the operation of the semiconductor device in Case 2, where leakage current is detected in Figure 14. Figure 17 shows an example of changes over time in the signals CEB, RESTORE, PWON, ACT, and SET, the control signals SET1N<1> and SET1P<1>, the potential VDE1, and the detection results DET1<1>, DET2<1>, and Q<1>.

In case 2 of Figure 14, where leakage current is detected, at timing t31a, the logic levels of both detection results DET1<1> and DET2<1> rise to the H level. At this time, the control signal setting circuit 43c1 raises the logic levels of the control signals SET1N<1>, SET1P<1> and the control signals SET2N<1>, SET2P<1> to the H level. This causes the power supply line 48a to be grounded.

During the standby period, the logic levels of the control signals SET1N<1>, SET1P<1> and control signals SET2N<1>, SET2P<1> supplied to the smoothing capacitance circuit 41a1 in which leakage current has been detected remain at the H level. As a result, all of the capacitance elements 46a1 to 46a4 and 46b1 to 46b4 of the smoothing capacitance circuit 41a1 no longer function as smoothing capacitances.

On the other hand, during the operating period, the control signal setting circuit 43c1 lowers the logic levels of the control signals SET1N<1> and SET1P<1> to the L level. This causes the power supply potentials VDD1 and VDD2 to be reapplied to the power supply lines 48a and 48b of the smoothing capacitance circuit 41a1 in which leakage current was detected, and the potential VDE1 begins to rise. Then, all of the capacitance elements 46a1 to 46a4 and 46b1 to 46b4 function as smoothing capacitances.

According to the semiconductor device 40 of the third embodiment described above, the same effects as those of the semiconductor device 20 of the second embodiment can be obtained, and the following effects can also be obtained.
By providing a capacitance element between the power supply lines 48a and 48b and between the power supply lines 48b and 49, a capacitance element with a relatively low resistance (for example, a ferroelectric capacitor) can be used as a smoothing capacitance for the power supply potential VDD1, which is the external power supply potential.

Furthermore, since capacitance elements are not simply connected in series between power supply lines 18 and 19 as in Comparative Example 2, the number of capacitance elements functioning as smoothing capacitance can be increased while limiting the increase in area due to capacitance elements. For example, even if the smoothing capacitance circuits in which leakage current is detected account for 5% of the total and these smoothing capacitance circuits are not used, the increase in area due to capacitance elements required to obtain a capacitance value equivalent to that of smoothing capacitance circuit 11b of semiconductor device 10b in Comparative Example 1 can be limited to approximately 1.05 times.

In the example of the smoothing capacitance circuit 41a1 in Figure 13, the capacitance elements are arranged in a two-stage configuration, but this is not limited to this. It is also possible to increase the power supply potential other than VDD2 obtained by stepping down the power supply potential VDD1, and also increase the number of power supply lines, thereby arranging the capacitance elements in a three-stage configuration or more.

18 is a diagram showing the circuit configuration of an example of a leakage current detection circuit, in which the same elements as those shown in FIG.
The leakage current detection circuit 47a includes an AND (logical product) circuit 47a1, a pMOS 47a2, and an nMOS 47a3 in addition to the elements of the leakage current detection circuit 17 shown in FIG.

AND circuit 47a1 outputs signal STBY, which is the logical product of signals xRESTORE, PWON, and ACT. Signal xRESTORE is a signal with the logical level of the aforementioned signal RESTORE inverted.

The signal STBY is input to the gate of pMOS47a2, the power supply voltage VDD2 is applied to the source of pMOS47a2, and the drain of pMOS47a2 is connected to the source of pMOS17b.

The signal STBY is input to the gate of nMOS 47a3, the drain of nMOS 47a3 is connected to the input terminal of inverter circuit 17d, and the source of pMOS 47a3 is grounded.

In this type of leakage current detection circuit 47a, when in standby mode (when the logic levels of the signals xRESTORE, PWON, and ACT are high and the logic level of the signal STBY becomes high), the pMOS 47a2 is turned off. In other words, the supply of power supply potential VDD2 is cut off. Furthermore, the nMOS 47a3 is turned on, and the input terminal of the inverter circuit 17d is grounded.

Therefore, even if the potential VDE1 of the power supply line 48a is in a high impedance state during standby, the occurrence of leakage current can be suppressed.
(Modification)
Fig. 19 is a diagram showing a modified example of a smoothing capacitance circuit, in which the same elements as those shown in Fig. 13 are denoted by the same reference numerals as in Fig. 13.

In the modified smoothing capacitance circuit 50, a VDE2 initialization circuit 51 is connected to the power supply line 48b. The VDE2 initialization circuit 51 sets the potential VDE2 at power-on to approximately (VDD1-VSS)/2. This causes the capacitive elements 46a1-46a4 and 46b1-46b4 to all function as smoothing capacitances for the power supply potential VDD1, preventing noise from affecting the power supply potential VDD2.

A switch may be provided so that such a VDE2 initialization circuit 51 can be connected to the power supply line 48b instead of the pMOS 45c and nMOS 45d shown in Figure 13 when the power is turned on.

The above describes one aspect of the semiconductor device and standby current reduction method of the present invention based on the embodiments, but these are merely examples and are not limited to the above description.

10a semiconductor device 11a1 to 11aN smoothing capacitance circuit 12 memory circuit 13 smoothing capacitance setting circuit 15 switch circuit 15a pMOS
15b nMOS
16a to 16d: Capacitor elements 17: Leak current detection circuit 18, 19: Power supply lines

Claims (10)

A semiconductor device in which a standby state period including a standby period and an operating period are repeated after a power supply is turned on,
a plurality of smoothing capacitance circuits each including: a switch circuit that switches whether or not a first power supply potential is applied to a first power supply line in response to a first control signal; a first capacitance element that is connected between the first power supply line and a second power supply line that has a second power supply potential that is lower than the first power supply potential; and a first detection circuit that detects a first leakage current in the first capacitance element every time the standby state is entered ;
a storage circuit that stores a first detection result of the first detection circuit;
a smoothing capacitance setting circuit that supplies the first control signal to the first smoothing capacitance circuit, which is a first smoothing capacitance circuit among the plurality of smoothing capacitance circuits and in which the first leakage current has been detected, based on the first detection result stored in the memory circuit, each time the standby state is entered; and
A semiconductor device having: 2. The semiconductor device according to claim 1, wherein the smoothing capacitance setting circuit supplies the first control signal, which applies the first power supply potential to the first power supply line, to all of the first smoothing capacitance circuits during the operating period after the standby state. 3. The semiconductor device according to claim 1, wherein the smoothing capacitance setting circuit supplies the first control signal to the smoothing capacitance circuit each time the standby state is entered, based on the first detection result stored in the memory circuit, to continue applying the first power supply potential to the first power supply line of a smoothing capacitance circuit among the plurality of smoothing capacitance circuits in which the first leakage current is not detected. A semiconductor device according to any one of claims 1 to 3, wherein the smoothing capacitance setting circuit has a latch circuit that holds the first detection result read from the memory circuit upon startup. The semiconductor device described in any one of claims 1 to 4, wherein the memory circuit is provided as part of a memory cell array of a ferroelectric memory. The semiconductor device described in any one of claims 1 to 5, wherein the first capacitive element is a ferroelectric capacitor. Each of the plurality of smoothing capacitance circuits
a third power supply line having a third power supply potential lower than the second power supply potential;
a second capacitance element connected between the second power supply line and the third power supply line;
a second detection circuit that detects a second leakage current in the second capacitance element;
and
the switch circuit switches whether or not the second power supply potential is applied to the second power supply line in response to a second control signal;
the storage circuit stores the first detection result and the second detection result of the second detection circuit;
the smoothing capacitance setting circuit, in the standby state, supplies the second control signal to the second smoothing capacitance circuit, based on the second detection result, for stopping application of the second power supply potential to the second power supply line of the second smoothing capacitance circuit in which the second leakage current is detected;
The semiconductor device according to claim 1 . The semiconductor device described in claim 7, wherein the second capacitive element is a ferroelectric capacitor. The semiconductor device described in claim 7 or 8, further comprising an initialization circuit that sets the second power supply potential to an intermediate potential between the first power supply potential and the third power supply potential upon startup. a plurality of smoothing capacitance circuits each including: a switch circuit that switches whether or not a first power supply potential is applied to a first power supply line in response to a first control signal; a first capacitance element that is connected between the first power supply line and a second power supply line that has a second power supply potential that is lower than the first power supply potential; and a first detection circuit that detects a first leakage current in the first capacitance element every time the device enters a standby state ;
a storage circuit that stores a first detection result of the first detection circuit;
A smoothing capacitance setting circuit;
a standby current reduction method for a semiconductor device in which a standby state period including a standby period and an operating period are repeated after a power supply is started,
The smoothing capacitance setting circuit is
every time the standby state is entered , the first control signal for stopping application of the first power supply potential to the first power supply line of a first smoothing capacitance circuit in which the first leakage current has been detected among the plurality of smoothing capacitance circuits is supplied to the first smoothing capacitance circuit based on the first detection result stored in the memory circuit;
Standby current reduction method.