JP7801616B2 - Power Conversion Device - Google Patents

Description

This disclosure relates to a power conversion device.

Patent Document 1 discloses a technology for power conversion using a power pulsation absorption circuit and a dual active bridge converter (hereinafter abbreviated as "DAB converter").

JP 2022-34820 A

The current output from a DAB converter depends on the phase difference between the primary and secondary voltages of the DAB converter. While Patent Document 1 touts the effectiveness of absorbing power pulsations, it does not mention the phase difference between the primary and secondary voltages of the DAB converter.

This disclosure proposes technology that enables stable output in a power conversion device that uses an active buffer circuit and a DAB converter.

A first aspect of the power conversion device (101) of the present disclosure includes a rectifier circuit (23A, 23B, 23C) that outputs a pulsating voltage (Vrec) that is full-wave rectified and high-frequency attenuated from a single-phase AC voltage (Vi); a DC link (7) including a first power supply line (LH) and a second power supply line (LL); an active buffer circuit (4A, 4C, 4D) that receives the pulsating voltage (Vrec) from the rectifier circuit (23A, 23B, 23C), boosts it to obtain a boosted voltage (Vc), partially buffers the input power (Pi) input from the rectifier circuit (23A, 23B, 23C), and outputs power (Pdc) to the DC link (7); The system includes a dual active bridge converter (5) including a first bridge (51) including a pair of input terminals (5a, 5b) connected between the first power supply line (LH) and the second power supply line (LL), a second bridge (52) including a pair of output terminals (5c, 5d), and a transformer (50) connecting the first bridge (51) and the second bridge (52) between the pair of input terminals (5a, 5b) and the pair of output terminals (5c, 5d); and a control circuit (9) that controls the operation of the active buffer circuits (4A, 4C, 4D) and the dual active bridge converter (5).

In the first aspect, the control circuit (9) causes the dual active bridge converter (5) to variably control the phase difference (φ) between the primary voltage (VA) and secondary voltage (VB) of the transformer (50).

A second aspect of the power conversion device (101) disclosed herein is the first aspect, in which the control circuit (9) causes the active buffer circuit (4A, 4C, 4D) to generate the power (Pdc) by combining a first lagging power (Pc) that lags a first portion (Pb) that is k times the input power (Pi) (where k is a positive number less than or equal to 1/2) by a quarter cycle of the single-phase AC voltage (Vi) with a second portion (Pr) that is (1-k) times the input power (Pi).

A third aspect of the power conversion device (101) disclosed herein is the second aspect, in which the control circuit (9) causes the active buffer circuit (4A, 4C, 4D) to generate the power (Pdc) by combining second phase-lag power (Py), which is obtained by delaying the AC component (Pba) contained in the first portion (Pb) by the quarter cycle, the DC component (Pbd) contained in the first portion (Pb), and the second portion (Pr).

The power conversion device according to the first aspect, the power conversion device according to the second aspect, and the power conversion device according to the third aspect provide a stable output.

A fourth aspect of the power conversion device (101) of the present disclosure is the first aspect, in which the control circuit (9) causes the active buffer circuit (4A, 4C, 4D) to flow a current (iL) that alternates between positive and negative symmetrical waveforms every half of the control period (T) of the dual active bridge converter (5) to the primary side of the transformer (50).

The power conversion device according to the fourth aspect simplifies control based on the phase of the single-phase AC voltage.

A fifth aspect of the power conversion device (101) of the present disclosure is any one of the first to fourth aspects, wherein the active buffer circuit (4A, 4C, 4D) has a first inductor (Lb), a first capacitor (Cb), a first diode (Db), a second diode (Dc), a first switch (Sb), and a second switch (Sc). The series connection of the first inductor (Lb) and the first switch (Sb) receives the pulsating voltage (Vrec). The cathode of the second diode (Dc) is connected to the cathode of the first diode (Db) and the first capacitor (Cb). The series connection of the first diode (Db) and the first capacitor (Cb) is connected in parallel to the first switch (Sb). The second switch (Sc) is connected in parallel to the second diode (Dc).

In the fifth aspect, the control circuit (9) controls the on/off of the first switch (Sb) and the second switch (Sc), and the on/off of the first switch (Sb) boosts the pulsating voltage (Vrec) to obtain the boosted voltage (Vc) in the first capacitor (Cb). When the second switch (Sc) is turned on, the boosted voltage (Vc) is applied between the first power supply line (LH) and the second power supply line (LL) from the series connection of the second diode (Dc) and the first capacitor (Cb). When the second switch (Sc) is turned off, the pulsating voltage (Vrec) is applied between the first power supply line (LH) and the second power supply line (LL) from the series connection of the second diode (Dc) and the first capacitor (Cb).

The power conversion device according to the fifth aspect provides the active buffer circuit.

A sixth aspect of the power conversion device (101) disclosed herein is the fifth aspect, wherein the active buffer circuit (4C, 4D) further includes a third diode (Dr) having an anode connected to the anode of the first switch (Sb) and the first diode (Db) via the first inductor (Lb) and a cathode connected to the anode of the second diode (Dc). The rectifier circuit (23C) includes a diode bridge (2C) that full-wave rectifies the single-phase AC voltage (Vi) and outputs a rectified voltage (|Vi|); and a low-pass filter (3C) that attenuates high frequencies of the rectified voltage (|Vi|) to obtain the pulsating voltage (Vrec). The low-pass filter (3C) has a second inductor (Li) and a second capacitor (Ci); the series connection of the second inductor (Li) and the second capacitor (Ci) receives the rectified voltage (|Vi|), and the pulsating voltage (Vrec) is obtained at the second capacitor (Ci).

A seventh aspect of the power conversion device (101) of the present disclosure is the sixth aspect, in which the first capacitor (Cb) is charged by regenerative current from the dual active bridge converter (5) via the second diode (Dc).

An eighth aspect of the power conversion device (101) of the present disclosure is the sixth aspect, wherein the active buffer circuit (4D) further includes a third switch (Sr) connected in parallel with the third diode (Dr) and turned on to allow current to flow in the reverse direction of the third diode (Dr).

In the power conversion device according to the sixth aspect, the power conversion device according to the seventh aspect, and the power conversion device according to the eighth aspect, the pulsating voltage is obtained from the rectified voltage.

A ninth aspect of the power conversion device (101) of the present disclosure is the fifth aspect thereof, in which the rectifier circuit (23A, 23B) includes a low-pass filter (3A) that receives the single-phase AC voltage (Vi) and outputs a filtered single-phase AC voltage (Vif) in which the high frequencies of the single-phase AC voltage (Vi) are attenuated; and a full-wave rectifier bridge (2A, 2B) that receives the filtered single-phase AC voltage (Vif) and generates the pulsating voltage (Vrec).

In the ninth aspect, the full-wave rectifier bridge (2A, 2B) includes a first input terminal (Psi); a second input terminal (Pri) that receives the filtered single-phase AC voltage (Vif) between the first input terminal (Psi); a fourth diode (Dsb) having an anode connected to the first input terminal (Psi) and a cathode connected to the first inductor (Lb); a fifth diode (Drb) having an anode connected to the second input terminal (Pri) and a cathode connected to the first inductor (Lb); a sixth diode (Dsp) having an anode connected to the second input terminal (Pri) and a cathode connected to the first power supply line (LH); a seventh diode (Drp) having an anode connected to the second input terminal (Pri) and a cathode connected to the first power supply line (LH); an eighth diode (Dsn) having a cathode connected to the first input terminal (Psi) and an anode connected to the second power supply line (LL); and a ninth diode (Drn) having a cathode connected to the second input terminal (Pri) and an anode connected to the second power supply line (LL).

A tenth aspect of the power conversion device (101) of the present disclosure is the ninth aspect thereof, wherein the full-wave rectifier bridge (2B) further includes a third switch (Ssp) connected in parallel to the sixth diode (Dsp) and turned on to allow current to flow in the reverse direction of the sixth diode (Dsp); a fourth switch (Srp) connected in parallel to the seventh diode (Drp) and turned on to allow current to flow in the reverse direction of the seventh diode (Drp); a fifth switch (Ssn) connected in parallel to the eighth diode (Dsn) and turned on to allow current to flow in the reverse direction of the eighth diode (Dsn); and a sixth switch (Srn) connected in parallel to the ninth diode (Drn) and turned on to allow current to flow in the reverse direction of the ninth diode (Drn).

An eleventh aspect of the power conversion device (101) of the present disclosure is the ninth aspect, in which the first capacitor (Cb) is charged by regenerative current from the dual active bridge converter (5) via the second diode (Dc).

The power conversion device according to the ninth aspect, the power conversion device according to the tenth aspect, and the power conversion device according to the eleventh aspect avoid steady-state on-state loss in the third diode according to the sixth aspect.

A twelfth aspect of the power conversion device (101) of the present disclosure is any one of the first to eleventh aspects, wherein the control circuit (9) fluctuates the phase difference (φ) with a frequency component twice the frequency of the single-phase AC voltage (Vi) for the dual active bridge converter (5); and makes the phase difference (φ) at the phase (θ = (2n + 1)π/2) of the single-phase AC voltage (Vi) where the ripple voltage (Vrec) is maximized larger than the phase difference (φ) at the phase (θ = nπ) of the single-phase AC voltage where the ripple voltage (Vrec) is minimized.

The power conversion device according to the twelfth aspect has little distortion in the waveform of the current input to the power conversion device.

A thirteenth aspect of the power conversion device (101) of the present disclosure is the twelfth aspect, in which, during the control period (T) of the dual active bridge converter (5), a first period (Tca: M11, M12, M21), a second period (Tra: M22), a third period (Tcb: M31, M32, M41), and a fourth period (Trb: M42) pass in this order.

In the thirteenth aspect, the boost voltage (Vc) is applied between the pair of input terminals (5a, 5b) during the first period (Tca: M11, M12, M21) and the third period (Tcb: M31, M32, M41), and the pulsating voltage (Vrec) is applied between the pair of input terminals (5a, 5b) during the second period (Tra: M22) and the fourth period (Trb: M42).

A fourteenth aspect of the power conversion device (101) of the present disclosure is the thirteenth aspect thereof, wherein, in the control period (T) of the dual active bridge converter (5), the first period (Tca: M11, M12, M21), the second period (Tra: M22), the fifth period (Tza: M23), the third period (Tcb: M31, M32, M41), the fourth period (Trb: M42), and the sixth period (Tzb: M43) pass in this order. The primary side voltage (VA) is zero in the fifth period (Tza: M23) and the sixth period (Tzb: M43).

The power conversion device according to the thirteenth and fourteenth aspects has small distortion in the waveform of the current input to the power conversion device at and near the phase of the single-phase AC voltage where the pulsating voltage is minimal.

A fifteenth aspect of the power conversion device (101) of the present disclosure is the twelfth aspect thereof, in which the control circuit (9) causes the dual active bridge converter (5) to fluctuate the phase difference (φ) to have a frequency component four times the frequency of the single-phase AC voltage (Vi); causes the phase difference (φ) to take a minimum value at the phase (θ = (2n + 1)π/2) of the single-phase AC voltage (Vi) where the ripple voltage (Vrec) is maximized; and causes the phase difference (φ) to take a maximum value at the phase (θ) of the single-phase AC voltage between the phase (θ = nπ) of the single-phase AC voltage (Vi) where the ripple voltage (Vrec) is minimized and the phase (θ = (2n + 1)π/2) of the single-phase AC voltage where the ripple voltage (Vrec) is maximized.

A sixteenth aspect of the power conversion device (101) of the present disclosure is the fifteenth aspect thereof, in which, during the control period (T) of the dual active bridge converter (5), a first period (Trc: M51, M52, M61), a second period (Tcc: M62), a third period (Trd: M71, M72, M81), and a fourth period (Tcd: M82) pass in this order.

In the sixteenth aspect, the pulsating voltage (Vrec) is applied between the pair of input terminals (5a, 5b) during the first period (Trc: M51, M52, M61) and the third period (Trd: M71, M72, M81), and the boosted voltage (Vc) is applied between the pair of input terminals (5a, 5b) during the second period (Tcc: M62) and the fourth period (Tcd: M82).

A 17th aspect of the power conversion device (101) of the present disclosure is the 16th aspect thereof, wherein, in the control period (T) of the dual active bridge converter (5), the first period (Trc: M51, M52, M61), the second period (Tcc: M62), the fifth period (Tzc: M63), the third period (Trd: M71, M72, M81), the fourth period (Tcd: M82), and the sixth period (Tzd: M83) pass in this order. The primary side voltage (VA) is zero during the fifth period (Tzc: M63) and the sixth period (Tzd: M83).

The power conversion device according to the fifteenth aspect, the sixteenth aspect, and the seventeenth aspect of the present invention provide a power conversion device with small distortion in the waveform of the current input to the power conversion device at and near the phase of the single-phase AC voltage where the pulsating voltage is at its maximum.

The 18th aspect of the power conversion device (101) of the present disclosure is any one of the first to 17th aspects, in which, in the first control period (Tca, Tra, Tza, Tcb, Trb, Tzb) of the dual active bridge converter (5), a first period (Tca: M11, M12, M21), a second period (Tra: M22), a third period (Tcb: M31, M32, M41), and a fourth period (Trb: M42) pass in this order. In the second control period (Trc, Tcc, Tzc, Trd, Tcd, Tzd) of the dual active bridge converter (5), a fifth period (Trc: M51, M52, M61), a sixth period (Tcc: M62), a seventh period (Trd: M71, M72, M81), and an eighth period (Tcd: M82) pass in this order.

In the 18th aspect, the control circuit (9) causes the active buffer circuit (4A, 4C, 4D) to apply the boost voltage (Vc) between the pair of input terminals (5a, 5b) during the first period (Tca: M11, M12, M21), the third period (Tcb: M31, M32, M41), the sixth period (Tcc: M62), and the eighth period (Tcd: M82); and to apply the pulsating voltage (Vrec) between the pair of input terminals (5a, 5b) during the second period (Tra: M22), the fourth period (Trb: M42), the fifth period (Trc: M51, M52, M61), and the seventh period (Trd: M71, M72, M81).

In the 18th aspect, the second control period (Trc, Tcc, Tzc, Trd, Tcd, Tzd) is adopted in the phase (θ=(2n+1)π/2) of the single-phase AC voltage (Vi) where the pulsating voltage (Vrec) is at its maximum, and the first control period (Tca, Tra, Tza, Tcb, Trb, Tzb) is adopted in the phase (θ=nπ) of the single-phase AC voltage (Vi) where the pulsating voltage (Vrec) is at its minimum.

According to the power conversion device of the 18th aspect, the distortion of the waveform of the current input to the power conversion device is small in the phase of the single-phase AC voltage where the pulsating voltage is at its maximum and in its vicinity, and the distortion of the waveform of the current input to the power conversion device is small in the phase of the single-phase AC voltage where the pulsating voltage is at its minimum and in its vicinity.

A 19th aspect of the power conversion device (101) of the present disclosure is any one of the first to eighteenth aspects, in which the phase difference (φ) is subject to feedback control of the current (Io) output from the dual active bridge converter.

The power conversion device according to the 19th aspect contributes to stabilizing the current output from the power conversion device.

A twentieth aspect of the power conversion device (101) of the present disclosure includes a DC link (7) including a first power line (LH) and a second power line (LL); a boost circuit (4A, 4D) that receives a pulsating voltage (Vrec) obtained by full-wave rectification and high-frequency attenuation of a single-phase AC voltage (Vi) and outputs a boosted voltage (Vc) obtained by boosting the pulsating voltage (Vrec) or the pulsating voltage (Vrec) to the DC link (7); and a pair of input terminals (5a, 5b) connected between the first power line (LH) and the second power line (LL). a dual active bridge converter (5) including a first bridge (51) including a pair of input terminals (5a, 5b), a second bridge (52) including a pair of output terminals (5c, 5d), and a transformer (50) connecting the first bridge (51) and the second bridge (52) between the pair of input terminals (5a, 5b) and the pair of output terminals (5c, 5d); and a control circuit (9) that controls the operation of the boost circuit (4A, 4D) and the dual active bridge converter (5).

In the twentieth aspect, in the first control period (Tca, Tra, Tza, Tcb, Trb, Tzb) of the dual active bridge converter (5), the first period (Tca: M11, M12, M21), the second period (Tra: M22), the third period (Tcb: M31, M32, M41), and the fourth period (Trb: M42) pass in this order.

In the twentieth aspect, in the second control period (Trc, Tcc, Tzc, Trd, Tcd, Tzd) of the dual active bridge converter (5), a fifth period (Trc: M51, M52, M61), a sixth period (Tcc: M62), a seventh period (Trd: M71, M72, M81), and an eighth period (Tcd: M82) pass in this order.

In the twentieth aspect, the control circuit (9) causes the boost circuit (4) to apply the boost voltage (Vc) between the pair of input terminals (5a, 5b) during the first period (Tca: M11, M12, M21), the third period (Tcb: M31, M32, M41), the sixth period (Tcc: M62), and the eighth period (Tcd: M82); and to apply the pulsating voltage (Vrec) between the pair of input terminals (5a, 5b) during the second period (Tra: M22), the fourth period (Trb: M42), the fifth period (Trc: M51, M52, M61), and the seventh period (Trd: M71, M72, M81).

In the twentieth aspect, the second control period (Trc, Tcc, Tzc, Trd, Tcd, Tzd) is adopted in the phase (θ=(2n+1)π/2) of the single-phase AC voltage (Vi) where the pulsating voltage (Vrec) is at its maximum. The first control period (Tca, Tra, Tza, Tcb, Trb, Tzb) is adopted in the phase (θ=nπ) of the single-phase AC voltage where the pulsating voltage (Vrec) is at its minimum.

According to the power conversion device of the twentieth aspect, the distortion of the waveform of the current input to the power conversion device is small in the phase of the single-phase AC voltage where the pulsating voltage is at its maximum and in its vicinity, and the distortion of the waveform of the current input to the power conversion device is small in the phase of the single-phase AC voltage where the pulsating voltage is at its minimum and in its vicinity.

A 21st aspect of the power conversion device (101) of the present disclosure is the 20th aspect thereof, further comprising a diode bridge (2C) that full-wave rectifies the single-phase AC voltage (Vi) and outputs a rectified voltage (|Vi|); and a low-pass filter (3C) that attenuates the high frequencies of the rectified voltage (|Vi|) to obtain the pulsating voltage (Vrec).

A 22nd aspect of the power conversion device (101) of the present disclosure is the 20th aspect thereof, further comprising a low-pass filter (3A) that receives the single-phase AC voltage (Vi) and outputs a filtered single-phase AC voltage (Vif) in which the high frequencies of the single-phase AC voltage (Vi) are attenuated; and a full-wave rectifier bridge (2A, 2B) that receives the filtered single-phase AC voltage (Vif) and generates the pulsating voltage (Vrec).

The power conversion device according to the 20th aspect, the power conversion device according to the 21st aspect, and the power conversion device according to the 22nd aspect have small distortions in the waveform of the current input to the power conversion device at and near the phase of the single-phase AC voltage where the pulsating voltage is at its maximum, and small distortions in the waveform of the current input to the power conversion device at and near the phase of the single-phase AC voltage where the pulsating voltage is at its minimum.

1 is a circuit diagram illustrating a configuration of a power conversion device according to an embodiment of the present invention; FIG. 2 is a block diagram illustrating the configuration of a control circuit. 10 is a graph illustrating the dependency of various duties on the power supply phase. 10 is a graph illustrating the operation of a discharge control unit and the operation of a dual active-bridge control unit. 10 is a graph illustrating the operation of a discharge control unit and the operation of a dual active-bridge control unit. 4 is a graph illustrating waveforms of a current, a primary voltage, and a secondary voltage; FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a part of a power conversion device. FIG. 2 is a circuit diagram illustrating a part of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a part of a power conversion device. 10 is a graph illustrating the relationship between a power supply phase and a phase difference. 10 is a graph illustrating an example of the relationship between the power supply phase and an average value. 1 is a graph illustrating the relationship between the power supply phase and various quantities; 1 is a graph illustrating the relationship between the power supply phase and various quantities; 4 is a graph illustrating waveforms of a current, a primary voltage, and a secondary voltage; FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a part of a power conversion device. FIG. 2 is a circuit diagram illustrating a part of a power conversion device. FIG. 2 is a circuit diagram illustrating a part of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a part of a power conversion device. FIG. 2 is a circuit diagram illustrating a part of a power conversion device. 10 is a graph illustrating the relationship between a power supply phase and a phase difference. 10 is a graph illustrating an example of the relationship between the power supply phase and an average value. 1 is a graph illustrating the relationship between the power supply phase and various quantities; 1 is a graph illustrating the relationship between the power supply phase and various quantities; 10 is a graph illustrating the relationship between the power supply phase and various quantities; 4 is a graph illustrating waveforms of a current, a primary voltage, and a secondary voltage; FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. 1 is a graph illustrating the relationship between the power supply phase and various quantities; 1 is a graph illustrating the relationship between the power supply phase and various quantities; 4 is a graph illustrating waveforms of a current, a primary voltage, and a secondary voltage; FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. FIG. 2 is a circuit diagram illustrating a portion of a power conversion device. 1 is a graph illustrating the relationship between the power supply phase and various quantities; 1 is a graph illustrating the relationship between the power supply phase and various quantities; FIG. 10 is a circuit diagram partially showing a first modification of the power conversion device. 10 is a graph illustrating the relationship between the power supply phase θ and various quantities in a second modification. 10 is a graph illustrating the relationship between the power supply phase θ and various quantities in a second modification. 10 is a graph illustrating the relationship between the power supply phase θ and various quantities in a second modification. FIG. 10 is a circuit diagram partially showing a third modification of the power conversion device. FIG. 10 is a circuit diagram partially showing a fourth modification of the power conversion device.

<Overall structure>
1 is a circuit diagram illustrating the configuration of a power conversion device 101 according to this embodiment. The power conversion device 101 includes a rectifier circuit 23C, a DC link 7, an active buffer circuit 4D, and a DAB converter 5. A control circuit 9 controls the active buffer circuit 4D and the DAB converter 5. The power conversion device 101 can also be considered to include the control circuit 9.

Rectifier circuit 23C outputs pulsating voltage Vrec. Pulsating voltage Vrec is obtained by full-wave rectifying and high-frequency attenuation of single-phase AC voltage Vi. When amplitude Vm, angular frequency ω, and time t of single-phase AC voltage Vi are introduced, single-phase AC voltage Vi can be expressed as Vm·sin(ωt). Ignoring the high-frequency attenuation, pulsating voltage Vrec can be expressed as |Vm·sin(ωt)|. Single-phase AC voltage Vi is applied to rectifier circuit 23C from single-phase power supply 1.

The DC link 7 includes a first power supply line LH and a second power supply line LL. The potential of the first power supply line LH is higher than the potential of the second power supply line LL by a positive voltage V1.

The active buffer circuit 4D functions as a boost circuit that receives the pulsating voltage Vrec from the rectifier circuit 23C and boosts it to obtain the boosted voltage Vc. This active buffer circuit 4D partially buffers the input power Pi input from the rectifier circuit 23C and outputs power Pdc= to the DC link 7.

Assuming that the power conversion device 101 operates at a power factor of 1, the input current Ii flowing from the single-phase power supply 1 to the rectifier circuit 23C is expressed as Im·sin(ωt). The input power Pi is expressed as Vi·Ii=Vm·Im·sin ² (ωt).

The input power Pi is the sum of its first portion Pb and second portion Pr. The first portion Pb of the input power Pi is expressed by equation (1) using a coefficient k that is positive and less than or equal to 1/2. The second portion Pr of the input power Pi is (1-k) times the input power Pi and is expressed by equation (2).

Let us assume that the lagging power Pc lags the first portion Pb by a quarter cycle of the single-phase AC voltage Vi. The lagging power Pc is output from the capacitor Cb (described below) via the switch Sc to the DC link 7. The lagging power Pc is expressed by equation (3).

The active buffer circuit 4D, for example, combines the phase-lagging power Pc and the second portion Pr to generate power Pdc = Pc + Pr = (Vm · Im/2) [1 - (1 - 2k) cos(2ωt)].

The control circuit 9 controls the active buffer circuit 4D to cause it to perform this synthesis and generation.

The first portion Pb is the sum of the DC component Pbd and the AC component Pba. The DC component Pbd is expressed by equation (4). The AC component Pba is expressed by equation (5).

The lagging power Py is introduced by lagging the AC component Pba by a quarter cycle of the single-phase AC voltage Vi. The lagging power Py is expressed by equation (6). The lagging power Pc is the sum of the lagging power Py and the DC component Pbd.

For example, the active buffer circuit 4D combines the phase-lag power Py, the DC component Pbd, and the second portion Pr to generate power Pdc.

The control circuit 9 controls the active buffer circuit 4D to cause it to perform this synthesis and generation.

The DAB converter 5 includes a DC-AC conversion unit 51, which is a first bridge, an AC-DC conversion unit 52, which is a second bridge, and a transformer 50.

The DC-AC conversion unit 51 includes a pair of input terminals 5a and 5b connected between the first power line LH and the second power line LL. Voltage V1 can also be considered the voltage at input terminal 5a relative to input terminal 5b.

The AC-DC conversion unit 52 includes a pair of output terminals 5c and 5d.

The transformer 50 connects the DC-AC conversion unit 51 and the AC-DC conversion unit 52 between a pair of input terminals 5a, 5b and a pair of output terminals 5c, 5d.

The control circuit 9 causes the DAB converter 5 to variably control the phase difference φ between the primary voltage VA and secondary voltage VB of the transformer 50. Control of the phase difference φ will be described in detail later.

<Active buffer circuit 4D>
The active buffer circuit 4D includes an inductor Lb, a capacitor Cb, diodes Db and Dc, and switches Sb and Sc.

The series connection of inductor Lb and switch Sb receives pulsating voltage Vrec. The cathode of diode Dc is connected to the cathode of diode Db and capacitor Cb. The series connection of diode Db and capacitor Cb is connected in parallel to switch Sb. Switch Sc is connected in parallel to diode Dc.

The control circuit 9 controls the on/off of the switches Sb and Sc. By turning the switch Sb on and off, the pulsating voltage Vrec is boosted to obtain the boosted voltage Vc in the capacitor Cb (from this perspective, the boosted voltage Vc may hereinafter be referred to as the capacitor voltage Vc). When the switch Sc is on, the capacitor voltage Vc is applied between the first power line LH and the second power line LL via the series connection of the diode Dc and the capacitor Cb. When the switch Sc is off, the pulsating voltage Vrec is applied between the first power line LH and the second power line LL via the series connection of the diode Dc and the capacitor Cb.

The active buffer circuit 4D further includes a diode Dr. The anode of the diode Dr is connected to the switch Sb and the anode of the diode Db via the inductor Lb. The cathode of the diode Dr is connected to the anode of the diode Dc.

The rectifier circuit 23C includes a diode bridge 2C and a low-pass filter 3C. The diode bridge 2C full-wave rectifies the single-phase AC voltage Vi and outputs the rectified voltage |Vi|.

Low-pass filter 3C attenuates the high frequencies of rectified voltage |Vi| to obtain pulsating voltage Vrec. Specifically, low-pass filter 3C has inductor Li and capacitor Ci. The series connection of inductor Li and capacitor Ci receives rectified voltage |Vi|, and pulsating voltage Vrec is obtained at capacitor Ci. Conversely, low-pass filter 3C attenuates the high frequencies of current Ir and inductor current Ib, which will be described later, thereby reducing their impact on input current Ii.

Inductor Lb can be seen as being connected between the connection point between inductor Li and capacitor Ci in low-pass filter 3C and the connection point between diode Db and switch Sb in active buffer circuit 4D.

Current Ir flows between rectifier circuit 23C and first power line LH. Current Ir flows through the parallel connection of diode Dr and switch Sr. The forward direction of diode Dr is used for the positive direction of current Ir.

Inductor current Ib flows through inductor Lb. Inductor current Ib flows between rectifier circuit 23C and switch Sb. The positive direction of inductor current Ib is from inductor Lb to switch Sb.

Current Ic flows between capacitor Cb and the first power line LH. Current Ic flows through the parallel connection of switch Sc and diode Dc. The positive direction of current Ic is the reverse direction of diode Dc.

All of the switches Sr, Sb, and Sc can be realized, for example, by metal-oxide-semiconductor field-effect transistors (MOSFETs).

All of switches Sr, Sb, and Sc can be realized, for example, by insulated gate bipolar transistors (IGBTs). When switch Sr is provided, diode Dr and switch Sr can be realized, for example, by reverse-conducting IGBTs. For example, diode Dc and switch Sc can be realized, for example, by reverse-conducting IGBTs.

<DAB Converter 5>
The configuration of the DAB converter 5 will be explained below.

<DC-AC conversion unit 51>
The DC-AC conversion unit 51 includes switches S1 and S2 connected in series between the input terminals 5a and 5b, and switches S3 and S4 connected in series between the input terminals 5a and 5b.

The output terminal of switch S1 is connected to the input terminal of switch S2 at connection point P12. The input terminal of switch S1 is connected to input terminal 5a. The output of switch S2 is connected to input terminal 5b. The output terminal of switch S3 is connected to the input terminal of switch S4 at connection point P34. The input terminal of switch S3 is connected to input terminal 5a. The output of switch S4 is connected to input terminal 5b.

When switch S1 is conductive, current flows from input terminal 5a to node P12. When switch S2 is conductive, current flows from node P12 to input terminal 5b. When switch S3 is conductive, current flows from input terminal 5a to node P34. When switch S4 is conductive, current flows from node P34 to input terminal 5b.

The DC-AC conversion unit 51 includes a diode D1 connected in parallel with the switch S1, a diode D2 connected in parallel with the switch S2, a diode D3 connected in parallel with the switch S3, and a diode D4 connected in parallel with the switch S4.

Diode D1 allows current to flow from node P12 to input terminal 5a. Diode D2 allows current to flow from input terminal 5b to node P12. Diode D3 allows current to flow from node P34 to input terminal 5a. Diode D4 allows current to flow from input terminal 5b to node P34.

<AC-DC conversion unit 52>
The AC-DC conversion unit 52 includes switches S5 and S6 connected in series between the output terminals 5c and 5d, and switches S7 and S8 connected in series between the output terminals 5c and 5d.

At connection point P56, the output terminal of switch S5 is connected to the input terminal of switch S6. The input terminal of switch S5 is connected to output terminal 5c. The output of switch S6 is connected to output terminal 5d. At connection point P78, the output terminal of switch S7 is connected to the input terminals of switches S8 and S6. The input terminal of switch S7 is connected to output terminal 5c. The output of switch S8 is connected to output terminal 5d.

When switch S5 is conductive, current flows from output terminal 5c to node P56. When switch S6 is conductive, current flows from node P56 to output terminal 5d. When switch S7 is conductive, current flows from output terminal 5c to node P78. When switch S8 is conductive, current flows from node P78 to output terminal 5d.

The AC-DC conversion unit 52 includes a diode D5 connected in parallel with the switch S5, a diode D6 connected in parallel with the switch S6, a diode D7 connected in parallel with the switch S7, and a diode D8 connected in parallel with the switch S8.

Diode D5 allows current to flow from node P56 to output terminal 5c. Diode D6 allows current to flow from output terminal 5d to node P56. Diode D7 allows current to flow from node P78 to output terminal 5c. Diode D8 allows current to flow from output terminal 5d to node P78.

The output voltage Vo is the voltage at output terminal 5c relative to output terminal 5d.

Any of switches S1, S2, S3, S4, S5, S6, S7, and S8 may be realized, for example, by a MOSFET.

All of switches S1, S2, S3, S4, S5, S6, S7, and S8 can be implemented, for example, by IGBTs. For example, diode D1 and switch S1, diode D2 and switch S2, diode D3 and switch S3, diode D4 and switch S4, diode D5 and switch S5, diode D6 and switch S6, diode D7 and switch S7, and diode D8 and switch S8 can each be implemented by a reverse-conducting IGBT.

<Transformer 50>
The transformer 50 has a primary coil L1 and a secondary coil L2. The primary coil L1 is connected between connection points P12 and P34. The secondary coil L2 is connected between connection points P56 and P78. The leakage inductance on the secondary side of the transformer 50 is converted equivalently to the primary side, and further combined with the stray inductance on the primary side to form a leakage inductance Ls connected in series with the primary coil L1.

The voltage on the input side of the DC-AC conversion unit 51 of the transformer 50 is the primary voltage VA. Specifically, the voltage at connection point P12 relative to connection point P34 is the primary voltage VA. The primary voltage VA can also be said to be generated in the primary coil L1.

The voltage on the output side of the AC-DC conversion unit 52 of the transformer 50 is the secondary voltage VB. Specifically, the voltage at connection point P56 relative to connection point P78 is the secondary voltage VB. The secondary voltage VB can also be said to be generated in the secondary coil L2.

For simplicity's sake, the following explanation will be given assuming that the winding ratio of the transformer 50 is 1:1. If the winding ratio is n1:n2, the following explanation will apply if the value of the secondary voltage VB is multiplied by n2/n1.

The difference between the phase φa of the primary voltage VA and the phase φb of the secondary voltage VB is controlled as the phase difference φ.

Current iL flows through leakage inductance Ls and primary coil L1. The direction of current iL is defined as the positive direction from connection point P12 to connection point P34.

<Filter 6>
The power conversion device 101 includes a filter 6. The filter 6 is connected to the DAB converter 5, more specifically, to the AC-DC conversion unit 52, at output terminals 5c and 5d.

The filter 6 has a capacitor Co and an inductor Lo. The capacitor Co is connected between the output terminals 5c and 5d. One end of the inductor Lo is connected to the output terminal 5c. The other end of the inductor Lo and the output terminal 5d both function as the output terminal of the filter 6.

The output current Io, whose high frequencies have been attenuated by the filter 6, flows from the output terminal 5c to the inductor Lo. The output voltage Vo is applied to the capacitor Co.

<Control circuit 9>
2 is a block diagram illustrating the configuration of the control circuit 9. The control circuit 9 includes a charge control section 91, a discharge control section 92, and a dual active bridge control section (abbreviated as "DAB control section" in FIG. 2) 93.

<Charging control unit 91>
The charge control unit 91 controls the charging of the capacitor Cb. Specifically, the charge control unit 91 outputs a switching signal SSb that controls the opening and closing of the switch Sb.

The charging control unit 91 receives the phase θ (=ωt) of the single-phase AC voltage Vi (hereinafter referred to as the "power supply phase"), the inductor current Ib, the capacitor voltage Vc, and its command value Vc*, and generates a switching signal SSb from these.

The charging control unit 91 includes a charging waveform table 911, subtractors 912 and 915, a proportional-integral controller 913, a multiplier 914, and a pulse-width modulator 916.

The charging waveform table 911 contains the waveform of the inductor current Ib as a table and outputs a function F(θ) that depends on the power supply phase θ. The subtractor 912 subtracts the capacitor voltage Vc from the command value Vc* and outputs the deviation ΔVc of the capacitor voltage Vc from the command value Vc*.

Proportional-integral controller 913 performs proportional-integral control on deviation ΔVc and outputs the result to multiplier 914. Multiplier 914 multiplies the output from proportional-integral controller 913 by function F(θ) to generate a command value Ib* for inductor current Ib. The generation of command value Ib* using deviation ΔVc and function F(θ) is publicly known, for example, from Japanese Patent No. 5874800, so details will not be given here.

Subtractor 915 subtracts inductor current Ib from command value Ib* and outputs the deviation ΔIb of inductor current Ib from command value Ib*. Pulse width modulator 916 receives the deviation ΔIb and performs pulse width modulation using the deviation ΔIb to generate switching signal SSb.

It will be obvious to those skilled in the art that by controlling the opening and closing of switch Sb with switching signal SSb obtained using deviation ΔIb, an inductor current Ib that follows command value Ib* can be obtained.

<Discharge control unit 92>
The discharge control unit 92 controls the discharge of the capacitor Cb. Specifically, the discharge control unit 92 outputs a switching signal SSc that controls the opening and closing of the switch Sc. The switching signal SSc controls the discharge of the capacitor Cb. The switching signal SSc is activated with a discharge duty dc to turn on the switch Sc.

The discharge control unit 92 receives the pulsating voltage Vrec, the capacitor voltage Vc, the power supply phase θ, the first carrier C1, and the control sequence mode M, and generates the switching signal SSc from these.

If the active buffer circuit 4D includes a switch Sr, the discharge control unit 92 also outputs a switching signal SSr. The switching signal SSr controls the opening and closing of the switch Sr. The switching signal SSr is activated by the rectification duty drec to turn on the switch Sr. When the switch Sr is turned on, it allows current to flow in the reverse direction through the diode Dr.

The discharge control unit 92 includes a current distribution ratio calculation unit 921, a group of comparators 922, an exclusive OR circuit (abbreviated as "XOR" in Figure 2) 923, and multiplexers (abbreviated as "MPX" in Figure 2) 924 and 925. The current distribution ratio calculation unit 921 inputs the pulsating voltage Vrec, the capacitor voltage Vc, and the power supply phase θ, and generates a discharge duty dc, a rectification duty drec, and a zero duty dz. The zero duty dz, the discharge duty dc, and the rectification duty drec are all non-negative, and the sum of the three is equal to 1.

The discharge duty dc, rectification duty drec, and zero duty dz correspond to the current distribution ratios in "Power Control Method for Improving the Voltage Utilization Rate of a Single-Phase to Three-Phase Power Converter with an Active Buffer" by Yamashita and Sakakibara (Institute of Electrical Engineers Transactions D, Vol. 137, No. 2, pp. 112-118; hereafter tentatively referred to as "Non-Patent Document 1"). The generation of these current distribution ratios, and therefore the generation of the discharge duty dc, rectification duty drec, and zero duty dz, is publicly known, and a detailed description of the current distribution ratio calculation unit 921 will be omitted here.

Figure 3 is a graph illustrating the dependence of the discharge duty dc, rectification duty drec, and zero duty dz on the power supply phase θ when the coefficient k is 1/2. The discharge duty dc, rectification duty drec, and zero duty dz are generated using, for example, the sixth to ninth equations in equation (29) described below. These equations are well known and are introduced as conditions for improving voltage utilization in, for example, Non-Patent Document 1.

The discharge duty dc, rectification duty drec, and zero duty dz when the coefficient k is positive and less than 1/2 will be described later in the sixth variant.

Referring to FIG. 2, the comparator group 922 receives a first sum (drec + dz) which is the sum of the rectification duty drec and the zero duty dz, a second sum (dc + dz) which is the sum of the discharge duty dc and the zero duty dz, the zero duty dz, and the first carrier C1. The comparator group 922 includes comparators 9221, 9222, and 9223.

The first carrier C1 is input to all of comparators 9221, 9222, and 9223. The first carrier C1 is a sawtooth wave that transitions between values 0 and 1 in a cycle of (T/2). For example, this sawtooth wave rises sharply from value 0 to value 1, and then decreases at a constant rate from value 1 to value 0.

Multiplexer 925 receives the control sequence mode M, the first sum (drec + dz), and the second sum (dc + dz).

The control sequence mode M takes two values: a first value and a second value. The control sequence mode M is input from the dual active bridge control unit 93 to the discharge control unit 92.

When control sequence mode M takes the first value, multiplexer 925 inputs the first sum (drec + dz) to comparator 9221 and the second sum (dc + dz) to comparator 9222.

When the control sequence mode M takes the first value:
The comparator 9221 outputs a logic value "H" when the value of the first carrier C1 is equal to or greater than the value of the first sum (drec+dz), and outputs a logic value "L" when the value of the first carrier C1 is less than the value of the first sum (drec+dz);
Comparator 9222 outputs a logical value "H" when the value of the first carrier C1 is less than the value of the second sum (dc + dz), and outputs a logical value "L" when the value of the first carrier C1 is greater than or equal to the value of the second sum (dc + dz).

When control sequence mode M takes the second value, multiplexer 925 inputs the second sum (dc + dz) to comparator 9221 and the first sum (drec + dz) to comparator 9222.

When the control sequence mode M takes the second value:
The comparator 9221 outputs a logic value "H" when the value of the first carrier C1 is equal to or greater than the value of the second sum (dc+dz), and outputs a logic value "L" when the value of the first carrier C1 is less than the value of the second sum (dc+dz);
Comparator 9222 outputs a logical value "H" when the value of first carrier C1 is less than the value of the first sum (drec+dz), and outputs a logical value "L" when the value of first carrier C1 is greater than or equal to the value of the first sum (drec+dz).

Comparator 9223 receives zero duty dz regardless of the value of control sequence mode M. Comparator 9223 outputs a logical value of "H" when the value of first carrier C1 is less than the value of zero duty dz, and outputs a logical value of "L" when the value of first carrier C1 is equal to or greater than the value of zero duty dz.

Exclusive OR circuit 923 receives the output of comparator 9222 and the output of comparator 9223 and outputs the exclusive OR of these.

When the control sequence mode M takes the first value, the output of the exclusive OR circuit 923 is:
When the first carrier C1 takes a value between 0 and the zero duty dz, it takes a logic value "L";
When the first carrier C1 takes a value between zero duty dz and the second sum (dc+dz), it takes a logic value “H”;
When the first carrier C1 takes a value between the second sum (dc+dz) and the value 1, it takes a logic value "L".

When the control sequence mode M takes the second value, the output of the exclusive OR circuit 923 is:
When the first carrier C1 takes a value between 0 and the zero duty dz, it takes a logic value "L";
When the first carrier C1 takes a value between the zero duty dz and the first sum (drec+dz), it takes a logic value “H”;
When the first carrier C1 takes a value between the first sum (drec+dz) and the value 1, it takes a logic value "L".

Multiplexer 924 receives control sequence mode M, the output of comparator 9221, and the output of exclusive OR circuit 923.

When the control sequence mode M takes on the first value, the multiplexer 924:
The output of the comparator 9221 is output as a switching signal SSc;
The output of the exclusive OR circuit 923 is output as the switching signal SSr.

When the control sequence mode M takes on a second value, the multiplexer 924:
outputting the output of the comparator 9221 as a switching signal SSr;
The output of the exclusive OR circuit 923 is output as the switching signal SSc.

<Operations of the Discharge Control Unit 92 and the Dual Active Bridge Control Unit 93>
4 and 5 are graphs illustrating the operation of the discharge control unit 92 and the operation of the dual active-bridge control unit 93. Fig. 4 illustrates the case where the control sequence mode M takes a first value. Fig. 5 illustrates the case where the control sequence mode M takes a second value. The operation of the dual active-bridge control unit 93 will be described later.

When the control sequence mode M takes the first value, with reference to FIG. 4:
In periods Tca and Tcb, the first carrier C1 takes a value between the first sum (drec+dz) and the value 1, the switching signal SSr takes a logic value "L", and the switching signal SSc takes a logic value "H";
In periods Tra and Trb, the first carrier C1 takes a value between zero duty dz and the first sum (drec+dz), the switching signal SSc takes a logical value "L", and the switching signal SSr takes a logical value "H";
In periods Tza and Tzb, the first carrier C1 takes a value between 0 and zero duty dz, and both the switching signals SSr and SSc take a logical value "L."

When the control sequence mode M takes the second value, with reference to FIG. 5:
In the periods Trc and Trd, the first carrier C1 takes a value between the second sum (dc+dz) and the value 1, the switching signal SSc takes a logic value "L", and the switching signal SSr takes a logic value "H";
In periods Tcc and Tcd, the first carrier C1 takes a value between zero duty dz and the second sum (dc+dz), the switching signal SSr takes a logical value "L", and the switching signal SSc takes a logical value "H";
During periods Tzc and Tzd, the first carrier C1 takes a value between 0 and zero duty dz, and both the switching signals SSr and SSc take a logical value "L."

The effects of the relationship between the periods Trc, Trd, Tcc, Tcd, Tzc, and Tzd and the switching signals SSr and SSc will be described later in the section <First Sequence>.

The effects of the relationship between the periods Tca, Tcb, Tra, Trb, Tza, and Tzb and the switching signals SSr and SSc will be described later in the "Second Sequence" section.

<Dual active bridge control unit 93>
The dual active bridge control unit 93 controls the operation of the DAB converter 5. Specifically, the dual active bridge control unit 93 outputs switching signals SS1, SS2, SS3, SS4, SS5, SS6, SS7, and SS8 that control the opening and closing of switches S1, S2, S3, S4, S5, S6, S7, and S8, respectively.

The dual active bridge control unit 93 receives the power supply phase θ, pulsating voltage Vrec, capacitor voltage Vc, inductance L, control frequency f (= 1/T), output current Io and its command value Io*, and generates switching signals SS1, SS2, SS3, SS4, SS5, SS6, SS7, and SS8 from these.

The dual active bridge control unit 93 controls the phase difference φ to follow the value obtained by subtracting the command value φa* from the command value φb* (hereinafter sometimes referred to as the "command value φ*").

The command value φa* is the command value for the phase φa of the primary voltage VA. For simplicity's sake, this corresponds to the phase at which the second carrier C2 (described below) takes its minimum value, and the value 0 is used as an example of this phase. The command value φb* is the command value for the phase φb of the secondary voltage VB.

The dual active bridge control unit 93 includes a phase command calculation unit 931, a comparator group 932, and set-reset flip-flops 936 and 937.

<Phase command calculation unit 931>
The phase command calculation unit 931 calculates command values HA and HB that determine the phase difference φ at which an output current Io that follows the command value Io* is obtained. The command value Io*, control frequency f, inductance L, pulsating voltage Vrec, and capacitor voltage Vc are input to the phase command calculation unit 931, and the phase command calculation unit 931 performs a calculation to calculate the command values HA and HB corresponding to the command values φa* and φb*. For example, equations (28) and (46) described below are used in this calculation.

The relationship between the output current Io obtained from the DAB converter 5 and the phase difference φ is publicly known, and is introduced, for example, in "From the Basics to the Applications of DC/DC Converters" by Katsuya Hirachi (published by the Institute of Electrical Engineers of Japan in 2018). When feedback control of the output current Io (hereinafter simply referred to as "feedback control") is performed, the dual active-bridge control unit 93 further includes a feedback control block 930. The feedback control block 930 includes a subtractor 933, a proportional-integral controller 934, and a multiplier 935. Here, we will first explain the case when feedback control is not performed.

<Comparator group 932, carrier generator 900>
The command values HA and HB calculated by the phase command calculation unit 931 are output to a comparator group 932. When feedback control is performed, the command value HB calculated by the phase command calculation unit 931 is corrected in a feedback control block 930 and then output to the comparator group 932.

Comparator group 932 compares both command values HA and HB with the second carrier C2 and third carrier C3 to obtain set signals SA and SB and reset signals RA and RB.

The second carrier C2 is, for example, a sawtooth wave that transitions between values 0 and 1 with a period T. This sawtooth wave, for example, rises sharply from value 0 to value 1, and then decreases at a constant rate from value 1 to value 0. The third carrier C3 is, for example, a sawtooth wave that transitions between values 0 and 1 with a period T. This sawtooth wave rises sharply from value 0 to value 1, and then decreases at a constant rate from value 1 to value 0.

There is a half-cycle (T/2) difference between the timing when the second carrier C2 rises and the timing when the third carrier C3 rises. The first carrier C1 rises at both the timing when the second carrier C2 rises and the timing when the third carrier C3 rises.

The carrier generator 900 generates the synchronized first carrier C1, second carrier C2, and third carrier C3 in this manner. The carrier generator 900 may be considered to be included in the discharge control unit 92, or may be considered to be included in the dual active bridge control unit 93. Alternatively, the part of the carrier generator 900 that generates the first carrier C1 may be considered to be included in the discharge control unit 92, and the part that generates the second carrier C2 and third carrier C3 may be considered to be included in the dual active bridge control unit 93.

When the second carrier C2 and the third carrier C3 both transition between the values 0 and 1, the value (π-φa*)/π is used as the command value HA, and the value (π-φb*)/π is used as the command value HB. Figures 4 and 5 illustrate the relationship between the second carrier C2 and the third carrier C3, the command values HA and HB, the set signals SA and SB, and the reset signals RA and RB.

The set signal SA is activated (e.g., takes on a logical value of "H") in the phase in which the command value HA is equal to or greater than the value of the second carrier C2. The set signal SB is activated in the phase in which the command value HB is equal to or greater than the value of the second carrier C2. The reset signal RA is activated in the phase in which the command value HA is equal to or greater than the value of the third carrier C3. The reset signal RB is activated in the phase in which the command value HB is equal to or greater than the value of the third carrier C3.

The phase at which reset signal RA changes from inactive to active, or in accordance with Figures 4 and 5, the phase at which reset signal RA rises, corresponds to the command value φa*. The phase at which reset signal RB changes from inactive to active, or in accordance with Figures 4 and 5, the phase at which reset signal RB rises, corresponds to the command value φb*. In Figures 4 and 5, the symbols "φa*" and "φa*" are added to the timings corresponding to the command values φa* and φa*, respectively, for convenience. In Figures 4 and 5, the symbol "φ*" is added to the period indicating the length (2π/T)(φb* - φa*), which corresponds to the command value φ* (= φb* - φa*) of the phase difference φ, for convenience.

<Set-Reset Flip-Flops 936, 937>
The set signals SA and SB and the reset signals RA and RB are used to generate switching signals SS1, SS2, SS3, SS4, SS5, SS6, SS7, and SS8.

The set-reset flip-flop 936 receives the set signal SA and the reset signal RA. The set-reset flip-flop 936 is set by the set signal SA and reset by the reset signal RA, and outputs the switching signals SS2 and SS3.

Switching signals SS2 and SS3 are inverted by an inverter to obtain switching signals SS1 and SS4.

The set-reset flip-flop 937 receives the set signal SB and the reset signal RB. The set-reset flip-flop 937 is set by the set signal SB and reset by the reset signal RB, and outputs the switching signals SS6 and SS7.

Switching signals SS6 and SS7 are inverted by an inverter to obtain switching signals SS5 and SS8.

<Synchronous Pulse Width Modulator 90>
Carrier generator 900 generates first carrier C1, second carrier C2, and third carrier C3, which are synchronized as described above. Comparator group 922 compares first carrier C1 with first sum (drec+dz), second sum (dc+dz), and zero duty dz to generate switching signals SSr and SSc themselves or signals used to generate them (specifically, signals that are processed by exclusive OR circuit 923 and multiplexer 924 to become switching signals SSr and SSc). Comparator group 932 compares second carrier C2 and third carrier C3 with command values HA and HB to generate set signals SA and SB and reset signals RA and RB, which are used to generate switching signals SS1, SS2, SS3, SS4, SS5, SS6, SS7, and SS8. From these perspectives, the comparators 922 and 932 and the carrier generator 900 can be collectively considered as a synchronous pulse width modulator 90 .

Feedback Control Block 930
In the feedback control block 930, a subtractor 933 subtracts the output current Io from a command value Io* and outputs a deviation ΔIo. A proportional-integral controller 934 performs proportional-integral control on the deviation ΔIo and outputs the result to a multiplier 935. The multiplier 935 multiplies the output from the proportional-integral controller 934 by a command value HB to update the command value HB. When feedback control of the output current Io is performed, the command value HB updated by the multiplier 935 is input to a comparator group 932 and compared with the second carrier C2 and the third carrier C3.

<First Sequence>
<Waveforms of current iL, primary voltage VA, and secondary voltage VB>
6 is a graph illustrating the waveforms of the current iL, the primary voltage VA, and the secondary voltage VB. Fig. 6 illustrates a case where the phase difference φ is equal to or less than half the product dc·T of the discharge duty dc and the period T (the product dc·T/2 of the half period T/2 and the discharge duty dc).

Switching in the power conversion device 101 is controlled at a predetermined control period. Specifically, the switching is controlled periodically with a period T. In Figure 6, period T starts at time t0 and ends at time t10. Time t0 is the start of period T, and time t10 is the end of period T. The length from time t0 to time t5 is equal to the length from time t5 to time t10. Time t5 is the midpoint of period T.

For convenience, the following explanation will be given assuming that time t0 corresponds to phase 0 of cycle T, time t5 corresponds to phase π of cycle T, and time t10 corresponds to phase 2π of cycle T.

Cycle T is divided into periods T1, T2, T3, and T4.

Period T1 begins at time t0, passes through time t1, and ends at time t2. Time t0 is the beginning of period T1, and time t2 is the end of period T1.

Period T2 begins at time t2, passes through times t3 and t4 in that order, and ends at time t5. Time t2 is the beginning of period T2, and time t5 is the end of period T2.

Period T3 begins at time t5, passes through time t6, and ends at time t7. Time t5 is the beginning of period T3, and time t7 is the end of period T3.

Period T4 begins at time t7, passes through times t8 and t9 in that order, and ends at time t10. Time t7 is the beginning of period T4, and time t10 is the end of period T4.

The period T is divided into periods Tca, Tra, Tza, Tcb, Trb, and Tzb.

Period Tca begins at time t0, passes through times t1 and t2, and ends at time t3. Time t0 is the beginning of period Tca, and time t3 is the end of period Tca.

The period Tra begins at time t3 and ends at time t4. Time t3 is the beginning of the period Tra, and time t4 is the end of the period Tra.

The period Tza begins at time t4 and ends at time t5. Time t4 is the beginning of the period Tza, and time t5 is the end of the period Tza.

The period Tcb begins at time t5, passes through times t6 and t7, and ends at time t8. Time t5 is the beginning of the period Tcb, and time t8 is the end of the period Tcb.

Period Trb begins at time t8 and ends at time t9. Time t8 is the beginning of period Trb, and time t9 is the end of period Trb.

Period Tzb begins at time t9 and ends at time t10. Time t9 is the beginning of period Tzb, and time t10 is the end of period Tzb.

During period Tca, the primary side voltage VA is equal to the capacitor voltage Vc. During period Tra, the primary side voltage VA is equal to the pulsating voltage Vrec. During period Tcb, the primary side voltage VA is equal to the voltage value (-Vc). During period Trb, the primary side voltage VA is equal to the voltage value (-Vrec). The sum of the capacitor voltage Vc and the voltage value (-Vc) is 0. The sum of the pulsating voltage Vrec and the voltage value (-Vrec) is 0. During periods Tza and Tzb, the primary side voltage VA is equal to 0.

The length of each of periods Tca and Tcb is equal to half the product dc·T of the discharge duty dc and the period T (the product dc·T/2 of the half period T/2 and the discharge duty dc).

The length of each of the periods Tra and Trb is equal to half the product drec·T of the rectification duty drec and the period T (the product drec·T/2 of the half period T/2 and the rectification duty drec).

The length of each of the periods Tza and Tzb is equal to half the product dz·T of the zero duty dz and the period T (the product dz·T/2 of the half period T/2 and the zero duty dz).

From time t2 through times t3, t4, t5, and t6 until time t7, the secondary side voltage VB maintains the output voltage Vo. During periods T2 and T3, the secondary side voltage VB maintains the output voltage Vo.

The secondary side voltage VB maintains a voltage value (-Vo) from time t0 through time t1 to time t2, and from time t7 through times t8 and t9 to time t10. During periods T1 and T4, the secondary side voltage VB maintains a voltage value (-Vo). The sum of the voltage value (-Vo) and the output voltage Vo is 0.

<Current flow path>
Table 1 shows examples of current path modes M11, M12, M21, M22, M23, M31, M32, M41, M42, and M43 and the ON/OFF relationships of the switches that realize these modes. The current path modes M11, M12, M21, M22, M23, M31, M32, M41, M42, and M43 represent various path patterns of the current flowing through the DAB converter 5.

In Table 1:
The symbol "ON(Dr)" indicates the situation where the switch Sr is on, but the current Ir (>0) flows through the diode Dr;
The symbol "ON(Dc)" indicates a situation in which the switch Sc is on, but the current Ic (<0) flows through the diode Dc;
The symbol "ON(D1)" indicates the situation where switch S1 is on but current flows through diode D1;
The symbol "ON(D2)" indicates the situation where switch S2 is on but current flows through diode D2;
The symbol "ON(D3)" indicates the situation where switch S3 is on but current flows through diode D3;
The symbol "ON(D4)" indicates the situation where switch S4 is on but current flows through diode D4;
The symbol "ON(D5)" indicates the situation where switch S5 is on but current flows through diode D5;
The symbol "ON(D6)" indicates the situation where switch S6 is on but current flows through diode D6;
The symbol "ON(D7)" indicates the situation where switch S7 is on but current flows through diode D7;
The symbol "ON (D8)" indicates a situation where switch S8 is on but current flows through diode D8.

When current flows through diodes Dr, Dc, D1, D2, D3, D4, D5, D6, D7, and D8, switches Sr, Sc, S1, S2, S3, S4, S5, S6, S7, and S8 may be turned off.

However, when MOSFETs are used for switches S1, S2, S3, S4, S5, S6, S7, and S8, synchronous rectification is expected. Therefore, even if current flows through diodes D1, D2, D3, D4, D5, D6, D7, and D8, it is desirable for switches S1, S2, S3, S4, S5, S6, S7, and S8 to be turned on.

Table 1 lists the positive and negative values of current iL for each current path mode: M11, M12, M21, M22, M23, M31, M32, M41, M42, and M43.

Figure 6 also shows the periods during cycle T during which current path modes M11, M12, M21, M22, M23, M31, M32, M41, M42, and M43 are adopted.

The current path mode M11 is adopted during the period from time t0 to time t1;
The current path mode M12 is adopted during the period from time t1 to time t2;
The current path mode M21 is adopted during the period from time t2 to time t3;
Current path mode M22 is adopted during the period from time t3 to time t4;
Current path mode M23 is adopted during the period from time t4 to time t5;
Current path mode M31 is adopted during the period from time t5 to time t6;
Current path mode M32 is adopted during the period from time t6 to time t7;
The current path mode M41 is adopted during the period from time t7 to time t8;
Current path mode M42 is adopted during the period from time t8 to time t9;
The current path mode M43 is employed during the period from time t9 to time t10.

In the first half cycle (T/2) of cycle T, current path modes M11, M12, M21, M22, and M23 are adopted in this order. In the second half cycle (T/2) of cycle T, current path modes M31, M32, M41, M42, and M43 are adopted in this order.

The switches Sr, Sc, S1, S2, S3, S4, S5, S6, S7, and S8 used to realize these current path modes M11, M12, M21, M22, M23, M31, M32, M41, M42, and M43 are controlled by switching signals SSr, SSc, SS1, SS2, SS3, SS4, SS5, SS6, SS7, and SS8, respectively.

The generation of switching signals SSr, SSc, SS1, SS2, SS3, SS4, SS5, SS6, SS7, and SS8 in the first sequence is illustrated by the graph shown in Figure 4. However, the inversions of switching signals SS1, SS4, SS5, and SS8 are indicated by overlines in their symbols.

Specifically, during period Tca, switching signals SSc and SSr assume logic "H" and "L," respectively, turning switches Sc and Sr on and off, respectively. As mentioned above, switch Sc may be turned on in the state indicated by the symbol "ON (Dc)" in Table 1, thereby realizing operation of active buffer circuit 4 from times t0 to t3, which corresponds to period Tca. The same is true for times t5 to t8, which corresponds to period Tcb.

During period Tra, switching signals SSc and SSr assume logic "L" and "H," respectively, turning switches Sc and Sr off and on, respectively. As mentioned above, switch Sr may be on when the symbol "ON (Dr)" is indicated in Table 1, thereby realizing operation of active buffer circuit 4 from times t3 to t4, which corresponds to period Tra. The same is true for times t8 to t9, which corresponds to period Trb.

During period Tza, both switching signals SSc and SSr assume a logic "L" level, turning off both switches Sc and Sr. This enables the active buffer circuit 4 to operate from times t4 to t5, which corresponds to period Tza. The same is true for times t9 to t10, which corresponds to period Tzb.

Figures 7 to 16 are circuit diagrams illustrating a portion of the power conversion device 101, with arrows indicating the path of current flowing through the DAB converter 5. These figures show the active buffer circuit 4, DAB converter 5, and capacitors Ci and Co of the power conversion device 101.

Figure 7 shows the current path when current path mode M11 is adopted. In current path mode M11, leakage inductance Ls serves as a current source, and current (iL < 0) is regenerated to capacitor Cb.

Referring to Table 1, in current path mode M11, switches Sr, S2, and S3 are off, and current (Ic = iL < 0) flows from the primary coil L1 and leakage inductance Ls to capacitor Cb via diodes D1, Dc, and D4. This can be said to be charging capacitor Cb with regenerative current from DAB converter 5 via diode Dc. At this time, referring also to Figure 6, the primary voltage VA takes on the capacitor voltage Vc.

Referring to Table 1, in current path mode M11, switches S5 and S8 are off, and the current flowing through the secondary coil L2 charges capacitor Co via diodes D6 and D7 (I>0). At this time, also referring to Figure 6, the secondary voltage VB takes on a voltage value of (-Vo).

Figure 8 shows the current path when current path mode M12 is adopted. In current path mode M12, capacitor Cb acts as a voltage source, causing current (iL > 0) to flow through primary coil L1 and leakage inductance Ls.

Referring to Table 1, in current path mode M12, switches Sr, S2, and S3 are off, and switches Sc, S1, and S4 are on. Current (Ic = iL > 0) flows from capacitor Cb (discharge of capacitor Cb) to primary coil L1 and leakage inductance Ls via switches Sc, S1, and S4. Also referring to Figure 6, at this time, primary voltage VA takes on capacitor voltage Vc.

Referring to Table 1, in current path mode M12, switches S5 and S8 are off and switches S6 and S7 are on. Current (I<0) flows from capacitor Co to secondary coil L2 via switches S6 and S7 (discharging of capacitor Co). Also referring to Figure 6, at this time, secondary voltage VB takes on a voltage value of -Vo.

Figure 9 shows the current path when current path mode M21 is adopted. In current path mode M21, capacitor Cb acts as a voltage source, causing current (iL > 0) to flow through primary coil L1 and leakage inductance Ls.

Referring to Table 1, in current path mode M21, switches Sr, S2, and S3 are off, and switches Sc, S1, and S4 are on. Current (Ic = iL > 0) flows from capacitor Cb (discharge of capacitor Cb) to primary coil L1 and leakage inductance Ls via switches Sc, S1, and S4. Also referring to Figure 6, at this time, primary voltage VA takes on capacitor voltage Vc.

Referring to Table 1, in current path mode M21, switches S6 and S7 are off. Current (I>0) flows from the secondary coil L2 via diodes D5 and D8 to charge capacitor Co. At this time, also referring to Figure 6, the secondary voltage VB is equal to the output voltage Vo.

Figure 10 shows the current path when current path mode M22 is adopted. In current path mode M22, rectifier circuit 2 serves as a voltage source, causing current (iL > 0) to flow through primary coil L1 and leakage inductance Ls via filter 3 and diode Dr.

Referring to Table 1, in current path mode M22, switches Sc, S2, and S3 are off, and switches S1 and S4 are on. Current (Ir = iL > 0) flows from filter 3 to primary coil L1 and leakage inductance Ls via diode Dr and switches S1 and S4. At this time, referring also to Figure 6, primary voltage VA takes on pulsating voltage Vrec.

Referring to Table 1, in current path mode M22, switches S6 and S7 are off. Current flowing from the secondary coil L2 via diodes D5 and D8 charges capacitor Co. At this time, also referring to Figure 6, the secondary voltage VB is equal to the output voltage Vo.

Figure 11 shows the current path when current path mode M23 is adopted. In current path mode M23, current (iL > 0) circulates within the DC-AC conversion unit 51.

Referring to Table 1, in current path mode M23, switches Sc and Sr are off, and either switch S1 or switch S4 is on.

When switch S1 is turned on, switches S2 and S4 are turned off, and current (iL > 0) flows through switch S1 and diode D3 (see solid arrow).

When switch S4 is turned on, switches S1 and S3 are turned off, and current (iL > 0) flows through switch S4 and diode D2 (see dashed arrow).

When current iL circulates in the DC-AC conversion unit 51 in this manner, referring also to Figure 6, the primary side voltage VA takes on a value of 0.

Referring to Table 1, in current path mode M23, switches S6 and S7 are off. Current (I>0) flows from the secondary coil L2 via diodes D5 and D8 to charge capacitor Co. At this time, also referring to Figure 6, the secondary voltage VB is equal to the output voltage Vo.

Figure 12 shows the current path when current path mode M31 is adopted. In current path mode M31, leakage inductance Ls serves as a current source, and current (iL > 0) is regenerated to capacitor Cb.

Referring to Table 1, in current path mode M31, switches Sr, S1, and S4 are off, and current (Ic = -iL < 0) flows from the primary coil L1 and leakage inductance Ls to capacitor Cb via diodes D3, Dc, and D2. This can be said to be charging capacitor Cb with regenerative current from DAB converter 5 via diode Dc. At this time, referring also to Figure 6, the primary voltage VA takes on a voltage value (-Vc).

Referring to Table 1, in current path mode M31, switches S6 and S7 are off, and the current (I>0) flowing through the secondary coil L2 charges capacitor Co via diodes D5 and D8. At this time, also referring to Figure 6, the secondary voltage VB is equal to the output voltage Vo.

Figure 13 shows the current path when current path mode M32 is adopted. In current path mode M32, capacitor Cb acts as a voltage source, causing current (iL < 0) to flow through primary coil L1 and leakage inductance Ls.

Referring to Table 1, in current path mode M32, switches Sr, S1, and S4 are off, and switches Sc, S2, and S3 are on. Current (Ic = -iL > 0) flows from capacitor Cb via switches Sc, S2, and S3 to primary coil L1 and leakage inductance Ls (discharging capacitor Cb). Also referring to Figure 6, at this time, primary voltage VA takes on a voltage value of (-Vc).

Referring to Table 1, in current path mode M32, switches S6 and S7 are off and switches S5 and S8 are on. Current (I<0) flows from capacitor Co to secondary coil L2 via switches S5 and S8 (discharging of capacitor Co). At this time, also referring to Figure 6, secondary voltage VB is equal to output voltage Vo.

Figure 14 shows the current path when current path mode M41 is adopted. In current path mode M41, capacitor Cb serves as a voltage source, causing current (iL < 0) to flow through primary coil L1 and leakage inductance Ls.

Referring to Table 1, in current path mode M41, switches Sr, S1, and S4 are off, and switches Sc, S2, and S3 are on. Current (Ic = -iL > 0) flows from capacitor Cb to primary coil L1 and leakage inductance Ls via switches Sc, S2, and S3 (discharging capacitor Cb). Also referring to Figure 6, at this time, primary voltage VA takes on a voltage value of (-Vc).

Referring to Table 1, in current path mode M41, switches S5 and S8 are off. Current (I>0) flows from the secondary coil L2 via diodes D6 and D7, charging capacitor Co. Also referring to Figure 6, at this time, the secondary voltage VB takes on a voltage value of -Vo.

Figure 15 shows the current path when current path mode M42 is adopted. In current path mode M42, rectifier circuit 2 serves as a voltage source, causing current (iL < 0) to flow through primary coil L1 and leakage inductance Ls via filter 3 and diode Dr.

Referring to Table 1, in current path mode M42, switches Sc, S1, and S4 are off, and switches Sr, S2, and S3 are on. Current (Ir = -iL > 0) flows from filter 3 to primary coil L1 and leakage inductance Ls via diode Dr and switches S2 and S3. At this time, referring also to Figure 6, primary voltage VA takes on a voltage value (-Vrec).

Referring to Table 1, in current path mode M42, switches S5 and S8 are off. Current (I>0) flows from the secondary coil L2 via diodes D6 and D7, charging capacitor Co. Also referring to Figure 6, at this time, the secondary voltage VB takes on a voltage value of -Vo.

Figure 16 shows the current path when current path mode M43 is adopted. In current path mode M43, current (iL < 0) circulates within the DC-AC conversion unit 51.

Referring to Table 1, in current path mode M43, switches Sc and Sr are off, and either switch S2 or switch S3 is on.

When switch S2 is turned on, switches S1 and S3 are turned off, and current (iL < 0) flows through switch S2 and diode D4 (see solid arrow).

When switch S3 is turned on, switches S2 and S4 are turned off, and current iL (<0) flows through switch S3 and diode D1 (see dashed arrow).

When current iL circulates in the DC-AC conversion unit 51 in this manner, referring also to Figure 6, the primary side voltage VA takes on a value of 0.

Referring to Table 1, in current path mode M43, switches S5 and S8 are off. Current (I>0) flows from the secondary coil L2 via diodes D6 and D7, charging capacitor Co. At this time, also referring to Figure 6, the secondary voltage VB takes on a voltage value (-Vo).

As described above, by adopting current path modes M11, M12, M21, M22, M23, M31, M32, M41, M42, and M43 in this order during period T, the secondary side voltage VB lags the primary side voltage VA by a phase difference φ. The switching timing that realizes current path modes M11, M12, M21, M22, M23, M31, M32, M41, M42, and M43 is set based on the phase difference φ adopted to perform the desired power conversion.

<Setting the phase difference φ>
Equations 7 to 28 derive an equation for setting the phase difference φ when the phase difference φ is equal to or less than the product dc·T/2. Referring to FIG. 6, the current iL takes on a value i(tj) at time tj (j=an integer between 0 and 10). Equation (7) is set by introducing current differences ΔIL1, ΔIL2, ΔIL3, and ΔIL4.

Referring to Figures 6 to 16, the transformer 50 is represented by an equivalent circuit using an ideal transformer including a primary coil L1 and a secondary coil L2 with a turns ratio of 1, and a leakage inductance Ls. The leakage inductance Ls is the sum of the leakage inductance on the secondary side of the transformer 50 converted to the primary side and the leakage inductance on the primary side of the transformer 50. An inductance L equal to the leakage inductance Ls in the equivalent circuit is introduced, and equation (8) is obtained by also taking into account the output voltage Vo.

Equation (9) can be obtained from equations (7) and (8). However, the voltage Vdc is introduced using equation (10).

By introducing the angular frequency ω = 2π/T, we obtain equation (11).

Equation (12) can be obtained from equations (9) and (11).

Equation (13) is obtained from equations (7), (8), and (12).

If we approximate that the current iL increases linearly during period T1, then equations (14) and (15) hold.

Taking into account periods Tca and Tra, times t0, t1, t2, t3, t4, and t5 are expressed by equation (16).

Equation (17) is obtained from equations (11), (13), and (15).

Therefore, the charge Q11 that moves between the transformer 50 and the capacitor Co by the current path mode M11 between time t0 and time t1 is given by equation (18).

The charge Q12 that moves between the transformer 50 and the capacitor Co due to the current path mode M12 between time t1 and time t2 is given by equation (19) using equations (15) and (17).

Equation (20) is obtained from equations (11) and (13).

Therefore, the charge Q21 that moves between the transformer 50 and the capacitor Co by the current path mode M21 between time t2 and time t3 is given by equation (21).

Equation (22) can be obtained from equation (13).

Therefore, the charge Q22 that moves between the transformer 50 and the capacitor Co by the current path mode M22 between time t3 and time t4 is given by equation (23).

Equation (24) can be obtained from equation (13).

Therefore, the charge Q23 that moves between the transformer 50 and the capacitor Co by the current path mode M23 between time t4 and time t5 is given by equation (25).

The charges Q11, Q21, Q22, and Q23 charge the capacitor Co (see Figures 7, 9, 10, and 11), and the charge Q12 discharges the capacitor Co (Figure 8). Therefore, the charge Q that contributes to charging the capacitor Co during periods T1 and T2 is calculated using equation (26).

As can be seen from the waveforms illustrated in Figure 6 and the current paths illustrated in Figures 7 to 16, the waveform of current iL during periods T3 and T4, the latter half of cycle T, is symmetrical in terms of positive and negative sign to current iL during periods T1 and T2, the former half of cycle T. This symmetry is obtained regardless of the power supply phase θ. For example, i(t6) = -i(t1) = 0, i(t7) = -i(t2), i(t8) = -i(t3), i(t9) = -i(t4), i(t10) = -i(t5), and the charge Q contributing to charging capacitor Co during periods T3 and T4 is calculated using equation (26). Introducing a control frequency f (= ω/(2π)), which is the reciprocal of cycle T, the current I flowing through capacitor Co is calculated using equation (27).

From equation (27), equation (28) is obtained by defining the phase difference φ as a function of the current I.

Figure 17 is a graph illustrating the relationship between the power supply phase θ and the phase difference φ based on equation (28). However, Figure 17 illustrates the case where k = 1/2 and the quantities are set as in equation (29).

Figure 18 is a graph illustrating the relationship between the power supply phase θ and the average value Ioa when the phase difference φ is fixed at 20 degrees. The average value Ioa is the average of the current I flowing through the capacitor Co over a period T. However, like Figure 17, Figure 18 also shows a case where the relationship φ≦dc·T/2 exists, and current path modes M11, M12, M21, M22, and M23 are adopted in this order during the first half period (T/2) of period T, and current path modes M31, M32, M41, M42, and M43 are adopted in this order during the second half period (T/2).

Figures 19 and 20 are graphs illustrating the relationship between the power supply phase θ and various quantities. In Figure 19, the top row shows the waveforms of voltage V1 and its average voltage V1a. Average voltage V1a is the average value of voltage V1 over period T. The second row from the top shows the waveform of current iL. The third row from the top shows the waveform of average value Ioa. The fourth row from the top (bottom row) shows the waveform of input current Ii and the waveforms of average currents Ira and Iba. Average current Ira is the average value of current Ir over period T. Average current Iba is the average value of inductor current Ib over period T.

In Figure 20, the top row shows the waveforms of voltage V1 and its average voltage V1a. The second row from the top shows the waveform of phase difference φ. The third row from the top shows the waveform of current iL. The fourth row from the top shows the waveform of average value Ioa. The fifth row from the top (bottom row) shows the waveform of input current Ii and the waveforms of average currents Ira and Iba.

In Figures 19 and 20, as in Figures 17 and 18, the relationship φ≦dc·T/2 exists, and the current path modes M11, M12, M21, M22, and M23 are adopted in this order during the first half cycle (T/2) of cycle T, and the current path modes M31, M32, M41, M42, and M43 are adopted in this order during the second half cycle (T/2).

Figure 19 shows the case where the phase difference φ is fixed at 20 degrees, while Figure 20 shows the case where the phase difference φ is set based on equations (28) and (29). It can be seen from Figures 19 and 20 that the average value Ioa is more stable and there is less distortion in the waveform of the input current Ii when the phase difference φ is set using equations (28) and (29) than when the phase difference φ is fixed.

From equation (28) and FIG. 17, the control circuit 9 determines for the DAB converter 5:
fluctuating the phase difference φ with a frequency component twice the frequency of the single-phase AC voltage Vi;
In other words, the phase difference φ at the power supply phase θ (= 2n + 1π/2) where the ripple voltage Vrec is at its maximum is made larger than the phase difference φ at the phase of the single-phase AC voltage (θ = nπ) where the ripple voltage Vrec is at its minimum.

In the first sequence, the control circuit 9 causes the active buffer circuit 4D to flow a current iL, which alternates between positive and negative symmetrical waveforms every half of the control period T of the DAB converter 5, to the primary side of the transformer 50, regardless of the power supply phase θ.

The fact that the waveform of current iL exhibits positive and negative symmetry between the first and second halves of the control period T has the advantage of simplifying control based on the power supply phase θ compared to the approximation of the equivalent square waveform introduced in Patent Document 1, which assumes asymmetry.

<Second Sequence>
<Waveforms of current iL, primary voltage VA, and secondary voltage VB>
21 is a graph illustrating the waveforms of the current iL, the primary side voltage VA, and the secondary side voltage VB. Fig. 21 illustrates a case where the phase difference φ is equal to or less than half the product drec·T of the rectification duty drec and the period T (the product drec·T/2 of the half period T/2 and the rectification duty drec).

As in the example in Figure 6, switching in the power conversion device 101 is controlled periodically with a period T. In Figure 21, period T starts at time t0 and ends at time t10. Time t0 is the start of period T, and time t10 is the end of period T. The length from time t0 to time t5 is equal to the length from time t5 to time t10. Time t5 is the midpoint of period T.

For convenience, the following explanation will be given assuming that time t0 corresponds to phase 0 of cycle T, time t5 corresponds to phase π of cycle T, and time t10 corresponds to phase 2π of cycle T. However, times t1, t2, t3, t4, t6, t7, t8, and t9 in the second sequence do not necessarily correspond to those in the first sequence.

Cycle T is divided into periods T5, T6, T7, and T8.

Period T5 begins at time t0, passes through time t1, and ends at time t2. Time t0 is the beginning of period T5, and time t2 is the end of period T5.

Period T6 begins at time t2, passes through times t3 and t4 in that order, and ends at time t5. Time t2 is the beginning of period T6, and time t5 is the end of period T6.

Period T7 begins at time t5, passes through time t6, and ends at time t7. Time t5 is the beginning of period T7, and time t7 is the end of period T7.

Period T8 begins at time t7, passes through times t8 and t9 in that order, and ends at time t10. Time t7 is the start of period T8, and time t10 is the end of period T8.

The period T is divided into periods Trc, Tcc, Tzc, Trd, Tcd, and Tzd.

The period Trc begins at time t0, passes through times t1 and t2, and ends at time t3. Time t0 is the beginning of the period Trc, and time t3 is the end of the period Trc.

The period Tcc begins at time t3 and ends at time t4. Time t3 is the beginning of the period Tcc, and time t4 is the end of the period Tcc.

The period Tzc begins at time t4 and ends at time t5. Time t4 is the beginning of the period Tzc, and time t5 is the end of the period Tzc.

The period Trd begins at time t5, passes through times t6 and t7, and ends at time t8. Time t5 is the beginning of the period Trd, and time t8 is the end of the period Trd.

The period Tcd begins at time t8 and ends at time t9. Time t8 is the beginning of the period Tcd, and time t9 is the end of the period Tcd.

The period Tzd begins at time t9 and ends at time t10. Time t9 is the beginning of the period Tzd, and time t10 is the end of the period Tzd.

During period Trc, the primary side voltage VA is the pulsating voltage Vrec. During period Tcc, the primary side voltage VA is the capacitor voltage Vc. During period Trd, the primary side voltage VA is at a voltage value (-Vrec). During period Tcd, the primary side voltage VA is at a voltage value (-Vc). During periods Tzc and Tzd, the primary side voltage VA is at a value of 0.

The length of each of the periods Trc and Trd is equal to half the product drec·T of the rectification duty drec and the period T (the product drec·T/2 of the half period T/2 and the rectification duty drec).

The length of each of periods Tcc and Tcd is equal to half the product dc·T of the discharge duty dc and the period T (the product dc·T/2 of the half period T/2 and the discharge duty dc).

The length of each of the periods Tzc and Tzc is equal to half the product dz·T of the zero duty dz and the period T (the product dz·T/2 of the half period T/2 and the zero duty dz).

From time t2 through times t3, t4, t5, and t6 until time t7, the secondary side voltage VB maintains the output voltage Vo. During periods T6 and T7, the secondary side voltage VB maintains the output voltage Vo.

The secondary side voltage VB maintains a voltage value (-Vo) from time t0 through time t1 to time t2, and from time t7 through times t8 and t9 to time t10. During periods T5 and T8, the secondary side voltage VB maintains a voltage value (-Vo).

<Current flow path>
Table 2 shows examples of current path modes M51, M52, M61, M62, M63, M71, M72, M81, M82, and M83 and the ON/OFF relationships of the switches that realize these modes. The current path modes M51, M52, M61, M62, M63, M71, M72, M81, M82, and M83 represent various path patterns of the current flowing through the DAB converter 5.

The symbols ON (Dr), ON (Dc), ON (D1), ON (D2), ON (D3), ON (D4), ON (D5), ON (D6), ON (D7), and ON (D8) in Table 2 are synonymous with the notations in Table 1. The correspondence between these symbols and the on/off states of switches Sr, Sc, S1, S2, S3, S4, S5, S6, S7, and S8 is also the same as in the first sequence.

Table 2 lists the positive and negative values of current iL for each current path mode: M51, M52, M61, M62, M63, M71, M72, M81, M82, and M83.

Figure 21 also shows the periods during cycle T during which current path modes M51, M52, M61, M62, M63, M71, M72, M81, M82, and M83 are adopted.

The current path mode M51 is adopted during the period from time t0 to time t1;
The current path mode M52 is adopted during the period from time t1 to time t2;
The current path mode M61 is adopted during the period from time t2 to time t3;
The current path mode M62 is adopted during the period from time t3 to time t4;
Current path mode M63 is adopted during the period from time t4 to time t5;
Current path mode M71 is adopted during the period from time t5 to time t6;
Current path mode M72 is adopted during the period from time t6 to time t7;
The current path mode M81 is adopted during the period from time t7 to time t8;
Current path mode M82 is adopted during the period from time t8 to time t9;
The current path mode M83 is employed during the period from time t9 to time t10.

In the first half cycle (T/2) of cycle T, current path modes M51, M52, M61, M62, and M63 are adopted in this order. In the second half cycle (T/2) of cycle T, current path modes M71, M72, M81, M82, and M83 are adopted in this order.

The switches Sr, Sc, S1, S2, S3, S4, S5, S6, S7, and S8 used to realize these current path modes M51, M52, M61, M62, M63, M71, M72, M81, M82, and M83 are controlled by switching signals SSr, SSc, SS1, SS2, SS3, SS4, SS5, SS6, SS7, and SS8, respectively.

The generation of switching signals SSr, SSc, SS1, SS2, SS3, SS4, SS5, SS6, SS7, and SS8 in the second sequence is illustrated by the graph shown in Figure 5. However, the inversion of switching signals SS1, SS4, SS5, and SS8 is indicated by an overline next to their symbols.

Specifically, during period Trc, switching signals SSr and SSc take on logic "H" and "L," respectively, turning switches Sr and Sc on and off, respectively. As mentioned above, switch Sr may be on when the symbol "ON (Dr)" is shown in Table 2, thereby realizing operation of active buffer circuit 4 from times t0 to t3, which corresponds to period Trc. The same is true for times t5 to t8, which corresponds to period Trd.

During period Tcc, switching signals SSr and SSc assume logic "L" and "H," respectively, turning switches Sr and Sc off and on, respectively. This enables the active buffer circuit 4 to operate from times t3 to t4, which corresponds to period Tcc. The same is true for times t8 to t9, which corresponds to period Tcd.

During period Tzc, both switching signals SSr and SSc are logic "L," turning off both switches Sr and Sc. This enables the active buffer circuit 4 to operate from times t4 to t5, which corresponds to period Tzc. The same is true for times t9 to t10, which corresponds to period Tzd.

Figures 22 to 31 are circuit diagrams illustrating a portion of the power conversion device 101, with arrows indicating the path of current flowing through the DAB converter 5. These figures show the active buffer circuit 4, DAB converter 5, and capacitors Ci and Co of the power conversion device 101.

Figure 22 shows the current path when current path mode M51 is adopted. In current path mode M51, leakage inductance Ls serves as a current source, and current (iL < 0) is regenerated to capacitor Ci.

Referring to Table 2, in current path mode M51, switches Sc, S2, and S3 are off, and switch Sr is on. Current (iL < 0) flows from the primary coil L1 and leakage inductance Ls to capacitor Ci via diodes D1 and D4 and switch Sr. This can be said to be charging capacitor Ci with regenerative current from DAB converter 5 via switch Sr. At this time, referring also to Figure 21, the primary voltage VA takes on the pulsating voltage Vrec.

Referring to Table 2, in current path mode M51, switches S5 and S8 are off, and the current flowing through the secondary coil L2 charges capacitor Co via diodes D6 and D7. At this time, also referring to Figure 21, the secondary voltage VB takes on a voltage value (-Vo).

Figure 23 shows the current path when current path mode M52 is adopted. In current path mode M52, rectifier circuit 2 serves as a voltage source, causing current (iL > 0) to flow through primary coil L1 via filter 3 and diode Dr.

Referring to Table 2, in current path mode M52, switches Sc, S2, and S3 are off, and switches S1 and S4 are on. Current (iL = Ir > 0) flows from filter 3 to primary coil L1 and leakage inductance Ls via diode Dr and switches S1 and S4. At this time, referring also to Figure 21, primary voltage VA is pulsating voltage Vrec.

Referring to Table 2, in current path mode M52, switches S5 and S8 are off and switches S6 and S7 are on. Current (I<0) flows from capacitor Co to secondary coil L2 via switches S6 and S7 (discharging of capacitor Co). At this time, also referring to Figure 21, secondary voltage VB takes on a voltage value of (-Vo).

Figure 24 shows the current path when current path mode M61 is adopted. In current path mode M61, current flows in the same way as in current path mode M22 (see Figure 10) in the first sequence. Specifically, in current path mode M61, rectifier circuit 2 serves as a voltage source, causing current (Ir = iL > 0) to flow through primary coil L1 and leakage inductance Ls via filter 3 and diode Dr.

Referring to Table 2, in current path mode M61, switches Sc, S2, and S3 are off, and switches S1 and S4 are on. Current iL flows from filter 3 to primary coil L1 and leakage inductance Ls via diode Dr and switches S1 and S4. At this time, also referring to Figure 21, primary voltage VA takes on pulsating voltage Vrec.

Referring to Table 2, in current path mode M61, switches S6 and S7 are off. Current (I>0) flows from the secondary coil L2 via diodes D5 and D8 to charge capacitor Co. At this time, also referring to Figure 21, the secondary voltage VB is equal to the output voltage Vo.

Figure 25 shows the current path when current path mode M62 is adopted. In current path mode M62, current flows in the same way as in current path mode M21 (see Figure 9) in the first sequence. Specifically, in current path mode M62, capacitor Cb serves as a voltage source, causing current (iL > 0) to flow through primary coil L1 and leakage inductance Ls.

Referring to Table 2, in current path mode M62, switches Sr, S2, and S3 are off, and switches Sc, S1, and S4 are on. Current (Ic = iL > 0) flows from capacitor Cb to primary coil L1 and leakage inductance Ls via switches Sc, S1, and S4 (discharging capacitor Cb). Also referring to Figure 21, at this time, primary voltage VA takes on capacitor voltage Vc.

Referring to Table 2, in current path mode M62, switches S6 and S7 are off. Current (I>0) flows from the secondary coil L2 via diodes D5 and D8 to charge capacitor Co. At this time, also referring to Figure 21, the secondary voltage VB is equal to the output voltage Vo.

Figure 26 shows the current path when current path mode M63 is adopted. In current path mode M63, current flows in the same way as in current path mode M23 in the first sequence (see Figure 11). Specifically, in current path mode M63, current (iL > 0) circulates within the DC-AC conversion unit 51.

Referring to Table 2, in current path mode M63, switches Sc and Sr are off, and either switch S1 or switch S4 is on.

When switch S1 is turned on, switches S2 and S4 are turned off, and current iL flows through switch S1 and diode D3 (see solid arrow).

When switch S4 is turned on, switches S1 and S3 are turned off, and current iL flows through switch S4 and diode D2 (see dashed arrow).

When current iL circulates in the DC-AC conversion unit 51 in this manner, referring also to Figure 21, the primary side voltage VA takes on a value of 0.

Referring to Table 2, in current path mode M63, switches S6 and S7 are off. Current (I>0) flows from the secondary coil L2 via diodes D5 and D8 to charge capacitor Co. At this time, also referring to Figure 21, the secondary voltage VB is equal to the output voltage Vo.

Figure 27 shows the current path when current path mode M71 is adopted. In current path mode M71, leakage inductance Ls serves as a current source, and current (iL > 0) is regenerated to capacitor Ci.

Referring to Table 2, in current path mode M71, switches Sc, S1, and S4 are off and switch Sr is on. Current (Ir = -iL < 0) flows from the primary coil L1 and leakage inductance Ls to capacitor Ci via diodes D2 and D3 and switch Sr. This can be said to be charging capacitor Ci with regenerative current from DAB converter 5 via switch Sr. At this time, referring also to Figure 21, the primary voltage VA takes on a voltage value (-Vrec).

Referring to Table 2, in current path mode M71, switches S6 and S7 are off, and the current (I>0) flowing through the secondary coil L2 charges capacitor Co via diodes D5 and D8. At this time, also referring to Figure 21, the secondary voltage VB is equal to the output voltage Vo.

Figure 28 shows the current path when current path mode M72 is adopted. In current path mode M72, rectifier circuit 2 serves as a voltage source, causing current (iL < 0) to flow through primary coil L1 and leakage inductance Ls via filter 3 and diode Dr.

Referring to Table 2, in current path mode M72, switches Sc, S1, and S4 are off, and switches S2 and S3 are on. Current (Ir = -iL > 0) flows from filter 3 to primary coil L1 and leakage inductance Ls via diode Dr and switches S2 and S3. At this time, referring also to Figure 21, primary voltage VA takes on a voltage value (-Vrec).

Referring to Table 2, in current path mode M72, switches S6 and S7 are off and switches S5 and S8 are on. Current (I<0) flows from capacitor Co to secondary coil L2 via switches S5 and S8 (discharging of capacitor Co). At this time, also referring to Figure 21, secondary voltage VB is equal to output voltage Vo.

Figure 29 shows the current path when current path mode M81 is adopted. In current path mode M81, current flows in the same way as in current path mode M42 (see Figure 15) in the first sequence. Specifically, in current path mode M81, rectifier circuit 2 serves as a voltage source, causing current (iL < 0) to flow through primary coil L1 and leakage inductance Ls via filter 3 and diode Dr.

Referring to Table 2, in current path mode M81, switches Sc, S1, and S4 are off, and switches Sc, S2, and S3 are on. Current (Ir = -iL > 0) flows from filter 3 to primary coil L1 and leakage inductance Ls via diode Dr and switches S2 and S3. At this time, referring also to Figure 21, primary voltage VA takes on a voltage value (-Vrec).

Referring to Table 2, in current path mode M81, switches S5 and S8 are off. Current (I>0) flows from the secondary coil L2 via diodes D6 and D7, charging capacitor Co. At this time, also referring to Figure 21, the secondary voltage VB takes on a voltage value of (-Vo).

Figure 30 shows the current path when current path mode M82 is adopted. In current path mode M82, current flows in the same way as in current path mode M41 (see Figure 14) in the first sequence. Specifically, in current path mode M82, capacitor Cb serves as a voltage source, causing current (iL < 0) to flow through primary coil L1 and leakage inductance Ls.

Referring to Table 2, in current path mode M82, switches Sr, S1, and S4 are off, and switches Sc, S2, and S3 are on. Current (Ic = -iL > 0) flows from capacitor Cb via switches Sc, S2, and S3 to primary coil L1 and leakage inductance Ls (discharging capacitor Cb). At this time, referring also to Figure 21, primary voltage VA takes on a voltage value (-Vc).

Referring to Table 2, in current path mode M82, switches S5 and S8 are off. Current (I>0) flows from the secondary coil L2 via diodes D6 and D7, charging capacitor Co. At this time, also referring to Figure 21, the secondary voltage VB takes on a voltage value of (-Vo).

Figure 31 shows the current path when current path mode M83 is adopted. In current path mode M63, current flows in the same way as in current path mode M43 in the first sequence (see Figure 16). Specifically, in current path mode M83, current (iL < 0) circulates within the DC-AC conversion unit 51.

Referring to Table 2, in current path mode M83, switches Sc and Sr are off, and either switch S2 or switch S3 is on.

When switch S2 is turned on, switches S1 and S3 are turned off, and current iL flows through switch S2 and diode D4 (see solid arrow).

When switch S3 is turned on, switches S2 and S4 are turned off, and current iL flows through switch S3 and diode D1 (see dashed arrow).

When current iL circulates in the DC-AC conversion unit 51 in this manner, referring also to Figure 21, the primary side voltage VA takes on a value of 0.

Referring to Table 2, in current path mode M83, switches S5 and S8 are off. Current (I>0) flows from the secondary coil L2 via diodes D6 and D7, charging capacitor Co. At this time, also referring to Figure 21, the secondary voltage VB takes on a voltage value of (-Vo).

As described above, by adopting current path modes M51, M52, M61, M62, M63, M71, M72, M81, M82, and M83 in this order during period T, the secondary side voltage VB lags the primary side voltage VA by a phase difference φ. The switching timing that realizes current path modes M51, M52, M61, M62, M63, M71, M72, M81, M82, and M83 is set based on the phase difference φ adopted to perform the desired power conversion.

<Setting the phase difference φ>
Equations 30 to 45 derive an equation for setting the phase difference φ when the phase difference φ is equal to or less than the product drec·T/2. Referring to FIG. 21, the current iL takes on a value i(tj) at time tj (j=an integer between 0 and 10). The current differences ΔIL1, ΔIL2, ΔIL3, and ΔIL4 are introduced to set the above equation (7).

Referring to Figures 21 to 31 and taking into account the output voltage Vo, equation (30) can be obtained.

Equation (31) can be obtained from equations (7) and (30). However, equation (10) has been introduced.

By introducing the angular frequency ω = 2π/T, we obtain equation (32).

Equation (12) is obtained from equations (31) and (32).

Equations (33) and (34) can be obtained in the same way as equations (13) to (16).

Equation (35) can be obtained in the same way as equation (17).

Therefore, the charge Q51 that moves between the transformer 50 and the capacitor Co by the current path mode M51 between time t0 and time t1 is given by equation (36).

The charge Q52 that moves between the transformer 50 and the capacitor Co by the current path mode M52 between time t1 and time t2 is given by equation (37) using equations (15) and (35).

Equation (38) is obtained from equations (11) and (34).

Therefore, the charge Q61 that moves between the transformer 50 and the capacitor Co by the current path mode M61 between time t2 and time t3 is given by equation (39).

Equation (40) is obtained from equation (34).

Therefore, the charge Q62 that moves between the transformer 50 and the capacitor Co by the current path mode M62 between time t3 and time t4 is given by equation (41).

Equation (42) is obtained from equation (34).

Therefore, the charge Q63 that moves between the transformer 50 and the capacitor Co by the current path mode M63 between time t4 and time t5 is given by equation (43).

Charges Q51, Q61, Q62, and Q63 charge capacitor Co (see Figures 22, 24, 25, and 26), and charge Q52 discharges capacitor Co (Figure 23). Therefore, the charge Q that contributes to charging capacitor Co during periods T5 and T6 is calculated using equation (44).

As can be seen from the waveforms illustrated in Figure 21 and the current paths illustrated in Figures 22 to 31, the current iL during periods T7 and T8 is symmetrical in terms of positive and negative relative to the current iL during periods T5 and T6, for example. This symmetry is obtained regardless of the power supply phase θ. For example, i(t6) = -i(t1), i(t7) = -i(t2), i(t8) = -i(t3) = 0, i(t9) = -i(t4), i(t10) = -i(t5), and the charge Q contributing to the charging of capacitor Co during periods T7 and T8 is calculated using equation (44). The current I flowing through capacitor Co is calculated using equation (45).

From equation (45), equation (46) is obtained by defining the phase difference φ as a function of the current I.

Figure 32 is a graph illustrating the relationship between the power supply phase θ and the phase difference φ based on equation (46). However, Figure 32 illustrates the case where the quantities are set as in equation (29).

Figure 33 is a graph illustrating the relationship between the power supply phase θ and the average value Ioa when the phase difference φ is fixed at 20 degrees. However, like Figure 32, Figure 33 also has the relationship φ≦drec·T/2, and the current path modes M51, M52, M61, M62, and M63 are adopted in this order during the first half cycle (T/2) of cycle T, and the current path modes M71, M72, M81, M82, and M83 are adopted in this order during the second half cycle (T/2).

Figures 34 and 35 are graphs illustrating the relationship between the power supply phase θ and various quantities. In each of Figures 34 and 35, the top row shows the voltage V1 and its average voltage V1a. The second row from the top shows the current iL. The third row from the top shows the average value Ioa. The fourth row from the top (bottom row) shows the waveform of the input current Ii and the average currents Ira and Iba.

In Figures 34 and 35, as in Figures 32 and 33, the relationship φ≦drec·T/2 exists, and the current path modes M51, M52, M61, M62, and M63 are adopted in this order during the first half period (T/2) of period T, and the current path modes M71, M72, M81, M82, and M83 are adopted in this order during the second half period (T/2).

Figure 34 shows the case where the phase difference φ is fixed at 20 degrees, while Figure 35 shows the case where the phase difference φ is set based on equations (46) and (29). It can be seen from Figures 34 and 35 that the average value Ioa is more stable and there is less distortion in the waveform of the input current Ii when the phase difference φ is set using equations (46) and (29) than when the phase difference φ is fixed.

As mentioned above, when the single-phase AC voltage Vi is expressed as Vm sin(ωt), the phase ωt is the power supply phase θ. By introducing the integer n, the pulsating voltage Vrec reaches a maximum when θ = (2n + 1) π/2, and reaches a minimum when θ = 2n π/2.

As illustrated in Figure 3, the rectification duty drec reaches a maximum at θ = (2n + 1) · π/2 and a minimum at θ = 2n · π/2. The discharge duty dc reaches a minimum at θ = (2n + 1) · π/2 and a maximum at θ = 2n · π/2.

When the pulsating voltage Vrec reaches its maximum, the rectification duty drec reaches its maximum and the discharge duty dc reaches its minimum. When the pulsating voltage Vrec reaches its minimum, the rectification duty drec reaches its minimum and the discharge duty dc reaches its maximum.

From equation (46) and FIG. 32, the control circuit 9 determines for the DAB converter 5:
fluctuating the phase difference φ with a frequency component twice the frequency of the single-phase AC voltage Vi;
In other words, the phase difference φ at the power supply phase θ (= 2n + 1π/2) where the ripple voltage Vrec is at its maximum is made larger than the phase difference φ at the phase of the single-phase AC voltage (θ = nπ) where the ripple voltage Vrec is at its minimum.

Furthermore, the control circuit 9 controls the DAB converter 5 to:
fluctuating the phase difference φ with a frequency component four times the frequency of the single-phase AC voltage Vi;
The phase difference φ is made to take a minimum value at the phase (θ=2n+1π/2) of the single-phase AC voltage Vi where the pulsating voltage Vrec is maximized;
In other words, the phase difference φ is made to take on a maximum value at the power supply phase θ between the phase (θ=nπ) of the single-phase AC voltage Vi at which the pulsating voltage Vrec is minimum and the power supply phase θ (=2n+1π/2) at which the pulsating voltage Vrec is maximum.

In the second sequence, the control circuit 9 also causes the active buffer circuit 4D to pass a current iL, which alternates between positive and negative symmetrical waveforms every half of the control period T of the DAB converter 5, to the primary side of the transformer 50, regardless of the power supply phase θ. This symmetry in the second sequence also provides the same advantages as the symmetry of the current iL in the first sequence.

<Whether Switch Sr is Conductive or Not in the First Sequence>
In the first sequence, the capacitor voltage Vc is utilized when the positive current iL supplies energy to the leakage inductance Ls. At and near the power supply phase θ where the ripple voltage Vrec is maximized, the period in which the capacitor voltage Vc is utilized is short and the period in which the ripple voltage Vrec is utilized is long.

When controlling using the first sequence, when the power supply phase θ is (2n+1)·π/2 and in the vicinity thereof, there is a possibility that the phase difference φ will deviate from the case assumed in the first sequence where the product is dc·T/2 or less.

Figure 36, like Figure 20, is a graph illustrating the relationship between the power supply phase θ and various quantities. In Figure 36, the top row shows the waveforms of voltage V1 and its average voltage V1a. The second row from the top shows the waveform of phase difference φ. The third row from the top shows the waveform of current iL. The fourth row from the top shows the waveform of current Ir. The fifth row from the top shows the waveform of current Ic. The sixth row from the top shows the waveform of average value Ioa. The seventh row from the top (bottom row) shows the waveform of input current Ii and the waveforms of average currents Ira and Iba.

Figure 36 shows the quantities when the power supply phase θ is in the range of 0 to 180 degrees, as an example when the power supply phase θ is between 2n·π and (2n+1)·π. Range G1 encompasses the waveform of current Ir when the power supply phase θ is (2n+1)·π/2 or nearby (as exemplified when the power supply phase θ is 90 degrees or nearby).

In range G1, the period Tca (see Figure 6) becomes significantly shorter, and current Ir can take a negative value. At this time, current Ir flows through switch Sr. When current Ir takes a negative value, average current Ira decreases, and distortion of input current Ii increases.

Figure 37 is a graph illustrating the waveforms of current iL, primary side voltage VA, and secondary side voltage VB when the power supply phase θ is (2n+1)·π/2 in the first sequence.

As can be seen from equation (29) and Figure 3, when the power supply phase θ is (2n+1)·π/2, the discharge duty dc is 0. At this time, the lengths of periods Tca and Tcb (see Figure 6) are 0. As a result, the period during which the primary side voltage VA is at the capacitor voltage Vc and the period during which the primary side voltage VA is at the voltage (-Vc) are both essentially zero (for convenience, in Figure 37, both the period during which the primary side voltage VA is at the capacitor voltage Vc and the period during which the primary side voltage VA is at the voltage (-Vc) are drawn as lines).

When the discharge duty dc is set to 0, time t3, which marks the start of period Tra, coincides with time t2, which marks the end of period T1. During period T1, the primary side voltage VA is the pulsating voltage Vrec, just as it was during period Tra.

In period T1, current path mode M13 appears from time t0 to t1, and current path mode M14 appears from time t1 to t2 (= t3).

Because the discharge duty dc is set to 0, time t8, which marks the start of period Trb, coincides with time t7, which marks the end of period T3. During period T3, the primary side voltage VA is at a voltage (-Vrec), just as it was during period Trb.

In period T3, current path mode M33 appears from times t5 to t6, and current path mode M34 appears from times t6 to t7 (= t8).

Table 3 shows examples of current path modes M13, M14, M22, M23, M33, M34, M42, and M43, and the ON/OFF relationships of each switch that realize these modes. Current path modes M13, M14, M22, M23, M33, M34, M42, and M43 represent various path patterns for the current flowing through the DAB converter 5.

The symbols ON (Dr), ON (D1), ON (D2), ON (D3), ON (D4), ON (D5), ON (D6), ON (D7), and ON (D8) in Table 3 are synonymous with the notations in Table 1. The correspondence between these symbols and the on/off states of switches Sr, S1, S2, S3, S4, S5, S6, S7, and S8 is also the same as in the first sequence.

Table 3 lists the positive and negative values of current iL for each current path mode: M13, M14, M22, M23, M33, M34, M42, and M43.

Figures 38 to 41 are circuit diagrams illustrating a portion of the power conversion device 101, with arrows indicating the path of current flowing through the DAB converter 5. These figures show the active buffer circuit 4, DAB converter 5, and capacitors Ci and Co of the power conversion device 101.

Figure 38 shows the current path when current path mode M13 appears. This current path is the same as the path through which current flows in current path mode M51.

Figure 39 shows the current path when current path mode M14 appears. This current path is the same as the path through which current flows in current path mode M52.

Figure 40 shows the current path when current path mode M33 appears. This current path is the same as the path through which current flows in current path mode M71.

Figure 41 shows the current path when current path mode M34 occurs. This current path is the same as the path through which current flows in current path mode M72.

As can be seen from the explanation using Table 1, current path modes M11, M12, M21, M22, M23, M31, M32, M41, M42, and M43 are realized even if switch Sr is not turned on. As can be seen from Figure 37 and Table 3, in current path modes M13 and M33, current Ir flows through switch Sr rather than diode Dr.

Therefore, not turning on switch Sr regardless of the power supply phase θ contributes to suppressing the decrease in average current Ira caused by current Ir taking a negative value, and ultimately the increase in distortion of input current Ii.

In current path modes M13 and M33, the current Ir (< 0) flowing through the switch Sr, which is turned on, becomes current Ic (< 0) when the switch Sr is turned off, and is used for regenerative operation to flow through diode Dc and charge capacitor Cb. This regenerative operation prevents current Ir from taking on negative values and, ultimately, helps prevent increased distortion in the input current Ii.

As can be seen from the waveforms illustrated in Figure 37, and the current paths illustrated in Figures 10, 11, and 15, as well as Figures 16, 38, and 41, the waveform of current iL during periods T3 and T4, the latter half of cycle T, is symmetrical in positive and negative to the waveform of current iL during periods T3 and T4, the former half of cycle T.

The advantage gained from the positive/negative symmetry of the waveform of current iL (see Figure 6) described in the <First Sequence> is not affected by whether switch Sr is conducting or not.

Figure 42, like Figure 36, is a graph illustrating the relationship between the power supply phase θ and various quantities. In Figure 42, the top row shows the waveforms of voltage V1 and its average voltage V1a. The second row from the top shows the waveform of phase difference φ. The third row from the top shows the waveform of current iL. The fourth row from the top shows the waveform of current Ir. The fifth row from the top shows the waveform of current Ic. The sixth row from the top shows the waveform of average value Ioa. The seventh row from the top (bottom row) shows the waveform of input current Ii and the waveforms of average currents Ira and Iba.

Figure 42 shows the quantities when the power supply phase θ is between 0 and 180 degrees, as an example when the power supply phase θ is between 2n·π and (2n+1)·π. However, as mentioned above, this shows the case where the switch Sr is not turned on, regardless of the power supply phase θ.

Range G2 encompasses the waveforms of voltage V1 and its average voltage V1a when the power supply phase θ is at or near (2n+1)·π/2 (as exemplified when the power supply phase θ is at or near 90 degrees). It can be seen that in range G2, the period during which voltage V1 is at the capacitor voltage Vc (here, 400 V: see equation (29)) is longer than when switch Sr is conductive (see Figure 36).

Range G3 encompasses the waveform of current Ic when the power supply phase θ is (2n+1)·π/2 or a value close to it (as exemplified by when the power supply phase θ is 90 degrees or a value close to it). In range G3, it can be seen that the period during which regenerated current Ic (<0) flows from the primary coil L1 and leakage inductance Ls to capacitor Cb via diode Dc is longer than when switch Sr is conductive (see Figure 36).

Range G4 encompasses the waveforms of the average current Ira and the input current Ii when the power supply phase θ is (2n+1)·π/2 or its vicinity (as exemplified when the power supply phase θ is 90 degrees or its vicinity). In range G4, the decrease in the average current Ira and the increase in distortion of the input current Ii are suppressed compared to when switch Sr is conductive (see Figure 36).

<Whether Switch Sr is Conductive or Not in the Second Sequence>
In the second sequence, the pulsating voltage Vrec is utilized when energy is supplied to the leakage inductance Ls by the positive current iL. At and near the power supply phase θ where the pulsating voltage Vrec is minimized, the period in which the pulsating voltage Vrec is utilized is short, and the period in which the capacitor voltage Vc is utilized is long.

When using control with the second sequence, when the power supply phase θ is (2n)·π/2 or in the vicinity thereof, there is a possibility that the phase difference φ will deviate from the case assumed by the second sequence where the product is drec·T/2 or less.

Like Figure 35, Figure 43 is a graph illustrating the relationship between the power supply phase θ and various quantities. In Figure 43, the top row shows the waveforms of voltage V1 and its average voltage V1a. The second row from the top shows the waveform of phase difference φ. The third row from the top shows the waveform of current iL. The fourth row from the top shows the waveform of current Ir. The fifth row from the top shows the waveform of current Ic. The sixth row from the top shows the waveform of average value Ioa. The seventh row from the top (bottom row) shows the waveform of input current Ii and the waveforms of average currents Ira and Iba.

Figure 43 shows the quantities when the power supply phase θ is between 0 and 180 degrees, as an example when the power supply phase θ is between 2n·π and (2n+1)·π. Range G5 encloses the waveform of current Ir when the power supply phase θ is at (2n)·π and its vicinity (an example when the power supply phase θ is at 0 degrees and its vicinity). Range G6 encloses the waveform of current Ir when the power supply phase θ is at (2n+1)·π and its vicinity (as exemplified when the power supply phase θ is at 180 degrees and its vicinity).

In ranges G5 and G6, the periods Trc and Trd (see Figure 21) are significantly shorter. The rate of increase of current iL in current path mode M51 is small, at (Vrec + Vo)/L, and as can be seen from Figure 32, the phase difference φ is also significantly small. Therefore, the period in which current path modes M51 and M52 appear is significantly shorter, the range over which average current Ira takes negative values is wide, and the input current Ii is also easily distorted.

Therefore, in the second sequence, as in the first sequence, not turning on switch Sr regardless of the power supply phase θ contributes to suppressing the decrease in average current Ira caused by current Ir taking a negative value, and ultimately to suppressing the increase in distortion of input current Ii.

In current path modes M51 and M71, the current Ir (< 0) flowing through the switch Sr, which is turned on, becomes the current Ic (< 0) flowing through the diode Dc when the switch Sr is turned off, and is used for regenerative operation to charge the capacitor Cb. This regenerative operation prevents the current Ir from taking on a negative value, thereby contributing to suppressing increased distortion in the input current Ii.

In current path modes M52, M61, M72, and M81, even if switch Sr is on, current Ir (>0) flows through diode Dr. Therefore, switch Sr does not need to be on between times t1 and t3 and between t6 and t8.

Table 4 illustrates current path modes M53, M52, M61, M62, M63, M73, M72, M81, M82, and M83, and the ON/OFF relationship of each switch that realizes them. However, switch Sr does not turn on but remains off. The ON/OFF of switch Sc in Table 4 matches the ON/OFF of switch Sc in Table 2.

Current path modes M53, M52, M61, M62, M63, M73, M72, M81, M82, and M83 represent various path patterns of current flowing through the DAB converter 5.

The symbols ON (D1), ON (D2), ON (D3), ON (D4), ON (D5), ON (D6), ON (D7), and ON (D8) in Table 4 are synonymous with the notations in Table 1. The correspondence between these symbols and the on/off states of switches S1, S2, S3, S4, S5, S6, S7, and S8 is also the same as in the first sequence.

The symbol OFF(Dr) in Table 4 indicates a situation in which switch Sr is off and current Ir(>0) flows through diode Dr. The symbol OFF(Dc) in Table 4 indicates a situation in which switch Sc is off and current Ic(<0) flows through diode Dc.

In current path modes M51 and M71, the current Ir (< 0) flowing through switch Sr, which is turned on, becomes current Ic (< 0) flowing through diode Dc when switch Sr is turned off, and is used for regenerative operation to charge capacitor Cb. This regenerative operation prevents current Ir from taking on negative values and, in turn, helps prevent increased distortion in input current Ii.

Table 4 lists the positive and negative values of current iL for each current path mode: M53, M52, M61, M62, M63, M73, M72, M81, M82, and M83.

Figure 44 is a graph illustrating the waveforms of current iL, primary side voltage VA, and secondary side voltage VB when switch Sr is not conductive regardless of the power supply phase θ in the second sequence. As can be seen from a comparison of Table 2 and Figure 21 with Table 4 and Figure 44, by not conducting switch Sr regardless of the power supply phase θ, current path modes M51 and M71 are changed to current path modes M53 and M73, respectively, while the other current path modes M52, M61, M62, M63, M72, M81, M82, and M83 remain unchanged.

Figures 45 and 46 are circuit diagrams illustrating a portion of the power conversion device 101, with arrows indicating the path of current flowing through the DAB converter 5. These figures show the active buffer circuit 4, DAB converter 5, and capacitors Ci and Co of the power conversion device 101.

Figure 45 shows the current path when current path mode M53 appears. This current path is the same as the path through which current flows in current path mode M11.

Figure 46 shows the current path when current path mode M73 appears. This current path is the same as the path through which current flows in current path mode M31.

Keeping switch Sr closed regardless of the power supply phase θ helps prevent a decrease in average current Ira caused by current Ir taking a negative value, thereby suppressing increased distortion in input current Ii. In current path modes M53 and M73, current Ir (< 0) flowing through switch Sr, which is turned on, is converted into current Ic (< 0) flowing through diode Dc when switch Sr is turned off, and is used for regenerative operation to charge capacitor Cb. This regenerative operation prevents current Ir from taking a negative value, thereby contributing to suppressing increased distortion in input current Ii.

As can be seen from the waveform illustrated in Figure 44 and the current paths illustrated in Figures 23 to 26, 28 to 31, 45, and 46, the waveform of current iL during periods T7 and T8, the latter half of cycle T, is symmetrical in positive and negative to the waveform of current iL during periods T5 and T6, the former half of cycle T, for example.

The advantage gained from the positive/negative symmetry of the waveform of current iL (see Figure 21) described in the <Second Sequence> is not affected by whether switch Sr is conductive or not.

Like Figure 43, Figure 47 is a graph illustrating the relationship between the power supply phase θ and various quantities. In Figure 42, the top row shows the waveforms of voltage V1 and its average voltage V1a. The second row from the top shows the waveform of phase difference φ. The third row from the top shows the waveform of current iL. The fourth row from the top shows the waveform of current Ir. The fifth row from the top shows the waveform of current Ic. The sixth row from the top shows the waveform of average value Ioa. The seventh row from the top (bottom row) shows the waveform of input current Ii and the waveforms of average currents Ira and Iba.

Figure 47 shows the quantities when the power supply phase θ is between 0 and 180 degrees, as an example when the power supply phase θ is between 2n·π and (2n+1)·π. However, it also shows a case where the switch Sr does not turn on, regardless of the power supply phase θ. In this case, current path modes M53 and M73 are used instead of current path modes M51 and M71, respectively. As a result, as described above, the distortion of the input current Ii in Figure 47 is reduced compared to the distortion of the input current Ii in Figure 43.

However, turning off switch Sr increases distortion in the primary voltage VA, as can be seen in Figure 44. This increased distortion leads to a decrease in the flatness of the average value Ioa, as can be seen in Figure 47.

<Switching Between First and Second Sequences>
When the power supply phase θ is n·π or its vicinity, φ≦dc·(T/2) is likely to hold, so it is desirable to adopt the first sequence in this case. When the power supply phase θ is (2n+1)·π or its vicinity, φ≦drec·(T/2) is likely to hold, so it is desirable to adopt the second sequence in this case. Therefore, switching between the first sequence and the second sequence depending on the power supply phase θ contributes to appropriate control of the power conversion device 101 in accordance with the respective assumptions of the first sequence and the second sequence.

Figure 48, like Figures 20 and 35, is a graph illustrating the relationship between the power supply phase θ and various quantities. In Figure 48, the top row shows the waveforms of voltage V1 and its average voltage V1a. The second row from the top shows the waveform of phase difference φ. The third row from the top shows the waveform of current iL. The fourth row from the top shows the waveform of average value Ioa. The fifth row from the top (bottom row) shows the waveform of input current Ii and the waveforms of average currents Ira and Iba.

The power supply phase θ is divided into ranges M1 and M2. Ranges M1 and M2 appear alternately. A pair of ranges M1 sandwiches one range M2, and a pair of ranges M2 sandwiches one range M1. In range M1, the power supply phase θ includes n·π and its vicinity. In range M2, the power supply phase θ(2n+1)·π and its vicinity. A first sequence is adopted in range M1, and a second sequence is adopted in range M2.

The phase difference φ is continuous at the boundary between ranges M1 and M2. The phase difference φ at this boundary satisfies both equations (28) and (46). If the condition of equation (29) is adopted and equations (28) and (46) are equal, the power supply phase θ that gives the phase difference φ at this boundary is 90°±15° and 270°±15°. In this case, range M1 occupies 0 to 75°, 105 to 255°, and 285 to 360°, while range M2 occupies 75 to 105° and 255 to 285°.

In both the first and second sequences, when the waveform of current iL exhibits positive and negative symmetry between the first and second halves of the control period T, switching between the first and second sequences does not affect the benefits of this symmetry. This is because this symmetry is obtained regardless of the power supply phase θ.

<Omission of Switch Sr (First Modification)>
As described in Tables 1 and 3 and Fig. 42, it is possible to control the power conversion device 101 even if the switch Sr is not turned on in the first sequence. As described in Tables 2 and 4 and Fig. 47, it is possible to control the power conversion device 101 even if the switch Sr is not turned on in the second sequence.

When the power conversion device 101 is controlled by switching between the first and second sequences as described above, it is easy to avoid the drawbacks resulting from regeneration to capacitor Cb via diode Dc. From this perspective, switch Sr may be omitted from the power conversion device 101, specifically from active buffer circuit 4D.

Figure 49 is a circuit diagram partially illustrating a first variant of the power conversion device 101. The first variant differs from the configuration shown in Figure 1 in that the active buffer circuit 4D is replaced with an active buffer circuit 4C, and the switching signal SSr output from the control circuit 9 is omitted.

Active buffer circuit 4C has a configuration in which switch Sr is omitted from active buffer circuit 4D, specifically, the open circuit is removed. By adopting this configuration, the switching signal SSr output from control circuit 9 is no longer necessary.

<Feedback Control (Second Variation)>
The following describes various characteristics when the feedback control block 930 is employed in the control circuit 9 and feedback control is performed on the output current Io.

Figures 50, 51, and 52 are all graphs illustrating the relationship between the power supply phase θ and various quantities when feedback control is performed (in the second variant).

Figure 50, like Figure 20, shows the quantities when the first sequence is adopted.

Figure 51, like Figure 35, shows the quantities when the second sequence is adopted.

Figure 52, like Figure 48, shows the quantities when the first sequence and the second sequence are alternately adopted.

From the waveforms of the average value Ioa shown in Figures 50, 51, and 52, it can be seen that feedback control contributes to stabilizing the output current Io.

<Modification Regarding the Position of the Low-Pass Filter (Third Modification)>
Fig. 53 is a circuit diagram partially showing a third modification of the power conversion device 101. The third modification differs from the configuration shown in Fig. 1 in that the active buffer circuit 4D is replaced with an active buffer circuit 4A, the rectifier circuit 23C is replaced with a rectifier circuit 23B, and the switching signal SSr output from the control circuit 9 is replaced with switching signals SSrp, SSrn, SSsp, and SSsn.

Active buffer circuit 4A differs from active buffer circuit 4D in that the diode Dr and switch Sr are removed, and the input side of active buffer circuit 4A has three points: the first power supply line LH, the second power supply line LL, and one end of inductor Lb.

If the connection between inductor Lb and the anode of diode Dr (see Figure 1) is made in rectifier circuit 23C rather than in active buffer circuit 4D, then diode Dr and switch Sr can be seen as being short-circuited out of active buffer circuit 4D, resulting in active buffer circuit 4A.

Rectifier circuit 23B is similar to rectifier circuit 23C in that it receives a single-phase AC voltage Vi and an input current Ii and outputs a pulsating voltage Vrec.

The rectifier circuit 23B has a bridge circuit 2B and a low-pass filter 3A. The low-pass filter 3A attenuates the high frequencies of the single-phase AC voltage Vi to obtain a filtered single-phase AC voltage Vif (hereinafter tentatively referred to as the "filtered single-phase AC voltage"). Specifically, the low-pass filter 3A has an inductor Li and a capacitor Ci. The series connection of the inductor Li and the capacitor Ci receives the single-phase AC voltage Vi, and the filtered single-phase AC voltage Vif is obtained at the capacitor Ci.

Bridge circuit 2B is a full-wave rectifier bridge that receives filtered single-phase AC voltage Vif and generates the pulsating voltage Vrec.

The bridge circuit 2B has a first input terminal Psi and a second input terminal Pri. The filtered single-phase AC voltage Vif is received between the first input terminal Psi and the second input terminal Pri.

Bridge circuit 2B has diodes Dsb and Drb. Diode Dsb has an anode connected to the first input terminal Psi and a cathode connected to inductor Lb. Diode Drb has an anode connected to the second input terminal Pri and a cathode connected to inductor Lb.

Diodes Dsb and Drb, like diode Db, function to pass inductor current Ib through inductor Lb.

The bridge circuit 2B has diodes Dsp, Drp, Dsn, and Drn. Diode Dsp has an anode connected to the first input terminal Psi and a cathode connected to the first power supply line LH. Diode Drp has an anode connected to the second input terminal Pri and a cathode connected to the first power supply line LH. Diode Dsn has a cathode connected to the first input terminal Psi and an anode connected to the second power supply line LL. Diode Drn has a cathode connected to the second input terminal Pri and an anode connected to the second power supply line LL.

Diodes Dsp, Drp, Dsn, and Drn, like diode Dr, allow current Ir (>0) to flow to the first power line LH.

The bridge circuit 2B has switches Ssp, Srp, Ssn, and Srn. Switch Ssp is connected in parallel to diode Dsp and is turned on to allow current to flow in the reverse direction of diode Dsp. Switch Srp is connected in parallel to diode Drp and is turned on to allow current to flow in the reverse direction of diode Drp. Switch Ssn is connected in parallel to diode Dsn and is turned on to allow current to flow in the reverse direction of diode Dsn. Switch Srn is connected in parallel to diode Drn and is turned on to allow current to flow in the reverse direction of diode Drn.

Similar to switch Sr, current Ir (<0) flows from the first power line through switches Ssp, Srp, Ssn, and Srn.

The opening and closing of switches Ssp, Srp, Ssn, and Srn are controlled by switching signals SSrp, SSrn, SSsp, and SSsn, respectively. The switching signals SSrp, SSrn, SSsp, and SSsn are generated and output, for example, by the discharge control unit 92 based on the switching signal SSr.

Switches Ssp and Ssn are exclusively conductive, and switches Srp and Srn are exclusively conductive. When both switches Ssp and Srn are conductive, current (Ir<0) is regenerated in capacitor Ci, and the potential of the first input terminal Psi increases relative to the potential of the second input terminal Pri. When both switches Srp and Ssn are conductive, current (Ir<0) is regenerated in capacitor Ci, and the potential of the second input terminal Pri increases relative to the potential of the first input terminal Psi.

So for example:
For both of the switching signals SSsp and SSrn, a signal is adopted which is activated when the switching signal SSr is activated and the power supply phase θ is in the range of nπ to (n+1)π;
For both of the switching signals SSrp and SSsn, signals that are activated when the switching signal SSr is activated and the power supply phase θ is between nπ and (n+1)π are adopted.

The generation of switching signals SSrp, SSrn, SSsp, and SSsn based on switching signal SSr and power supply phase θ can be easily achieved using a well-known circuit, such as a logical product circuit, so a detailed description thereof will be omitted.

In the third variant, low-pass filter 3A, to which single-phase AC voltage Vi is input, is required to have a higher withstand voltage than low-pass filter 3C, to which rectified voltage |Vi| is input. Diodes Dsp, Drp, Dsn, and Drn ensure the functionality of diode Dr and avoid steady-state on-state loss in diode Dr (see, for example, Non-Patent Document 1).

Even in such a modification, it is possible to execute either the first sequence or the second sequence, or a combination of both (see Figure 48), and it is clear that the above-mentioned effects can be obtained.

<Omission of Switches Ssp, Srp, Ssn, and Srn (Fourth Variation)>
Fig. 54 is a circuit diagram partially showing a fourth modification of the power conversion device 101. The fourth modification differs from the configuration (third modification) shown in Fig. 53 in that the rectifier circuit 23B is replaced with a rectifier circuit 23A, and that the switching signals SSrp, SSrn, SSsp, and SSsn output from the control circuit 9 are omitted.

Rectifier circuit 23A has a configuration in which bridge circuit 2B of rectifier circuit 23B is replaced with bridge circuit 2A. Bridge circuit 2B has a configuration in which switches Ssp, Srp, Ssn, and Srn are omitted from bridge circuit 2A, specifically, the switches are removed from the open state. By adopting this configuration, the switching signals SSrp, SSrn, SSsp, and SSsn output from control circuit 9 are no longer necessary.

In the fourth variant, as in the first variant (Figure 49), current is regenerated from the primary coil L1 and leakage inductance Ls via the diode Dc.

<Approximation of Phase Difference φ (Fifth Modification)>
In the calculations in the phase command calculation unit 931, approximate expressions may be used instead of the calculations of expressions (28) and (46).

For example, equation (47) is an approximation of the phase difference φ relative to the power supply phase θ when equation (29) is used in the first sequence, and is depicted by the dashed curve in Figure 17. Figures 20, 36, 42, 48, and 50 show the waveforms of various quantities when this approximation is used.

For example, equation (48) is an approximation of the phase difference φ relative to the power supply phase θ when equation (29) is used in the second sequence, and is depicted by the dashed curve in Figure 32. Figures 35, 43, 47, 48, and 51 show the waveforms of various quantities when this approximation is used.

<When the coefficient k is positive and less than ½ (sixth modification)>
As described above, when the coefficient k introduced in equations (1) to (6) takes the value 1/2, the discharge duty dc, the rectification duty drec, and the zero duty dz are generated using, for example, the sixth to ninth equations in equation (29). The following describes how to set the discharge duty dc, the rectification duty drec, and the zero duty dz when the coefficient k is positive and less than 1/2.

The current Ir is expressed by equation (49).

The power Pdc generated by the active buffer circuit 4D is input to the DAB converter 5. The output voltage Vo of the DAB converter 5 is the absolute value of the secondary side voltage VB applied across the capacitor Co. In both the first and second sequences, the absolute value of the secondary side voltage VB is equal to the output voltage Vo (see Figures 6, 21, 37, and 44). The power output from the DAB converter 5, calculated as the product of the output voltage Vo and the output current Io, is equal to the power Pdc (= Pc + Pr) input to the DAB converter 5, and therefore equation (50) holds.

As can be seen from Non-Patent Document 1, the commutation duty drec is expressed by equation (51).

From equations (2), (49), (50), and (51), the commutation duty drec is obtained by equation (52).

As can be seen from Non-Patent Document 1, the discharge duty drec is expressed by equation (53).

Therefore, from equations (3) and (50), the discharge duty dc can be obtained from equation (54).

As can be seen from Non-Patent Document 1, when the zero duty dz is at its minimum, the voltage Vdc is at its maximum. From equations (53) and (54), the zero duty dz can be expressed by equation (55).

If k = 1/2 in equations (52) and (54), they correspond to equations 8 and 9 of equation (29), respectively.

<Supplementary explanation for formula (29)>
The value of the control frequency f shown in the third equation of equation (29) is approximately 1/10 of the value used in an actual circuit. The value of the leakage inductance Ls shown in the fourth equation of equation (29) is approximately 10 times the value used in an actual circuit. This setting was adopted to improve the visibility of the various waveforms shown in Figures 19, 20, 34, 35, 36, 42, 43, 47, 48, 50, 51, and 52. However, in equation (28), the product of the value of the control frequency f and the value of the leakage inductance Ls is used. The fact that the above setting differs from the value used in an actual circuit does not affect Figures 17, 18, 32, and 33.

Although the embodiments have been described above, it will be understood that various changes in form and details are possible without departing from the spirit and scope of the claims. The various embodiments and modifications described above can be combined with each other.

2A, 2B Bridge circuit 2C Diode bridge 3A, 3C Low pass filter 4A, 4C, 4D Active buffer circuit 5 Dual active bridge converter 5a, 5b Input terminal 5c, 5d Output terminal 7 DC link 9 Control circuit 23A, 23B, 23C Rectifier circuit 50 Transformer 51 DC-AC conversion section 52 AC-DC conversion section 101 Power conversion device Cb, Ci Capacitors Db, Dc, Dr, Drb, Dsb, Drn, Drp, Dsn, Dsp Diodes Io Output current LH First power supply line LL Second power supply line Lb, Li Inductor M11, M12, M21, M22, M23, M31, M32, M41, M42, M43, M51, M52, M61, M62, M63, M71, M72, M81, M82, M83 Current path mode Pb First part Pba AC component (of first part) Pbd DC component (of first part) Pc, Py Lagging power Pdc Power Pi Input power Pr Second part Pri Second input terminal Psi First input terminal Sb, Sc, Sr, Srn, Srp, Ssn, Ssp Switch T Period Tca, Tcb, Tcc, Tcd, Tra, Trb, Trc, Trd, Tza, Tzb, Tzc, Tzd Period VA Primary side voltage VB Secondary side voltage Vc Step-up voltage Vi Single-phase AC voltage Vif Filtered single-phase AC voltage Vrec Pulsating voltage θ Power supply phase φ Phase difference

Claims (22)

a rectifier circuit (23A, 23B, 23C) for outputting a pulsating voltage (Vrec) in which a single-phase AC voltage (Vi) has been full-wave rectified and high-frequency attenuated;
a DC link (7) including a first power line (LH) and a second power line (LL);
an active buffer circuit (4A, 4C, 4D) that receives the pulsating voltage (Vrec) from the rectifier circuit (23A, 23B, 23C), boosts it to obtain a boosted voltage (Vc), partially buffers the input power (Pi) input from the rectifier circuit (23A, 23B, 23C), and outputs power (Pdc) to the DC link (7);
a dual active bridge converter (5) including a first bridge (51) including a pair of input terminals (5a, 5b) connected between the first power supply line (LH) and the second power supply line (LL), a second bridge (52) including a pair of output terminals (5c, 5d), and a transformer (50) connecting the first bridge (51) and the second bridge (52) between the pair of input terminals (5a, 5b) and the pair of output terminals (5c, 5d); and a control circuit (9) for controlling the operation of the active buffer circuits (4A, 4C, 4D) and the dual active bridge converter (5).
Equipped with
The control circuit (9)
The power conversion device (101) causes the dual active bridge converter (5) to variably control the phase difference (φ) between the primary side voltage (VA) and the secondary side voltage (VB) of the transformer (50). The control circuit (9)
2. The power conversion device (101) according to claim 1, wherein the active buffer circuit (4A, 4C, 4D) generates the power (Pdc) by combining a first lagging power (Pc) that lags a first portion (Pb) that is k times (where k is a positive number equal to or less than ½) the input power (Pi) by a quarter cycle of the single-phase AC voltage (Vi) and a second portion (Pr) that is (1-k) times the input power (Pi). The control circuit (9)
3. The power conversion device (101) according to claim 2, wherein the active buffer circuit (4A, 4C, 4D) generates the power (Pdc) by combining a second phase-lagging power (Py) obtained by delaying the AC component (Pba) contained in the first portion (Pb) by the quarter cycle, a DC component (Pbd) contained in the first portion (Pb), and the second portion (Pr). The control circuit (9)
The active buffer circuits (4A, 4C, 4D)
2. The power conversion device (101) according to claim 1, wherein a current (iL) that alternately exhibits a symmetrical positive and negative waveform every half of a control period (T) of the dual active bridge converter (5) regardless of the phase (θ) of the single-phase AC voltage (Vi) is caused to flow through a primary side of the transformer (50). The active buffer circuits (4A, 4C, 4D)
having a first inductor (Lb), a first capacitor (Cb), a first diode (Db), a second diode (Dc), a first switch (Sb), and a second switch (Sc);
The series connection of the first inductor (Lb) and the first switch (Sb) receives the pulsating voltage (Vrec);
The cathode of the second diode (Dc) is connected to the cathode of the first diode (Db) and to the first capacitor (Cb);
The series connection of the first diode (Db) and the first capacitor (Cb) is connected in parallel to the first switch (Sb);
The second switch (Sc) is connected in parallel with the second diode (Dc),
The control circuit (9) controls the on/off of the first switch (Sb) and the second switch (Sc),
The pulsating voltage (Vrec) is boosted by turning on and off the first switch (Sb), and the boosted voltage (Vc) is obtained in the first capacitor (Cb);
When the second switch (Sc) is turned on, the boosted voltage (Vc) is applied between the first power supply line (LH) and the second power supply line (LL) through the series connection of the second diode (Dc) and the first capacitor (Cb),
2. The power conversion device (101) according to claim 1, wherein, when the second switch (Sc) is turned off, the pulsating voltage (Vrec) is applied between the first power supply line (LH) and the second power supply line (LL) from the series connection of the second diode (Dc) and the first capacitor (Cb). The active buffer circuits (4C, 4D)
a third diode (Dr) having an anode connected to the first switch (Sb) and the anode of the first diode (Db) via the first inductor (Lb) and a cathode connected to the anode of the second diode (Dc);
The rectifier circuit (23C)
a diode bridge (2C) that full-wave rectifies the single-phase AC voltage (Vi) and outputs a rectified voltage (|Vi|); and a low-pass filter (3C) that attenuates the high frequencies of the rectified voltage (|Vi|) to obtain the pulsating voltage (Vrec).
and
The low-pass filter (3C)
having a second inductor (Li) and a second capacitor (Ci);
6. The power conversion device (101) according to claim 5, wherein the series connection of the second inductor (Li) and the second capacitor (Ci) receives the rectified voltage (|Vi|) to obtain the pulsating voltage (Vrec) in the second capacitor (Ci). The power conversion device (101) described in claim 6, wherein the first capacitor (Cb) is charged by regenerative current from the dual active bridge converter (5) via the second diode (Dc). The power conversion device (101) of claim 6, wherein the active buffer circuit (4D) further includes a third switch (Sr) connected in parallel with the third diode (Dr) and turned on to allow current to flow in the reverse direction of the third diode (Dr). The rectifier circuits (23A, 23B)
a low-pass filter (3A) that receives the single-phase AC voltage (Vi) and outputs a filtered single-phase AC voltage (Vif) in which the high frequencies of the single-phase AC voltage (Vi) are attenuated; and a full-wave rectifier bridge (2A, 2B) that receives the filtered single-phase AC voltage (Vif) and generates the pulsating voltage (Vrec).
and
The full-wave rectifier bridge (2A, 2B)
First input (Psi);
a second input terminal (Pri) for receiving the filtered single-phase AC voltage (Vif) between the first input terminal (Psi);
a fourth diode (Dsb) having an anode connected to the first input (Psi) and a cathode connected to the first inductor (Lb);
a fifth diode (Drb) having an anode connected to the second input (Pri) and a cathode connected to the first inductor (Lb);
a sixth diode (Dsp) having an anode connected to the first input terminal (Psi) and a cathode connected to the first power supply line (LH);
a seventh diode (Drp) having an anode connected to the second input terminal (Pri) and a cathode connected to the first power line (LH);
an eighth diode (Dsn) having a cathode connected to the first input terminal (Psi) and an anode connected to the second power supply line (LL); and a ninth diode (Drn) having a cathode connected to the second input terminal (Pri) and an anode connected to the second power supply line (LL).
The power converter of claim 5 , comprising: The full-wave rectifier bridge (2B)
a third switch (Ssp) connected in parallel to the sixth diode (Dsp) and turned on to allow current to flow in the reverse direction of the sixth diode (Dsp);
a fourth switch (Srp) connected in parallel to the seventh diode (Drp) and turned on to allow current to flow in the reverse direction of the seventh diode (Drp);
a fifth switch (Ssn) connected in parallel to the eighth diode (Dsn) and turned on to allow a current to flow in the reverse direction of the eighth diode (Dsn); and a sixth switch (Srn) connected in parallel to the ninth diode (Drn) and turned on to allow a current to flow in the reverse direction of the ninth diode (Drn).
The power converter of claim 9 further comprising: The power conversion device (101) described in claim 9, wherein the first capacitor (Cb) is charged by regenerative current from the dual active bridge converter (5) via the second diode (Dc). The control circuit (9) controls the dual active bridge converter (5) to:
fluctuating the phase difference (φ) with a frequency component twice the frequency of the single-phase AC voltage (Vi);
2. The power conversion device according to claim 1, wherein the phase difference (φ) in a phase (θ=(2n+1)π/2) of the single-phase AC voltage (Vi) at which the ripple voltage (Vrec) is maximized is made larger than the phase difference (φ) in the phase (θ=nπ) of the single-phase AC voltage at which the ripple voltage (Vrec) is minimized. In a control cycle (T) of the dual active bridge converter (5), a first period (Tca: M11, M12, M21), a second period (Tra: M22), a third period (Tcb: M31, M32, M41), and a fourth period (Trb: M42) pass in this order,
In the first period (Tca: M11, M12, M21) and the third period (Tcb: M31, M32, M41), the boosted voltage (Vc) is applied between the pair of input terminals (5a, 5b),
The power conversion device according to claim 12, wherein the pulsating voltage (Vrec) is applied between the pair of input terminals (5a, 5b) during the second period (Tra: M22) and the fourth period (Trb: M42). In a control cycle (T) of the dual active bridge converter (5), the first period (Tca: M11, M12, M21), the second period (Tra: M22), the fifth period (Tza: M23), the third period (Tcb: M31, M32, M41), the fourth period (Trb: M42), and the sixth period (Tzb: M43) pass in this order,
The power conversion device according to claim 13, wherein the primary side voltage (VA) is zero in the fifth period (Tza: M23) and the sixth period (Tzb: M43). The control circuit (9) controls the dual active bridge converter (5) to:
fluctuating the phase difference (φ) with a frequency component four times the frequency of the single-phase AC voltage (Vi);
The phase difference (φ) is made to take a minimum value in the phase (θ=(2n+1)π/2) of the single-phase AC voltage (Vi) where the pulsating voltage (Vrec) is maximized;
13. The power conversion device according to claim 12, wherein the phase difference (φ) takes a maximum value at the phase (θ) of the single-phase AC voltage between the phase (θ=nπ) of the single-phase AC voltage (Vi) where the ripple voltage (Vrec) is minimum and the phase (θ=(2n+1)π/2) of the single-phase AC voltage where the ripple voltage (Vrec) is maximum. In a control period (T) of the dual active bridge converter (5), a first period (Trc: M51, M52, M61), a second period (Tcc: M62), a third period (Trd: M71, M72, M81), and a fourth period (Tcd: M82) pass in this order,
In the first period (Trc: M51, M52, M61) and the third period (Trd: M71, M72, M81), the pulsating voltage (Vrec) is applied between the pair of input terminals (5a, 5b),
The power conversion device according to claim 15, wherein the boosted voltage (Vc) is applied between the pair of input terminals (5a, 5b) during the second period (Tcc: M62) and the fourth period (Tcd: M82). In a control period (T) of the dual active bridge converter (5), the first period (Trc: M51, M52, M61), the second period (Tcc: M62), the fifth period (Tzc: M63), the third period (Trd: M71, M72, M81), the fourth period (Tcd: M82), and the sixth period (Tzd: M83) pass in this order,
The power conversion device according to claim 16, wherein the primary side voltage (VA) is zero during the fifth period (Tzc: M63) and the sixth period (Tzd: M83). In a first control period (Tca, Tra, Tza, Tcb, Trb, Tzb) of the dual active bridge converter (5), a first period (Tca: M11, M12, M21), a second period (Tra: M22), a third period (Tcb: M31, M32, M41), and a fourth period (Trb: M42) pass in this order,
In a second control period (Trc, Tcc, Tzc, Trd, Tcd, Tzd) of the dual active bridge converter (5), a fifth period (Trc: M51, M52, M61), a sixth period (Tcc: M62), a seventh period (Trd: M71, M72, M81), and an eighth period (Tcd: M82) pass in this order,
The control circuit (9) controls the active buffer circuits (4A, 4C, 4D) to:
applying the boosted voltage (Vc) between the pair of input terminals (5a, 5b) during the first period (Tca: M11, M12, M21), the third period (Tcb: M31, M32, M41), the sixth period (Tcc: M62), and the eighth period (Tcd: M82);
The pulsating voltage (Vrec) is applied between the pair of input terminals (5a, 5b) during the second period (Tra: M22), the fourth period (Trb: M42), the fifth period (Trc: M51, M52, M61), and the seventh period (Trd: M71, M72, M81),
the second control period (Trc, Tcc, Tzc, Trd, Tcd, Tzd) is adopted in a phase (θ=(2n+1)π/2) of the single-phase AC voltage (Vi) where the pulsating voltage (Vrec) is maximized;
2. The power conversion device according to claim 1, wherein the first control period (Tca, Tra, Tza, Tcb, Trb, Tzb) is adopted in a phase (θ=nπ) of the single-phase AC voltage (Vi) where the pulsating voltage (Vrec) is minimized. A power conversion device (101) according to any one of claims 1 to 18, wherein the phase difference (φ) is subjected to feedback control of the current (Io) output from the dual active bridge converter. a DC link (7) including a first power line (LH) and a second power line (LL);
a boost circuit (4A, 4D) that receives a pulsating voltage (Vrec) obtained by full-wave rectification and high-frequency attenuation of a single-phase AC voltage (Vi) and outputs a boosted voltage (Vc) obtained by boosting the pulsating voltage (Vrec) or the pulsating voltage (Vrec) to the DC link (7);
a dual active bridge converter (5) including a first bridge (51) including a pair of input terminals (5a, 5b) connected between the first power supply line (LH) and the second power supply line (LL), a second bridge (52) including a pair of output terminals (5c, 5d), and a transformer (50) connecting the first bridge (51) and the second bridge (52) between the pair of input terminals (5a, 5b) and the pair of output terminals (5c, 5d); and a control circuit (9) for controlling the operation of the boost circuit (4A, 4D) and the dual active bridge converter (5).
Equipped with
In a first control period (Tca, Tra, Tza, Tcb, Trb, Tzb) of the dual active bridge converter (5), a first period (Tca: M11, M12, M21), a second period (Tra: M22), a third period (Tcb: M31, M32, M41), and a fourth period (Trb: M42) pass in this order,
In a second control period (Trc, Tcc, Tzc, Trd, Tcd, Tzd) of the dual active bridge converter (5), a fifth period (Trc: M51, M52, M61), a sixth period (Tcc: M62), a seventh period (Trd: M71, M72, M81), and an eighth period (Tcd: M82) pass in this order,
The control circuit (9) controls the boost circuit (4) to
applying the boosted voltage (Vc) between the pair of input terminals (5a, 5b) during the first period (Tca: M11, M12, M21), the third period (Tcb: M31, M32, M41), the sixth period (Tcc: M62), and the eighth period (Tcd: M82);
The pulsating voltage (Vrec) is applied between the pair of input terminals (5a, 5b) during the second period (Tra: M22), the fourth period (Trb: M42), the fifth period (Trc: M51, M52, M61), and the seventh period (Trd: M71, M72, M81),
the second control period (Trc, Tcc, Tzc, Trd, Tcd, Tzd) is adopted in a phase (θ=(2n+1)π/2) of the single-phase AC voltage (Vi) where the pulsating voltage (Vrec) is maximized;
A power conversion device in which the first control period (Tca, Tra, Tza, Tcb, Trb, Tzb) is adopted in a phase (θ=nπ) of the single-phase AC voltage in which the ripple voltage (Vrec) is minimized. a diode bridge (2C) that full-wave rectifies the single-phase AC voltage (Vi) and outputs a rectified voltage (|Vi|); and a low-pass filter (3C) that attenuates the high frequencies of the rectified voltage (|Vi|) to obtain the pulsating voltage (Vrec).
The power converter (101) of claim 20, further comprising: a low-pass filter (3A) that receives the single-phase AC voltage (Vi) and outputs a filtered single-phase AC voltage (Vif) in which the high frequencies of the single-phase AC voltage (Vi) are attenuated; and a full-wave rectifier bridge (2A, 2B) that receives the filtered single-phase AC voltage (Vif) and generates the pulsating voltage (Vrec).
The power converter (101) of claim 20, further comprising: