JP7803707B2 - Device package manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a device package, which produces a device package having a device chip sealed with resin.

Device chips are typically mounted in electronic devices in a resin-sealed device package. In recent years, as electronic devices have become smaller, there has been a demand for smaller device packages as well. In response to this demand for miniaturization, device packages such as WLP (Wafer Level Package) and WLCSP (Wafer Level Chip Size(Scale) Package) are being manufactured.

In recent years, device packages known as FOWLP (Fan Out Wafer Level Package) have also been manufactured, in which package terminals are formed outside the device chip area using wafer-level rewiring technology (see, for example, Patent Document 1).

As an example of a FOWLP manufacturing method, first, multiple device chips are arranged at a predetermined interval on one surface of a support substrate. Next, a liquid thermosetting resin is supplied to this surface, and the resin is then hardened by heating, sealing each device chip with a resin layer.

Next, the resin layer and the support substrate are separated to obtain an encapsulating substrate having a device chip and a resin layer. A redistribution layer is then formed on the outer surface of the encapsulating substrate that was in contact with the support substrate, and the encapsulating substrate and redistribution layer are then singulated into individual device chips. This allows the FOWLP to be manufactured.

However, when each device chip is sealed with a resin layer, warpage occurs, where the center of the sealing substrate protrudes more than the periphery when viewed from above. Warped sealing substrates are difficult to handle during transport, suction holding, processing, etc., making the manufacture of device packages relatively difficult.

JP 2013-58520 A

The present invention was made in consideration of these problems, and aims to reduce warpage of the central convex shape in the sealing substrate.

According to one aspect of the present invention, a method for manufacturing a device package includes: an arrangement step of arranging a plurality of device chips spaced apart from one another on a surface side of a support substrate and arranging one or more dummy chips in an area of the surface side where no device chips are arranged; a sealing substrate formation step of encapsulating each of the device chips and each of the dummy chips arranged on the surface side of the support substrate with resin to form a sealing substrate on the surface side; and a division step of dividing the sealing substrate into individual device packages, each dummy chip having a first surface and a second surface located on the opposite side to the first surface in the thickness direction and having an area larger than an area of the first surface. and a method for manufacturing a device package in which, in the arranging step, each dummy chip is arranged on the front surface side so that the first surface faces the surface of the support substrate , and after the sealing substrate forming step and before the dividing step, the first surface of each device chip and the first surface of each dummy chip are covered with the support substrate formed of single crystal silicon, and the second surface of each device chip and the second surface of each dummy chip, which are located on the opposite side to the first surface of each device chip in the thickness direction of each device chip, are covered with the resin, and after the dividing step, the first surface of each device chip remains covered with a part of the support substrate .

Preferably, each dummy chip tapers in the thickness direction from the second surface to the first surface, and in the placing step, each dummy chip is placed on the surface of the support substrate so that the first surface faces the surface.

Also, preferably, at least one dummy chip has a tapered or stepped shape on the side, and in the placing step, each dummy chip is placed on the front surface side so that the first surface faces the surface of the support substrate.
According to another aspect of the present invention, there is provided a method for manufacturing a device package, the method including: an arrangement step of arranging a plurality of device chips at a distance from one another on a surface side of a support substrate, and arranging one or more dummy chips in an area of the surface side where no device chips are arranged; a sealing substrate formation step of encapsulating each of the device chips and each of the dummy chips arranged on the surface side of the support substrate with a resin to form a sealing substrate on the surface side; a separation step of separating the support substrate from the sealing substrate by relatively separating the support substrate from the sealing substrate; a rewiring layer formation step of forming a rewiring layer on one surface of the sealing substrate that faced the support substrate, the rewiring layer including a low-dielectric-constant interlayer insulating film and a metal wiring layer formed in the low-dielectric-constant interlayer insulating film; and a dividing step of dividing the dummy chip into individual device packages, wherein each dummy chip has a first surface and a second surface located on the opposite side of the first surface in the thickness direction and having an area larger than that of the first surface, and in the arranging step, each dummy chip is arranged on the front surface side of the support substrate so that the first surface faces the front surface, and after the sealing substrate forming step and before the dividing step, the first surface of each device chip and the first surface of each dummy chip are covered with the redistribution layer, and a second surface of each device chip located on the opposite side of the first surface of each device chip in the thickness direction of each device chip and the second surface of each dummy chip are covered with the resin.
According to yet another aspect of the present invention, there is provided a method for manufacturing a device package, the method comprising: an arrangement step of arranging a plurality of device chips spaced apart from one another on a surface side of a support substrate, and arranging one or more dummy chips in an area of the surface side where no device chips are arranged; a sealing substrate forming step of encapsulating each of the device chips and each of the dummy chips arranged on the surface side of the support substrate with resin to form a sealing substrate on the surface side; and a dividing step of dividing the sealing substrate into individual device packages, wherein each dummy chip has a first surface and a second surface located on the opposite side to the first surface in the thickness direction and having an area larger than an area of the first surface, and In the device package, each dummy chip is arranged on the front surface side so that the first surface faces the surface of the support substrate, and after the sealing substrate forming step and before the dividing step, the first surface of each device chip and the first surface of each dummy chip are covered with a redistribution layer including a low dielectric constant interlayer insulating film and a metal wiring layer formed in the low dielectric constant interlayer insulating film, and the second surface of each device chip and the second surface of each dummy chip, which are located on the opposite side to the first surface of each device chip in the thickness direction of each device chip, are covered with the resin, and after the dividing step, the first surface of each device chip remains covered with a part of the redistribution layer.

According to yet another aspect of the present invention, there is provided a method for manufacturing a device package, comprising: an arrangement step of arranging a plurality of device chips spaced apart from one another on a surface side of a support substrate, and arranging one or more dummy chips in an area of the surface side where no device chips are arranged; a sealing substrate formation step of encapsulating each of the device chips and each dummy chip arranged on the surface side of the support substrate with resin to form a sealing substrate on the surface side; and a division step of dividing the sealing substrate into individual device packages, wherein each dummy chip is located on a side opposite to the first surface in a thickness direction, and a second surface having an area larger than that of the first surface, and in the arranging step, each dummy chip is arranged on the surface side so that the first surface faces the surface of the support substrate, and at least one dummy chip has a flat first chip and a flat second chip which has an area larger than that of the first chip when viewed in a plane and is stacked on the first chip, and in the arranging step, the at least one dummy chip is arranged on the surface side so that the first chip faces the surface of the support substrate.

In the placement step of a method for manufacturing a device package according to one aspect of the present invention, a dummy chip having a first surface and a second surface located on the opposite side of the first surface in the thickness direction is placed on the surface side of the support substrate so that the first surface faces the surface of the support substrate. The area of the second surface of this dummy chip is larger than the area of the first surface.

As a result, the amount of expansion in a predetermined direction parallel to the surface of the resin at the same height as the second surface is smaller than the amount of expansion in the same direction of the resin at the same height as the first surface. This reduces warping of the central convex shape in the sealing substrate.

FIG. 1 is a flow diagram of a method for manufacturing a device package. FIG. 10 is a perspective view showing a device chip placement step. FIG. 3A is a perspective view showing the dummy chip placement step, and FIG. 3B is a cross-sectional view of the dummy chip. FIG. 10 is a top view of the support substrate after the disposing step. 10 is a cross-sectional view of the support substrate etc. after the placement step. FIG. 10 is a cross-sectional view of a stack of a support substrate and an encapsulation substrate after a curing step. FIG. 8A is an enlarged cross-sectional view of the sealing substrate etc. in the comparative example, and FIG. 8B is an enlarged cross-sectional view of the sealing substrate etc. in the first embodiment. FIG. 1 illustrates a division step. FIG. 10 shows the device package after the division step. FIG. 10 is a flow diagram of a method for manufacturing a device package according to a second embodiment. FIG. 1 illustrates a separation step. 10A and 10B are diagrams illustrating a rewiring layer forming step. FIG. 10 is a diagram illustrating a division step in the second embodiment. 10 is a cross-sectional view of the support substrate and the like after the placement step in the third embodiment. FIG. FIG. 16(A) is a diagram showing a dummy chip in a first modified example, FIG. 16(B) is a diagram showing a dummy chip in a second modified example, and FIG. 16(C) is a diagram showing a dummy chip in a third modified example.

An embodiment of the present invention will be described with reference to the accompanying drawings. Figure 1 is a flow diagram of a method for manufacturing a device package 2 (see Figure 10) in a first embodiment. When manufacturing the device package 2, first, multiple device chips 6 are placed on a disk-shaped support substrate 4, as shown in Figure 2.

The support substrate 4 has a circular front surface 4a and a circular back surface 4b. The outer edges of the front surface 4a and the back surface 4b are chamfered (see Figure 5, etc.). A notch 4c is also formed in part of the support substrate 4.

In this embodiment, the support substrate 4 is a wafer made of single-crystal silicon with a diameter of 6 inches (approximately 150 mm). However, the material of the support substrate 4 is not limited to silicon, and it may be made of other semiconductor materials such as silicon carbide or gallium arsenide.

In the rectangular area of the support substrate 4 where the device chip 6 is placed, terminals, circuits, etc. (none of which are shown) for electrical connection with the device chip 6 are formed, and further, electrodes (e.g., TSVs (Through-Silicon Vias)) that penetrate from the front surface 4a to the back surface 4b are formed.

In addition, a conductive adhesive such as silver paste (not shown) is pre-applied to the terminals of the rectangular area where the device chip 6 is placed, and the device chip 6 placed in the rectangular area is fixed to the surface 4a side with this conductive adhesive.

The device chip 6 has a rectangular parallelepiped shape. For example, the device chip 6 is a roughly square, flat plate with dimensions of 10 mm in length, 10 mm in width, and 0.6 mm in thickness. Devices such as ICs (Integrated Circuits) and DRAMs (Dynamic Random Access Memory) are formed on the device chip 6.

Figure 2 is a perspective view showing the device chip arrangement step S12. In the device chip arrangement step S12, multiple device chips 6 are arranged along the first direction 8a and the second direction 8b of the support substrate 4 so that adjacent device chips 6 are spaced a predetermined distance 6a apart.

In this embodiment, five device chips 6 are arranged along the first direction 8a and five more along a second direction 8b that is parallel to the surface 4a and perpendicular to the first direction 8a, in a lattice pattern in the rectangular central portion _4a1 on the surface 4a side. That is, 25 (=5×5) device chips 6 are arranged in the central portion _4a1 on the surface 4a side.

In addition, device chips 6 are also arranged on the outer periphery 4a2 of the surface 4a on one side of the first direction _8a from the device chip 6 located at the center (i.e., the third one) in the second direction 8b among the device chips 6 located at the outermost position on one side of the first direction 8a in the central portion _4a1 .

Similarly, a device chip 6 is also arranged on the outer periphery 4a2 of the surface 4a on the other side of the first direction _8a from the device chip 6 located at the center (i.e., the third one) in the second direction 8b among the device chips 6 located at the outermost position on the other side of the first direction 8a in the central portion _4a1 .

In addition, device chips 6 are also arranged on the outer periphery 4a2 of the surface _4a on one side of the second direction 8b from the device chip 6 located at the center (i.e., the third one) in the first direction 8a among the device chips 6 located at the outermost position on one side of the second direction 8b in the central portion _4a1 .

Similarly, a device chip 6 is also arranged on the outer periphery 4a2 of the surface 4a on the other side of the second direction _8b from the device chip 6 located at the center (i.e., the third one) in the first direction 8a among the device chips 6 located at the outermost position on the other side of the second direction 8b in the central portion _4a1 .

In this manner, the device chips 6 are arranged in a predetermined region on the front surface 4a side, including the central portion _4a1 and the outer peripheral portion _4a2 . The distance between the device chips ₆ arranged in the outer peripheral portion 4a2 and the device chips 6 arranged in the central portion _4a1 is also set to a predetermined distance 6a.

By arranging each device chip 6 at a predetermined distance 6a, multiple planned division lines 12 (see dashed lines in Figure 4) each having a predetermined width are set on the front surface 4a.

In the device chip placement step S12 shown in FIG. 2, each device chip 6 is placed individually on the front surface 4a, but multiple or all of the device chips 6 may be placed on the front surface 4a at the same time.

After the device chip placement step S12, one or more dummy chips 10, each having approximately the same thickness as the device chip 6, are placed in areas of the front surface 4a where no device chip 6 is placed (dummy chip placement step S14).

Figure 3(A) is a perspective view showing the dummy chip placement step S14. In Figure 3(A), for convenience, a dot pattern is applied to the dummy chip 10 to make it easier to distinguish between the device chip 6 and the dummy chip 10.

The dummy chip 10 has a lower surface (first surface) 10a that faces the front surface 4a. The dummy chip 10 also has an upper surface (second surface) 10b that is located on the opposite side of the lower surface 10a in the thickness direction 10c and has an area larger than the area of the lower surface 10a.

Figure 3(B) is a cross-sectional view of the dummy chip 10. The dummy chip 10 shown in Figure 3(B) has four tapered side surfaces 10d and an inverted truncated pyramid shape that gradually becomes thinner in the thickness direction 10c from the top surface 10b to the bottom surface 10a.

For example, the upper surface 10b is 6 mm long and 6 mm wide, and the lower surface 10a is 4 mm long and 4 mm wide, with a thickness of 0.6 mm. The dummy chip 10 can be formed, for example, by cutting a wafer (e.g., a bare wafer) made of single-crystal silicon with an annular cutting blade (not shown).

More specifically, a cutting blade (also called a bevel blade) with a V-shaped, pointed outer peripheral side in a cross section taken along the radial direction of the cutting blade is used to cut a wafer of a predetermined thickness into a grid pattern, thereby forming dummy chips 10.

In the dummy chip placement step S14, each dummy chip 10 is placed on the outer periphery 4a2 on the surface 4a side so that it does not extend beyond the outer periphery of the support substrate 4 in the radial direction of the support substrate 4 and is placed within an area defined by a plurality of planned division lines 12 (see dotted lines in Figure 4 ₎ each having a predetermined width.

In the dummy chip placement step S14 shown in FIG. 3(A), each dummy chip 10 is placed individually on the front surface 4a, but multiple or all of the dummy chips 10 may be placed on the front surface 4a at the same time. Each dummy chip 10 is fixed to the front surface 4a with, for example, an adhesive (not shown).

In this embodiment, the device chip placement step S12 and the dummy chip placement step S14 are collectively referred to as placement step S10 (see Figure 1). Figure 4 is a top view of the support substrate 4, with the surface 4a side viewed from above, after placement step S10. Note that in Figure 4, the planned division lines 12 are indicated by dashed lines.

Figure 5 is a cross-sectional view of the support substrate 4, device chip 6, and dummy chip 10 after placement step S10, corresponding to cross section A-A in Figure 4. After placement step S10, a sealing substrate 15 (see Figure 7) is formed in which the device chip 6 and dummy chip 10 are sealed with hardened resin 13 (sealing substrate formation step S20).

In the sealing substrate formation step S20, the sealing substrate 15 (see FIG. 7) is formed, for example, by compression molding. To do this, first, the support substrate 4 and other components are placed in the lower part of a molding die (not shown) that has an upper part and a lower part.

At this time, the support substrate 4 is placed on the lower mold so that the back surface 4b contacts the lower mold and the front surface 4a is exposed. Next, liquid resin 11 (see Figure 6) is supplied to the front surface 4a side. Figure 6 shows the resin supply step S22.

Resin 11 is a liquid thermosetting resin (e.g., epoxy resin) containing fillers, etc., and is also called EMC (Epoxy Molding Compound). After resin supply step S22, the upper mold is pressed into the lower mold and heated to a predetermined temperature (e.g., 280°C to 300°C).

This hardens the resin 11, forming a sealing substrate 15 (see Figure 7) on the surface 4a of the support substrate 4, in which each device chip 6 and each dummy chip 10 is sealed with solid resin 13 (hardening step S24).

Figure 7 is a cross-sectional view of the laminate of the support substrate 4 and the sealing substrate 15 after the curing step S24. As shown in Figure 1, in this embodiment, the resin supplying step S22 and the curing step S24 are collectively referred to as the sealing substrate forming step S20.

The resin 11 used in the sealing substrate formation step S20 is not limited to liquid resin 11. Instead of liquid resin 11, granular, sheet, or gel resin may be supplied to the surface 4a side. As an alternative method, instead of compression molding, the sealing substrate 15 may be formed by transfer molding.

Note that the device chip 6 and dummy chip 10 being sealed with resin 13 does not necessarily mean that the entire surfaces of the device chip 6 and dummy chip 10 (for example, all six surfaces in the case of a hexahedron) are in contact with resin 13.

In this embodiment, if five faces of the device chip 6 and dummy chip 10, each of which is a hexahedron, excluding the face facing surface 4a, are in contact with solid resin 13, the device chip 6 and dummy chip 10 are said to be sealed with resin 13.

Next, the function of the dummy chip 10 will be explained using a comparative example. Figure 8(A) is an enlarged cross-sectional view of the sealing substrate 15 and other components of the comparative example. The dummy chip 20 of the comparative example has a rectangular, flat plate shape, and the areas of the upper surface 20b and lower surface 20a are the same as the area of the upper surface 10b of the dummy chip 10.

In the comparative example of Figure 8 (A), the distance 24b from the dummy chip 10 to the outer peripheral side surface of the resin 13 in a predetermined direction B parallel to the surface 4a at the height position of the upper surface 20b is the same as the distance 24a from the dummy chip 10 to the outer peripheral side surface of the resin 13 in the predetermined direction B at the height position of the lower surface 20a.

Furthermore, at the height position of the upper surface 20b, the distance 26b from the device chip 6 to the dummy chip 10 in the specified direction B is the same as the distance 26a from the device chip 6 to the dummy chip 10 in the specified direction B at the height position of the lower surface 20a.

In this case, the amount of warping of the sealing substrate 15 can be reduced compared to when the dummy chip 20 is not provided, but due to the influence of the predetermined thickness region 13a of the resin 13 located on the upper surface 20b side of the dummy chip 20, warping still remains to a degree that makes handling relatively difficult.

Figure 8(B) is an enlarged cross-sectional view of the sealing substrate 15 and other components in the first embodiment. As described above, the area of the upper surface 10b of the dummy chip 10 in the first embodiment is larger than the area of the lower surface 10a.

Therefore, at the height position of the upper surface 10b, the distance 14b from the dummy chip 10 to the outer peripheral side surface of the resin 13 in the specified direction B is smaller than the distance 14a from the dummy chip 10 to the outer peripheral side surface of the resin 13 in the specified direction B at the height position of the lower surface 10a.

Similarly, at the height position of the upper surface 10b, the distance 16b from the device chip 6 to the dummy chip 10 in the specified direction B is smaller than the distance 16a from the device chip 6 to the dummy chip 10 in the specified direction B at the height position of the lower surface 10a.

Since the linear thermal expansion coefficient of resin 13 is constant, the amount of expansion (ΔL) of resin 13 in specified direction B at the same height as upper surface 10b is smaller than the amount of expansion (ΔL + δ) of resin 13 in specified direction B at the same height as lower surface 10a.

This difference in thermal expansion (δ) acts to mitigate the effects of thermal expansion of the predetermined thickness region 13a of the resin 13. Therefore, the warpage of the central convex shape in the sealing substrate 15 can be reduced compared to when the dummy chip 20 shown in the comparative example is placed. Of course, the warpage of the central convex shape can also be sufficiently reduced compared to when the dummy chip 10 is not placed.

After the sealing substrate formation step S20, as shown in FIG. 9, a cutting device 30 is used to divide the laminate of the support substrate 4 and the sealing substrate 15 into device chips 6 (division step S30). FIG. 9 is a diagram showing the division step S30. Note that the X-axis, Y-axis, and Z-axis directions shown in FIG. 9 are perpendicular to one another.

The cutting device 30 has a disk-shaped chuck table (not shown). The chuck table has a substantially flat, circular holding surface arranged substantially parallel to the X-Y plane. Negative pressure is applied to the holding surface from a suction source (not shown), such as an ejector.

The chuck table is configured to be rotatable around the Z-axis direction (cutting feed direction) perpendicular to the X-Y plane, and movable in the X-axis direction (processing feed direction). The cutting unit 32 is located above the chuck table.

The cutting unit 32 has a spindle housing (not shown) with a longitudinal portion extending along the Y-axis direction (indexing feed direction). The spindle housing is configured to be movable along the Y-axis direction and the Z-axis direction.

A camera unit (not shown), such as an infrared camera, is fixed to the spindle housing. The camera unit is used to detect the planned division line 12, among other things. The camera unit has a predetermined optical system including an objective lens and an imaging element such as a CCD (Charge-Coupled Device) image sensor.

The spindle housing rotatably accommodates a portion of a cylindrical spindle 34, the longitudinal axis of which is aligned along the Y-axis direction. A rotary drive source (not shown), such as a motor, is provided at the base end of the spindle 34, and a cutting blade 36 with an annular cutting edge is attached to the tip end of the spindle 34.

In the dividing step S30, first, dicing tape (not shown) is attached to the back surface 4b of the support substrate 4, and then the back surface 4b is held by suction on a chuck table. Next, an image of the front surface 4a is captured by a camera unit.

By imaging the front surface 4a, any target such as the outer edge of the device chip 6 or a predetermined pattern (alignment mark, key pattern) pre-installed on the front surface 4a is used as a landmark to adjust the orientation of the chuck table so that the planned division line 12 is approximately parallel to the X-axis direction.

Then, the laminate of the support substrate 4 and the sealing substrate 15 is divided into individual device packages 2 along each planned division line 12. Figure 10 shows the device package 2 after division step S30.

In this embodiment, the warpage of the central convex shape in the sealing substrate 15 can be reduced compared to when the dummy chip 10 is not arranged. Furthermore, the warpage can be reduced even compared to when the dummy chip 20 is arranged. Therefore, the stack of the support substrate 4 and the sealing substrate 15 is relatively easy to handle when transporting, holding by suction, processing, etc., and the device package 2 can be relatively easily manufactured.

Next, a second embodiment will be described. Figure 11 is a flow diagram of a method for manufacturing a device package 2 in the second embodiment. The second embodiment differs from the first embodiment mainly in that a separation step S26 and a rewiring layer formation step S28 are performed. Note that a description of content that overlaps with the first embodiment will be omitted.

In the placement step S10 of the second embodiment, the device chip 6 and dummy chip 10 are temporarily fixed to the support substrate 4 with an adhesive layer (not shown). The adhesive layer is, for example, an ultraviolet-curing resin whose adhesive strength decreases when exposed to ultraviolet light.

The support substrate 4 in the second embodiment is a substantially transparent glass substrate having a thickness of 700 μm to 800 μm and no circuits or the like formed thereon. The support substrate 4 is also capable of transmitting ultraviolet light when the adhesive strength of the adhesive layer is reduced. The support substrate 4 in the second embodiment is intended to be separated from the sealing substrate 15 in the separation step S26.

In the second embodiment, after the sealing substrate formation step S20 and before the division step S30, a separation step S26 is performed to separate the support substrate 4 and the sealing substrate 15. Figure 12 shows the separation step S26.

In the separation step S26, light having a wavelength in the ultraviolet band, a laser beam, or the like is irradiated through the support substrate 4 to reduce the adhesive strength, and then the support substrate 4 and the sealing substrate 15 are separated by pulling them apart relative to each other.

If any adhesive layer remains on the sealing substrate 15, this remaining adhesive layer is removed by physical or chemical treatment. Next, a rewiring layer 17 is formed on the surface 15a of the sealing substrate 15 that faced the surface 4a of the support substrate 4 (rewiring layer formation step S28).

Figure 13 shows the redistribution layer formation step S28. The redistribution layer 17 includes a low-dielectric constant interlayer insulating film (low-k film) and a metal wiring layer formed in the low-dielectric constant interlayer insulating film. After the redistribution layer formation step S28, the stack of the redistribution layer 17 and the sealing substrate 15 is divided into device chips 6 (division step S30).

Figure 14 is a diagram showing the division step S30 in the second embodiment. In the second embodiment, terminals exposed on one surface of the redistribution layer 17 can be used as alignment marks, so the camera unit mounted on the cutting unit 32 is a camera unit that captures images with wavelengths in the visible light band.

The second embodiment also reduces warpage of the central convex shape in the sealing substrate 15. This makes it relatively easy to handle the laminate of the sealing substrate 15 and the redistribution layer 17 during transport, suction holding, processing, etc., and makes it relatively easy to manufacture the device package.

Next, a third embodiment will be described with reference to FIG. 15. In the third embodiment, in the placement step S10, the device chip 6 and dummy chip 10 are placed on the surface 4a of the support substrate 4 on which the redistribution layer 17 is formed.

For this reason, the above-mentioned adhesive layer is provided between the rewiring layer 17 and the surface 4a of the support substrate 4. In addition, a conductive adhesive (not shown) is provided in advance in each rectangular area of the rewiring layer 17 where the device chips 6 and dummy chips 10 are arranged.

Once the device chip 6 and dummy chip 10 are placed in the corresponding rectangular regions on the rewiring layer 17 (i.e., on the surface 4a side), they are fixed to the rewiring layer 17 with a conductive adhesive (placement step S10). The dummy chip 10 may also be fixed to the rewiring layer 17 with a non-conductive resin adhesive.

Figure 15 is a cross-sectional view of the support substrate 4 and other components after placement step S10 in the third embodiment. The steps following placement step S10 are the same as those in the flow diagram shown in Figure 11, except that redistribution layer formation step S28 is omitted.

In an alternative embodiment, a silicon circuit board (not shown) approximately 50 μm thick may be provided instead of the redistribution layer 17. The circuit board has a predetermined circuit and functions to control the operation of the device chip 6.

Next, modified examples of the dummy chip 10 will be described with reference to Figures 16(A) to 16(C). Figures 16(A) to 16(C) correspond to enlarged cross-sectional views (see Figure 8(B)) of the stack of the support substrate 4 and the sealing substrate 15 after the curing step S24.

Figure 16 (A) shows a dummy chip 40 in a first modified example. The dummy chip 40 has a lower surface (first surface) 40a facing the front surface 4a and an upper surface (second surface) 40b located on the opposite side of the lower surface 40a in the thickness direction 40c, and the area of the upper surface 40b is larger than the area of the lower surface 40a.

The dummy chip 40 has a square plate shape from the top surface 40b to approximately half 40d in the thickness direction 40c, including a side surface _40e1 perpendicular to the top surface 40b. Furthermore, from approximately half 40d in the thickness direction 40c to the bottom surface 40a, the dummy chip 40 has four tapered side surfaces _40e2 , each of which has an inverted truncated pyramid shape that gradually becomes thinner in the thickness direction 40c.

Like the dummy chip 10, the dummy chip 40 has an upper surface 40b measuring 6 mm in length and 6 mm in width, a lower surface 40a measuring 5 mm in length and 5 mm in width, and a thickness of 0.6 mm.

When manufacturing dummy chips 40, for example, the above-mentioned bevel blade is first cut into the bare wafer to half its thickness, and half-cut grooves are formed along multiple planned division lines (not shown) set in a grid pattern.

Then, a cutting blade with a thinner blade thickness than the bevel blade is used to further cut into the bottom of the half-cut groove to break the bare wafer into smaller pieces, thereby forming a dummy chip 40 in which the top half of the surface 40b is flat and the bottom half of the surface 40a is in the shape of an inverted truncated pyramid.

Figure 16 (B) shows a dummy chip 50 in a second modified example. The dummy chip 50 has a lower surface (first surface) 50a facing the front surface 4a, and an upper surface (second surface) 50b located on the opposite side of the lower surface 50a in the thickness direction 50c. However, as with the dummy chip 10, the area of the upper surface 50b of the dummy chip 50 is larger than the area of the lower surface 50a.

The dummy chip 50 has a square flat plate shape from the top surface 50b to approximately half 50d in the thickness direction 50c, including a side surface _50e1 perpendicular to the top surface 50b. Also, the dummy chip 50 has a square flat plate shape from approximately half 50d in the thickness direction 50c to the bottom surface 50a, including a side surface _50e2 perpendicular to the bottom surface 50a.

The side surfaces _50e1 and _50e2 form stepped sides. For example, the dummy chip 50 has an upper surface 50b measuring 6 mm in length and 6 mm in width, a lower surface 50a measuring 3 mm in length and 3 mm in width, and a thickness of 0.6 mm.

For example, the dummy chip 50 is first created by cutting a flat-dressed cutting blade into the bare wafer to half its thickness, and then forming half-cut grooves along multiple planned division lines (not shown) set in a grid pattern.

Note that a flat-dressed cutting blade refers to a cutting blade whose outer peripheral side (i.e., the shape of the tip of the cutting blade) is approximately flat when viewed in a cross section passing through the radial direction of the annular cutting blade.

After forming the half-cut groove, a regular cutting blade with a thinner blade is used to further cut into the bottom of the half-cut groove and break the bare wafer into smaller pieces, thereby forming dummy chips 50 with stepped sides.

Figure 16(C) shows a dummy chip 60 in a third modified example. The dummy chip 60 has an upper chip (second chip) 62 and a lower chip (first chip) 64, each of which is a substantially square, flat plate.

The dummy chip 60 is formed, for example, by stacking an upper chip 62 and a lower chip 64, each formed by cutting a bare wafer into small pieces, and fixing them together with an adhesive (not shown).

The lower chip 64 has a lower surface (first surface) 60a facing the front surface 4a, and the upper chip 62 has an upper surface (second surface) 60b located on the opposite side of the lower surface 60a in the thickness direction 60c. As shown in Figure 16 (C), when viewed in a plane, the upper chip 62 has a larger area than the lower chip 64.

In other words, like the dummy chip 10, the area of the upper surface 60b of the dummy chip 60 is larger than the area of the lower surface 60a. The sides of the upper chip 62 and the lower chip 64 form a stepped shape.

For example, the upper chip 62 is 6 mm long, 6 mm wide, and 0.3 mm thick, and the lower chip 64 is 3 mm long, 3 mm wide, and 0.3 mm thick. Using the first to third variants also reduces the warpage of the central convex shape in the sealing substrate 15.

In addition, the structures, methods, etc. according to the above-described embodiments may be modified as appropriate without departing from the scope of the present invention. For example, the dummy chips used in the first to third embodiments may be a combination of two or more of the dummy chips 10, 40, 50, and 60.

In the above explanation, an example was given in which dummy chips 10, 40, 50, and 60 were formed by dicing a bare wafer, but as long as the condition that the second surface is larger than the first surface is met, dummy chips 10, 40, 50, and 60 may also be formed by dicing a device wafer.

In the above description, the dummy chips 10, 40, 50, and 60 are arranged only in the outer peripheral portion _4a2 on the front surface 4a of the support substrate _4. However, if there is an empty area (excluding the planned division lines 12) in the rectangular central portion _4a1 where no device chips 6 are arranged, in addition to the outer peripheral portion 4a2, the dummy chips 10, 40, 50, and 60 may be arranged in this empty area.

By the way, since the dummy chips 10, 40, 50, and 60 have an inverted truncated pyramid shape or a stepped shape, they appear rectangular (e.g., square) when viewed from above on the surface 4a side. However, because they have an inverted truncated cone shape, they may appear circular when viewed from above on the surface 4a side.

Furthermore, the dummy chips 10, 40, 50, and 60 may have an inverted triangular truncated pyramid shape, which may make them appear triangular when viewed from above on the surface 4a side, or may have an inverted polygonal truncated pyramid shape with pentagons or more, which may make them appear polygonal with pentagons or more when viewed from above on the surface 4a side.

Furthermore, the diameter of the support substrate 4 may be larger or smaller than 6 inches (approximately 150 mm) depending on the arrangement and number of device chips 6 and dummy chips 10, 40, 50, 60, etc., arranged on the front surface 4a side. For example, the diameter of the support substrate 4 is 12 inches (approximately 300 mm) or 4 inches (approximately 100 mm).

2: Device package 4: Support substrate, 4a: Front surface, _4a1 : Central portion, _4a2 : Peripheral portion 4b: Back surface, 4c: Notch 6: Device chip, 6a: Predetermined distance, 8a: First direction, 8b: Second direction 10: Dummy chip, 10a: Lower surface (first surface), 10b: Upper surface (second surface)
10c: thickness direction, 10d: side surface, 11: resin (liquid), 13: resin (solid), 13a: predetermined thickness region, 12: planned division lines, 14a, 14b, 16a, 16b: distance, 15: sealing substrate, 15a: one surface, 17: rewiring layer, 20: dummy chip, 20a: lower surface, 20b: upper surface, 24a, 24b, 26a, 26b: distance, 30: cutting device, 32: cutting unit, 34: spindle, 36: cutting blade, 40, 50, 60: dummy chip, 40a, 50a, 60a: lower surface (first surface),
40b, 50b, 60b: Top surface (second surface)
40c, 50c, 60c: thickness direction 40d, 50d: halves, 40e ₁ , 40e ₂ , 50e ₁ , 50e ₂ : side surface 62: upper chip (second chip), 64: lower chip (first chip), B: predetermined direction S10: placement step S12: device chip placement step, S14: dummy chip placement step S20: sealing substrate formation step, S22: resin supply step, S24: hardening step S26: separation step, S28: rewiring layer formation step, S30: division step

Claims (6)

1. A method of manufacturing a device package, comprising:
an arrangement step of arranging a plurality of device chips at a distance from each other on a front surface side of a support substrate and arranging one or a plurality of dummy chips in an area of the front surface side where no device chips are arranged;
a sealing substrate forming step of sealing each device chip and each dummy chip arranged on the front surface side of the support substrate with resin to form a sealing substrate on the front surface side;
a dividing step of dividing the encapsulation substrate into individual device packages;
Each dummy chip has a first surface and a second surface located on the opposite side of the first surface in the thickness direction and having an area larger than that of the first surface;
In the arranging step, each dummy chip is arranged on the front surface side so that the first surface faces the front surface of the support substrate ;
after the sealing substrate forming step and before the dividing step, a first surface of each device chip and the first surface of each dummy chip are covered with the support substrate made of single crystal silicon, and a second surface of each device chip and the second surface of each dummy chip located on the opposite side to the first surface of each device chip in the thickness direction of each device chip are covered with the resin;
After the dividing step, the first surface of each device chip remains covered by a portion of the support substrate . Each dummy chip tapers in the thickness direction going from the second surface to the first surface,
2. The method for manufacturing a device package according to claim 1, wherein in the placing step, each dummy chip is placed on the surface of the support substrate so that the first surface faces the surface. At least one dummy chip has a tapered or stepped side,
3. The method for manufacturing a device package according to claim 1, wherein in the arranging step, each dummy chip is arranged on the front surface side of the support substrate so that the first surface faces the front surface. 1. A method of manufacturing a device package, comprising:
an arrangement step of arranging a plurality of device chips at a distance from each other on a front surface side of a support substrate and arranging one or a plurality of dummy chips in an area of the front surface side where no device chips are arranged;
a sealing substrate forming step of sealing each device chip and each dummy chip arranged on the front surface side of the support substrate with resin to form a sealing substrate on the front surface side;
a separating step of separating the support substrate and the sealing substrate by relatively separating the support substrate and the sealing substrate;
a rewiring layer forming step of forming a rewiring layer including a low dielectric constant interlayer insulating film and a metal wiring layer formed in the low dielectric constant interlayer insulating film on one surface of the sealing substrate that faced the support substrate;
a dividing step of dividing the encapsulation substrate into individual device packages;
Each dummy chip has a first surface and a second surface located on the opposite side of the first surface in the thickness direction and having an area larger than that of the first surface;
In the arranging step, each dummy chip is arranged on the front surface side so that the first surface faces the front surface of the support substrate;
a first surface of each device chip and a first surface of each dummy chip that are located on the opposite side of the first surface of each device chip in the thickness direction of each device chip to the first surface of each device chip in the thickness direction of each device chip, the first surface of each device chip and the second surface of each dummy chip that are located on the opposite side of the first surface of each device chip in the thickness direction of each device chip, the second ... covered with the resin; 1. A method of manufacturing a device package, comprising:
an arrangement step of arranging a plurality of device chips at a distance from each other on a front surface side of a support substrate and arranging one or a plurality of dummy chips in an area of the front surface side where no device chips are arranged;
a sealing substrate forming step of sealing each device chip and each dummy chip arranged on the front surface side of the support substrate with resin to form a sealing substrate on the front surface side;
a dividing step of dividing the encapsulation substrate into individual device packages;
Each dummy chip has a first surface and a second surface located on the opposite side of the first surface in the thickness direction and having an area larger than that of the first surface;
In the arranging step, each dummy chip is arranged on the front surface side so that the first surface faces the front surface of the support substrate;
after the sealing substrate forming step and before the dividing step, a first surface of each device chip and the first surface of each dummy chip are covered with a rewiring layer including a low-dielectric-constant interlayer insulating film and a metal wiring layer formed in the low-dielectric-constant interlayer insulating film, and a second surface of each device chip and the second surface of each dummy chip located on the opposite side to the first surface of each device chip in the thickness direction of each device chip are covered with the resin;
After the dividing step, the first surface of each device chip remains covered with a portion of the redistribution layer. 1. A method of manufacturing a device package, comprising:
an arrangement step of arranging a plurality of device chips at a distance from each other on a front surface side of a support substrate and arranging one or a plurality of dummy chips in an area of the front surface side where no device chips are arranged;
a sealing substrate forming step of sealing each device chip and each dummy chip arranged on the front surface side of the support substrate with resin to form a sealing substrate on the front surface side;
a dividing step of dividing the encapsulation substrate into individual device packages;
Each dummy chip has a first surface and a second surface located on the opposite side of the first surface in the thickness direction and having an area larger than that of the first surface;
In the arranging step, each dummy chip is arranged on the front surface side such that the first surface faces the front surface of the support substrate;
At least one dummy chip
a flat first chip;
a second chip having a flat plate shape and having an area larger than that of the first chip when viewed from above and stacked on the first chip;
and
In the placing step, the at least one dummy chip is placed on the front surface side of the support substrate so that the first chip faces the front surface.