JP7804466B2 - Chip Varistor - Google Patents

Description

The present invention relates to a chip varistor.

Chip varistors with a varistor structure provided inside the element body are known. The following Patent Documents 1 and 2 disclose multilayer chip varistors that have multiple conductors provided inside an element body with a multilayer structure, and multiple electrodes provided on the surface of the element body so as to be connected to each of the multiple conductors.

International Publication No. 2018/144987 International Publication No. 2021/095368

In the chip varistor described above, the varistor characteristics can be adjusted by adjusting the dimensions of the element region (functional region) sandwiched between the conductors in the stacking direction. The inventors have conducted extensive research into adjusting varistor characteristics and have discovered a new technology that allows for easy adjustment of varistor characteristics.

The objective of the present invention is to provide a chip varistor whose varistor characteristics can be easily adjusted.

A chip varistor according to one embodiment of the present invention comprises an element body having a laminated structure and having first and second surfaces that extend parallel to the lamination direction and face each other, and third and fourth surfaces that extend parallel to the lamination direction, connect the first and second surfaces, and face each other; a first conductor extending from the first surface in a predetermined layer of the element body along the opposing direction between the first and second surfaces; a second conductor extending from the second surface in a predetermined layer of the element body along the opposing direction between the first and second surfaces; a third conductor extending from the third surface to the fourth surface and extending in a direction intersecting the opposing direction between the third and fourth surfaces, and having an intersection portion that forms an overlapping portion with each of the first conductor and the second conductor in the lamination direction of the element body; a first electrode provided on the first surface of the element body and connected to the first conductor; a second electrode provided on the second surface of the element body and connected to the second conductor; and a pair of third electrodes provided on the third and fourth surfaces of the element body, respectively, and connected to ends of the third conductor.

In the above chip varistor, the third conductor has an intersection, and the third conductor forms overlapping portions where it overlaps with the first conductor and the second conductor at the intersection. Therefore, by adjusting the shape and dimensions of the intersection of the third conductor, the dimensions of the functional area can be easily adjusted, and thereby the varistor characteristics can be easily adjusted.

In another embodiment of the chip varistor, when the distance from the connection point between the first conductor and the first electrode to the overlapping portion where the first conductor and the third conductor overlap is L1, and the distance from the connection point between the third conductor and the third electrode to the overlapping portion where the first conductor and the third conductor overlap, along the shape of the third conductor, is L2, the relationship L1/2≦L2≦2L1 is satisfied.

In another embodiment of the chip varistor, the third conductor has a widening portion whose width gradually increases from the end toward the intersection when viewed in the stacking direction of the element body.

In another embodiment of the chip varistor, the first conductor and the second conductor extend within the same layer of the element body.

In another embodiment of the chip varistor, the width of the first conductor and the second conductor is the same as the width of the intersection of the third conductor.

In another embodiment of the chip varistor, the widths of the first and second conductors are different from the width of the intersection of the third conductor.

The present invention provides a chip varistor whose varistor characteristics can be easily adjusted.

1 is a schematic perspective view showing a chip varistor according to an embodiment. FIG. 2 is a perspective view showing each conductor inside the element body shown in FIG. 1 . 2 is a cross-sectional view showing each conductor inside the element body shown in FIG. 1. FIG. 3 is a cross-sectional view showing the positional relationship of each conductor. FIG. 3 is a cross-sectional view showing the positional relationship of each conductor. FIG. 10 is a cross-sectional view showing a chip varistor according to a different embodiment. FIG. 10 is a cross-sectional view showing a chip varistor according to a different embodiment. FIG. 10 is a cross-sectional view showing a chip varistor according to a different embodiment. FIG. 10 is a cross-sectional view showing a chip varistor according to a different embodiment. FIG. 10 is a cross-sectional view showing a chip varistor according to a different embodiment. FIG. 10 is a cross-sectional view showing a chip varistor according to a different embodiment. FIG. 10 is a cross-sectional view showing a chip varistor according to a different embodiment.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that, in the description, identical elements or elements with identical functions will be designated by the same reference numerals, and duplicate descriptions will be omitted.

First, the configuration of the chip varistor 1 according to the embodiment will be described with reference to Figures 1 to 3.

The chip varistor 1 is a multi-terminal multilayer chip varistor, and is composed of an element body 10 and four terminal electrodes 20A to 20D. The chip varistor 1 has a roughly rectangular parallelepiped outer shape, and is the so-called 1608 size (longitudinal length: 1.6 mm, lateral length: 0.8 mm, height: 0.8 mm).

Element body 10 is a laminated structure with a roughly rectangular parallelepiped outer shape. Element body 10 has rectangular end faces 10a and 10b that face each other in the longitudinal direction, and four rectangular side faces 10c to 10f that are perpendicular to end faces 10a and 10b. The four side faces 10c to 10f extend to connect end faces 10a and 10b. End faces 10a and 10b extend parallel to the stacking direction of element body 10. Of the four side faces 10c to 10f, side faces 10c and 10d extend parallel to the stacking direction of element body 10 and face each other. Of the four side faces 10c to 10f, side faces 10e and 10f extend perpendicular to the stacking direction of element body 10 and face each other in the stacking direction of element body 10.

The element body 10 is made of a sintered body (semiconductor ceramic) that exhibits varistor characteristics. The element body 10 is a laminated structure consisting of multiple layers of sintered bodies that exhibit varistor characteristics. In an actual element body 10, the constituent layers are integrated to the extent that the boundaries between them are not visible. The element body 10 contains ZnO (zinc oxide) as its primary component, and also contains metals and oxides thereof as secondary components, such as Co, rare earth metal elements, Group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, Rb, Cs), and alkaline earth metal elements (Mg, Ca, Sr, Ba). In this embodiment, the element body 10 contains Co, Pr, Cr, Ca, K, and Al as secondary components. The ZnO content in the element body 10 is not particularly limited, but is typically 99.8 to 69.0% by mass, assuming that the total material constituting the element body 10 is 100% by mass. Rare earth metal elements (e.g., Pr) act as substances that exhibit varistor characteristics. The content of rare earth metal elements in the element body 10 is set to, for example, approximately 0.01 to 10 atomic percent.

The chip varistor 1 comprises a pair of first conductors 30A, a pair of second conductors 30B, and a third conductor 30C within the element body 10. The first conductors 30A, the second conductors 30B, and the third conductors 30C contain conductive materials. The conductive material contained in each of the conductors 30A, 30B, and 30C is not particularly limited, but is preferably made of Pd or an Ag-Pd alloy. The thickness (length in the stacking direction) of each of the conductors 30A, 30B, and 30C is, for example, approximately 0.1 to 10 μm.

The pair of first conductors 30A each have a band-like shape with a uniform width, and extend in the opposing direction of the end faces 10a, 10b within the layers that make up the element body 10. The pair of first conductors 30A are located in different layers of the element body 10. One end 30a of each first conductor 30A is exposed at the end face 10a (first surface), and the other end 30b is located within the element body 10. The pair of first conductors 30A have the same dimensions and shape when viewed from the stacking direction of the element body 10, and are completely aligned. The width w1 of the first conductors 30A (the length in the opposing direction of the side faces 10c, 10d) is, for example, 0.4 mm.

The pair of second conductors 30B each have a band-like shape with a uniform width, and extend in the same layer as the first conductor 30A, along the opposing direction of the end faces 10a, 10b. One end 30a of the second conductor 30B is exposed at the end face 10b (second surface), and the other end 30b is located within the element body 10. The pair of second conductors 30B have the same dimensions and shape when viewed from the stacking direction of the element body 10, and are completely aligned. The width of the second conductors 30B is designed to be the same as the width w1 of the first conductors 30A, for example, 0.4 mm.

The first conductor 30A and the second conductor 30B are aligned with each other when viewed from the stacking direction of the element body 10, and extend toward each other along the opposing direction of the end faces 10a, 10b. However, the end 30b of the first conductor 30A and the end 30b of the second conductor 30B located within the element body 10 are spaced apart in the opposing direction of the end faces 10a, 10b, and do not overlap in the stacking direction of the element body 10.

The third conductor 30C has a shape that extends along the opposing direction of the side surfaces 10c and 10d, and extends from the side surface 10c (third surface) to the side surface 10d (fourth surface). As shown in Figure 3, the third conductor 30C has a pair of end portions 31 and an intersection portion 32.

Each end 31 of the third conductor 30C is located near the side surfaces 10c and 10d and is exposed from the side surfaces 10c and 10d. Each end 31 has a uniform width W1 (the length in the opposing direction of the end surfaces 10a and 10b), which is, for example, 0.2 mm.

The intersection 32 of the third conductor 30C is located at the center of the third conductor 30C between both end portions 31 and extends in a direction intersecting the direction in which the side surfaces 10c, 10d face each other. In this embodiment, the intersection 32 of the third conductor 30C extends in a direction perpendicular to the direction in which the side surfaces 10c, 10d face each other, and the width W2 of the intersection 32 (the length in the direction in which the end faces 10a, 10b face each other) is designed to be wider than the width W1 of the end portion 31 (W2 > W1). The width W2 of the intersection 32 is, for example, 0.6 mm. The third conductor 30C as a whole has a cross shape when viewed in the stacking direction of the element body 10. In this embodiment, the length (width) w2 of the intersection 32 in the direction in which the side surfaces 10c, 10d face each other is designed to be the same as the width w1 of the first conductor 30A and the second conductor 30B.

The intersection 32 of the third conductor 30C overlaps with the end 30b of the first conductor 30A at its tip extending toward the end face 10a, forming an overlapping portion 40A. Similarly, the intersection 32 of the third conductor 30C overlaps with the end 30b of the second conductor 30B at its tip extending toward the end face 10b, forming an overlapping portion 40B. The third conductor 30C overlaps with the pair of first conductors 30A only at the overlapping portion 40A, and with the pair of second conductors 30B only at the overlapping portion 40B.

As shown in Figures 4 and 5, the third conductor 30C extends within a layer located midway between a pair of first conductors 30A. Therefore, in the stacking direction of the element body 10, the distance between the third conductor 30C and one of the first conductors 30A is substantially the same as the distance between the third conductor 30C and the other first conductor 30A. The intersection 32 forms a first functional layer 42 between each of the ends 30b of the pair of first conductors 30A. The first functional layer 42 is a portion of the element body sandwiched between the tip 32a of the intersection 32 and the end 30b of the first conductor 30A. The first functional layer 42 has a capacitance of, for example, approximately 20 to 50 pF. Similarly, in the stacking direction of the element body 10, the distance between the third conductor 30C and one of the second conductors 30B is substantially the same as the distance between the third conductor 30C and the other second conductor 30B. The intersection 32 forms a second functional layer 44 between each of the ends 30b of the pair of second conductors 30B. The second functional layer 44 is an element portion sandwiched between the tip 32b of the intersection 32 and the end 30b of the second conductor 30B. The second functional layer 44 has a capacitance of, for example, approximately 20 to 50 pF. In this embodiment, the overlapping portion 40A and the overlapping portion 40B have the same overlapping area, and therefore the first functional layer 42 and the second functional layer 44 have substantially the same capacitance.

The first electrode 20A, one of the four terminal electrodes 20A-20D, is positioned on the end face 10a side of the element body 10. The first electrode 20A is formed to cover the end face 10a and the portions of the four side faces 10c-10f closer to the end face 10a. The first electrode 20A is also formed to cover one end 30a of each of a pair of first conductors 30A exposed on the end face 10a of the element body 10, and the first electrode 20A is directly connected to each of the pair of first conductors 30A.

The element is designed so that the relationship L1/2≦L2≦2L1 is satisfied, where L1 is the distance from the connection point between the first conductor 30A and the first electrode 20A to the overlapping portion 40A, and L2 is the distance from the connection point between the third conductor 30C and the third electrodes 20C, 20D to the overlapping portion 40A along the shape of the third conductor 30C (more specifically, the outer shape when viewed from the stacking direction of the element body 10). In this embodiment, the distance from the connection point between the second conductor 30B and the second electrode 20B to the overlapping portion 40B is the same as the distance L1 from the connection point between the first conductor 30A and the first electrode 20A to the overlapping portion 40A. Furthermore, in this embodiment, the distance from the connection point between the third conductor 30C and the third electrodes 20C, 20D to the overlapping portion 40B along the shape of the third conductor 30C is the same as the distance L2 to the overlapping portion 40B along the shape of the third conductor 30C. In this embodiment, distance L2 is the length of the L-shaped portion along the outer shape of the third conductor 30C, and is calculated as the sum of the lengths of the two straight lines.

The second electrode 20B, one of the four terminal electrodes 20A-20D, is positioned on the end face 10b side of the element body 10. The second electrode 20B is formed to cover the end face 10b and the portions of the four side faces 10c-10f that are closer to the end face 10b. The second electrode 20B is also formed to cover one end 30a of each of a pair of second conductors 30B exposed on the end face 10b of the element body 10, and the second electrode 20B is directly connected to each of the pair of second conductors 30B.

Of the four terminal electrodes 20A-20D, third electrodes 20C and 20D form a pair and are arranged on side surfaces 10c and 10d of the element body 10, respectively. Specifically, third electrode 20C extends in the stacking direction at the midpoint of the long side of rectangular side surface 10c and wraps around side surfaces 10e and 10f, while third electrode 20D extends in the stacking direction at the midpoint of the long side of rectangular side surface 10d and wraps around side surfaces 10e and 10f. Third electrodes 20C and 20D are also formed to cover both end portions 31 of third conductor 30C exposed on side surfaces 10c and 10d of the element body 10, respectively, and third electrodes 20C and 20D are directly connected to third conductor 30C. Because the pair of third electrodes 20C and 20D and third conductor 30C are arranged symmetrically, uniform discharge can be achieved.

Each of the terminal electrodes 20A-20D may have a single-layer structure or a multi-layer structure. Each of the terminal electrodes 20A-20D is, for example, a fired electrode, formed by applying a conductive paste to the surface of the element body 10 and firing it. The conductive paste is made by mixing a powder made of a metal (for example, Pd, Cu, Ag, or an Ag-Pd alloy) with a glass component, an organic binder, and an organic solvent. A plating layer can also be formed on such a fired electrode. The plating layer may include a Ni plating layer and a Sn plating layer formed on the Ni plating layer.

In the chip varistor 1 described above, the third conductor 30C has an intersection 32, and the third conductor 30C forms overlapping portions 40A and 40B that overlap the first conductor 30A and the second conductor 30B, respectively, at the intersection 32. Therefore, by adjusting the shape and dimensions of the intersection 32 of the third conductor 30C, the dimensions of the functional regions of the first functional layer 42 and the second functional layer 44 can be easily adjusted, and thereby the varistor characteristics can be easily adjusted.

In addition, in the chip varistor 1, the distance L1 from the connection point between the first conductor 30A and the first electrode 20A to the overlapping portion 40A and the distance L2 from the connection point between the third conductor 30C and the third electrodes 20C, 20D along the shape of the third conductor 30C to the overlapping portion 40A satisfy the relationship L1/2≦L2≦2L1, thereby improving the symmetry of the varistor characteristics. Furthermore, because the distance L2 is the length of the L-shaped portion that follows the external shape of the third conductor 30C and is calculated as the sum of the lengths of two straight lines, the conductor design can be performed without changing the chip size.

Each of the conductors 30A to 30C of the chip varistor 1 can be modified into various shapes, such as those shown in Figures 6 to 9.

The embodiment shown in Figure 6 differs from the chip varistor 1 described above only in that the length w2 of the intersection 32 in the opposing direction of the side surfaces 10c, 10d is different from the width w1 of the first conductor 30A and the second conductor 30B, and the length w2 is narrower than the width w1. In the embodiment shown in Figure 6, even if a relative positional misalignment occurs between the intersection 32 of the third conductor 30C and the first conductor 30A and the second conductor 30B in the opposing direction of the side surfaces 10c, 10d, for example, during conductor formation, the overlapping area of the overlapping portions 40A, 40B does not change. This makes it possible to suppress variations in the characteristics of individual chip varistor products.

The embodiment shown in Figure 7 differs from the chip varistor 1 described above only in that the length w2 of the intersection 32 in the opposing direction of the side surfaces 10c, 10d is different from the width w1 of the first conductor 30A and the second conductor 30B, and the length w2 is wider than the width w1. In the embodiment shown in Figure 7, as in the embodiment shown in Figure 6, even if a relative positional misalignment occurs between the intersection 32 of the third conductor 30C and the first conductor 30A and the second conductor 30B in the opposing direction of the side surfaces 10c, 10d, for example, during conductor formation, the overlapping area of the overlapping portions 40A, 40B does not change. This makes it possible to suppress variations in the characteristics of individual chip varistor products.

The embodiment shown in Figure 8 differs from the chip varistor 1 described above only in that the length w2 of the intersection 32 in the opposing direction of the side surfaces 10c, 10d is different at one end 32a and the other end 32b of the intersection 32. In the embodiment shown in Figure 8, the overlapping area of the overlapping portions 40A, 40B can be changed without changing the dimensions and shapes of the first conductor 30A and the second conductor 30B, thereby making it possible to differentiate the varistor characteristics between the path (channel) passing through the first conductor 30A and the path passing through the second conductor 30B.

The embodiment shown in Figure 9 differs from the chip varistor 1 described above only in that widened portions 33, which are portions whose width gradually widens from the end portions 31 toward the intersection portions 32, are interposed between both end portions 31 and the intersection portions 32 of the third conductor 30C. In the embodiment shown in Figure 9, because the third conductor 30C has widened portions 33, even if the end portions 31 and the intersection portions 32 have different widths, stress concentration at the boundaries between the end portions 31 and the intersection portions 32 is suppressed, and the occurrence of defects such as cracks is suppressed.

The stacked structure of each conductor 30A-30C of the chip varistor 1 can also be changed, for example, to the stacked structures shown in Figures 10-12.

In the embodiment shown in FIG. 10, the first conductor 30A is one layer, the second conductor 30B is also one layer, and the first conductor 30A and the second conductor 30B extend within the same layer. In the embodiment shown in FIG. 11, the first conductor 30A is one layer, the second conductor 30B is also one layer, and the first conductor 30A and the second conductor 30B extend within different layers, and the third conductor 30C extends within a layer located intermediate the first conductor 30A and the second conductor 30B. In the embodiment shown in FIG. 12, the first conductor 30A is one layer, the second conductor 30B is also one layer, and the third conductor 30C is two layers. The two layers of third conductor 30C have the same dimensions and shape when viewed in the stacking direction of the element body 10, and are completely aligned. Furthermore, the first conductor 30A and the second conductor 30B extend within the same layer located intermediate the two layers of third conductor 30C.

In the chip varistor 1 of the embodiment shown in Figures 6 to 12, the third conductor 30C also has an intersection 32, and the third conductor 30C forms overlapping portions 40A and 40B that overlap with the first conductor 30A and the second conductor 30B, respectively, at the intersection 32. Therefore, by adjusting the shape and dimensions of the intersection 32 of the third conductor 30C, the dimensions of the functional regions of the first functional layer 42 and the second functional layer 44 can be easily adjusted, and thereby the varistor characteristics can be easily adjusted.

The above describes a preferred embodiment of the present invention, but the present invention is not necessarily limited to the above-described embodiment, and various modifications are possible without departing from the spirit of the invention.

For example, distance L2 may be the sum of the lengths of three or more straight lines, as long as it follows the shape of the third conductor 30C. The widened portion of the third conductor may have a width that gradually increases to form a hypotenuse, a width that gradually increases to form a curve, or a width that gradually increases to form a step. The external dimensions of the chip varistor and the element body may be increased or decreased as appropriate. The dimensions of each conductor and each terminal electrode may also be increased or decreased as appropriate. Furthermore, the materials that make up the element body, each conductor, and each terminal electrode may be changed as appropriate to known materials that are applicable to chip varistors.

1...chip varistor, 10...element body, 20A...first electrode, 20B...second electrode, 20C, 20D...third electrode, 30A...first conductor, 30B...second conductor, 30C...third conductor, 31...end, 32...intersection, 33...widened portion, 40A, 40B...overlapped portion, 42...first functional layer, 44...second functional layer.

Claims (7)

an element body having a laminated structure, the element body having a first surface and a second surface extending parallel to the lamination direction and facing each other, and a third surface and a fourth surface extending parallel to the lamination direction, connecting the first surface and the second surface, and facing each other;
a first conductor extending from the first surface along the opposing direction of the first surface and the second surface in a predetermined layer of the element body;
a second conductor extending from the second surface along the opposing direction of the first surface and the second surface in a predetermined layer of the element body;
a third conductor extending from the third surface to the fourth surface and extending in a direction intersecting the opposing direction of the third surface and the fourth surface, the third conductor having an intersection portion forming an overlapping portion overlapping with each of the first conductor and the second conductor in the stacking direction of the element body;
a first electrode provided on the first surface of the element body and connected to the first conductor;
a second electrode provided on the second surface of the element body and connected to the second conductor;
a pair of third electrodes provided on the third surface and the fourth surface of the element body, respectively, and connected to ends of the third conductor;
Equipped with
a relationship of 2L1>W2 is satisfied, where L1 is a distance from a connection point between the first conductor and the first electrode to the overlapping portion where the first conductor and the third conductor overlap, and W2 is a length of the intersection portion in an opposing direction between the first surface and the second surface,
A chip varistor in which the relationship L1/2≦L2≦2L1 is satisfied, where L1 is the distance from the connection point between the first conductor and the first electrode to the overlapping portion where the first conductor and the third conductor overlap, and L2 is the distance from the connection point between the third conductor and the third electrode to the overlapping portion where the first conductor and the third conductor overlap , along the shape of the third conductor. 2. The chip varistor according to claim 1, wherein, when viewed from the stacking direction of the element body, a portion along the outer shape of the third conductor from a connection point between the third conductor and the third electrode to the overlapping portion where the first conductor and the third conductor overlap is L-shaped. 2. The chip varistor according to claim 1 , wherein the third conductor has a widened portion whose width gradually increases from the end portion toward the intersection portion when viewed from the stacking direction of the element body. 4. The chip varistor according to claim 1 , wherein the first conductor and the second conductor extend within the same layer of the element body. 5. The chip varistor according to claim 1 , wherein the widths of the first conductor and the second conductor are the same as the width of the intersection of the third conductor. 5. The chip varistor according to claim 1 , wherein widths of the first conductor and the second conductor are different from a width of the intersection of the third conductor. the third conductor includes a pair of ends sandwiching the intersection in an opposing direction of the third surface and the fourth surface and exposed from the third surface and the fourth surface, respectively;
7. The chip varistor according to claim 1, wherein, with respect to an opposing direction between the first surface and the second surface, the first conductor is provided on the first surface side of a boundary position between the intersection and the end of the third conductor located on the first surface side, and the second conductor is provided on the second surface side of a boundary position between the intersection and the end of the third conductor located on the second surface side.