JP7804867B2 - Substrate processing apparatus, substrate processing method, and storage medium - Google Patents

Description

This disclosure relates to a substrate processing apparatus, a substrate processing method, and a storage medium.

In the manufacturing process of semiconductor devices, semiconductor wafers (hereinafter referred to as wafers) are transported between various processing modules within a substrate processing apparatus, where they undergo processes such as liquid processing and heat treatment. Wafers are transported to the substrate processing apparatus by carriers. Patent Document 1 discloses a substrate processing apparatus equipped with a carrier block that transfers wafers to and from the carrier. This carrier block is equipped with two transport mechanisms that sandwich a stack consisting of multiple substrate mounting sections, and each transport mechanism has a holding section for transferring wafers between the mounting sections, and a holding section for transferring wafers to and from the carrier.

JP 2013-69916 A

This disclosure provides technology that can increase throughput in substrate processing equipment while reducing the floor space required.

The substrate processing apparatus according to the present disclosure includes a carrier block including a carrier placement portion on which a carrier for storing a substrate is placed;
a processing block including a plurality of processing modules stacked on top of each other, each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate, the processing block being provided on either the left or right side of the carrier placement unit in a plan view;
a plurality of processing modules each configured to process the substrate and stacked on top of one another; and a main transport mechanism shared by the plurality of processing modules and configured to transport the substrate, the other processing block being vertically overlapped with the first processing block;
a transport region for the substrate provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view;
a first transport mechanism for transferring the substrate to and from the carrier;
a stack of platform units, each of which receives and delivers the substrate by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, and which are vertically stacked one on top of the other, and which are provided in the transport region in a plan view;
a second transport mechanism provided in the transport region in a plan view for transporting the substrate between the first and second receivers and between the first and third receivers;
Equipped with
In a plan view, a direction in which the stack of the carriers on the placement unit is located relative to a position where the first transport mechanism is provided in the carrier block differs by 90° from a direction in which the carrier placement unit is located relative to a position where the first transport mechanism is provided;
Of the first transport mechanism and the second transport mechanism, only the first transport mechanism delivers the substrate to the carrier.
Another substrate processing apparatus according to the present disclosure includes: a carrier block including a carrier placement portion on which a carrier for storing a substrate is placed;
a processing block including a plurality of processing modules stacked on top of each other, each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate, the processing block being provided on either the left or right side of the carrier placement unit in a plan view;
a plurality of processing modules each configured to process the substrate and stacked on top of one another; and a main transport mechanism shared by the plurality of processing modules and configured to transport the substrate, the other processing block being vertically overlapped with the first processing block;
a transport region for the substrate provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view;
a first transport mechanism for transferring the substrate to and from the carrier;
a stack of platform units, each of which receives and delivers the substrate by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, and which are vertically stacked one on top of the other, and which are provided in the transport region in a plan view;
a second transport mechanism provided in the transport region in a plan view for transporting the substrate between the first and second receivers and between the first and third receivers;
Equipped with
a fourth processing module to which the substrate is transferred by the second transfer mechanism is provided on one of the front and rear sides of the second transfer mechanism;
If the processing module of the one processing block and the processing module of the other processing block are respectively referred to as a first processing module and a second processing module,
the plurality of first processing modules or the plurality of second processing modules includes a coating film forming module that supplies a coating liquid to the substrate to form a coating film;
the fourth processing module is a hydrophobic processing module that performs a gas processing on the substrate to hydrophobize the substrate before the supply of the coating liquid;
An airflow forming mechanism is provided in the transport area to form an airflow from the other of the front and rear sides toward the fourth processing module and an airflow from the first processing block and the other processing block toward the transport area.

This disclosure increases the throughput of substrate processing equipment while reducing the floor space required.

1 is a cross-sectional plan view of a coating and developing apparatus according to an embodiment of a substrate processing apparatus of the present disclosure. FIG. 2 is a vertical sectional front view of the coating and developing apparatus. FIG. 2 is a vertical sectional front view of the coating and developing apparatus. FIG. 2 is a left side view of the coating and developing apparatus. FIG. 2 is a vertical sectional side view of the coating and developing apparatus. 5A to 5C are explanatory views showing the operation of a transport mechanism provided in the coating and developing apparatus. 5A to 5C are explanatory views showing the operation of a transport mechanism provided in the coating and developing apparatus. 5A to 5C are explanatory views showing the operation of a transport mechanism provided in the coating and developing apparatus. FIG. 2 is a schematic view of a transport path in the coating and developing apparatus. FIG. 2 is a schematic view of a transport path in the coating and developing apparatus. 3 is a schematic view showing an air flow formed in the coating and developing apparatus. FIG. FIG. 2 is a schematic diagram showing a wafer transport path in the substrate processing apparatus.

A coating and developing apparatus 1 according to one embodiment of a substrate processing apparatus of the present disclosure will be described with reference to the cross-sectional plan view of FIG. 1 and the longitudinal front views of FIGS. 2 and 3. FIGS. 2 and 3 show cross sections at different positions of the apparatus. The coating and developing apparatus 1 comprises a carrier block D1, a first processing block D2, a second processing block D3, and an interface block D4, arranged in this order in a horizontal linear fashion, with adjacent blocks connected to each other. These blocks (carrier block, first and second processing blocks, interface block) D1 to D4 are each partitioned by a housing, and a transport area for substrates, i.e., wafers W, is formed inside each housing.

In the following explanation, the arrangement direction of these blocks D1 to D4 will be referred to as the left-right direction, with carrier block D1 on the left side and interface block D4 on the right side. Furthermore, in terms of the front-to-back direction of the device, when looking at carrier block D1 from the left, the front will be referred to as the front and the back will be referred to as the rear. The exposure machine 20 is connected to interface block D4, which acts as a relay block, from the right side.

Before explaining each of blocks D1 to D4 in detail, we will explain the general configuration of the coating and developing apparatus 1. Wafers W are transported to the coating and developing apparatus 1 while stored in a carrier C, such as a FOUP (Front Opening Unify Pod). The coating and developing apparatus 1 forms a coating film by supplying various coating liquids, including resist, to the wafer W, and develops the resist film exposed by the exposure machine 20.

The first processing block (left-hand processing block) D2 and the second processing block (right-hand processing block) D3 are each partitioned vertically into two. The lower and upper sides of the partitioned first processing block D2 are referred to as the first lower processing block D21 and the first upper processing block D22, respectively. The lower and upper sides of the partitioned second processing block D3 are referred to as the second lower processing block D31 and the second upper processing block D32, respectively. Therefore, the first lower processing block D21 and the first upper processing block D22 are stacked on top of each other, and the second lower processing block D31 and the second upper processing block D32 are stacked on top of each other. The first lower processing block D21 and the first upper processing block D22 are adjacent to each other, and the second lower processing block D31 and the second upper processing block D32 are adjacent to each other.

Each of these processing blocks (D21, D22, D31, D32) is equipped with the above-mentioned processing modules and a transfer mechanism (main transfer mechanism) capable of transferring wafers to and from the processing modules. Furthermore, the first upper processing block D22 and the second upper processing block D32 are each equipped with a transfer mechanism separate from the transfer mechanism that transfers wafers to the processing modules. Hereinafter, this separate transfer mechanism will be referred to as a shuttle. This shuttle is a bypass transfer mechanism that transfers wafers W to downstream blocks without passing through the processing modules, and the first upper processing block D22 and second upper processing block D32, in which this shuttle is equipped, are bypass transfer path forming blocks.

The first lower processing block D21 and the second lower processing block D31 form an outbound route for transporting wafers W from the carrier block D1 to the interface block D4. The first upper processing block D22 and the second upper processing block D32 form a return route for transporting wafers W that have been exposed in the exposure machine 20 from the interface block D4 to the carrier block D1, and the same type of processing modules are provided so that the same processing can be performed in both blocks. On the return route, wafers W are transported to a processing module by a transport mechanism in one of the first upper processing block D22 and the second upper processing block D32 and processed there, and then transported by a shuttle in the other block.

The first lower processing block D21 and second lower processing block D31 that make up the outbound path may be collectively referred to as lower processing block G1, and the first upper processing block D22 and second upper processing block D32 that make up the return path may be collectively referred to as upper processing block G2. As described above, lower processing block G1 and upper processing block G2 are stacked vertically. By providing a shuttle as described above, wafers W are transported in upper processing block G2 via one of two transport paths. A module is a location other than the transport mechanism (including the shuttle) where wafers W are placed, i.e., a wafer W placement area. A module that processes wafers W is referred to as a processing module as described above, but this processing also includes acquiring images for inspection.

Carrier block D1 will be described below with reference to the side view of Figure 4. Carriers C are loaded and unloaded into carrier block D1 by a carrier transport mechanism (external transport mechanism) (not shown) installed in the clean room where coating and developing apparatus 1 is installed. Carrier block D1 loads and unloads wafers W into and out of carrier C, and is also a block that transfers wafers W to and from upper processing block G2 and lower processing block G1.

The aforementioned housing that constitutes carrier block D1 is designated 11. Housing 11 is formed in a rectangular shape, and its lower side protrudes to the left to form support base 12. Furthermore, on the left side of housing 11 above support base 12, two locations spaced apart vertically protrude to the left, forming support bases 13 and 14. The lower support base and upper support base are designated 13 and 14, respectively.

Each of the support bases 12-14 can accommodate, for example, four carriers C, spaced apart in the front-to-back direction, and each has a stage on which the carriers C are placed, which are arranged, for example, in a 3x4 matrix when viewed from the left. The left end of the support base 12 protrudes further left than the support bases 13 and 14, and the stage for the support base 12 is located to the right of the support base 12, below the support bases 13 and 14. As already mentioned, the interior of the support base 12 is used as an area for storing bottles containing processing liquid for liquid processing in the first processing block D2 and the second processing block D3.

Carriers C can be transferred between each stage using the carrier transfer mechanism 21, which will be described later. Regarding these stages, the two front stages of each of the support bases 13 and 14 are configured as movable stages 15 on which carriers C are placed to load and unload wafers W into and from the equipment. Therefore, a total of four movable stages 15 are arranged in a 2x2 matrix when viewed from the left. The movable stages 15 move between a load position on the right side for loading and unloading wafers W, and an unload position on the left side for transferring carriers C to and from the carrier transfer mechanism 21. In this example, the movable stage 15 of the support base 12 is used as a stage on which carriers C are placed to load unprocessed wafers W into the equipment, while the movable stage 15 of the support base 13 is used as a stage on which carriers C are placed to store processed wafers W in the equipment.

Regarding the other stages, the two rear stages of the support bases 13 and 14 and the two stages on the support base 14 are configured as temporary placement stages 16. The other two stages on the support base 14 are configured as the carry-in stage 17 and the carry-out stage 18. For example, the stage on the rear end side and the stage on the front end side of the support base 14 are the carry-in stage 17 and the carry-out stage 18, respectively. These carry-in stage 17 and carry-out stage 18 are stages on which the carrier C is placed so that the external transport mechanism described above can carry the carrier C into and out of the coating and developing apparatus 1, respectively.

Carrier C is transferred in the following order: loading stage 17 → moving stage 15 on support base 12 → moving stage 15 on support base 13 → unloading stage 18. When transferring carrier C between stages in this way, if the destination stage is not available (if it is occupied by another carrier C), the carrier C will wait on the temporary placement stage 16 until the destination stage becomes available.

A carrier transfer mechanism 21 is provided above the left side of the support base 12. The carrier transfer mechanism 21 includes an articulated arm 22 that can hold the held portion provided on the top of the carrier C, and a movement mechanism 23 that can move the articulated arm 22 up and down and back and forth, and can transfer the carrier C between stages as described above.

Four transfer ports 24 for loading and unloading wafers W are formed on the left side wall of the housing 11, arranged in a 2x2 matrix to match the arrangement of the movable stages 15. Each transfer port 24 is provided with a door 25. The door 25 is capable of holding the lid of the carrier C on the movable stage 15 when it is in the load position, and can move while holding the lid to open and close the transfer port 24.

The transfer opening 24 faces a wafer W transfer area 31 formed within the housing 11. In plan view, the transfer area 31 is formed in a long, linear shape extending from front to back, and is located between the mobile stage 15, which serves as the carrier placement section, and the first processing block G2. A transfer mechanism 32 is provided on the front side (the other side) of the transfer area 31. The transfer mechanism 32 includes a base that is movable back and forth, vertically movable, and rotatable around a vertical axis, and a wafer W holder that can move forward and backward on the base. The transfer mechanism 32, which serves as the first transfer mechanism, can access the carrier C on the mobile stage 15 in the load position described above, and the module stack T1 and pre-processing inspection module 41 described below, to transfer the wafer W.

Carrier block D1 is provided with a third processing module, a pre-processing inspection module 41, which captures an image of the surface of the wafer W before processing by the coating and developing apparatus 1. The image data obtained by this capture is sent to the control unit 10, which will be described later, and the presence or absence of abnormalities in the wafer W is determined by the control unit 10 based on the image data. The pre-processing inspection module 41 has a housing that is elongated and flat in the left-right direction, with the right side located in the center of the front and rear of the transport area 31 and the left side penetrating the left wall of the housing 11 and protruding outside the housing 11.

The housing of the pre-processing inspection module 41 contains a stage 42 that can move left and right within the module, a half mirror 43 located above the path of movement of the stage 42, an illumination unit 44 that emits light downward via the half mirror 43, and a camera 45 located to the left of the half mirror 43 (see Figure 3). A wafer W is delivered to the stage 42, which is located on the right side of the housing, by the transport mechanism 32. As the stage 42 to which the wafer W has been delivered moves to the left side of the housing and passes below the half mirror 43, light is emitted by the illumination unit 44 and an image of the wafer W reflected in the half mirror 43 is captured by the camera 45, thereby obtaining the image data described above.

As shown in FIG. 1, a second transfer mechanism, transfer mechanism 33, is provided in the transfer region 31, positioned behind the pre-processing inspection module 41 in a plan view. The transfer mechanism 33 includes a base that can be raised and lowered and rotated about a vertical axis, and a wafer W holder that can move forward and backward on the base, and is capable of transferring wafers W to and from the module stack T1 (described below) and the shuttle TRS12 of the first upper processing block D22.

Next, the module stack T1 will be described. This module stack T1 is composed of transfer modules TRS, on which wafers W are temporarily placed, and temperature adjustment modules SCPL, stacked vertically, and is located in the front-to-back center of the transfer area 31. Therefore, in a plan view, the module stack T1 is located behind the transfer mechanism 32, sandwiched between the transfer mechanisms 32 and 33, and overlaps the right side of the pre-processing inspection module 41. Therefore, in a plan view, the pre-processing inspection module 41 is configured to extend leftward from a position overlapping the stack T1. Furthermore, with regard to the stages for the carrier C described above, the two front vertical rows of stages, including the moving stage 15, are located forward of the module stack T1. Of the two rear vertical rows of stages, one row is located to the left of the module stack T1, and the other row is located rearward of the module stack T1.

The transfer module TRS has, for example, multiple pins arranged horizontally, and wafers W are transferred to and from these pins by the lifting and lowering motion of the transfer mechanism. The SCPL is configured, for example, by connecting a refrigerant flow path to a plate on which the wafer W is placed, thereby cooling the temporarily placed wafer W, and the transfer mechanism is configured to transfer the wafer W to and from the plate. SCPLs are also provided in blocks other than carrier block D1, and the SCPLs in blocks other than D1 have the same configuration as, for example, the SCPL in carrier block D1. TRSs are also provided in blocks other than D1. These TRSs have the same configuration as the TRS in carrier block D1, except for the TRS for the shuttle that transfers wafers W to and from the shuttle, which will be described later.

Hereinafter, in order to distinguish the SCPL and TRS at each location, which are temporary placement modules, numbers will be added after the SCPL and TRS. For example, multiple TRS and SCPLs may be stacked at each location. In other words, multiple TRSs and SCPLs with the same number are provided, but for convenience of illustration, only one is shown. Note that in this specification, a stack of modules refers to modules that are stacked in a planar view, and the modules may be separated from each other or may be in contact with each other.

Some of the modules that make up the module stack T1 are located below the pre-processing inspection module 41, and others are located above the pre-processing inspection module 41. For example, from bottom to top, the modules are arranged in the order TRS1, TRS2, SCPL1, TRS3, and SCPL2, with the pre-processing inspection module 41 located between SCPL1 and TRS3 (see Figure 3). For example, TRS1, TRS2, and SCPL1 are each located at the height of the first lower processing block D21, and TRS3 and SCPL2 are each located at the height of the first upper processing block D22. The transport mechanism 33 can access each of the modules that make up the module stack T1, and the transport mechanism 32 can access TRS1 and TRS2. Furthermore, with regard to the transfer of wafers W to and from carriers C and between modules in module stack T1, transfer mechanism 32 is dedicated to transfer to and from carriers C, and transfer mechanism 33 is dedicated to transfer between modules in module stack T1.

TRS1 and TRS2 are used to transfer wafers W between transfer mechanisms 32 and 33, and both constitute first placement units used to transfer wafers W to and from carriers C. SCPL1 is used to transfer wafers W between the first lower processing block D21 and carrier block D1. Therefore, the second placement unit SCPL1 is also accessible by the transfer mechanism 6A of the first lower processing block D21, described below. TRS3 is used to transfer wafers W between the first upper processing block D22 and carrier block D1. Therefore, the transfer mechanism 6B of the first upper processing block D22, described below, is also accessible to TRS3. SCPL2 is a module used to adjust the temperature of wafers W before they undergo development processing in the first upper processing block D22, and is accessed by the transfer mechanism 6B.

A hydrophobization processing module 30, a fourth processing module that supplies processing gas to wafers W to perform hydrophobization processing before a coating film is formed, is provided on the rear side (either the front or rear) of the transfer mechanism 33. For example, multiple hydrophobization processing modules 30 are stacked at the same height as the second upper processing block D22, and wafers W are transferred to and from the hydrophobization processing module 30 by the transfer mechanism 33. The hydrophobization processing module 30 includes a heating plate on which the wafer W is placed, similar to the heating plate 55 provided in the heating module 54 described below, and a cover that can be raised and lowered to cover the heating plate. Processing gas is supplied into the sealed space above the heating plate formed by the cover, thereby performing hydrophobization processing on the wafers W.

Next, the first processing block D2 will be described with reference to Figure 5, a vertical side view. The front side of the first processing block D2 is vertically partitioned to form eight levels, which are numbered E1 to E8 from bottom to top. The lower levels E1 to E4 are included in the first lower processing block D21, and the upper levels E5 to E8 are included in the first upper processing block D22. Each level forms an area where a liquid processing module can be installed.

First, we will explain the first upper processing block D22. Each of the floors E5 to E8 is provided with a developing module 51 as a liquid processing module. The developing module 51 is equipped with two cups 52, each of which is arranged side by side and holds a wafer W, and a nozzle (not shown). The developing liquid supplied from the bottle is supplied to the surface of the wafer W by a pump (not shown) to perform processing.

A wafer W transfer area 53 is provided at the rear of floors E5 to E8, and is formed in a straight line in a plan view, extending from the left end to the right end of the upper processing block D22. Therefore, the extension direction of the transfer area 53 is perpendicular to the extension direction of the transfer area 31 of the carrier block D1. The transfer area 53 is formed from the height of floor E5 to the height of floor E8. In other words, the transfer area 53 is not divided into floors E5 to E8.

Furthermore, behind the transport area 53, processing modules are stacked vertically in, for example, seven levels, with two stacks of processing modules arranged side by side. In other words, these stacks of processing modules and the cups 52 are each arranged along the extension direction of the transport area 53.

The stack of processing modules arranged side by side as described above is referred to as the rear processing section 50. The processing modules that make up this rear processing section 50 include multiple heating modules 54 and multiple post-processing inspection modules 57. The heating module 54 is a module that performs post-exposure bake (PEB) and includes a hot plate 55 on which the wafer W is placed and heated, and a cooling plate 56 that adjusts the temperature of the wafer W. The cooling plate 56 is movable between a front position where the wafer W is transferred by the lifting and lowering operation of the transfer mechanism 6B (described below), and a rear position where it overlaps with the hot plate 55. The lifting and lowering operation of pins (not shown) on the hot plate 55 cooperates with the movement of the cooling plate 56 to transfer the wafer W between the hot plate 55 and the cooling plate 56.

The post-processing inspection module 57 has the same configuration as the pre-processing inspection module 41, and is positioned so that the movement direction of the wafer W during imaging is the forward/backward direction. This post-processing inspection module 57 acquires image data of the surface of the wafer W that has been processed by the coating and developing apparatus 1, or more specifically, the surface of the wafer W on which a resist pattern has been formed by development, and transmits this image data to the control unit 10.

The transport area 53, which is the main transport path, is provided with the transport mechanism 6B, which is the main transport mechanism described above. The transport mechanism 6B has a base 61 that can move left and right, move up and down, and rotate around a vertical axis, and a wafer W holder 62 that can move forward and backward on the base 61. Each transport mechanism other than the shuttle within the coating and developing apparatus 1, including this transport mechanism 6B, has two holders, which can move forward and backward independently of each other on the base.

A moving mechanism 63 for moving the base 61 of the transfer mechanism 6B left and right is provided below the rear processing unit 50, and a flat space 71A is formed between the moving mechanism 63 and the rear processing unit 50 (see FIG. 5). Space 71A is formed from the left end to the right end of the first upper processing block D22. A shuttle and its associated TRS12 and TRS14 are installed in space 71A, which will be described in detail later. The transfer mechanism 6B can transfer wafers W to and from each processing module in the first upper processing block D22, TRS3 and SCPL2 of the carrier block D1, and the shuttle TRS14. In other words, the transfer mechanism 6B is shared by each liquid processing module provided on multiple stacked levels and each processing module constituting the rear processing unit 50.

Next, we will explain the first lower processing block D21. This first lower processing block D21 has a configuration generally similar to the first upper processing block D22 already described, and the following explanation will focus on the differences from the first upper processing block D22. No processing modules are provided on level E1, and anti-reflective coating formation modules 47 are provided as liquid processing modules on levels E2 to E4. The anti-reflective coating formation module 47, which is the first processing module and also a coating film formation module, has a configuration similar to the developing module 51, which is the second processing module, except that it supplies a coating liquid for forming an anti-reflective coating from a nozzle instead of a developer.

The rear processing section 50 is composed of heating modules 54. However, unlike the heating modules 54 in the first upper processing block D22, the heating modules 54 in this first lower processing block D21 and the second lower processing block D32 described below are designed to remove solvent from the coating film. The main transport mechanism in the transfer region 53 is shown as transfer mechanism 6A and has the same configuration as the previously described transfer mechanism 6B. This transfer mechanism 6A delivers wafers W to and from each processing module in the first lower processing block D21, SCPL1 of the module stack T1 described above, and module stack T2 described below. The first lower processing block D21 does not have a shuttle or a shuttle TRS.

The first processing block D2 is provided with a module stack T2 (see Figures 1 and 3). This module stack T2 is located to the right of the transfer region 53 of the first lower processing block D21 and to the right of the transfer region of the second upper processing block D22, and is composed of SCPLs. The SCPL in the first lower processing block D21 is indicated as SCPL3, and the SCPL in the first upper processing block D22 is indicated as SCPL4. The module stack T2 is located so that its right end slightly extends into the second processing block D3. SCPL3 is used to adjust the temperature of wafers W before processing in the resist film formation module of the second lower processing block D22 (described below), and SCPL4 is used to adjust the temperature of wafers W before processing in the development module 51 of the second upper processing block D22 (described below).

Regarding the layout of the modules in the first upper processing block D22 and the first lower processing block D21, the rear processing unit 50 and the cups 52 of the liquid processing modules are located to the left of the module stack T2 to enable transfer by the transport mechanisms 6A and 6B. The layout of the liquid processing modules and rear processing unit 50 is common to the first and second lower processing blocks D21 and D31 and the first and second upper processing blocks D22 and D32. Therefore, in the second lower processing block D31 and second upper processing block D32 described below, the rear processing unit 50 and the cups 52 of the liquid processing modules are also located away from the right end of the block.

Next, the second processing block D3 will be described. The second processing block D3 has a configuration similar to the first processing block D2, except that it does not have the module stack T2. The following description will focus on the differences from the first processing block D2. First, the second upper processing block D32 will be described. The main transport mechanism in this second upper processing block D32 is designated 6D. A space 71B similar to space 71A in the first upper processing block D22 is formed between the transfer mechanism 63 that moves this transport mechanism 6D and the rear processing unit 50. Space 71B is located at the same height as space 71A and is connected to space 71A. A shuttle and shuttle TRS11 and TRS13 are installed in space 71B, which will be described later. The transfer mechanism 6D transfers wafers W to and from each processing module in the upper processing block D22, the module stack T3 in the interface block D4 (described below), and the shuttle TRS11.

Next, the second lower processing block D31 will be described. Resist film formation modules 49 are provided on floors E2 to E4. These resist film formation modules 49 have the same configuration as the developing module 51, except that the processing liquid supplied to the wafers W is resist instead of developer. The rear processing unit 50 also has the same configuration as the rear processing unit 50 of the first lower processing block D21. The main transport mechanism in the second lower processing block D31 is the transport mechanism 6C. This transport mechanism 6C delivers wafers W to and from each processing module in the lower processing block D21 and the module stack T3 in the interface block D4.

The following describes interface block D4. Interface block D4 has a module stack T3 located in the center between the front and rear. This module stack T3 is composed of stacked modules TRS5 to TRS7 and a temperature adjustment module ICPL. In addition to these modules, other modules such as a buffer module for temporarily waiting wafers W are also provided, but their description will be omitted. ICPL is a module to which wafers W are transferred immediately before exposure. It is located at the bottom of module stack T3 and, like SCPL, adjusts the temperature of the wafer W placed thereon. TRS5 and TRS6 are located at the height of the lower processing block G1, and TRS7 is located at the height of the upper processing block G2. Transfer mechanisms 36, 37, and 38 are located at the front, rear, and right of module stack T3, respectively.

Transfer mechanisms 36 and 37 are configured similarly to transfer mechanism 33 and are capable of transferring wafers W between each module constituting module stack T3. Transfer mechanism 36 is also capable of transferring wafers W to backside cleaning module 65, which will be described later, and transfer mechanism 37 is also capable of transferring wafers W to shuttle TRS13 and post-exposure cleaning module 66, which will be described later. Transfer mechanism 38 is configured similarly to transfer mechanism 32 and transfers wafers W between ICPL, TRS6, and exposure machine 20.

Furthermore, multiple back surface cleaning modules 65 are stacked and provided in front of the transfer mechanism 36. The back surface cleaning module 65 has a configuration similar to the developing module 51, except that instead of being provided with a nozzle that supplies developing solution to the front surface of the wafer W, it is provided with a nozzle that supplies cleaning solution to the back surface of the wafer W, and it has only one cup 52. Multiple post-exposure cleaning modules 66 are stacked and provided behind the transfer mechanism 37. The post-exposure cleaning module 66 has a configuration similar to the developing module 51, except that instead of being provided with developing solution to the front surface of the wafer W, it supplies cleaning solution to the front surface of the wafer W, and it has only one cup 52.

Next, the shuttles provided in the first upper processing block D22 and the second upper processing block D32 will be described as 7A and 7B, respectively. Shuttle 7A comprises a moving mechanism 72A, a moving body 73A, and a support 74A. Moving mechanism 72A is configured as an elongated member extending left and right, and is arranged to fit within space 71A of the first upper processing block D22 described above. Moving body 73A is connected to the front side of moving mechanism 72A and extends left and right. Support 74A is connected to the front side of moving body 73A and is formed in the shape of a rectangular parallelepiped that is elongated left and right. Wafers W are supported on this support 74A and transported horizontally and linearly in the left-right direction.

The moving mechanism 72A allows the moving body 73A to move left and right relative to the moving mechanism 72A. The support 74A moves left and right relative to the moving body 73A in response to the movement of the moving body 73A relative to the moving mechanism 72A (see Figures 6 to 8). The moving body 73A moves between a right position, where its right end is located to the right of the right end of the moving mechanism 72A (toward the interface block D4), and a left position, where its left end is located to the left of the left end of the moving mechanism 72A (toward the carrier block D1). When the moving body 73A is located in the right position, the right end of the support 74A is located to the right of the right end of the moving body 73A (the state shown in Figure 6). The position of the support 74A in this state is referred to as the right transport position. When the moving body 73A is located in the left position, the left end of the support 74A is located to the left of the left end of the moving body 73A (the state shown in Figure 8). The position of the support 74A in this state is referred to as the left transport position.

Shuttle 7A transports wafers W from TRS11 in the second upper processing block D32 to TRS12 (fourth mounting section) in the first upper processing block D22. TRS11 includes a support plate 75, which forms the mounting section body and is recessed to form a recess with an open left side in a plan view, three pins 76 protruding upward from the support plate 75, and a lifting mechanism (not shown) for raising and lowering the support plate 75. It is located, for example, at the left end of the second upper processing block D32. The lifting mechanism, which may be an actuator such as a cylinder or motor, is connected to the back (lower) side of each support plate 75 and is positioned so as not to interfere with the movement trajectories of the movable body 73A and support 74A. As the support plate 75 is raised and lowered, the pins 76 move between raised and lowered positions to support the underside of the wafer W. When in the right transfer position, the right end of the support 74A is fitted in the recess formed by the support plate 75 in a plan view, and the wafer W can be transferred between the support 74A and the TRS11 by raising and lowering the pins 76.

TRS12 has the same configuration as TRS11, except that the support plate 75 is formed with a recess that is open on the right side in plan view. In the left transfer position, the left end of support 74A is fitted into the recess formed by support plate 75 in plan view, allowing wafers W to be transferred between support 74A and TRS12. TRS12 is located at the left end of the first upper processing block D22 so that wafers W can be transferred between support 74A and the transfer mechanism 33 of carrier block D1. As mentioned above, the transfer of a substrate (wafer W) supported by support 74 is performed by multiple components, such as movable body 73A and support 74A, arranged in the front-to-rear direction, changing their relative left-to-right positions. By transferring the substrate in this manner, TRS11 and TRS12, which are positioned to the left and right of support 74A, are less likely to interfere with movable body 73A, making it possible to arrange pins 76 in three or more positions that can easily support the substrate.

Shuttle 7B, the second bypass transport mechanism, is located at a different height than shuttle 7A, for example, lower than shuttle 7A. Shuttle 7B is configured similarly to shuttle 7A, and the reference numerals for the components of shuttle 7B, namely the moving mechanism, moving body, and support, are denoted by a B instead of an A after the numeral to distinguish them from the components of shuttle 7A. Specifically, for example, the moving mechanism of shuttle 7B is denoted as 72B. This moving mechanism 72B is arranged to fit within space 71B of the second upper processing block D32.

Shuttle 7B transports wafers W from TRS13, which is provided in the second upper processing block D32, to TRS14, which is provided in the first upper processing block D22. TRS13 has the same configuration as TRS11 and is provided at the right end of the second upper processing block D32 so that wafers W can be transferred between it and interface block D4. TRS14 has the same configuration as TRS12 and is provided to the left of module stack T2 and to the right of TRS12 so that wafers W can be transferred between it and transfer mechanism 6B.

As described above, shuttle 7B is provided below shuttle 7A, so the height at which the second bypass substrate placement portions TRS13 and TRS14 are located is lower than the height at which the first bypass substrate placement portions TRS11 and TRS12 are located. In other words, as shown in FIG. 2, the set of shuttle 7A, TRS11, and TRS12 and the set of shuttle 7B, TRS13, and TRS14 are positioned offset from each other in the longitudinal (vertical) direction.

Let us assume that the wafer W transport path (first bypass transport path) by shuttle 7A and the wafer W transport path (second bypass transport path) by shuttle 7B are 77A and 77B, respectively. The forward and backward positions of these transport paths 77A and 77B are the same. Corresponding to the positions of TRS11 to TRS14 described above, transport path 77A protrudes into the second upper processing block D22, and transport path 77B protrudes into the first upper processing block D22. This protrusion allows the right side of transport path 77A and the left side of transport path 77B to overlap in a plan view. Note that transport paths 77A and 77B may be positioned, for example, away from the heating plate 55 of heating module 54 and overlapping with the standby position of cooling plate 56 in a plan view. Positioning the transport paths relatively far from the heating plate 55 in this way more reliably minimizes the thermal effects on the transported wafer W.

The transfer of wafers W by shuttle 7A will be explained step by step with reference to Figures 6 to 8. The transfer mechanism 6D in second upper processing block D32 transfers wafers W processed in each processing module in second upper processing block D32 onto pins 76 in the raised position of TRS11. The pins 76 move to the lowered position, and the wafer W is transferred to support 74A in the right transfer position described above (Figure 6). While movable body 73A and support 74A each move to the left, pins 76 of TRS11 return to the raised position (Figure 7).

When support 74A moves to the left transfer position described above, pins 76 in the lowered position of TRS12 move to the raised position to support the wafer W (Figure 8). When support 74A moves toward the right transfer position, pins 76 return to the lowered position. The transfer mechanism 33 of carrier block D1 then receives the wafer W. In this way, shuttle 7A transfers the wafer W toward carrier block D1, which is the downstream block. Shuttles 7B, TRS13, and TRS14 operate in the same way as shuttles 7A, TRS11, and TRS12, respectively, and transfer the wafer W from TRS13 to TRS14. In other words, shuttle 7B transfers the wafer W toward the first upper processing block D22, which is the downstream block.

The coating and developing apparatus 1 also includes a control unit 10 (see Figure 1). This control unit 10 is configured as a computer and includes a program, memory, and a CPU. The program incorporates steps that enable a series of operations in the coating and developing apparatus 1 to be performed. The program causes the control unit 10 to output control signals to each part of the coating and developing apparatus 1, controlling the operation of each part. Specifically, it controls the operation of the transfer mechanisms 6A-6D, shuttles 7A and 7B, and each processing module. This allows for the transfer of wafers W, processing of wafers W, and abnormality determination of wafers W, as described below. The above program is stored on a storage medium such as a compact disc, hard disk, or DVD, and installed in the control unit 10.

Next, the processing and transport paths of wafers W in the coating and developing apparatus 1 will be described with reference to Figures 9 and 10, which show the aforementioned outbound and return paths, respectively. In Figures 9 and 10, the transport mechanisms used for transporting wafers W between modules are shown on or near some of the arrows.

First, the transfer mechanism 32 transfers the wafer W from the carrier C placed on the moving stage 15 of the support table 12. The transfer mechanism 32 then transfers the wafer W to the pre-processing inspection module 41, where image data is acquired and the presence or absence of abnormalities is determined.

The wafer W is then transferred to TRS1 by transfer mechanism 32. The wafer W is then transferred by transfer mechanism 33 to hydrophobization processing module 30 and then to SCPL1, and then loaded into the first lower processing block D21 by transfer mechanism 6A. The wafer W is then transferred to anti-reflection film forming module 47 and then to heating module 54, where an anti-reflection film is formed. The wafer W is then transferred to SCPL4 of module stack T2, and then transferred by transfer mechanism 6C to resist film forming module 49 and then to heating module 54, where a resist film is formed. The wafer W is then transferred to TRS5 of module stack T3.

The wafer W is then transported by the front transfer mechanism 36 through the back surface cleaning module 65 and ICPL, and then by the transfer mechanism 38 to the exposure machine 20, where the resist film on the front surface of the wafer W is exposed according to a predetermined pattern. After exposure, the wafer W is transported by the transfer mechanism 38 to the TRS 6, and then transported by the rear transfer mechanism 37 to the post-exposure cleaning module 66.

The wafer W's subsequent transport path splits into two paths: one for processing in the first upper processing block D22 (referred to as the first path), and the other for processing in the second upper processing block D32 (referred to as the second path). Regarding the second path, the transport mechanism 37 transports the wafer W to TRS7 of the module stack T3, and the wafer W is then taken into the second upper processing block D32 by the transport mechanism 6D. The wafer W is then transported in the order of heating module 54 → SCPL3 → developing module 51 → post-processing inspection module 57. After a resist pattern is formed, image data is acquired and the presence or absence of abnormalities is determined.

Then, as described in Figures 6 to 8, the wafer W is transferred in the order of transfer mechanism 6D → TRS11 → shuttle 7A → TRS12, and then transfer mechanism 33 of carrier block D1 receives the wafer W and transfers it to TRS2. In this way, the wafer W is transferred toward the downstream block by transfer mechanism 6D, one of transfer mechanisms 6B and 6D that are the main transfer mechanisms of the first upper processing block D22 and the second upper processing block D22, which are bypass transfer path forming blocks, and shuttle 7A. The wafer W is then stored in carrier C on moving stage 15 of support table 13 by transfer mechanism 32.

Continuing with the above-mentioned first path, the wafer W is transferred in the order of transfer mechanism 37 → TRS13 → shuttle 7B → TRS14 → transfer mechanism 6B, and the wafer W is loaded into the first upper processing block D22. The wafer W is then transferred by transfer mechanism 6B in the order of heating module 54 → SCPL2 → developing module 51 → post-processing inspection module 57, and after undergoing processing similar to that of the wafer W on the second path, is transferred to TRS3 in carrier block D1. In this way, the wafer W is transferred toward downstream blocks by transfer mechanisms 6B and 6D, which are the main transfer mechanisms of the first and second upper processing blocks D22 and D22, which are bypass transfer path forming blocks, and shuttle 7B. The wafer W is then transferred to TRS2 by transfer mechanism 33, and thereafter, like the wafer W on the second path, by transfer mechanism 32 to carrier C on moving stage 15 of support table 13.

As described above, the carrier block D1 in the coating and developing apparatus 1 is provided with a module stack T1 including TRSs and SCPLs for transferring wafers W to and from the carrier C, the lower processing block (one processing block) G1, and the upper processing block (another processing block) G2. Transfer mechanisms 32 and 33 are also provided, with the transfer mechanism 32 responsible for transferring wafers W to and from the carrier C, and the transfer mechanism 33 responsible for transferring wafers W between modules in the module stack T1. By dividing the roles of the transfer mechanism 32 and the transfer mechanism 33 in this manner, the transfer mechanism 32 can quickly load and unload wafers W into and from the carrier C. Meanwhile, processing modules are stacked in each of the processing blocks D21, D22, D31, and D32 constituting the lower processing block G1 and upper processing block G2, to which wafers W are transferred via the transfer mechanism 33, and wafers W can be processed in each processing module. Therefore, the coating and developing apparatus 1 can achieve high throughput. Furthermore, the transfer area 31, which faces the transfer port 24 through which wafers W are transferred to and from the carrier C, extends from front to back, and by providing transfer mechanisms 32 and 33 in this transfer area 31 at the front and rear of the module stack T1, respectively, the left-to-right width of the carrier block D1 can be made relatively small. Therefore, the coating and developing apparatus 1 can reduce its footprint (occupied floor area).

A pre-processing inspection module 41 is provided on the carrier block D1. The right end of this pre-processing inspection module 41 overlaps the module stack T1 and penetrates the side wall of the housing 11, with the left end protruding from the transport area 31. In other words, the pre-processing inspection module 41 is placed in the space formed in the center of the front and rear of the transport area 31 by arranging the module stack T1, as well as in the space outside the housing 11 where the carrier C is transferred. In other words, the pre-processing inspection module 41 is installed in the carrier block D1, while preventing the footprint of the carrier block D1 from increasing.

Furthermore, a hydrophobic treatment module 30 is arranged as a treatment module behind the transfer mechanism 33, and is accessible by the transfer mechanism 33. This arrangement of the hydrophobic treatment module 30 also prevents the left and right width of the coating and developing apparatus 1 from increasing. The transfer mechanism 33 delivers wafers W to the hydrophobic treatment module 30, and the transfer mechanism 32 delivers wafers W to the pre-treatment inspection module 41. This prevents uneven load distribution between the transfer mechanisms 32 and 33, and prevents a decrease in throughput due to the installation of these treatment modules. However, the transfer mechanism 33 may also be configured to deliver wafers W to the pre-treatment inspection module 41.

Furthermore, when providing multiple movable stages 15 on which carriers C are placed for loading and unloading wafers W, they are arranged in multiple tiers on the front side of the module stack T1. By arranging the movable stages 15 so that they are concentrated on the front side of the module stack T1 in this way, it is possible to install the necessary number of movable stages 15 to ensure sufficient throughput, while also allowing the central portion of the transfer area 31, from front to back, to be used as an installation area for the module stack T1 and pre-processing inspection module 41. Furthermore, by arranging the module stack T1 in this manner, the transfer mechanism 33 can be placed behind it. Therefore, as already described, providing each movable stage 15 on the front side of the module stack T1 and at different heights from each other contributes to increasing throughput while reducing the footprint of the device.

By providing a temporary storage stage 16, which serves as a temporary storage section for carriers, unnecessary carriers C can be retracted from the movable stage 15, allowing wafers W to be loaded and unloaded efficiently into and from the carriers C. In the carrier block D1, the temporary storage stage 16 is located at the same position as the module stack T1 in the front-to-rear direction, and at a position rearward of the module stack T1. In other words, by providing the movable stage 15 in the layout described above, the temporary storage stage 16 is located in empty space that is not accessed by the transport mechanism 32. In other words, the temporary storage stage 16 is arranged in a layout that prevents the carrier block D1 from becoming larger.

Furthermore, the coating and developing apparatus 1 is provided with shuttles 7A and 7B, which transport wafers W toward carrier block D1. As a result, a wafer W being processed in one of the first upper processing block D22 and the second upper processing block D32 is transported toward carrier block D1 so as to bypass the processing modules in the other block. This reduces the load on the transport mechanism 6B of the first upper processing block D22 and the transport mechanism 6D of the second upper processing block D32 (more specifically, the number of transport processes required within the block). As a result, the throughput of the coating and developing apparatus 1 can be further improved.

By the way, air flow forming units (not shown) are provided above the housing 11 of the carrier block D1, above the housings of the first and second processing blocks D2 and D3, and above the housing of the interface block D4. Each air flow forming unit takes in air from outside the coating and developing apparatus 1 and supplies it to the wafer W transport path in the block in which the air flow forming unit is provided, thereby forming an air flow. In Figure 11, the air flow forming units of the carrier block D1 and the second processing block D22 are shown as 81 and 82, respectively. For ease of illustration, these air flow forming units 81 and 82 are shown in positions distant from the carrier block D1 and the first processing block D2, respectively.

The airflow forming unit 82 supplies air via a duct (not shown) to filters installed in the ceiling of each transport area 53 of the first lower processing block D21 and the first upper processing block D22 that make up the first processing block D2. The air supplied from the filters flows downward through the transport area 53 and is exhausted from exhaust ports (not shown) installed on the lower side of the first lower processing block D21 and the first upper processing block D22 (not shown).

For example, in carrier block D1, as shown in FIG. 11, a vertically elongated filter 83 is provided at the front end of the transport area 31. Air supplied from the airflow forming unit 81 to the filter 83 is then supplied from the filter 83 toward the rear of the transport area 31. An exhaust hole 84 is opened, for example, at the bottom of the block behind the module stack T1, and the air supplied from the filter 83 is exhausted from the exhaust hole 84.

By adjusting the balance between the air supply and exhaust rates in each block, the first lower processing block D21 and the first upper processing block D22 are placed under higher pressure than the transfer region 31. As a result, some of the air supplied to the transfer region 53 as described above flows into the transfer region 31 and is exhausted through the exhaust hole 84. Figure 11 shows the airflow formed in the transfer regions 31 and 53 using arrows. This airflow more reliably prevents the processing gas used in the hydrophobization processing module 30 from flowing into the transfer region 31. If the processing gas were to flow into the development module 51 via the transfer region 31 and react with the developer, this could result in development defects. However, the formation of this airflow prevents such defects from occurring. In other words, the formation of this airflow prevents a decrease in the yield of products manufactured from wafers W. The filter 83 and airflow generating units 81 and 82 form an airflow generating mechanism.

Incidentally, a post-processing inspection module 57 may be provided in place of the pre-processing inspection module 41 described above. In that case, the outbound route described in FIG. 9 may be a route that does not involve transport to the inspection module. Specifically, the wafer W may be transported in the order carrier C → transport mechanism 32 → TRS1 → transport mechanism 33 → SCPL1 and loaded into the first lower processing block D21. The return route described in FIG. 10 may then pass through the post-processing inspection module 57 provided in carrier block D1. Specifically, after processing, the wafer W may be transported to TRS2 of carrier block D1 by transport mechanism 32, and then returned to carrier C.

When the post-processing inspection module 57 is arranged in the carrier block D1 in this manner, the pre-processing inspection module 41 may be provided as a processing module constituting, for example, the rear processing section 50 of the first lower processing block D21. Note that the carrier block D1 may not be provided with either the pre-processing inspection module 41 or the post-processing inspection module 57. In this case, wafers W can be transferred between the transfer mechanisms 32 and 33 using each module of the module stack T1, and transported as appropriate.

In the above transfer example, the mobile stage 15 (loader) on which the carrier C is placed to unload the wafer W is different from the mobile stage 15 (unloader) on which the carrier C is placed to load the wafer W. However, one mobile stage 15 may serve as both a loader and an unloader. The above transfer mechanism 32 is configured to be shared by four mobile stages 15, which has the advantage of making it easy to switch the use of the mobile stages 15 in this way.

In addition, in the coating and developing apparatus 1, the upper processing block G2 may serve as the outbound route for wafers W, and the lower processing block G1 may serve as the return route for wafers W. Specifically, for example, without forming an anti-reflective coating within the apparatus, a resist film forming module 49 may be installed as a liquid processing module in each of the first upper processing block D22 and the second upper processing block D32. A developing module 51 may be installed as a liquid processing module in each of the first lower processing block D21 and the second lower processing block D31. Wafers W may be transported between blocks along a transport path reverse to the previously described transport path, thereby forming a resist film, exposing, and developing the wafers, in that order, to form a resist pattern. Therefore, the shuttle is not limited to forming a return route, and the carrier block D1 is not limited to being configured to transfer wafers W to the shuttle TRS on the return route. Shuttles may also be installed in the first lower processing block D21 and the second lower processing block D31. For example, the liquid processing modules in the first lower processing block D21 and the second lower processing block D31 can both be resist film formation modules 49, and the apparatus can be configured so that a wafer W is processed in the resist film formation module 49 of either block using a shuttle.

Furthermore, the liquid processing performed by the apparatus is not limited to the above examples, and may include forming an insulating film by applying a chemical liquid, forming a protective film to protect the surface of a resist film by applying a chemical liquid, and applying an adhesive to bond wafers W to each other. A cleaning process may also be performed in which a cleaning liquid is supplied to the front or back surface of the wafer W. Therefore, the substrate processing apparatus of this technology is not limited to a coating and developing apparatus.

Furthermore, the lower processing block G1 and the upper processing block G2 do not have to be connected to each other by the interface block D4. The following description will be given with reference to the schematic diagram of the substrate processing apparatus 8 in Figure 12. Assume that the module stack T1 includes TRS21 to TRS23. TRS21 is used for transfer to and from carrier C, and wafers W are transported between carrier C and TRS21 by a transport mechanism 32. TRS22 and TRS23 are used for transfer to and from the lower processing block G1 and upper processing block G2, and wafers W are transported between TRS21 and TRS22 and between TRS21 and TRS23 by a transport mechanism 33, respectively. Wafers W are loaded from carrier C via TRS21 to TRS22, and from TRS23 to the lower processing block G1 and upper processing block G2, respectively, and are returned to carrier C via TRS22, TRS23, and TRS21 after processing. In other words, the apparatus may be configured so that wafers W are processed in only one of the lower processing block G1 and the upper processing block G2 and then returned to the carrier C.

Furthermore, each of the lower processing block G1 and the upper processing block G2 is not limited to being composed of two processing blocks lined up horizontally, but may be composed of a single processing block. Furthermore, each of the lower processing block G1 and the upper processing block G2 may be composed of three or more processing blocks lined up horizontally, and wafers W may be transported between the processing blocks lined up horizontally.

In each processing block, the liquid processing module is located at the front and the processing module that forms the rear processing unit 50 is located at the rear, but this layout may be reversed. Also, in carrier block D1, the layout of the transport mechanisms 32, 33 and the stages for carrier C may be reversed. Also, the arrangement of carrier block D1 and the other blocks may be reversed left to right.

In addition, in the carrier block D1, other modules such as a post-processing inspection module 57 may be provided instead of the hydrophobic processing module 30, and transported by the transfer mechanism 33. However, the hydrophobic processing module 30 does not require the placement portion (hot plate) on which the wafer W is placed to be moved laterally during processing. In other words, when providing a processing module behind the transfer mechanism 33, providing a processing module that performs processing without moving the placement portion for the wafer W laterally is preferable in order to prevent the carrier block D1 and, ultimately, the substrate processing apparatus from becoming larger. Note that the order of the TRS and SCPL that make up the module stack T1 may be adjusted in height or stacked in a different order as long as the wafer W can be transported within the apparatus.

Furthermore, the hydrophobic treatment module 30 may be arranged so as to overlap the TRS and SCPL that make up the module stack T1. However, by arranging multiple TRS and SCPL in the module stack T1 and loading wafers W on them, it is possible to quickly transfer wafers W between the carrier block D1 and the first processing block D2, and between the carrier C and the carrier block D1. Therefore, as already mentioned, it is preferable to arrange the hydrophobic treatment module 30 at the rear of the transfer region 31. Furthermore, in the coating and developing apparatus 1, after the transfer mechanism 32 transfers the wafer W to the pre-processing inspection module 41, the transfer mechanism 33 may receive the wafer W at the inspection module 41, transfer it to SCPL1, and then the wafer W may be taken into the lower processing block D21. In other words, the transfer of wafers W between the transfer mechanisms 32 and 33 does not necessarily have to be performed using the temporary storage module.

The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The above-described embodiments may be omitted, substituted, modified, and combined in various ways without departing from the scope and spirit of the appended claims.

C Carrier D2 First processing block D21 First lower processing block D22 First upper processing block 15 Moving stage TRS Transfer module T1 Module stack W Wafer 31 Transfer areas 32, 33 Transfer mechanisms 6A, 6B, 6C, 6D Transfer mechanism

Claims (16)

a carrier block including a carrier placement portion on which a carrier for storing a substrate is placed;
a processing block including a plurality of processing modules stacked on top of each other, each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate, the processing block being provided on either the left or right side of the carrier placement unit in a plan view;
a plurality of processing modules each configured to process the substrate and stacked on top of one another; and a main transport mechanism shared by the plurality of processing modules and configured to transport the substrate, the other processing block being vertically overlapped with the first processing block;
a transport region for the substrate provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view;
a first transport mechanism for transferring the substrate to and from the carrier;
a stack of platform units, each of which receives and delivers the substrate by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, and which are vertically stacked one on top of the other, and which are provided in the transport region in a plan view;
a second transport mechanism provided in the transport region in a plan view for transporting the substrate between the first and second receivers and between the first and third receivers;
Equipped with
In a plan view, a direction in which the stack of the carriers on the placement unit is located relative to a position where the first transport mechanism is provided in the carrier block differs by 90° from a direction in which the carrier placement unit is located relative to a position where the first transport mechanism is provided;
The substrate processing apparatus , wherein only the first transport mechanism of the first transport mechanism and the second transport mechanism transfers the substrate to and from the carrier . 2. A substrate processing apparatus as described in claim 1, wherein, when viewed from the front, the area in which the carrier mounting portion is provided and the position in which the second transport mechanism is provided are aligned on the left and right, separated only by the side wall of the side wall that faces the outside of the carrier block. If the processing module of the one processing block and the processing module of the other processing block are respectively referred to as a first processing module and a second processing module,
3. The substrate processing apparatus according to claim 1 , further comprising a third processing module, to which the substrate is transferred by the first transport mechanism or the second transport mechanism, provided at a position overlapping the stack in a plan view. 4. The substrate processing apparatus according to claim 3 , wherein the third processing module is an inspection module for inspecting the substrate. The substrate processing apparatus according to claim 4 , wherein the inspection module extends to the other of the left and right sides from a position overlapping the stack in a plan view, and is provided so as to protrude outside a housing that forms the transfer area. 6. The substrate processing apparatus according to claim 4 , wherein the substrate is transported to the inspection module before being transported to the first processing block and the second processing block. a fourth processing module to which the substrate is transferred by the second transfer mechanism is provided on one of the front and rear sides of the second transfer mechanism;
7. The substrate processing apparatus according to claim 3 , wherein the substrate is transferred to the third processing module by the first transfer mechanism. a carrier block including a carrier placement portion on which a carrier for storing a substrate is placed;
a processing block including a plurality of processing modules stacked on top of each other, each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate, the processing block being provided on either the left or right side of the carrier placement unit in a plan view;
a plurality of processing modules each configured to process the substrate and stacked on top of one another; and a main transport mechanism shared by the plurality of processing modules and configured to transport the substrate, the other processing block being vertically overlapped with the first processing block;
a transport region for the substrate provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view;
a first transport mechanism for transferring the substrate to and from the carrier;
a stack of platform units, each of which receives and delivers the substrate by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, and which are vertically stacked one on top of the other, and which are provided in the transport region in a plan view;
a second transport mechanism provided in the transport region in a plan view for transporting the substrate between the first and second receivers and between the first and third receivers;
Equipped with
a fourth processing module to which the substrate is transferred by the second transfer mechanism is provided on one of the front and rear sides of the second transfer mechanism;
If the processing module of the one processing block and the processing module of the other processing block are respectively referred to as a first processing module and a second processing module,
the plurality of first processing modules or the plurality of second processing modules includes a coating film forming module that supplies a coating liquid to the substrate to form a coating film;
the fourth processing module is a hydrophobic processing module that performs a gas processing on the substrate to hydrophobize the substrate before the supply of the coating liquid;
a substrate processing apparatus provided with an airflow forming mechanism for forming an airflow from the other of the front and rear sides in the transfer region toward the fourth processing module and an airflow from the first processing block and the other processing block toward the transfer region ; The substrate processing apparatus according to claim 7 , wherein a plurality of the carrier placement sections are provided at different heights on the other side of the stack. On the other side of the conveying area,
a temporary carrier placement section for temporarily placing the carrier, the temporary placement section being provided at the same position as the stack body in the front and rear or on one side of the stack body in the front and rear;
The substrate processing apparatus according to claim 9 , further comprising: a carrier transfer mechanism that transfers the carrier between the temporary placement unit and the carrier placement unit. A substrate processing apparatus according to any one of claims 1 to 10, wherein the first transport mechanism does not transfer the substrate to or from the second platform and the third platform. A substrate processing apparatus according to any one of claims 1 to 11, wherein the second transport mechanism does not transfer the substrate to or from the carrier. an inspection module for inspecting the substrate is provided in the carrier block;
13. The substrate processing apparatus according to claim 1, wherein only the first transport mechanism of the first and second transport mechanisms transfers the substrate to and from the inspection module. a step of placing a carrier for storing substrates on a carrier placement portion provided in a carrier block;
a process of transporting the substrate in one processing block provided on either the left or right side of the carrier mounting part in a plan view, the processing block including a plurality of processing modules stacked on top of each other and each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate;
a step of transporting the substrate in another processing block that is vertically overlapped with the one processing block, the processing block including a plurality of processing modules that are stacked on top of each other and that process the substrate, and a main transport mechanism that is shared by the plurality of processing modules and transports the substrate;
transporting the substrate in a substrate transport region provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view;
transferring the substrate to the carrier by a first transport mechanism;
transferring the substrate to a first platform, a second platform, and a third platform which are stacked one on top of the other in the vertical direction and which, in a plan view, constitute a stack of platform parts provided in the transport region, by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, respectively;
transporting the substrate between the first and second receivers and between the first and third receivers by a second transport mechanism provided in the transport region in a plan view;
Equipped with
In a plan view, a direction in which the stack of the carriers on the placement unit is located relative to a position where the first transport mechanism is provided in the carrier block differs by 90° from a direction in which the carrier placement unit is located relative to a position where the first transport mechanism is provided;
A substrate processing method , wherein only the first transport mechanism of the first and second transport mechanisms transfers the substrate to and from the carrier . a step of placing a carrier for storing substrates on a carrier placement portion provided in a carrier block;
a process of transporting the substrate in one processing block provided on either the left or right side of the carrier mounting part in a plan view, the processing block including a plurality of processing modules stacked on top of each other and each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate;
a step of transporting the substrate in another processing block that is vertically overlapped with the one processing block, the processing block including a plurality of processing modules that are stacked on top of each other and that process the substrate, and a main transport mechanism that is shared by the plurality of processing modules and transports the substrate;
transporting the substrate in a substrate transport region provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view;
transferring the substrate to the carrier by a first transport mechanism;
transferring the substrate to a first platform, a second platform, and a third platform which are stacked one on top of the other in the vertical direction and which, in a plan view, constitute a stack of platform parts provided in the transport region, by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, respectively;
transporting the substrate between the first and second receivers and between the first and third receivers by a second transport mechanism provided in the transport region in a plan view;
transferring the substrate to a fourth processing module provided on one of the front and rear sides of the second transfer mechanism by the second transfer mechanism;
Equipped with
If the processing module of the one processing block and the processing module of the other processing block are respectively referred to as a first processing module and a second processing module,
the plurality of first processing modules or the plurality of second processing modules includes a coating film forming module;
a step of supplying a coating liquid to the substrate in the coating film forming module to form a coating film;
a step of hydrophobizing the substrate by gas treatment before supplying the coating liquid in a hydrophobic treatment module that is the fourth treatment module;
forming an air flow from the other of the front and rear sides of the transport region toward the fourth processing module and an air flow from the first processing block and the other processing block toward the transport region by an air flow forming mechanism;
A substrate processing method comprising: A storage medium for storing a computer program used in a substrate processing apparatus,
16. A storage medium, wherein the computer program is a set of steps for executing the substrate processing method according to claim 14 or 15 .