JP7806715B2 - Multilayer Printed Circuit Board - Google Patents

Description

This disclosure relates to multilayer printed circuit boards.

Electronic control devices installed in vehicles have strict requirements for radiated emissions, so they are constructed using multilayer printed circuit boards that can utilize inner layer wiring. These types of multilayer printed circuit boards are becoming increasingly multilayered, allowing for higher density wiring and also requiring high-speed signal transmission at speeds exceeding several GHz.

To meet this demand, it is necessary to match the impedance between the wiring patterns on each layer and the via holes that connect those wiring patterns, thereby suppressing reflection of transmitted signals. For this reason, as described in Patent Document 1, it has been proposed to match the impedance of the via holes with the wiring patterns by providing ground vias around the via holes and adjusting the clearance between the via holes and the surrounding ground patterns.

Patent No. 6535546

In the case of build-up boards, which are a type of multilayer printed circuit board, the wiring patterns on each layer are connected using laser via holes (hereinafter referred to as LVHs) and inner via holes (hereinafter referred to as IVHs). LVHs and IVHs have lower impedance than the wiring patterns on each layer.

In particular, IVHs have strong electromagnetic field coupling with the ground due to the ratio of the via diameter to the insulating layer thickness, resulting in lower impedance compared to other via holes such as LVHs. For this reason, the method described in Patent Document 1 has the problem that, given the large wiring constraints, the impedance improvement effect is weak, and it is difficult to match the impedance of the IVH with the impedance of the surface wiring pattern.

One aspect of the present disclosure aims to reduce reflections of transmission signals that occur in the signal path from the wiring pattern to the IVH via the LVH in a multilayer printed circuit board, even if the impedance of the IVH does not match the surface wiring pattern.

A multilayer printed circuit board according to one aspect of the present disclosure comprises multiple dielectric layers (D1-D7) and multiple pattern layers (P1-P8) alternately stacked, and includes an IVH (26) and an LVH (22, 24). As noted above, IVH stands for inner via hole, and LVH stands for laser via hole.

IVHs penetrate two or more dielectric layers on the inner layer side of a multilayer printed circuit board, providing electrical continuity between the wiring patterns (16-18) formed on the two pattern layers that sandwich those two or more dielectric layers. In other words, IVHs are a type of interstitial via hole also known as a buried via hole that connects inner layers.

The LVH is located on a dielectric layer on the surface side of the IVH, and provides electrical continuity between the wiring patterns (12-14, 14-16) of the pattern layers stacked on the front and back surfaces of that dielectric layer, forming a signal path between the wiring patterns on the surface side of the multilayer printed circuit board and the IVH.

In addition, in the multiple pattern layers arranged on both ends of the LVH, the clearance between the LVH and the ground pattern surrounding the LVH is smaller on the inner layer side than on the surface layer side of the LVH.

As a result, in the multilayer printed circuit board disclosed herein, the impedance of the input section on the surface side of the LVH can be maintained high while the impedance of the output section on the opposite side can be lowered. This makes it possible to suppress reflections of transmission signals between the surface wiring pattern and the LVH, and between the LVH and the IVH.

In other words, the multilayer printed circuit board disclosed herein provides a gradual change in impedance in the signal path from the surface wiring pattern to the IVH, reducing the reflection loss of the transmission signal that occurs in that signal path.

The multilayer printed circuit board disclosed herein can therefore reduce the reflection loss of transmission signals even when the impedance of the IVH is not matched to the impedance of the surface wiring pattern. Therefore, compared to the multilayer printed circuit board described in Patent Document 1, restrictions on manufacturing conditions and peripheral wiring can be relaxed, allowing for greater freedom in designing multilayer printed circuit boards.

1 is a cross-sectional view illustrating a configuration of a multilayer printed circuit board according to an embodiment. 10A and 10B are explanatory diagrams illustrating the shapes of pattern layers at both ends of an LVH connected to an IVH via a wiring pattern. 3 is a perspective view showing a clearance between the LVH and the ground pattern in the pattern layers on both ends of the LVH shown in FIG. 2. FIG. FIG. 10 is an explanatory diagram showing the size of the clearance around the LVH. FIG. 10 is an explanatory diagram illustrating an example of a connection between a surface wiring pattern, an LVH, and an IVH. 6 is an explanatory diagram showing the relationship between the impedance and the return loss of the wiring pattern, LVH, and IVH shown in FIG. 5 . 10 is an explanatory diagram showing a change in impedance when the clearances on the front and rear surfaces of the LVH of the embodiment are the same. FIG. 10A and 10B are explanatory diagrams showing changes in impedance when the clearance between the front and rear surfaces of the LVH of the embodiment is changed. 1 is an explanatory diagram illustrating a reflection loss occurring in a transmission path from a surface layer of a multilayer printed circuit board to an IVH according to an embodiment.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.
[composition]
As shown in Figure 1, the multilayer printed circuit board 1 of this embodiment is a build-up board having N dielectric layers D1 to DN and N+1 pattern layers P1 to PN+1. A build-up board is a board manufactured by alternately stacking dielectric layers D and pattern layers P on a core printed circuit board. In this embodiment, the case where N = 7 is illustrated.

As shown in FIG. 1, electronic components 10 are mounted on pattern layer P1, which is the surface layer of multilayer printed circuit board 1. In addition, wiring patterns 18 are formed on pattern layer P6, an inner layer of multilayer printed circuit board 1, which constitute a circuit that transmits and receives high-frequency signals to and from electronic components 10 and performs signal processing.

In addition, the multilayer printed circuit board 1 uses LVHs 22, 24 and IVHs 26 to connect the electronic components 10 on the surface layer with the wiring pattern 18 on the inner layer, thereby forming a transmission path for high-frequency signals.

IVH 26 is an inner layer of multilayer printed circuit board 1, and is provided so as to penetrate two or more dielectric layers, specifically dielectric layers D3, D4, and D5. IVH 26 provides electrical continuity between wiring patterns 16, 18 formed on pattern layers P3, P6 on the outer and inner sides of these multiple dielectric layers D3-D5, respectively.

LVHs 22 and 24 penetrate the dielectric layers D1 and D2 on the surface side of IVH 26, respectively, and provide electrical continuity between the signal transmission wiring patterns 12-14 and 14-16 formed on the pattern layers P1, P2, and P3 laminated on the front and back surfaces of each dielectric layer D1 and D2.

An LVH is a well-known buried via that penetrates one dielectric layer D and connects two adjacent pattern layers P across that dielectric layer D, and is drilled using a laser.

As a result, the high-frequency signal output from the surface electronic component 10 is transmitted to the inner layer wiring pattern 18 via the surface wiring pattern 12, LVH 22, wiring pattern 14, LVH 24, wiring pattern 16, and IVH 26 in that order.

To suppress the reflection of high-frequency signals that occurs along this transmission path and transmit high-frequency signals with low loss, it is necessary to match the impedance of the wiring patterns 12, 14, 16, LVHs 22, 24, and IVHs 26 that make up the transmission path with the impedance of wiring pattern 18.

However, since IVH 26 is arranged to sandwich multiple dielectric layers D, the impedance is smaller than that of LVHs 22 and 24 due to the ratio between the via diameter and the thickness of the insulating layer composed of multiple dielectric layers D.

Therefore, even if the impedance of the IVH 26 is adjusted as described in Patent Document 1, it is difficult to match the impedance with the surface wiring pattern 12.
Therefore, in this embodiment, instead of adjusting the impedance of the IVH 26, reflections occurring in the transmission path from the surface wiring pattern 12 to the IVH 26 are reduced, assuming that the impedance of the IVH 26 is low. In other words, by gradually changing the impedance of the LVHs 22, 24 arranged between the surface wiring pattern 12 and the IVH 26, reflections occurring in the transmission path are reduced.

For this reason, in this embodiment, in the pattern layers P1, P2, and P3 located on both ends of the LVHs 22 and 24, the clearance between the LVHs 22 and 24 and the surrounding ground patterns is adjusted so that it becomes smaller toward the inner layer.

For example, Figures 2 and 3 show the LVH 24 and its surrounding ground patterns 32 and 33 on pattern layers P2 and P3. As is clear from these figures, the sizes of the antipads AP1 and AP2 between the LVH 24 and its surrounding ground patterns 32 and 33 have been adjusted so that the antipad AP2 on the inner layer side is smaller than the antipad AP1 on the exterior side.

Specifically, in each pattern layer P2, P3, the diameters Φap1, Φap2 of the anti-pads AP1, AP2 from the center of the LVH 24 to the ground patterns 32, 33 are set so that Φap1 > Φap2.

Note that Figures 2 and 3 show the LVH 24 and its surrounding ground patterns 32 and 33 on pattern layers P2 and P3, but the antipads between the LVH 22 and its surrounding ground patterns on pattern layers P1 and P2 are set in the same way.

That is, the diameter of these anti-pads is set so that the anti-pads on the pattern layer P1 are larger than the anti-pads on the pattern layer P2.
Below, we will explain why the diameter of the anti-pads around LVH22 and LVH24 on the pattern layers P1-P2 and P2-P3 is made smaller on the inner layer side than on the surface layer side to adjust the size of the clearance between them and the ground pattern.

First, the impedance Zo of the interlayer line formed by the LVH is expressed by equation (1), where L is the inductance of the LVH and C is the coupling capacitance between the LVH and ground. Furthermore, as shown in Figure 4, the coupling capacitance C is expressed by equation (2), where d is the distance between the LVH and the ground pattern.

In equation (2), the distance d is calculated as "d = Φap - Φvp/2", where Φvp is the diameter of the LVH in the pattern layer and Φap is the diameter of the anti-pad AP around the LVH, as shown in Figure 4. ε represents the relative dielectric constant of the dielectric layer, and S represents the area of the LVH end pattern.

From equations (1) and (2), it can be seen that as the diameter Φap of the anti-pad AP decreases, the distance d decreases, the coupling capacitance C increases, and the impedance decreases.
On the other hand, as shown in Figure 5, if the impedance of the surface wiring pattern is Z1, the impedance of the LVH is Z2, and the impedance of the IVH is Z3, if there is a mismatch between the impedances Z1, Z2, and Z3, high-frequency signals will be reflected at the connection points.

In this case, the reflection coefficient γ is expressed by equation (3). Note that equation (3) represents the reflection coefficient at the connection between the surface wiring pattern and the LVH, but the reflection coefficient at the connection between the LVH and IVH can also be calculated in a similar manner.

In this case, reflections at the connection points can be suppressed by matching the impedances Z2 and Z3 of the LVH and IVH with the impedance Z1 of the surface wiring pattern. The impedance Z2 of the surface-side LVH can be matched with the surface wiring pattern by providing ground via holes 44 around the LVH or adjusting the distance between the LVH and the ground pattern, as shown in Figure 2.

However, since there are ground patterns on each layer around the impedance Z2 of the IVH on the inner layer side, the electromagnetic field coupling with the ground patterns is strong, resulting in a smaller impedance than the LVH.

For this reason, even if the LVH impedance Z2 can be set to 85 Ω, the same as the surface wiring pattern impedance Z1, the IVH impedance Z3 cannot be matched to impedance Z1, as shown in the upper part of Figure 6.

In this case, if the impedance Z3 of the IVH is 55 Ω, the reflection coefficient γ at the connection with the LVH is 0.214, and if the input signal Vin to the wiring pattern is 1000 mV, the reflected signal Vr at the connection will be 214 mV.

In contrast, if the impedance Z2 of the LVH is set to an intermediate value between the impedance Z1 of the surface wiring pattern and the impedance Z3 of the IVH, for example 70 Ω, reflections will also occur at the connection between the surface wiring pattern and the LVH.

In this case, as shown in the lower part of Figure 6, the reflection coefficient γ1 at the connection between the surface wiring pattern and the LVH is 0.096, and the reflected signal Vr1 at this connection is 96 mV. Furthermore, the reflection coefficient γ2 at the connection between the LVH and IVH is 0.12, and the reflected signal Vr2 at this connection is 108 mV.

Therefore, in this case, the transmission loss of the input signal Vin occurring in the transmission path from the surface wiring pattern via the LVH to the IVH is Vr1 + Vr2 = 204 mV, which is smaller than when the LVH impedance Z2 is matched to the surface wiring pattern.

Therefore, in this embodiment, the impedance of the LVHs 22, 24 is set to an intermediate value between the impedance of the surface wiring pattern 12 and the impedance of the IVH 26, and the LVH 24 on the built-in side is set to be smaller than the LVH 22 on the surface side.

However, in this case, if the diameters of both ends of the LVHs 22 and 24 on the pattern layers P1-P2 and P2-P3 are made to match the diameter of the surrounding anti-pads AP, the impedance in the transmission path from the surface wiring pattern to the IVH will change in a stepped manner, as shown in Figure 7.

Furthermore, in this embodiment, in the pattern layers P1-P2 and P2-P3, the diameter of the surrounding anti-pads AP is set to gradually decrease from the surface layer side to the inner layer side relative to the diameter of the end portions of the LVHs 22 and 24.

In other words, in the pattern layers P1-P2 and P2-P3, the clearance between the LVHs 22, 24 and the surrounding ground patterns is set to gradually decrease from the surface layer toward the inner layer.

As a result, as shown in Figure 8, the impedance in the transmission path from the surface wiring pattern 12 to the IVH 26 changes gradually rather than stepwise, further reducing the reflection of high-frequency signals in this transmission path.

Therefore, as shown in the example in Figure 9, when the wavelength of the transmission signal is λ, by setting the length of the transmission path from the surface wiring pattern 12 to the IVH 26 to "n x λ/2 + λ/4", it is possible to suppress reflection loss of the transmission signal and transmit the transmission signal with low loss.

In Figure 9, the reflection characteristics indicated by the dotted line are those obtained as a comparative example when the clearances around both ends of the LVHs 22 and 24 are the same. This shows that this embodiment can improve the reflection loss of the transmission signal by 5 dB or more.

In this embodiment, the clearances around the LVHs 22 and 24 on the pattern layers P1-P2 and P2-P3 are adjusted to suppress reflections that occur in the transmission path up to the IVH 26, but reflections of the transmission signal also occur at the connection between the IVH 26 and the wiring pattern 18.

Furthermore, as shown by the dotted line in Figure 8, if the impedance of wiring pattern 18 is set to match that of the surface wiring pattern 12, the reflection that occurs at the connection between VH 26 and wiring pattern 18 will be large.

Therefore, in this embodiment, the impedance of the wiring pattern 18 is adjusted to match the impedance of the IVH 26 .
2 to 4, in the multilayer printed circuit board 1 of this embodiment, the wiring patterns 12, 14, 16, and 18 connected via the LVHs 22 and 24 and the IVHs 26 are wiring patterns for balanced transmission, in which two microstrip lines are arranged in parallel. The differential impedance of this wiring pattern for balanced transmission can be adjusted by changing the line width and the line spacing of the two microstrip lines.

For this reason, the differential impedance of the inner layer wiring pattern 18 is set to match the differential impedance of the two IVHs 26 to which each microstrip line is connected by adjusting the line width and wiring spacing of each microstrip line.

As a result, in the multilayer printed circuit board 1 of this embodiment, not only can reflections occurring in the transmission path from the surface wiring pattern 12 to the IVH 26 be suppressed, but reflections occurring between the IVH 26 and the wiring pattern 18 can also be suppressed.

[effect]
As described above, in the multilayer printed circuit board 1 of this embodiment, the clearances between the LVHs 22, 24 and the surrounding ground patterns are set to become smaller toward the inner layers in the pattern layers P1 to P3. In addition, the differential impedance of the wiring pattern 18 on the inner layers is adjusted to match the differential impedance of the two IVHs to which the two microstrip lines constituting this wiring pattern 18 are connected.

As a result, in the multilayer printed circuit board 1 of this embodiment, reflection of the transmission signal along the transmission path from the surface wiring pattern 12 to the inner layer wiring pattern 18 can be suppressed, improving the transmission characteristics of the transmission signal.

In addition, to reduce reflection loss along this transmission path, reflection loss of the transmission signal can be reduced even when the impedance of LVHs 22, 24, and IVHs 26 is not matched to the impedance of the surface wiring pattern. Therefore, according to this embodiment, restrictions on the manufacturing conditions and peripheral wiring of the multilayer printed circuit board 1 can be relaxed, allowing for greater design freedom.

Other Embodiments
Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be implemented in various modified forms.

(a) For example, in the multilayer printed circuit board 1 of the above embodiment, two wiring patterns 14 and 16 are provided on the pattern layers P2 and P3, connecting the LVH 22 and LVH 24, and the LVH 24 and IVH 26, respectively.

The length of these wiring patterns 14, 16 can be made extremely short. However, if the differential impedance of these wiring patterns 14, 16 deviates from the differential impedance at the ends of the LVHs 22, 24 and IVHs 26 to which each wiring pattern 14, 16 is connected, reflection of the transmission signal will increase.

For this reason, the differential impedance of the wiring pattern 14 may be set to an intermediate value between the differential impedance of the end of the pattern layer P2 of the LVH 22 and the differential impedance of the end of the pattern layer P2 of the LHV 24.

Similarly, the differential impedance of the wiring pattern 16 may be set to an intermediate value between the differential impedance of the LVH 24 at the end of the pattern layer P3 and the differential impedance of the IHV 26 at the end of the pattern layer P3.

This also reduces the reflection loss of the transmission signal that occurs in the wiring patterns 14 and 16, enabling the transmission of high-frequency signals with less loss in the multilayer printed circuit board 1.

The differential impedance of the wiring patterns 14, 16 can be adjusted by adjusting the spacing between the two microstrip lines that make up each wiring pattern 14, 16.

(b) Also, as shown in Figure 1, a surface wiring pattern different from wiring pattern 12 may be connected to a location of wiring pattern 18 other than the connection portion with IVH 26 via an IVH and two LHVs.

In this way, when an IVH and two LHVs are connected to the wiring pattern 18 for connection to the surface wiring pattern, the diameter of the anti-pad around the LHV and the impedance of the IVHs on each pattern layer P1, P2, and P3 can be set in the same manner as above.

In other words, this arrangement can reduce the reflection loss of a transmission signal that occurs in the transmission path from the wiring pattern on the inner layer to the wiring pattern on the surface layer.
(c) In the above embodiment, the wiring patterns 12 to 18 are described as wiring patterns for balanced transmission, but the wiring patterns 12 to 18 may also be wiring patterns for unbalanced transmission composed of a single microstrip line.

In this case, only one LVH 22, 24 and IVH 26 are connected to each wiring pattern 12-18, and there is no need to adjust the spacing between the two via holes that make up the LVH 22, 24 and IVH 26, making design easier.

(d) In the above embodiment, two LVHs 22, 24 are provided between the surface wiring pattern 12 and the IVH 26, but the number of LVHs per layer connecting the wiring pattern 12 and the IVH 26 may be one, three, or more.

(e) Multiple functions possessed by one component in the above embodiments may be realized by multiple components, or one function possessed by one component may be realized by multiple components. Furthermore, multiple functions possessed by multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Furthermore, part of the configuration of the above embodiments may be omitted. Furthermore, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments.

(f) In addition to the multilayer printed circuit board described above, the present disclosure can also be realized in various forms, such as a system that includes the multilayer printed circuit board as a component, or a method for adjusting the impedance of a multilayer printed circuit board.

1...Multilayer printed circuit board, 10...Electronic components, 12-18...Wiring patterns, 22, 24...LVH (laser via holes), 26...IVH (inner via holes), 32, 33...Ground patterns, D1-D7...Dielectric layers, P1-P8...Pattern layers.

Claims (3)

A multilayer printed circuit board in which a plurality of dielectric layers (D1 to D7) and a plurality of pattern layers (P1 to P8) are alternately stacked,
an inner via hole (26) that penetrates two or more of the dielectric layers on the inner layer side of the multilayer printed circuit board and electrically connects the wiring patterns (16-18) formed on the two pattern layers that sandwich the two or more dielectric layers;
laser via holes (22, 24) provided in the dielectric layer on the surface side of the inner via holes in the multilayer printed circuit board, for conducting the wiring patterns (12-14, 14-16) of the pattern layers laminated on the front and back surfaces of the dielectric layer to form a signal path between the wiring patterns on the surface side of the multilayer printed circuit board and the inner via holes;
and in the plurality of pattern layers arranged on both ends of the laser via hole, a clearance between the ground pattern around the laser via hole and the laser via hole is smaller on the inner layer side than on the surface layer side of the laser via hole. 2. The multilayer printed circuit board according to claim 1,
The impedance of the wiring pattern connected to the opposite side of the inner via hole from the laser via hole is matched to the impedance of the inner via hole. 3. The multilayer printed circuit board according to claim 1,
A multilayer printed circuit board, wherein the impedance of the wiring pattern connected to the inner layer side of the laser via hole is set to be intermediate between the impedances of two via holes connected to both ends of the wiring pattern.