JP7808768B2 - Multilayer alumina substrates for electronic devices, electronic devices and chip resistors - Google Patents

Description

This disclosure relates to laminated alumina substrates for electronic devices, electronic devices, and chip resistors.

Alumina substrates have excellent insulation and thermal conductivity, and have traditionally been widely used as substrates for electronic devices, such as chip resistors. A chip resistor typically comprises an insulating substrate, a pair of upper electrodes provided at both ends of the upper surface of the insulating substrate, and a resistor provided on the upper surface of the insulating substrate and connected between the pair of upper electrodes.

The chip resistor further includes a protective film provided to cover at least the resistor element, a pair of end electrodes provided on both end surfaces of the insulating substrate to be electrically connected to the pair of upper electrodes, and a plating layer formed on a portion of the upper electrode and the surface of the pair of end electrodes.

Typically, when manufacturing the above chip resistors, multiple sets of surface electrodes and resistor elements are formed together on a large alumina substrate. The large substrate on which the surface electrodes are formed is then divided (broken) along the primary and secondary dividing grooves that extend in a grid pattern, or a dicing blade is used instead of the dividing grooves to cut the large substrate into a grid pattern, thereby obtaining individual chip elements.

However, the surface of an alumina substrate is not smooth and has minute irregularities and undulations. This poses the problem of the shape of the front electrodes and resistors formed on the surface of the alumina substrate being difficult to stabilize. In particular, when the front electrodes and resistors are formed as thin films using photolithography, the thin film front electrodes and resistors are affected by the surface condition of the alumina substrate, resulting in problems such as distortion, breaks, and cracks.

To solve the above problem, for example, Patent Document 1 proposes a technology in which a small amount of silica glass is incorporated into the alumina substrate itself, a glass coating is formed over the entire surface of the alumina substrate, and an upper electrode, resistor, etc. are formed on the glass coating.

JP 2017-168749 A

The technology described in Patent Document 1 above suffers from the problem that, when subjected to annealing or repeated thermal loads in later processes of chip resistor manufacturing, defects such as resistor breakage occur, resulting in a decrease in chip resistor yield. This disclosure has been made in light of the above circumstances, and its purpose is to provide electronic devices such as chip resistors that have excellent heat resistance and exhibit stable characteristics even after undergoing the above annealing process, as well as laminated alumina substrates for use in such electronic devices.

The laminated alumina substrate for electronic devices according to an embodiment of the present disclosure that can achieve the above object is:
an alumina substrate made of a sintered body of alumina particles and having an uneven surface;
The alumina substrate further comprises a planarizing film, the main component of which is alumina, provided on the upper surface of the alumina substrate.

The chip resistor according to an embodiment of the present disclosure, which achieves the above-mentioned objective, is characterized in that at least a resistor element is disposed on the upper surface of the planarization film of the laminated alumina substrate for electronic devices according to an embodiment of the present disclosure.

This disclosure makes it possible to provide electronic devices such as chip resistors with excellent heat resistance, as well as laminated alumina substrates for use in such electronic devices.

FIG. 1 is a schematic cross-sectional view of a chip resistor according to an embodiment of the present disclosure. FIG. 2 is a diagram showing an example of a scanning electron microscope photograph of a cross section of an alumina substrate in an example. FIG. 3 is a diagram showing an example of a scanning electron microscope photograph of a cross section of an alumina substrate on which a planarizing film is formed in an example.

As mentioned above, the technology in Patent Document 1 causes defects such as resistor breakage in chip resistors, resulting in variations in resistance values. The cause of this is thought to be that when the chip resistor is annealed or subjected to repeated thermal loads after resistor formation during the chip resistor manufacturing process, the glass coating, which is the layer under the resistor, differs greatly in thermal expansion coefficient from the alumina substrate, causing the glass coating to peel off from the alumina substrate or cracks to form in the glass coating.

Therefore, in consideration of these circumstances, we have conducted extensive research and have found that the substrate in the electronic device such as the chip resistor is
an alumina substrate made of a sintered body of alumina particles and having an uneven surface;
It has been found that a laminated alumina substrate is provided with a planarizing film made mainly of alumina and provided on the upper surface of the alumina substrate.

First, a laminated alumina substrate for electronic devices according to an embodiment of the present disclosure will be described below. Note that hereinafter, the laminated alumina substrate for electronic devices may be simply referred to as a "laminated alumina substrate."

[Laminated alumina substrate for electronic devices]
(alumina substrate)
The alumina substrate used in the laminated alumina substrate for electronic devices is made of a sintered body of alumina particles. The sintered body is preferably formed of alumina with a purity of 96% or more, which has excellent heat resistance and insulating properties. Furthermore, the alumina substrate has surface irregularities. The irregularities on the surface of this alumina substrate are due to the shape of the alumina particles that make up the sintered body, and the height of the irregularities is, for example, approximately several hundred to several thousand nanometers. In an embodiment of the present disclosure, by providing a planarizing film on the alumina substrate, it is possible to form, for example, an upper electrode or a resistor without being affected by the surface condition of the alumina substrate.

(Planarization film)
The planarization film is mainly composed of alumina. The term "main component" means that the proportion of alumina in the planarization film is 50% by mass or more, preferably 80% by mass or more, and more preferably 90% by mass or more. In addition to alumina, the planarization film may contain metal oxides such as silica, zirconia, and titania, organic or inorganic binders, etc., within a range that does not result in an excessive difference in thermal expansion coefficient from the alumina substrate.

Since the main component of the planarization film is alumina, when it is placed on an alumina substrate, there is little difference in the thermal expansion coefficient between the film and the alumina substrate even when subjected to thermal load. Furthermore, since a planarization film whose main component is alumina is similar in material to the alumina substrate, it exhibits the same excellent insulation and thermal conductivity as the alumina substrate. As a result, the characteristics of alumina substrates, such as their excellent insulation and thermal conductivity, can be fully utilized in electronic devices.

As mentioned above, the surface of a typical alumina substrate has irregularities ranging from several hundred to several thousand nanometers due to the shape of the alumina particles that make up the sintered body. Therefore, it is preferable that the thickness of the planarization film be equal to or greater than the height of the irregularities. Since the height of the irregularities can also be the particle diameter of the alumina particles that make up the sintered body, it can also be said that it is preferable that the thickness of the planarization film be equal to or greater than the average particle diameter of the alumina particles that make up the sintered body. The thickness of the planarization film depends on the height of the irregularities and the average particle diameter of the alumina particles that make up the sintered body, but is preferably equal to or greater than 1.0 μm, for example. There is no particular upper limit to the thickness of the planarization film, but the thickness of the planarization film can be, for example, 20 μm or less.

(Maximum height Rz of planarization film)
When manufacturing an electronic device such as a chip resistor, a resistor is provided on a planarization film. In this case, it is desirable that the resistor be firmly adhered to the surface of the planarization film. After examining the adhesion between the planarization film and the resistor, it was found that the surface of the planarization film preferably has a moderate roughness. Specifically, it was found that the maximum height Rz of the planarization film is preferably 100 nm or more and 1500 nm or less. The maximum height Rz is more preferably 200 nm or more and more preferably 1000 nm or less. The maximum height Rz was determined as the maximum height roughness of a roughness curve based on Japanese Industrial Standard JIS B0601:2013.

The reason why the above range is preferable will be explained using a chip resistor as an example. When the maximum height Rz is within the above range, the resistor penetrates into the macroscopic uneven structure on the surface of the planarization film, increasing the mutual contact area and creating an anchor effect, improving adhesion between the planarization film and the resistor.

If the maximum height Rz is below 100 nm, there are few fine irregularities on the surface of the planarization film, so the contact between the planarization film and the resistor remains within a two-dimensional plane, making the resistor more likely to peel off from the planarization film. On the other hand, if the maximum height Rz of the planarization film exceeds 1500 nm, the surface roughness of the planarization film itself is too great and it does not adequately fulfill its role of planarizing the alumina substrate, resulting in wiring breakage and poor connection during resistor deposition, leading to increased variation in resistance values.

(Average spacing S of local peaks of planarization film)
The adhesion between the planarization film and the resistor is further improved if the mean spacing S between the local peaks in the surface of the planarization film is preferably 500 nm or less. The mean spacing S between the local peaks is more preferably 300 nm or less. The mean spacing S between the local peaks is determined based on JIS B0601:1994.

If the average spacing S of the local peaks is 500 nm or less, the resistor will penetrate into the microscopic uneven structure of the planarization film surface, increasing the mutual contact area and creating an anchor effect, improving adhesion between the planarization film and the resistor.

Preferably, if either the maximum height Rz or the average spacing S of the local peaks is within the above range, adhesion between the resistor and the planarization film is improved. As a result, as mentioned above, even when dicing is performed during the manufacture of the chip element, peeling of the resistor due to the impact of the dicing is suppressed, and high adhesion can be maintained. More preferably, if both the maximum height Rz and the average spacing S of the local peaks are within the above range, adhesion is further improved, and durability against thermal loads as well as durability against the impact of the dicing can be further improved.

[Electronic Devices]
An embodiment of the present disclosure includes an electronic device including the laminated alumina substrate. The electronic device may be a chip resistor. The chip resistor may include a chip resistor having at least a resistor disposed on the upper surface of the planarizing film of the laminated alumina substrate.

The following describes a chip resistor equipped with a laminated alumina substrate according to an embodiment of the present disclosure, and a method for manufacturing the same, with reference to the drawings. Note that the embodiment of the present disclosure is not limited to the form shown in the drawings below, and can be modified as appropriate without impairing the effects of the present disclosure. In the following description, identical components are designated by the same reference numerals, and their description will be omitted where appropriate.

First, referring to FIG. 1, a chip resistor including a laminated alumina substrate according to one embodiment of the present disclosure will be described. A chip resistor 21 according to one embodiment of the present disclosure has the configuration shown in FIG. 1. Specifically, the chip resistor 21 includes an alumina substrate 11, a pair of upper electrodes 12, a pair of lower electrodes 12a, a planarization film 13, a resistor 14, and a pair of end electrodes 15. The pair of upper electrodes 12 are provided at both ends of one surface (top surface) of the alumina substrate 11. Alternatively, as shown in FIG. 1, a pair of lower electrodes 12a may be provided at both ends of the back surface of the alumina substrate 11. The planarization film 13 is provided over the entire top surface of the alumina substrate 11, and the resistor 14 is provided on the top surface of the planarization film 13 and connected between the pair of upper electrodes 12. The pair of end electrodes 15 are provided on both end surfaces of the alumina substrate 11 so as to be electrically connected to the pair of upper electrodes 12. Note that although the chip resistor 21 illustrated in FIG. 1 is provided with a lower electrode 12a, the chip resistor according to the present disclosure does not necessarily have to be provided with a lower electrode 12a.

In the above configuration, the alumina substrate 11 has a rectangular shape (rectangular when viewed from above).

The method for manufacturing the alumina substrate 11 is not particularly limited. It is generally produced by molding and sintering alumina particles. Note that, from the perspective of improving the properties of the alumina substrate, it is preferable that the alumina particles used to manufacture the sintered body that makes up the alumina substrate 11 have a larger aspect ratio than spherical particles, for example, feather-like particles.

The method for providing the planarizing film 13 on the alumina substrate 11 is not particularly limited, but a sol-gel method, for example, can be preferably used. A method for manufacturing a chip resistor according to a preferred embodiment of the present disclosure includes applying a sol material of feathery or fibrous colloidal alumina particles to an alumina substrate by the sol-gel method, drying the sol material, and then performing an annealing process. The sol-gel method is a ceramic synthesis method that can produce a planarizing film at a lower temperature than conventional melting or sintering methods. Furthermore, because the raw materials are in solution, a thin planarizing film can be produced.

In the sol-gel method, a planarizing film 13 can be formed by applying a sol material to an alumina substrate 11 and drying it. Various application methods are possible, including spin coating, dipping, spraying, transfer coating, die coating, gravure printing, flexographic printing, offset printing, screen printing, and inkjet printing.

When using methods such as the sol-gel method, the leveling effect of the sol-gel liquid is exerted when forming the planarizing film, making it possible to obtain a planarizing film with a smooth surface even if the film thickness is approximately the same as the height of the irregularities on the alumina substrate surface.

To efficiently achieve the leveling effect, additives can be added to control the increase in viscosity due to drying, with the aim of controlling the time until leveling. Leveling can also be promoted by reducing surface tension, so additives that promote a reduction in surface tension can also be added. Leveling can also be promoted by adding additives that improve wettability with the substrate.

The above describes the materials that make up the planarization film, but this is not the only option; it is also possible to perform treatments on the substrate side. For example, to improve wettability, hydrophilic or lipophilic treatments can be performed on the substrate side depending on the properties of the material that makes up the planarization film.

Alumina sol is produced by various methods, producing boehmite crystals, pseudo-boehmite crystals, or amorphous colloidal alumina, and sols of colloidal alumina particles are produced in a variety of shapes, including rod-like, fibrous, feathery, and granular. As mentioned above, it is preferable to form a planarization film 13 with a thickness equal to or greater than the height of the irregularities on the alumina substrate surface.

The colloidal alumina particles used to form the planarization film 13 are preferably feather-like or fibrous, and more preferably feather-like. By using colloidal alumina particles of this shape to form the planarization film 13, the colloidal alumina particles become entangled with each other and are able to withstand internal stress caused by volumetric shrinkage, thereby suppressing the occurrence of cracks in the planarization film 13 due to drying or sintering.

It is preferable to apply the alumina sol to the alumina substrate 11, dry it to form the planarization film 13, and then anneal it. By performing the annealing, the crystal structure of the alumina particles changes, reducing the specific surface area of the particles and achieving a denser film state. By making the planarization film 13 dense, it is possible to prevent alumina particles from falling off the surface of the planarization film, and as a result, it is possible to prevent the surface roughness of the planarization film 13 from becoming smaller than necessary.

The annealing process is performed after the planarization film 13 is formed but before the resistor 14 is formed, so that the resistor 14 formed on the planarization film 13 is not affected by volumetric shrinkage due to the annealing. This annealing process is preferably performed at a temperature equal to or higher than that of the annealing process performed in the subsequent process. For example, the annealing process may be performed at a temperature in the range of 600 to 900°C for, for example, 12 hours, as in the example described below.

After the annealing process, as shown in the examples below, a thin film made of a NiCrAlSi alloy is formed on the planarizing film by sputtering or other methods. Subsequently, the thin film is patterned into a meandering shape by photolithography (resist application, drying, exposure, development, etching, and resist removal), forming the resistor 14. Materials that can be used to make the resistor 14 include the NiCrAlSi alloy, as well as pure metals such as Pt, Ni, and Cu, and alloys containing 50% or more of each metal by mass, such as Pt-Co alloys. These materials have a high temperature coefficient of resistance (TCR), and resistors made of these materials can be used for temperature measurement in addition to functioning as chip resistors.

The methods for forming the alumina substrate 11, planarization film 13, and resistor 14 shown in Figure 1 are not particularly limited. For example, the upper electrode 12 is formed by printing a thick film material made of copper onto the planarization film 13 and firing it. Other electrodes, protective films, and plating layers can also be formed using commonly used methods.

In the manufacturing process for the chip resistor, an annealing treatment can be performed after the resistor is formed but before the electrodes are formed, or after the resistor and electrodes are formed. According to an embodiment of the present disclosure, the inclusion of a laminated alumina substrate with excellent heat resistance can prevent cracks from occurring in the resistor after the annealing treatment.

The present disclosure will be explained in more detail below using examples. The present disclosure is not limited to the following examples, and appropriate modifications can be made within the scope of the above-mentioned and below-mentioned aims, and all such modifications are within the technical scope of the present disclosure.

[Example 1]
First, a planarizing film was prepared on an alumina substrate as follows. A feathery alumina sol (product name: Alumina Sol 200 (AS-200)) manufactured by Nissan Chemical Industries, Ltd. was applied to the upper surface of an alumina substrate (size: 4 square inches) made of alumina with a purity of 96% or higher by spin coating at 1000 rpm for 20 seconds using a spin coater (manufactured by Mikasa Co., Ltd.), and then dried at room temperature. The thickness of the planarizing film after drying was approximately 4.8 μm. The film was then annealed in an electric drying furnace at 700°C for 12 hours.

Examples of scanning electron microscope photographs of the cross section of the alumina substrate used in this example and the cross section of the alumina substrate after a planarization film was formed are shown in Figure 2, and Figures 3(a) and 3(b). Figure 2 was taken using a scanning electron microscope (S-5000, manufactured by Hitachi High-Technologies Corporation), while Figures 3(a) and 3(b) were taken using a scanning electron microscope (VE-9800, manufactured by Keyence Corporation). Figure 3(b) is an enlarged microscope photograph of the area enclosed by the dashed line in Figure 3(a).

The maximum height Rz and arithmetic mean roughness Ra of the surface of the alumina substrate were measured using an atomic force microscope (manufactured by Hitachi High-Tech Science Corporation). The maximum height Rz was 2,450 nm, and the arithmetic mean roughness Ra was 219 nm. Furthermore, after a planarization film was formed on the alumina substrate, the maximum height Rz, arithmetic mean roughness Ra, and mean spacing S of the local peaks of the planarization film were measured using the same atomic force microscope. The maximum height Rz was 240 nm, the arithmetic mean roughness Ra was 16.9 nm, and the mean spacing S of the local peaks was 210 nm. Figures 2, 3(a), and 3(b) above also show that the formation of the planarization film results in a flat surface suitable for forming electrodes and resistors, without being affected by the surface condition of the alumina substrate.

Next, a resistor was formed on the planarizing film as follows. Specifically, a thin film made of a NiCrAlSi alloy was formed on the planarizing film by sputtering or other methods, and then the thin film was patterned using photolithography (resist application, drying, exposure, development, etching, and resist removal) to form a 15 μm linewidth bellows (meandering) shape, forming the resistor.

Using a sample in which the above-mentioned alumina substrate, planarization film, and resistor were stacked in this order, the adhesion between the resistor and planarization film after a thermal load was evaluated as heat resistance, as detailed below. Furthermore, the adhesion between the resistor and planarization film after dicing and the electrostatic resistance characteristics were also evaluated.

(Evaluation of adhesion between resistor and planarization film after heat load)
Using the above samples, the heat resistance was evaluated as follows: the adhesion between the resistor and the planarizing film after heat treatment. First, a heat load test was performed in which the sample was heated (annealed) at 900°C. Then, after the test, the surfaces of the resistor and the planarizing film were visually inspected using an electron microscope. A sample with no cracks or peeling on either the surface of the resistor or the planarizing film was evaluated as good (◎); a sample with cracks or peeling on the planarizing film but no cracks or peeling on the surface of the resistor was evaluated as fair (◯); and a sample with cracks or peeling on the planarizing film and cracks or peeling on the resistor was evaluated as poor (×).

(Evaluation of adhesion between resistor and planarization film after dicing process)
After the annealing for evaluating the adhesion between the resistor and the planarization film after the heat load, an impact resistance test was conducted to apply external stress to the resistor. Specifically, the substrate was diced to divide the chip resistors into 2012 size (2 mm × 1.2 mm). Then, after the test, the surface of the resistor and the planarization film were visually inspected using an electron microscope. Those without cracks or peeling on either the surface of the resistor or the planarization film were evaluated as good (◎), those with cracks or peeling on the planarization film but no cracks or peeling on the surface of the resistor were evaluated as fair (◯), and those with cracks or peeling on the planarization film and cracks or peeling on the resistor were evaluated as poor (×).

(Static resistance characteristic evaluation)
For this example, in which the adhesion evaluation between the resistor and the planarization film after the above-mentioned heat load and dicing process was good, an electrostatic resistance characteristic evaluation was also performed (the same applies to Examples 2 to 5 below). In detail, an electrostatic discharge resistance test (AEC-Q200) was performed, and products with a resistance change rate of 0.05% or less when 1 kV was applied were evaluated as good products. A total of 20 pieces were tested, and products with a good product rate of 80% or more were evaluated as good, with a "◯"; products with a rate of 50% or more but less than 80% were evaluated as acceptable, with a "△"; and products with a rate of less than 50% were evaluated as poor, with a "X".

[Example 2]
In Example 2, a planarizing film was prepared in the same manner as in Example 1, except that the rotation speed of the spin coater was set to 3000 rpm to obtain a planarizing film having a thickness of 1.8 μm after drying, and the obtained sample was evaluated in the same manner as in Example 1.

[Example 3]
In Example 3, a planarization film was prepared in the same manner as in Example 1, except that a fibrous alumina sol (product name: Cataloid A Series (AS-3)) manufactured by JGC Catalysts and Chemicals Co., Ltd. was used to form the planarization film, and the obtained sample was evaluated in the same manner as in Example 1.

[Example 4]
In Example 4, a planarization film was prepared in the same manner as in Example 1, except that particulate alumina sol (product name: Alumina Sol 10-A) manufactured by Kawaken Fine Chemical Co., Ltd. was used to form the planarization film, and the obtained sample was evaluated in the same manner as in Example 1.

[Example 5]
In Example 5, a sample was prepared in the same manner as in Example 1, in which an alumina substrate, a planarizing film, and a resistor were laminated in this order, except that the material constituting the resistor was Pt and etching and heat treatment conditions in the process were changed accordingly, and an evaluation similar to that in Example 1 was carried out.

[Comparative Example 1]
In Comparative Example 1, a planarization film was prepared in the same manner as in Example 1, except that particulate silica sol (product name: SI-80P) manufactured by JGC Catalysts and Chemicals Co., Ltd. was used to form the planarization film, and the obtained sample was subjected to the same evaluation.

[Comparative Example 2]
In Comparative Example 2, a planarization film was prepared in the same manner as in Example 1, except that a particulate silica sol (product name: SS-300) manufactured by JGC Catalysts and Chemicals Co., Ltd. was used to form the planarization film, and the same evaluation was performed on the obtained sample.

[Comparative Example 3]
In Comparative Example 3, a siloxane (product name: S05-018H) manufactured by Merck Performance Materials Co., Ltd. was used to form the planarization film. Siloxane provides excellent flatness during film formation but has poor heat resistance. Therefore, after the siloxane was applied and allowed to dry naturally, no annealing treatment was performed. The heat load test was also not performed. Other than these, samples were prepared and evaluated in the same manner as in Example 1.

The measurement results for the surface texture of the resistors and the evaluation results for the sample characteristics are shown in Table 1. Below, Examples 1 to 5 and Comparative Examples 1 to 3 will be explained using Table 1.

As is clear from Table 1, in Examples 1 to 5, a planarizing film made of the same alumina as the alumina substrate was formed on the surface of the alumina substrate with a textured structure, and therefore, excellent adhesion was achieved between the resistor and the planarizing film after the sample heat load test and dicing process. In other words, Examples 1 to 5 also had excellent heat resistance and impact resistance.

Furthermore, in these examples, the planarization film is made of the same material as the alumina substrate, allowing the excellent thermal conductivity of the alumina substrate to be fully utilized. Furthermore, as in Example 5, by using a material with a large temperature coefficient of resistance (TCR) for the resistor, it was confirmed that the desired heat resistance and shock resistance were excellent, and that the advantage of a large TCR could be utilized to measure temperature.

Of these examples, Examples 1 to 3 and 5 had a maximum height Rz in the range of 100 nm to 1500 nm and an average spacing S between local peaks of 500 nm or less. They exhibited excellent adhesion between the resistor and the planarizing film after the sample was subjected to a thermal load test and dicing process, as well as excellent electrostatic resistance. In particular, Examples 1, 2 and 5 exhibited particularly excellent adhesion between the resistor and the planarizing film after the sample was subjected to a thermal load test and dicing process. This is thought to be because the average spacing S between the local peaks was sufficiently small, allowing for a sufficient anchoring effect between the planarizing film and the resistor.

The maximum height Rz of Example 4 was higher than that of Examples 1 to 3 and 5. This is thought to be because the alumina sol material used in Example 4 had a lower viscosity than the alumina sol materials of Examples 1 to 3 and 5, which made it easier for the surface of the planarization film to reflect the unevenness of the alumina substrate surface. In Example 4, the unevenness of the planarization film produced an anchoring effect, resulting in excellent adhesion between the resistor and the planarization film after the sample's thermal load test and dicing process. However, the electrostatic resistance characteristics varied more than in Examples 1 to 3 and 5. This is thought to be because the unevenness of the planarization film caused part of the resistor's wiring to break or partial wiring to be missing when electricity was applied during the electrostatic discharge resistance test, resulting in a larger rate of change in resistance value.

Comparing Examples 1 to 3 and 5 with Example 4, it is clear that in order to further improve electrostatic discharge resistance, it is preferable that the maximum height Rz of the planarization film be 1,500 nm or less.

Comparative Example 1 was found to be poor in adhesion evaluation due to thermal load. This is because an anchor effect was observed between the alumina substrate and the planarization film, resulting in adhesion. However, because the material of the planarization film is silica, unlike the alumina substrate, the application of thermal load is thought to have created interfacial stress due to differences in thermal expansion coefficients, resulting in cracks and film peeling at the interface of the planarization film with the alumina substrate. Furthermore, it is thought that cracks and film peeling in the planarization film also caused cracks and film peeling in the resistor formed on the surface of the planarization film. The maximum height Rz and average spacing S of local peaks in Comparative Example 1 were within the preferred range, and the dicing adhesion evaluation was good.

In Comparative Example 2, like Comparative Example 1, the planarization film was made of silica rather than alumina, the same material as the substrate. For the reasons mentioned above, this resulted in poor adhesion due to heat load. Furthermore, unlike Comparative Example 1, Comparative Example 2 also showed poor adhesion between the resistor and planarization film, even when dicing was performed without heat treatment. This is thought to be because the average spacing S between the local peaks was not within the preferred range, and a sufficient anchoring effect was not fully achieved between the planarization film and the resistor.

In Comparative Example 3, the planarization film was made of siloxane, not alumina, the same material as the substrate, and for the same reason as in Comparative Example 1, a poor adhesion evaluation was confirmed. Furthermore, as in Comparative Example 2, poor adhesion was observed between the resistor and planarization film even when dicing was performed without heat treatment. This is thought to be because the maximum height Rz was below the preferred range and the average spacing S of the local peaks exceeded the preferred upper limit, preventing a sufficient anchor effect between the planarization film and the resistor, causing cracks or peeling in the resistor. Furthermore, when the maximum height Rz of the planarization film was 100 nm or less, as in Comparative Example 3, a correlation was observed between the maximum height Rz and the average spacing S of the local peaks, with the average spacing S being a wide spacing of 500 nm or more.

The laminated alumina substrate disclosed herein can improve adhesion between the alumina substrate and the planarization film, and also between the planarization film and, for example, a resistor. Therefore, it exhibits excellent heat resistance even when subjected to repeated thermal loads, making it useful as a substrate component for use in electronic devices.

REFERENCE SIGNS LIST 11 alumina substrate 12 upper electrode 12a lower electrode 13 planarizing film 14 resistor 15 end electrode 21 chip resistor

Claims (3)

an alumina substrate made of a sintered body of alumina particles and having an uneven surface;
a planarization film mainly composed of alumina provided on the upper surface of the alumina substrate, the planarization film having a maximum height Rz of 200 nm or more and 1000 nm or less;
The average spacing S of the local peaks of the planarization film is 500 nm or less.
1. A laminated alumina substrate for electronic devices, comprising: An electronic device comprising the laminated alumina substrate for electronic devices according to claim 1 . 2. A chip resistor, comprising: at least a resistor disposed on an upper surface of the planarizing film of the laminated alumina substrate for electronic devices according to claim 1 .